diff options
author | Vikas Manocha <vikas.manocha@st.com> | 2016-02-11 15:47:19 -0800 |
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committer | Tom Rini <trini@konsulko.com> | 2016-02-24 18:43:54 -0500 |
commit | 6a12cebd90a752b0214a65b152703ca63a941478 (patch) | |
tree | 2ea29850ad03b15d7f0908294941ad57951ff844 /drivers | |
parent | 09959ba3c5f0f56bed4b3ab008f9e159e1b28cd9 (diff) | |
download | u-boot-imx-6a12cebd90a752b0214a65b152703ca63a941478.zip u-boot-imx-6a12cebd90a752b0214a65b152703ca63a941478.tar.gz u-boot-imx-6a12cebd90a752b0214a65b152703ca63a941478.tar.bz2 |
stm32x7: add support for stm32x7 serial driver
This patch adds support for stm32f7 family usart peripheral.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/serial/Makefile | 1 | ||||
-rw-r--r-- | drivers/serial/serial_stm32x7.c | 83 | ||||
-rw-r--r-- | drivers/serial/serial_stm32x7.h | 37 |
3 files changed, 121 insertions, 0 deletions
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index c63999a..05bdf56 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -37,6 +37,7 @@ obj-$(CONFIG_ARC_SERIAL) += serial_arc.o obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o obj-$(CONFIG_STM32_SERIAL) += serial_stm32.o obj-$(CONFIG_PIC32_SERIAL) += serial_pic32.o +obj-$(CONFIG_STM32X7_SERIAL) += serial_stm32x7.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_USB_TTY) += usbtty.o diff --git a/drivers/serial/serial_stm32x7.c b/drivers/serial/serial_stm32x7.c new file mode 100644 index 0000000..cfbfab7 --- /dev/null +++ b/drivers/serial/serial_stm32x7.c @@ -0,0 +1,83 @@ +/* + * (C) Copyright 2016 + * Vikas Manocha, <vikas.manocha@st.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <asm/io.h> +#include <serial.h> +#include <dm/platform_data/serial_stm32x7.h> +#include "serial_stm32x7.h" + +DECLARE_GLOBAL_DATA_PTR; + +static int stm32_serial_setbrg(struct udevice *dev, int baudrate) +{ + struct stm32x7_serial_platdata *plat = dev->platdata; + struct stm32_usart *const usart = plat->base; + writel(plat->clock/baudrate, &usart->brr); + + return 0; +} + +static int stm32_serial_getc(struct udevice *dev) +{ + struct stm32x7_serial_platdata *plat = dev->platdata; + struct stm32_usart *const usart = plat->base; + + if ((readl(&usart->sr) & USART_SR_FLAG_RXNE) == 0) + return -EAGAIN; + + return readl(&usart->rd_dr); +} + +static int stm32_serial_putc(struct udevice *dev, const char c) +{ + struct stm32x7_serial_platdata *plat = dev->platdata; + struct stm32_usart *const usart = plat->base; + + if ((readl(&usart->sr) & USART_SR_FLAG_TXE) == 0) + return -EAGAIN; + + writel(c, &usart->tx_dr); + + return 0; +} + +static int stm32_serial_pending(struct udevice *dev, bool input) +{ + struct stm32x7_serial_platdata *plat = dev->platdata; + struct stm32_usart *const usart = plat->base; + + if (input) + return readl(&usart->sr) & USART_SR_FLAG_RXNE ? 1 : 0; + else + return readl(&usart->sr) & USART_SR_FLAG_TXE ? 0 : 1; +} + +static int stm32_serial_probe(struct udevice *dev) +{ + struct stm32x7_serial_platdata *plat = dev->platdata; + struct stm32_usart *const usart = plat->base; + setbits_le32(&usart->cr1, USART_CR1_RE | USART_CR1_TE | USART_CR1_UE); + + return 0; +} + +static const struct dm_serial_ops stm32_serial_ops = { + .putc = stm32_serial_putc, + .pending = stm32_serial_pending, + .getc = stm32_serial_getc, + .setbrg = stm32_serial_setbrg, +}; + +U_BOOT_DRIVER(serial_stm32) = { + .name = "serial_stm32x7", + .id = UCLASS_SERIAL, + .ops = &stm32_serial_ops, + .probe = stm32_serial_probe, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/serial/serial_stm32x7.h b/drivers/serial/serial_stm32x7.h new file mode 100644 index 0000000..6190d67 --- /dev/null +++ b/drivers/serial/serial_stm32x7.h @@ -0,0 +1,37 @@ +/* + * (C) Copyright 2016 + * Vikas Manocha, <vikas.manocha@st.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SERIAL_STM32_X7_ +#define _SERIAL_STM32_X7_ + +struct stm32_usart { + u32 cr1; + u32 cr2; + u32 cr3; + u32 brr; + u32 gtpr; + u32 rtor; + u32 rqr; + u32 sr; + u32 icr; + u32 rd_dr; + u32 tx_dr; +}; + + +#define USART_CR1_RE (1 << 2) +#define USART_CR1_TE (1 << 3) +#define USART_CR1_UE (1 << 0) + +#define USART_SR_FLAG_RXNE (1 << 5) +#define USART_SR_FLAG_TXE (1 << 7) + +#define USART_BRR_F_MASK 0xFF +#define USART_BRR_M_SHIFT 4 +#define USART_BRR_M_MASK 0xFFF0 + +#endif |