Merge git://git.denx.de/u-boot-fsl-qoriq

trini: Drop local memset() from
examples/standalone/mem_to_mem_idma2intr.c

Signed-off-by: Tom Rini <trini@konsulko.com>

8 files changed, 224 insertions, 292 deletions

diff --git a/drivers/ddr/fsl/Makefile b/drivers/ddr/fsl/Makefile
index 01ea862..00dea42 100644
--- a/drivers/ddr/fsl/Makefile
+++ b/drivers/ddr/fsl/Makefile
@@ -33,3 +33,4 @@ obj-$(CONFIG_SYS_FSL_DDRC_GEN3)	+= mpc85xx_ddr_gen3.o
 obj-$(CONFIG_SYS_FSL_DDR_86XX)		+= mpc86xx_ddr.o
 obj-$(CONFIG_SYS_FSL_DDRC_ARM_GEN3)	+= arm_ddr_gen3.o
 obj-$(CONFIG_SYS_FSL_DDRC_GEN4) += fsl_ddr_gen4.o
+obj-$(CONFIG_SYS_FSL_MMDC) += fsl_mmdc.o
diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c
index d37e247..042af09 100644
--- a/drivers/ddr/fsl/fsl_ddr_gen4.c
+++ b/drivers/ddr/fsl/fsl_ddr_gen4.c
@@ -50,8 +50,13 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 	u32 temp_sdram_cfg;
 	u32 total_gb_size_per_controller;
 	int timeout;
+#if defined(CONFIG_SYS_FSL_ERRATUM_A008511) || \
+	defined(CONFIG_SYS_FSL_ERRATUM_A009801)
+	u32 temp32;
+#endif
+
 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
-	u32 temp32, mr6;
+	u32 mr6;
 	u32 vref_seq1[3] = {0x80, 0x96, 0x16};	/* for range 1 */
 	u32 vref_seq2[3] = {0xc0, 0xf0, 0x70};	/* for range 2 */
 	u32 *vref_seq = vref_seq1;
@@ -218,7 +223,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 	ddr_out32(&ddr->err_disable, regs->err_disable);
 #endif
 	ddr_out32(&ddr->err_int_en, regs->err_int_en);
-	for (i = 0; i < 32; i++) {
+	for (i = 0; i < 64; i++) {
 		if (regs->debug[i]) {
 			debug("Write to debug_%d as %08x\n",
 			      i+1, regs->debug[i]);
@@ -238,7 +243,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
 	/* Part 1 of 2 */
-	/* This erraum only applies to verion 5.2.0 */
 	if (fsl_ddr_get_version(ctrl_num) == 0x50200) {
 		/* Disable DRAM VRef training */
 		ddr_out32(&ddr->ddr_cdr2,
@@ -247,13 +251,25 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 		temp32 = ddr_in32(&ddr->debug[28]);
 		temp32 |= DDR_TX_BD_DIS;
 		ddr_out32(&ddr->debug[28], temp32);
-		/* Disable D_INIT */
-		ddr_out32(&ddr->sdram_cfg_2,
-			  regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
 		ddr_out32(&ddr->debug[25], 0x9000);
+	} else if (fsl_ddr_get_version(ctrl_num) == 0x50201) {
+		/* Output enable forced off */
+		ddr_out32(&ddr->debug[37], 1 << 31);
+		/* Enable Vref training */
+		ddr_out32(&ddr->ddr_cdr2,
+			  regs->ddr_cdr2 | DDR_CDR2_VREF_TRAIN_EN);
+	} else {
+		debug("Erratum A008511 doesn't apply.\n");
 	}
 #endif
 
+#if defined(CONFIG_SYS_FSL_ERRATUM_A009803) || \
+	defined(CONFIG_SYS_FSL_ERRATUM_A008511)
+	/* Disable D_INIT */
+	ddr_out32(&ddr->sdram_cfg_2,
+		  regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
+#endif
+
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009801
 	temp32 = ddr_in32(&ddr->debug[25]);
 	temp32 &= ~DDR_CAS_TO_PRE_SUB_MASK;
@@ -331,21 +347,21 @@ step2:
 #if defined(CONFIG_SYS_FSL_ERRATUM_A008511) || \
 	defined(CONFIG_SYS_FSL_ERRATUM_A009803)
 	/* Part 2 of 2 */
-	/* This erraum only applies to verion 5.2.0 */
-	if (fsl_ddr_get_version(ctrl_num) == 0x50200) {
-		/* Wait for idle */
-		timeout = 40;
-		while (!(ddr_in32(&ddr->debug[1]) & 0x2) &&
-		       (timeout > 0)) {
-			udelay(1000);
-			timeout--;
-		}
-		if (timeout <= 0) {
-			printf("Controler %d timeout, debug_2 = %x\n",
-			       ctrl_num, ddr_in32(&ddr->debug[1]));
-		}
+	timeout = 40;
+	/* Wait for idle. D_INIT needs to be cleared earlier, or timeout */
+	while (!(ddr_in32(&ddr->debug[1]) & 0x2) &&
+	       (timeout > 0)) {
+		udelay(1000);
+		timeout--;
+	}
+	if (timeout <= 0) {
+		printf("Controler %d timeout, debug_2 = %x\n",
+		       ctrl_num, ddr_in32(&ddr->debug[1]));
+	}
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
+	/* This erraum only applies to verion 5.2.0 */
+	if (fsl_ddr_get_version(ctrl_num) == 0x50200) {
 		/* The vref setting sequence is different for range 2 */
 		if (regs->ddr_cdr2 & DDR_CDR2_VREF_RANGE_2)
 			vref_seq = vref_seq2;
@@ -392,32 +408,32 @@ step2:
 			printf("Controler %d timeout, debug_2 = %x\n",
 			       ctrl_num, ddr_in32(&ddr->debug[1]));
 		}
-		/* Restore D_INIT */
-		ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
+	}
 #endif /* CONFIG_SYS_FSL_ERRATUM_A008511 */
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009803
-		if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
-			/* if it's RDIMM */
-			if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) {
-				for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
-					if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN))
-						continue;
-					set_wait_for_bits_clear(&ddr->sdram_md_cntl,
-								MD_CNTL_MD_EN |
-								MD_CNTL_CS_SEL(i) |
-								0x070000ed,
-								MD_CNTL_MD_EN);
-					udelay(1);
-				}
+	if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
+		/* if it's RDIMM */
+		if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) {
+			for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+				if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN))
+					continue;
+				set_wait_for_bits_clear(&ddr->sdram_md_cntl,
+							MD_CNTL_MD_EN |
+							MD_CNTL_CS_SEL(i) |
+							0x070000ed,
+							MD_CNTL_MD_EN);
+				udelay(1);
 			}
-
-			ddr_out32(&ddr->err_disable,
-				  regs->err_disable & ~DDR_ERR_DISABLE_APED);
 		}
-#endif
+
+		ddr_out32(&ddr->err_disable,
+			  regs->err_disable & ~DDR_ERR_DISABLE_APED);
 	}
 #endif
+	/* Restore D_INIT */
+	ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
+#endif
 
 	total_gb_size_per_controller = 0;
 	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
diff --git a/drivers/ddr/fsl/fsl_mmdc.c b/drivers/ddr/fsl/fsl_mmdc.c
new file mode 100644
index 0000000..52eec0f
--- /dev/null
+++ b/drivers/ddr/fsl/fsl_mmdc.c
@@ -0,0 +1,156 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/*
+ * Generic driver for Freescale MMDC(Multi Mode DDR Controller).
+ */
+
+#include <common.h>
+#include <fsl_mmdc.h>
+#include <asm/io.h>
+
+static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
+{
+	int timeout = 1000;
+
+	out_be32(ptr, value);
+
+	while (in_be32(ptr) & bits) {
+		udelay(100);
+		timeout--;
+	}
+	if (timeout <= 0)
+		printf("Error: %p wait for clear timeout.\n", ptr);
+}
+
+void mmdc_init(const struct fsl_mmdc_info *priv)
+{
+	struct mmdc_regs *mmdc = (struct mmdc_regs *)CONFIG_SYS_FSL_DDR_ADDR;
+	unsigned int tmp;
+
+	/* 1. set configuration request */
+	out_be32(&mmdc->mdscr, MDSCR_ENABLE_CON_REQ);
+
+	/* 2. configure the desired timing parameters */
+	out_be32(&mmdc->mdotc, priv->mdotc);
+	out_be32(&mmdc->mdcfg0, priv->mdcfg0);
+	out_be32(&mmdc->mdcfg1, priv->mdcfg1);
+	out_be32(&mmdc->mdcfg2, priv->mdcfg2);
+
+	/* 3. configure DDR type and other miscellaneous parameters */
+	out_be32(&mmdc->mdmisc, priv->mdmisc);
+	out_be32(&mmdc->mpmur0,	MMDC_MPMUR0_FRC_MSR);
+	out_be32(&mmdc->mdrwd, priv->mdrwd);
+	out_be32(&mmdc->mpodtctrl, priv->mpodtctrl);
+
+	/* 4. configure the required delay while leaving reset */
+	out_be32(&mmdc->mdor, priv->mdor);
+
+	/* 5. configure DDR physical parameters */
+	/* set row/column address width, burst length, data bus width */
+	tmp = priv->mdctl & ~(MDCTL_SDE0 | MDCTL_SDE1);
+	out_be32(&mmdc->mdctl, tmp);
+	/* configure address space partition */
+	out_be32(&mmdc->mdasp, priv->mdasp);
+
+	/* 6. perform a ZQ calibration - not needed here, doing in #8b */
+
+	/* 7. enable MMDC with the desired chip select */
+#if (CONFIG_CHIP_SELECTS_PER_CTRL == 1)
+		out_be32(&mmdc->mdctl, tmp | MDCTL_SDE0);
+#elif (CONFIG_CHIP_SELECTS_PER_CTRL == 2)
+		out_be32(&mmdc->mdctl, tmp | MDCTL_SDE0 | MDCTL_SDE1);
+#endif
+
+	/* 8a. dram init sequence: update MRs for ZQ, ODT, PRE, etc */
+	out_be32(&mmdc->mdscr,  CMD_ADDR_LSB_MR_ADDR(8) | MDSCR_ENABLE_CON_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2);
+
+	out_be32(&mmdc->mdscr,  CMD_ADDR_LSB_MR_ADDR(0) | MDSCR_ENABLE_CON_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3);
+
+	out_be32(&mmdc->mdscr,  CMD_ADDR_LSB_MR_ADDR(4) | MDSCR_ENABLE_CON_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1);
+
+	out_be32(&mmdc->mdscr,  CMD_ADDR_MSB_MR_OP(0x19) |
+				CMD_ADDR_LSB_MR_ADDR(0x30) |
+				MDSCR_ENABLE_CON_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0);
+
+	/* 8b. ZQ calibration */
+	out_be32(&mmdc->mdscr,  CMD_ADDR_MSB_MR_OP(0x4) | MDSCR_ENABLE_CON_REQ |
+				CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0);
+
+	set_wait_for_bits_clear(&mmdc->mpzqhwctrl, priv->mpzqhwctrl,
+				MPZQHWCTRL_ZQ_HW_FORCE);
+
+	/* 9a. calibrations now, wr lvl */
+	out_be32(&mmdc->mdscr,  CMD_ADDR_LSB_MR_ADDR(0x84) |
+				MDSCR_ENABLE_CON_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1);
+
+	out_be32(&mmdc->mdscr,  MDSCR_ENABLE_CON_REQ | MDSCR_WL_EN |
+				CMD_NORMAL);
+
+	set_wait_for_bits_clear(&mmdc->mpwlgcr, MPWLGCR_HW_WL_EN,
+				MPWLGCR_HW_WL_EN);
+
+	mdelay(1);
+
+	out_be32(&mmdc->mdscr,  CMD_ADDR_LSB_MR_ADDR(4) | MDSCR_ENABLE_CON_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1);
+	out_be32(&mmdc->mdscr, MDSCR_ENABLE_CON_REQ);
+
+	mdelay(1);
+
+	/* 9b. read DQS gating calibration */
+	out_be32(&mmdc->mdscr,  CMD_ADDR_MSB_MR_OP(4) | MDSCR_ENABLE_CON_REQ |
+				CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0);
+
+	out_be32(&mmdc->mdscr,  CMD_ADDR_LSB_MR_ADDR(4) | MDSCR_ENABLE_CON_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3);
+
+	out_be32(&mmdc->mppdcmpr2, MPPDCMPR2_MPR_COMPARE_EN);
+
+	/* set absolute read delay offset */
+	if (priv->mprddlctl)
+		out_be32(&mmdc->mprddlctl, priv->mprddlctl);
+	else
+		out_be32(&mmdc->mprddlctl, MMDC_MPRDDLCTL_DEFAULT_DELAY);
+
+	set_wait_for_bits_clear(&mmdc->mpdgctrl0,
+				AUTO_RD_DQS_GATING_CALIBRATION_EN,
+				AUTO_RD_DQS_GATING_CALIBRATION_EN);
+
+	out_be32(&mmdc->mdscr,  MDSCR_ENABLE_CON_REQ | CMD_LOAD_MODE_REG |
+				CMD_BANK_ADDR_3);
+
+	/* 9c. read calibration */
+	out_be32(&mmdc->mdscr,  CMD_ADDR_MSB_MR_OP(4) | MDSCR_ENABLE_CON_REQ |
+				CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0);
+	out_be32(&mmdc->mdscr,  CMD_ADDR_LSB_MR_ADDR(4) | MDSCR_ENABLE_CON_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3);
+	out_be32(&mmdc->mppdcmpr2,  MPPDCMPR2_MPR_COMPARE_EN);
+	set_wait_for_bits_clear(&mmdc->mprddlhwctl,
+				MPRDDLHWCTL_AUTO_RD_CALIBRATION_EN,
+				MPRDDLHWCTL_AUTO_RD_CALIBRATION_EN);
+
+	out_be32(&mmdc->mdscr,  MDSCR_ENABLE_CON_REQ | CMD_LOAD_MODE_REG |
+				CMD_BANK_ADDR_3);
+
+	/* 10. configure power-down, self-refresh entry, exit parameters */
+	out_be32(&mmdc->mdpdc, priv->mdpdc);
+	out_be32(&mmdc->mapsr, MMDC_MAPSR_PWR_SAV_CTRL_STAT);
+
+	/* 11. ZQ config again? do nothing here */
+
+	/* 12. refresh scheme */
+	set_wait_for_bits_clear(&mmdc->mdref, priv->mdref,
+				MDREF_START_REFRESH);
+
+	/* 13. disable CON_REQ */
+	out_be32(&mmdc->mdscr, MDSCR_DISABLE_CFG_REQ);
+}
diff --git a/drivers/ddr/fsl/interactive.c b/drivers/ddr/fsl/interactive.c
index d23e6e5..49352b3 100644
--- a/drivers/ddr/fsl/interactive.c
+++ b/drivers/ddr/fsl/interactive.c
@@ -670,7 +670,7 @@ static void print_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
 
 	print_option_table(options, n_opts, ddr);
 
-	for (i = 0; i < 32; i++)
+	for (i = 0; i < 64; i++)
 		printf("debug_%02d = 0x%08X\n", i+1, ddr->debug[i]);
 }
 
@@ -771,7 +771,7 @@ static void fsl_ddr_regs_edit(fsl_ddr_info_t *pinfo,
 	if (handle_option_table(options, n_opts, ddr, regname, value_str))
 		return;
 
-	for (i = 0; i < 32; i++) {
+	for (i = 0; i < 64; i++) {
 		unsigned int value = simple_strtoul(value_str, NULL, 0);
 		sprintf(buf, "debug_%u", i + 1);
 		if (strcmp(buf, regname) == 0) {
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index c0e5f03..e4f2464 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -16,7 +16,6 @@ obj-$(CONFIG_CROS_EC_LPC) += cros_ec_lpc.o
 obj-$(CONFIG_CROS_EC_I2C) += cros_ec_i2c.o
 obj-$(CONFIG_CROS_EC_SANDBOX) += cros_ec_sandbox.o
 obj-$(CONFIG_CROS_EC_SPI) += cros_ec_spi.o
-obj-$(CONFIG_FSL_DEBUG_SERVER) += fsl_debug_server.o
 endif
 obj-$(CONFIG_FSL_IIM) += fsl_iim.o
 obj-$(CONFIG_GPIO_LED) += gpio_led.o
diff --git a/drivers/misc/fsl_debug_server.c b/drivers/misc/fsl_debug_server.c
deleted file mode 100644
index 98d9fbe..0000000
--- a/drivers/misc/fsl_debug_server.c
+++ /dev/null
@@ -1,250 +0,0 @@
-/*
- * Copyright (C) 2014 Freescale Semiconductor
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <errno.h>
-#include <asm/io.h>
-#include <asm/system.h>
-
-#include <fsl-mc/fsl_mc.h>
-#include <fsl_debug_server.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-static int debug_server_ver_info_maj, debug_server_ver_info_min;
-
-/**
- * Copying Debug Server firmware to DDR
- */
-static int debug_server_copy_image(const char *title, u64 image_addr,
-				   u32 image_size, u64 debug_server_ram_addr)
-{
-	debug("%s copied to address %p\n", title,
-	      (void *)debug_server_ram_addr);
-	memcpy((void *)debug_server_ram_addr, (void *)image_addr, image_size);
-
-	return 0;
-}
-
-/**
- * Debug Server FIT image parser checks if the image is in FIT
- * format, verifies integrity of the image and calculates
- * raw image address and size values.
- *
- * Returns 0 if success and -1 if any of the above mentioned
- * task fail.
- **/
-int debug_server_parse_firmware_fit_image(const void **raw_image_addr,
-					  size_t *raw_image_size)
-{
-	int format;
-	void *fit_hdr;
-	int node_offset;
-	const void *data;
-	size_t size;
-	const char *uname = "firmware";
-	char *desc;
-	char *debug_server_ver_info;
-	char *debug_server_ver_info_major, *debug_server_ver_info_minor;
-
-	/* Check if the image is in NOR flash */
-#ifdef CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
-	fit_hdr = (void *)CONFIG_SYS_DEBUG_SERVER_FW_ADDR;
-#else
-#error "CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR not defined"
-#endif
-
-	/* Check if Image is in FIT format */
-	format = genimg_get_format(fit_hdr);
-	if (format != IMAGE_FORMAT_FIT) {
-		printf("Debug Server FW: Not a FIT image\n");
-		goto out_error;
-	}
-
-	if (!fit_check_format(fit_hdr)) {
-		printf("Debug Server FW: Bad FIT image format\n");
-		goto out_error;
-	}
-
-	node_offset = fit_image_get_node(fit_hdr, uname);
-	if (node_offset < 0) {
-		printf("Debug Server FW:Can not find %s subimage\n", uname);
-		goto out_error;
-	}
-
-	/* Verify Debug Server firmware image */
-	if (!fit_image_verify(fit_hdr, node_offset)) {
-		printf("Debug Server FW: Bad Debug Server firmware hash");
-		goto out_error;
-	}
-
-	if (fit_get_desc(fit_hdr, node_offset, &desc) < 0) {
-		printf("Debug Server FW: Failed to get FW description");
-		goto out_error;
-	}
-
-	debug_server_ver_info = strstr(desc, "Version");
-	debug_server_ver_info_major = strtok(debug_server_ver_info, ".");
-	debug_server_ver_info_minor = strtok(NULL, ".");
-
-	debug_server_ver_info_maj =
-			simple_strtoul(debug_server_ver_info_major, NULL, 10);
-	debug_server_ver_info_min =
-			simple_strtoul(debug_server_ver_info_minor, NULL, 10);
-
-	/* Debug server version checking */
-	if ((debug_server_ver_info_maj < DEBUG_SERVER_VER_MAJOR) ||
-	    (debug_server_ver_info_min < DEBUG_SERVER_VER_MINOR)) {
-		printf("Debug server FW mismatches the min version required\n");
-		printf("Expected:%d.%d, Got %d.%d\n",
-		       DEBUG_SERVER_VER_MAJOR, DEBUG_SERVER_VER_MINOR,
-		       debug_server_ver_info_maj,
-		       debug_server_ver_info_min);
-		goto out_error;
-	}
-
-	/* Get address and size of raw image */
-	fit_image_get_data(fit_hdr, node_offset, &data, &size);
-
-	*raw_image_addr = data;
-	*raw_image_size = size;
-
-	return 0;
-
-out_error:
-	return -1;
-}
-
-/**
- * Return the actual size of the Debug Server private DRAM block.
- *
- * NOTE: For now this function always returns the minimum required size,
- * However, in the future, the actual size may be obtained from an environment
- * variable.
- */
-unsigned long debug_server_get_dram_block_size(void)
-{
-	return CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE;
-}
-
-int debug_server_init(void)
-{
-	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
-	int error, timeout = CONFIG_SYS_DEBUG_SERVER_TIMEOUT;
-	int debug_server_boot_status;
-	u64 debug_server_ram_addr, debug_server_ram_size;
-	const void *raw_image_addr;
-	size_t raw_image_size = 0;
-
-	debug("debug_server_init called\n");
-	/*
-	 * The Debug Server private DRAM block was already carved at the end of
-	 * DRAM by board_init_f() using CONFIG_SYS_MEM_TOP_HIDE:
-	 */
-	debug_server_ram_size = debug_server_get_dram_block_size();
-	if (gd->bd->bi_dram[1].start)
-		debug_server_ram_addr =
-			gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size;
-	else
-		debug_server_ram_addr =
-			gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size;
-
-#ifdef CONFIG_FSL_MC_ENET
-	debug_server_ram_addr += mc_get_dram_block_size();
-#endif
-
-	error = debug_server_parse_firmware_fit_image(&raw_image_addr,
-							&raw_image_size);
-	if (error != 0)
-		goto out;
-
-	debug("debug server (ram addr = 0x%llx, ram size = 0x%llx)\n",
-	      debug_server_ram_addr, debug_server_ram_size);
-	/*
-	 * Load the Debug Server FW at the beginning of the Debug Server
-	 * private DRAM block:
-	 */
-	debug_server_copy_image("Debug Server Firmware",
-				(u64)raw_image_addr, raw_image_size,
-				debug_server_ram_addr);
-
-	/* flush dcache */
-	flush_dcache_range((unsigned long)debug_server_ram_addr,
-			   (unsigned long)debug_server_ram_addr +
-			   (unsigned long)debug_server_ram_size);
-
-	/*
-	 * Tell SP that the Debug Server FW is about to be launched. Before that
-	 * populate the following:
-	 * 1. Write the size allocated to SP Memory region into Bits {31:16} of
-	 *    SCRATCHRW5.
-	 * 2. Write the start address of the SP memory regions into
-	 *    SCRATCHRW5 (Bits {15:0}, contain most significant bits, Bits
-	 *    {47:32} of the SP Memory Region physical start address
-	 *    (SoC address)) and SCRATCHRW6 (Bits {31:0}).
-	 * 3. To know the Debug Server FW boot status, set bit 0 of SCRATCHRW11
-	 *    to 1. The Debug Server sets this to 0 to indicate a
-	 *    successul boot.
-	 * 4. Wakeup SP by writing 0x1F to VSG GIC reg VIGR2.
-	 */
-
-	/* 512 MB */
-	out_le32(&gur->scratchrw[5 - 1],
-		 (u32)((u64)debug_server_ram_addr >> 32) | (0x000D << 16));
-	out_le32(&gur->scratchrw[6 - 1],
-		 ((u32)debug_server_ram_addr) & 0xFFFFFFFF);
-
-	out_le32(&gur->scratchrw[11 - 1], DEBUG_SERVER_INIT_STATUS);
-	/* Allow the changes to reflect in GUR block */
-	mb();
-
-	/*
-	 * Program VGIC to raise an interrupt to SP
-	 */
-	out_le32(CONFIG_SYS_FSL_SP_VSG_GIC_VIGR2, 0x1F);
-	/* Allow the changes to reflect in VIGR2 */
-	mb();
-
-	dmb();
-	debug("Polling for Debug server to launch ...\n");
-
-	while (1) {
-		debug_server_boot_status = in_le32(&gur->scratchrw[11 - 1]);
-		if (!(debug_server_boot_status & DEBUG_SERVER_INIT_STATUS_MASK))
-			break;
-
-		udelay(1);	/* throttle polling */
-		if (timeout-- <= 0)
-			break;
-	}
-
-	if (timeout <= 0) {
-		printf("Debug Server FW timed out (boot status: 0x%x)\n",
-		       debug_server_boot_status);
-		error = -ETIMEDOUT;
-		goto out;
-	}
-
-	if (debug_server_boot_status & DEBUG_SERVER_INIT_STATUS_MASK) {
-		printf("Debug server FW error'ed out (boot status: 0x%x)\n",
-		       debug_server_boot_status);
-		error = -ENODEV;
-		goto out;
-	}
-
-	printf("Debug server booted\n");
-	printf("Detected firmware %d.%d, (boot status: 0x0%x)\n",
-	       debug_server_ver_info_maj, debug_server_ver_info_min,
-	       debug_server_boot_status);
-
-out:
-	if (error != 0)
-		debug_server_boot_status = -error;
-	else
-		debug_server_boot_status = 0;
-
-	return debug_server_boot_status;
-}
-
diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile
index 344fbe2..316fef4 100644
--- a/drivers/net/fm/Makefile
+++ b/drivers/net/fm/Makefile
@@ -39,4 +39,4 @@ obj-$(CONFIG_PPC_T4080) += t4240.o
 obj-$(CONFIG_PPC_B4420) += b4860.o
 obj-$(CONFIG_PPC_B4860) += b4860.o
 obj-$(CONFIG_LS1043A)	+= ls1043.o
-obj-$(CONFIG_LS1046A)	+= ls1046.o
+obj-$(CONFIG_ARCH_LS1046A)	+= ls1046.o
diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c
index ce4a307..89f0d6a 100644
--- a/drivers/net/fm/fm.c
+++ b/drivers/net/fm/fm.c
@@ -368,8 +368,18 @@ int fm_init_common(int index, struct ccsr_fman *reg)
 	void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
 	int ret = 0;
 
+#ifdef CONFIG_DM_SPI_FLASH
+	struct udevice *new;
+
+	/* speed and mode will be read from DT */
+	ret = spi_flash_probe_bus_cs(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
+				     0, 0, &new);
+
+	ucode_flash = dev_get_uclass_priv(new);
+#else
 	ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
 			CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
+#endif
 	if (!ucode_flash)
 		printf("SF: probe for ucode failed\n");
 	else {