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author | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2015-04-10 14:22:23 +0200 |
---|---|---|
committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2015-04-10 14:22:23 +0200 |
commit | b491d9757d14415edcb1468ed896a704d0f0cfe7 (patch) | |
tree | 477707170048989accc9ea69cd6ac5edae7b1aec /drivers | |
parent | 79d75d752717fb4106ec49abaddbd7744c775a35 (diff) | |
parent | 385a08a60f042061b004642d6b9bb6cfb794ad5a (diff) | |
download | u-boot-imx-b491d9757d14415edcb1468ed896a704d0f0cfe7.zip u-boot-imx-b491d9757d14415edcb1468ed896a704d0f0cfe7.tar.gz u-boot-imx-b491d9757d14415edcb1468ed896a704d0f0cfe7.tar.bz2 |
Merge branch 'u-boot/master'
Diffstat (limited to 'drivers')
34 files changed, 1046 insertions, 387 deletions
diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c index c908fab..88b90e0 100644 --- a/drivers/block/ahci.c +++ b/drivers/block/ahci.c @@ -785,7 +785,7 @@ static int ata_scsiop_read_write(ccb *pccb, u8 is_write) /* Read/Write from ahci */ if (ahci_device_data_io(pccb->target, (u8 *) &fis, sizeof(fis), - user_buffer, user_buffer_size, + user_buffer, transfer_size, is_write)) { debug("scsi_ahci: SCSI %s10 command failure.\n", is_write ? "WRITE" : "READ"); diff --git a/drivers/dfu/dfu_nand.c b/drivers/dfu/dfu_nand.c index f9ee189..a975492 100644 --- a/drivers/dfu/dfu_nand.c +++ b/drivers/dfu/dfu_nand.c @@ -64,7 +64,7 @@ static int nand_block_op(enum dfu_op op, struct dfu_entity *dfu, return ret; /* then write */ ret = nand_write_skip_bad(nand, start, &count, &actual, - lim, buf, 0); + lim, buf, WITH_WR_VERIFY); } if (ret != 0) { diff --git a/drivers/mmc/bcm2835_sdhci.c b/drivers/mmc/bcm2835_sdhci.c index 92f7d89..4ec2968 100644 --- a/drivers/mmc/bcm2835_sdhci.c +++ b/drivers/mmc/bcm2835_sdhci.c @@ -39,8 +39,8 @@ #include <common.h> #include <malloc.h> #include <sdhci.h> -#include <asm/arch/timer.h> -#include <asm/arch-bcm2835/sdhci.h> +#include <mach/timer.h> +#include <mach/sdhci.h> /* 400KHz is max freq for card ID etc. Use that as min */ #define MIN_FREQ 400000 diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c index b16e3aa..a2016e7 100644 --- a/drivers/mtd/nand/atmel_nand.c +++ b/drivers/mtd/nand/atmel_nand.c @@ -1456,6 +1456,9 @@ int board_nand_init(struct nand_chip *nand) nand->dev_ready = at91_nand_wait_ready; #endif nand->chip_delay = 20; +#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT + nand->bbt_options |= NAND_BBT_USE_FLASH; +#endif #ifdef CONFIG_ATMEL_NAND_HWECC #ifdef CONFIG_ATMEL_NAND_HW_PMECC @@ -1522,6 +1525,9 @@ int atmel_nand_chip_init(int devnum, ulong base_addr) nand->dev_ready = at91_nand_ready; #endif nand->chip_delay = 75; +#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT + nand->bbt_options |= NAND_BBT_USE_FLASH; +#endif ret = nand_scan_ident(mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL); if (ret) diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c index 41689b5..a397074 100644 --- a/drivers/mtd/nand/davinci_nand.c +++ b/drivers/mtd/nand/davinci_nand.c @@ -405,18 +405,6 @@ static int nand_davinci_write_page(struct mtd_info *mtd, struct nand_chip *chip, goto err; } -#ifdef CONFIG_MTD_NAND_VERIFY_WRITE - /* Send command to read back the data */ - chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); - - if (chip->verify_buf(mtd, buf, mtd->writesize)) { - ret = -EIO; - goto err; - } - - /* Make sure the next page prog is preceded by a status read */ - chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); -#endif err: /* restore ECC layout */ if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) { diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c index 3372b64..e85832d 100644 --- a/drivers/mtd/nand/fsl_elbc_nand.c +++ b/drivers/mtd/nand/fsl_elbc_nand.c @@ -561,41 +561,6 @@ static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len) len, avail); } -#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) -/* - * Verify buffer against the FCM Controller Data Buffer - */ -static int fsl_elbc_verify_buf(struct mtd_info *mtd, - const u_char *buf, int len) -{ - struct nand_chip *chip = mtd->priv; - struct fsl_elbc_mtd *priv = chip->priv; - struct fsl_elbc_ctrl *ctrl = priv->ctrl; - int i; - - if (len < 0) { - printf("write_buf of %d bytes", len); - return -EINVAL; - } - - if ((unsigned int)len > ctrl->read_bytes - ctrl->index) { - printf("verify_buf beyond end of buffer " - "(%d requested, %u available)\n", - len, ctrl->read_bytes - ctrl->index); - - ctrl->index = ctrl->read_bytes; - return -EINVAL; - } - - for (i = 0; i < len; i++) - if (in_8(&ctrl->addr[ctrl->index + i]) != buf[i]) - break; - - ctrl->index += len; - return i == len && ctrl->status == LTESR_CC ? 0 : -EIO; -} -#endif - /* This function is called after Program and Erase Operations to * check for success or failure. */ @@ -727,9 +692,6 @@ static int fsl_elbc_chip_init(int devnum, u8 *addr) nand->read_byte = fsl_elbc_read_byte; nand->write_buf = fsl_elbc_write_buf; nand->read_buf = fsl_elbc_read_buf; -#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) - nand->verify_buf = fsl_elbc_verify_buf; -#endif nand->select_chip = fsl_elbc_select_chip; nand->cmdfunc = fsl_elbc_cmdfunc; nand->waitfunc = fsl_elbc_wait; diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c index b283eae..7903eeb 100644 --- a/drivers/mtd/nand/fsl_ifc_nand.c +++ b/drivers/mtd/nand/fsl_ifc_nand.c @@ -683,41 +683,6 @@ static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len) __func__, len, avail); } -#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) -/* - * Verify buffer against the IFC Controller Data Buffer - */ -static int fsl_ifc_verify_buf(struct mtd_info *mtd, - const u_char *buf, int len) -{ - struct nand_chip *chip = mtd->priv; - struct fsl_ifc_mtd *priv = chip->priv; - struct fsl_ifc_ctrl *ctrl = priv->ctrl; - int i; - - if (len < 0) { - printf("%s of %d bytes", __func__, len); - return -EINVAL; - } - - if ((unsigned int)len > ctrl->read_bytes - ctrl->index) { - printf("%s beyond end of buffer " - "(%d requested, %u available)\n", - __func__, len, ctrl->read_bytes - ctrl->index); - - ctrl->index = ctrl->read_bytes; - return -EINVAL; - } - - for (i = 0; i < len; i++) - if (in_8(&ctrl->addr[ctrl->index + i]) != buf[i]) - break; - - ctrl->index += len; - return i == len && ctrl->status == IFC_NAND_EVTER_STAT_OPC ? 0 : -EIO; -} -#endif - /* This function is called after Program and Erase Operations to * check for success or failure. */ @@ -940,9 +905,6 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr) nand->write_buf = fsl_ifc_write_buf; nand->read_buf = fsl_ifc_read_buf; -#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) - nand->verify_buf = fsl_ifc_verify_buf; -#endif nand->select_chip = fsl_ifc_select_chip; nand->cmdfunc = fsl_ifc_cmdfunc; nand->waitfunc = fsl_ifc_wait; diff --git a/drivers/mtd/nand/fsl_upm.c b/drivers/mtd/nand/fsl_upm.c index 65ce98a..5426c32 100644 --- a/drivers/mtd/nand/fsl_upm.c +++ b/drivers/mtd/nand/fsl_upm.c @@ -153,21 +153,6 @@ static void upm_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) buf[i] = in_8(chip->IO_ADDR_R); } -#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) -static int upm_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) -{ - int i; - struct nand_chip *chip = mtd->priv; - - for (i = 0; i < len; i++) { - if (buf[i] != in_8(chip->IO_ADDR_R)) - return -EFAULT; - } - - return 0; -} -#endif - static int nand_dev_ready(struct mtd_info *mtd) { struct nand_chip *chip = mtd->priv; @@ -193,9 +178,6 @@ int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun) chip->read_byte = upm_nand_read_byte; chip->read_buf = upm_nand_read_buf; chip->write_buf = upm_nand_write_buf; -#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) - chip->verify_buf = upm_nand_verify_buf; -#endif if (fun->dev_ready) chip->dev_ready = nand_dev_ready; diff --git a/drivers/mtd/nand/mpc5121_nfc.c b/drivers/mtd/nand/mpc5121_nfc.c index 7233bfc..e621c36 100644 --- a/drivers/mtd/nand/mpc5121_nfc.c +++ b/drivers/mtd/nand/mpc5121_nfc.c @@ -459,29 +459,6 @@ static void mpc5121_nfc_write_buf(struct mtd_info *mtd, mpc5121_nfc_buf_copy(mtd, (u_char *) buf, len, 1); } -#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) -/* Compare buffer with NAND flash */ -static int mpc5121_nfc_verify_buf(struct mtd_info *mtd, - const u_char * buf, int len) -{ - u_char tmp[256]; - uint bsize; - - while (len) { - bsize = min(len, 256); - mpc5121_nfc_read_buf(mtd, tmp, bsize); - - if (memcmp(buf, tmp, bsize)) - return 1; - - buf += bsize; - len -= bsize; - } - - return 0; -} -#endif - /* Read byte from NFC buffers */ static u8 mpc5121_nfc_read_byte(struct mtd_info *mtd) { @@ -609,9 +586,6 @@ int board_nand_init(struct nand_chip *chip) chip->read_word = mpc5121_nfc_read_word; chip->read_buf = mpc5121_nfc_read_buf; chip->write_buf = mpc5121_nfc_write_buf; -#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) - chip->verify_buf = mpc5121_nfc_verify_buf; -#endif chip->select_chip = mpc5121_nfc_select_chip; chip->bbt_options = NAND_BBT_USE_FLASH; chip->ecc.mode = NAND_ECC_SOFT; diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c index 2e5b5b9..f12b07e 100644 --- a/drivers/mtd/nand/mxc_nand.c +++ b/drivers/mtd/nand/mxc_nand.c @@ -949,34 +949,6 @@ static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) host->col_addr = col; } -#ifdef __UBOOT__ -#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) -/* - * Used by the upper layer to verify the data in NAND Flash - * with the data in the buf. - */ -static int mxc_nand_verify_buf(struct mtd_info *mtd, - const u_char *buf, int len) -{ - u_char tmp[256]; - uint bsize; - - while (len) { - bsize = min(len, 256); - mxc_nand_read_buf(mtd, tmp, bsize); - - if (memcmp(buf, tmp, bsize)) - return 1; - - buf += bsize; - len -= bsize; - } - - return 0; -} -#endif -#endif - /* * This function is used by upper layer for select and * deselect of the NAND chip @@ -1207,11 +1179,6 @@ int board_nand_init(struct nand_chip *this) this->read_word = mxc_nand_read_word; this->write_buf = mxc_nand_write_buf; this->read_buf = mxc_nand_read_buf; -#ifdef __UBOOT__ -#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) - this->verify_buf = mxc_nand_verify_buf; -#endif -#endif host->regs = (struct mxc_nand_regs __iomem *)CONFIG_MXC_NAND_REGS_BASE; #ifdef MXC_NFC_V3_2 diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c index 7a064ab..2d2b938 100644 --- a/drivers/mtd/nand/mxs_nand.c +++ b/drivers/mtd/nand/mxs_nand.c @@ -453,7 +453,7 @@ static void mxs_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int length) d->cmd.data = MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ | MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_DEC_SEM | - MXS_DMA_DESC_WAIT4END | (4 << MXS_DMA_DESC_PIO_WORDS_OFFSET); + MXS_DMA_DESC_WAIT4END | (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET); d->cmd.address = 0; @@ -510,7 +510,7 @@ static void mxs_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, d->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ | MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END | - (4 << MXS_DMA_DESC_PIO_WORDS_OFFSET) | + (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) | (length << MXS_DMA_DESC_BYTES_OFFSET); d->cmd.address = (dma_addr_t)nand_info->data_buf; diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 6db6566..c0e381a 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -361,51 +361,6 @@ void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) ioread8_rep(chip->IO_ADDR_R, buf, len); } -#ifdef __UBOOT__ -#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) -/** - * nand_verify_buf - [DEFAULT] Verify chip data against buffer - * @mtd: MTD device structure - * @buf: buffer containing the data to compare - * @len: number of bytes to compare - * - * Default verify function for 8bit buswidth. - */ -static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len) -{ - int i; - struct nand_chip *chip = mtd->priv; - - for (i = 0; i < len; i++) - if (buf[i] != readb(chip->IO_ADDR_R)) - return -EFAULT; - return 0; -} - -/** - * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer - * @mtd: MTD device structure - * @buf: buffer containing the data to compare - * @len: number of bytes to compare - * - * Default verify function for 16bit buswidth. - */ -static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) -{ - int i; - struct nand_chip *chip = mtd->priv; - u16 *p = (u16 *) buf; - len >>= 1; - - for (i = 0; i < len; i++) - if (p[i] != readw(chip->IO_ADDR_R)) - return -EFAULT; - - return 0; -} -#endif -#endif - /** * nand_write_buf16 - [DEFAULT] write buffer to chip * @mtd: MTD device structure @@ -2435,20 +2390,6 @@ static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, status = chip->waitfunc(mtd, chip); } - -#ifdef __UBOOT__ -#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) - /* Send command to read back the data */ - chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); - - if (chip->verify_buf(mtd, buf, mtd->writesize)) - return -EIO; - - /* Make sure the next page prog is preceded by a status read */ - chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); -#endif -#endif - return 0; } @@ -3139,12 +3080,6 @@ static void nand_set_defaults(struct nand_chip *chip, int busw) chip->read_buf = busw ? nand_read_buf16 : nand_read_buf; if (!chip->scan_bbt) chip->scan_bbt = nand_default_bbt; -#ifdef __UBOOT__ -#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) - if (!chip->verify_buf) - chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf; -#endif -#endif if (!chip->controller) { chip->controller = &chip->hwcontrol; diff --git a/drivers/mtd/nand/nand_util.c b/drivers/mtd/nand/nand_util.c index afdd160..12dd26a 100644 --- a/drivers/mtd/nand/nand_util.c +++ b/drivers/mtd/nand/nand_util.c @@ -464,6 +464,87 @@ static size_t drop_ffs(const nand_info_t *nand, const u_char *buf, #endif /** + * nand_verify_page_oob: + * + * Verify a page of NAND flash, including the OOB. + * Reads page of NAND and verifies the contents and OOB against the + * values in ops. + * + * @param nand NAND device + * @param ops MTD operations, including data to verify + * @param ofs offset in flash + * @return 0 in case of success + */ +int nand_verify_page_oob(nand_info_t *nand, struct mtd_oob_ops *ops, loff_t ofs) +{ + int rval; + struct mtd_oob_ops vops; + size_t verlen = nand->writesize + nand->oobsize; + + memcpy(&vops, ops, sizeof(vops)); + + vops.datbuf = malloc(verlen); + + if (!vops.datbuf) + return -ENOMEM; + + vops.oobbuf = vops.datbuf + nand->writesize; + + rval = mtd_read_oob(nand, ofs, &vops); + if (!rval) + rval = memcmp(ops->datbuf, vops.datbuf, vops.len); + if (!rval) + rval = memcmp(ops->oobbuf, vops.oobbuf, vops.ooblen); + + free(vops.datbuf); + + return rval ? -EIO : 0; +} + +/** + * nand_verify: + * + * Verify a region of NAND flash. + * Reads NAND in page-sized chunks and verifies the contents against + * the contents of a buffer. The offset into the NAND must be + * page-aligned, and the function doesn't handle skipping bad blocks. + * + * @param nand NAND device + * @param ofs offset in flash + * @param len buffer length + * @param buf buffer to read from + * @return 0 in case of success + */ +int nand_verify(nand_info_t *nand, loff_t ofs, size_t len, u_char *buf) +{ + int rval = 0; + size_t verofs; + size_t verlen = nand->writesize; + uint8_t *verbuf = malloc(verlen); + + if (!verbuf) + return -ENOMEM; + + /* Read the NAND back in page-size groups to limit malloc size */ + for (verofs = ofs; verofs < ofs + len; + verofs += verlen, buf += verlen) { + verlen = min(nand->writesize, (uint32_t)(ofs + len - verofs)); + rval = nand_read(nand, verofs, &verlen, verbuf); + if (!rval || (rval == -EUCLEAN)) + rval = memcmp(buf, verbuf, verlen); + + if (rval) + break; + } + + free(verbuf); + + return rval ? -EIO : 0; +} + + + +/** * nand_write_skip_bad: * * Write image to NAND flash. @@ -499,24 +580,7 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, if (actual) *actual = 0; -#ifdef CONFIG_CMD_NAND_YAFFS - if (flags & WITH_YAFFS_OOB) { - if (flags & ~WITH_YAFFS_OOB) - return -EINVAL; - - int pages; - pages = nand->erasesize / nand->writesize; - blocksize = (pages * nand->oobsize) + nand->erasesize; - if (*length % (nand->writesize + nand->oobsize)) { - printf("Attempt to write incomplete page" - " in yaffs mode\n"); - return -EINVAL; - } - } else -#endif - { - blocksize = nand->erasesize; - } + blocksize = nand->erasesize; /* * nand_write() handles unaligned, partial page writes. @@ -554,6 +618,10 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, if (!need_skip && !(flags & WITH_DROP_FFS)) { rval = nand_write(nand, offset, length, buffer); + + if ((flags & WITH_WR_VERIFY) && !rval) + rval = nand_verify(nand, offset, *length, buffer); + if (rval == 0) return 0; @@ -581,48 +649,22 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, else write_size = blocksize - block_offset; -#ifdef CONFIG_CMD_NAND_YAFFS - if (flags & WITH_YAFFS_OOB) { - int page, pages; - size_t pagesize = nand->writesize; - size_t pagesize_oob = pagesize + nand->oobsize; - struct mtd_oob_ops ops; - - ops.len = pagesize; - ops.ooblen = nand->oobsize; - ops.mode = MTD_OPS_AUTO_OOB; - ops.ooboffs = 0; - - pages = write_size / pagesize_oob; - for (page = 0; page < pages; page++) { - WATCHDOG_RESET(); - - ops.datbuf = p_buffer; - ops.oobbuf = ops.datbuf + pagesize; - - rval = mtd_write_oob(nand, offset, &ops); - if (rval != 0) - break; - - offset += pagesize; - p_buffer += pagesize_oob; - } - } - else -#endif - { - truncated_write_size = write_size; + truncated_write_size = write_size; #ifdef CONFIG_CMD_NAND_TRIMFFS - if (flags & WITH_DROP_FFS) - truncated_write_size = drop_ffs(nand, p_buffer, - &write_size); + if (flags & WITH_DROP_FFS) + truncated_write_size = drop_ffs(nand, p_buffer, + &write_size); #endif - rval = nand_write(nand, offset, &truncated_write_size, - p_buffer); - offset += write_size; - p_buffer += write_size; - } + rval = nand_write(nand, offset, &truncated_write_size, + p_buffer); + + if ((flags & WITH_WR_VERIFY) && !rval) + rval = nand_verify(nand, offset, + truncated_write_size, p_buffer); + + offset += write_size; + p_buffer += write_size; if (rval != 0) { printf("NAND write to offset %llx failed %d\n", diff --git a/drivers/mtd/nand/ndfc.c b/drivers/mtd/nand/ndfc.c index 2659595..8a68cb0 100644 --- a/drivers/mtd/nand/ndfc.c +++ b/drivers/mtd/nand/ndfc.c @@ -118,21 +118,6 @@ static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len out_be32((u32 *)(base + NDFC_DATA), *p++); } -#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) -static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len) -{ - struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) this->IO_ADDR_W & 0xffffff00; - uint32_t *p = (uint32_t *) buf; - - for (; len > 0; len -= 4) - if (*p++ != in_be32((u32 *)(base + NDFC_DATA))) - return -1; - - return 0; -} -#endif - /* * Read a byte from the NDFC. */ @@ -207,9 +192,6 @@ int board_nand_init(struct nand_chip *nand) #endif nand->write_buf = ndfc_write_buf; -#if defined(CONFIG_MTD_NAND_VERIFY_WRITE) - nand->verify_buf = ndfc_verify_buf; -#endif nand->read_byte = ndfc_read_byte; chip++; diff --git a/drivers/mtd/nand/vf610_nfc.c b/drivers/mtd/nand/vf610_nfc.c index 928d58b..d98dd28 100644 --- a/drivers/mtd/nand/vf610_nfc.c +++ b/drivers/mtd/nand/vf610_nfc.c @@ -146,6 +146,7 @@ struct vf610_nfc { void __iomem *regs; uint column; int spareonly; + int page_sz; int page; /* Status and ID are in alternate locations. */ int alt_buf; @@ -329,6 +330,11 @@ static void vf610_nfc_addr_cycle(struct mtd_info *mtd, int column, int page) ROW_ADDR_SHIFT, page); } +static inline void vf610_nfc_transfer_size(void __iomem *regbase, int size) +{ + __raw_writel(size, regbase + NFC_SECTOR_SIZE); +} + /* Send command to NAND chip */ static void vf610_nfc_command(struct mtd_info *mtd, unsigned command, int column, int page) @@ -342,12 +348,14 @@ static void vf610_nfc_command(struct mtd_info *mtd, unsigned command, switch (command) { case NAND_CMD_PAGEPROG: nfc->page = -1; + vf610_nfc_transfer_size(nfc->regs, nfc->page_sz); vf610_nfc_send_commands(nfc->regs, NAND_CMD_SEQIN, command, PROGRAM_PAGE_CMD_CODE); vf610_nfc_addr_cycle(mtd, column, page); break; case NAND_CMD_RESET: + vf610_nfc_transfer_size(nfc->regs, 0); vf610_nfc_send_command(nfc->regs, command, RESET_CMD_CODE); break; /* @@ -363,14 +371,15 @@ static void vf610_nfc_command(struct mtd_info *mtd, unsigned command, if (nfc->page == page) return; nfc->page = page; + vf610_nfc_transfer_size(nfc->regs, nfc->page_sz); vf610_nfc_send_commands(nfc->regs, NAND_CMD_READ0, NAND_CMD_READSTART, READ_PAGE_CMD_CODE); vf610_nfc_addr_cycle(mtd, column, page); break; case NAND_CMD_ERASE1: - if (nfc->page == page) - nfc->page = -1; + nfc->page = -1; + vf610_nfc_transfer_size(nfc->regs, 0); vf610_nfc_send_commands(nfc->regs, command, NAND_CMD_ERASE2, ERASE_CMD_CODE); vf610_nfc_addr_cycle(mtd, column, page); @@ -378,11 +387,13 @@ static void vf610_nfc_command(struct mtd_info *mtd, unsigned command, case NAND_CMD_READID: nfc->alt_buf = ALT_BUF_ID; + vf610_nfc_transfer_size(nfc->regs, 0); vf610_nfc_send_command(nfc->regs, command, READ_ID_CMD_CODE); break; case NAND_CMD_STATUS: nfc->alt_buf = ALT_BUF_STAT; + vf610_nfc_transfer_size(nfc->regs, 0); vf610_nfc_send_command(nfc->regs, command, STATUS_READ_CMD_CODE); break; @@ -580,7 +591,6 @@ static int vf610_nfc_nand_init(int devnum, void __iomem *addr) struct nand_chip *chip; struct vf610_nfc *nfc; int err = 0; - int page_sz; struct vf610_nfc_config cfg = { .hardware_ecc = 1, #ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT @@ -634,9 +644,8 @@ static int vf610_nfc_nand_init(int devnum, void __iomem *addr) chip->bbt_td = &bbt_main_descr; chip->bbt_md = &bbt_mirror_descr; - page_sz = PAGE_2K + OOB_64; - page_sz += cfg.width == 16 ? 1 : 0; - vf610_nfc_write(mtd, NFC_SECTOR_SIZE, page_sz); + nfc->page_sz = PAGE_2K + OOB_64; + nfc->page_sz += cfg.width == 16 ? 1 : 0; /* Set configuration register. */ vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_ADDR_AUTO_INCR_BIT); @@ -665,16 +674,15 @@ static int vf610_nfc_nand_init(int devnum, void __iomem *addr) chip->ecc.mode = NAND_ECC_SOFT; /* default */ - page_sz = mtd->writesize + mtd->oobsize; + nfc->page_sz = mtd->writesize + mtd->oobsize; /* Single buffer only, max 256 OOB minus ECC status */ - if (page_sz > PAGE_2K + 256 - 8) { + if (nfc->page_sz > PAGE_2K + 256 - 8) { dev_err(nfc->dev, "Unsupported flash size\n"); err = -ENXIO; goto error; } - page_sz += cfg.width == 16 ? 1 : 0; - vf610_nfc_write(mtd, NFC_SECTOR_SIZE, page_sz); + nfc->page_sz += cfg.width == 16 ? 1 : 0; if (cfg.hardware_ecc) { if (mtd->writesize != PAGE_2K && mtd->oobsize < 64) { diff --git a/drivers/net/Makefile b/drivers/net/Makefile index b8b0803..3ff86b7 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -46,6 +46,7 @@ obj-$(CONFIG_DRIVER_NE2000) += ne2000.o ne2000_base.o obj-$(CONFIG_DRIVER_AX88796L) += ax88796.o ne2000_base.o obj-$(CONFIG_NETCONSOLE) += netconsole.o obj-$(CONFIG_NS8382X) += ns8382x.o +obj-$(CONFIG_PCH_GBE) += pch_gbe.o obj-$(CONFIG_PCNET) += pcnet.o obj-$(CONFIG_RTL8139) += rtl8139.o obj-$(CONFIG_RTL8169) += rtl8169.o diff --git a/drivers/net/e1000.h b/drivers/net/e1000.h index 6d110eb..f3b77b1 100644 --- a/drivers/net/e1000.h +++ b/drivers/net/e1000.h @@ -430,12 +430,11 @@ struct e1000_phy_stats { #define ENET_HEADER_SIZE 14 #define MAXIMUM_ETHERNET_FRAME_SIZE 1518 /* With FCS */ #define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */ -#define ETHERNET_FCS_SIZE 4 #define MAXIMUM_ETHERNET_PACKET_SIZE \ - (MAXIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE) + (MAXIMUM_ETHERNET_FRAME_SIZE - ETH_FCS_LEN) #define MINIMUM_ETHERNET_PACKET_SIZE \ - (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE) -#define CRC_LENGTH ETHERNET_FCS_SIZE + (MINIMUM_ETHERNET_FRAME_SIZE - ETH_FCS_LEN) +#define CRC_LENGTH ETH_FCS_LEN #define MAX_JUMBO_FRAME_SIZE 0x3F00 /* 802.1q VLAN Packet Sizes */ diff --git a/drivers/net/pch_gbe.c b/drivers/net/pch_gbe.c new file mode 100644 index 0000000..976848d --- /dev/null +++ b/drivers/net/pch_gbe.c @@ -0,0 +1,466 @@ +/* + * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> + * + * Intel Platform Controller Hub EG20T (codename Topcliff) GMAC Driver + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <asm/io.h> +#include <pci.h> +#include <malloc.h> +#include <miiphy.h> +#include "pch_gbe.h" + +#if !defined(CONFIG_PHYLIB) +# error "PCH Gigabit Ethernet driver requires PHYLIB - missing CONFIG_PHYLIB" +#endif + +static struct pci_device_id supported[] = { + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_GBE }, + { } +}; + +static void pch_gbe_mac_read(struct pch_gbe_regs *mac_regs, u8 *addr) +{ + u32 macid_hi, macid_lo; + + macid_hi = readl(&mac_regs->mac_adr[0].high); + macid_lo = readl(&mac_regs->mac_adr[0].low) & 0xffff; + debug("pch_gbe: macid_hi %#x macid_lo %#x\n", macid_hi, macid_lo); + + addr[0] = (u8)(macid_hi & 0xff); + addr[1] = (u8)((macid_hi >> 8) & 0xff); + addr[2] = (u8)((macid_hi >> 16) & 0xff); + addr[3] = (u8)((macid_hi >> 24) & 0xff); + addr[4] = (u8)(macid_lo & 0xff); + addr[5] = (u8)((macid_lo >> 8) & 0xff); +} + +static int pch_gbe_mac_write(struct pch_gbe_regs *mac_regs, u8 *addr) +{ + u32 macid_hi, macid_lo; + ulong start; + + macid_hi = addr[0] + (addr[1] << 8) + (addr[2] << 16) + (addr[3] << 24); + macid_lo = addr[4] + (addr[5] << 8); + + writel(macid_hi, &mac_regs->mac_adr[0].high); + writel(macid_lo, &mac_regs->mac_adr[0].low); + writel(0xfffe, &mac_regs->addr_mask); + + start = get_timer(0); + while (get_timer(start) < PCH_GBE_TIMEOUT) { + if (!(readl(&mac_regs->addr_mask) & PCH_GBE_BUSY)) + return 0; + + udelay(10); + } + + return -ETIME; +} + +static int pch_gbe_reset(struct eth_device *dev) +{ + struct pch_gbe_priv *priv = dev->priv; + struct pch_gbe_regs *mac_regs = priv->mac_regs; + ulong start; + + priv->rx_idx = 0; + priv->tx_idx = 0; + + writel(PCH_GBE_ALL_RST, &mac_regs->reset); + + /* + * Configure the MAC to RGMII mode after reset + * + * For some unknown reason, we must do the configuration here right + * after resetting the whole MAC, otherwise the reset bit in the RESET + * register will never be cleared by the hardware. And there is another + * way of having the same magic, that is to configure the MODE register + * to have the MAC work in MII/GMII mode, which is how current Linux + * pch_gbe driver does. Since anyway we need program the MAC to RGMII + * mode in the driver, we just do it here. + * + * Note: this behavior is not documented in the hardware manual. + */ + writel(PCH_GBE_RGMII_MODE_RGMII | PCH_GBE_CHIP_TYPE_INTERNAL, + &mac_regs->rgmii_ctrl); + + start = get_timer(0); + while (get_timer(start) < PCH_GBE_TIMEOUT) { + if (!(readl(&mac_regs->reset) & PCH_GBE_ALL_RST)) { + /* + * Soft reset clears hardware MAC address registers, + * so we have to reload MAC address here in order to + * make linux pch_gbe driver happy. + */ + return pch_gbe_mac_write(mac_regs, dev->enetaddr); + } + + udelay(10); + } + + debug("pch_gbe: reset timeout\n"); + return -ETIME; +} + +static void pch_gbe_rx_descs_init(struct eth_device *dev) +{ + struct pch_gbe_priv *priv = dev->priv; + struct pch_gbe_regs *mac_regs = priv->mac_regs; + struct pch_gbe_rx_desc *rx_desc = &priv->rx_desc[0]; + int i; + + memset(rx_desc, 0, sizeof(struct pch_gbe_rx_desc) * PCH_GBE_DESC_NUM); + for (i = 0; i < PCH_GBE_DESC_NUM; i++) + rx_desc->buffer_addr = pci_phys_to_mem(priv->bdf, + (u32)(priv->rx_buff[i])); + + writel(pci_phys_to_mem(priv->bdf, (u32)rx_desc), + &mac_regs->rx_dsc_base); + writel(sizeof(struct pch_gbe_rx_desc) * (PCH_GBE_DESC_NUM - 1), + &mac_regs->rx_dsc_size); + + writel(pci_phys_to_mem(priv->bdf, (u32)(rx_desc + 1)), + &mac_regs->rx_dsc_sw_p); +} + +static void pch_gbe_tx_descs_init(struct eth_device *dev) +{ + struct pch_gbe_priv *priv = dev->priv; + struct pch_gbe_regs *mac_regs = priv->mac_regs; + struct pch_gbe_tx_desc *tx_desc = &priv->tx_desc[0]; + + memset(tx_desc, 0, sizeof(struct pch_gbe_tx_desc) * PCH_GBE_DESC_NUM); + + writel(pci_phys_to_mem(priv->bdf, (u32)tx_desc), + &mac_regs->tx_dsc_base); + writel(sizeof(struct pch_gbe_tx_desc) * (PCH_GBE_DESC_NUM - 1), + &mac_regs->tx_dsc_size); + writel(pci_phys_to_mem(priv->bdf, (u32)(tx_desc + 1)), + &mac_regs->tx_dsc_sw_p); +} + +static void pch_gbe_adjust_link(struct pch_gbe_regs *mac_regs, + struct phy_device *phydev) +{ + if (!phydev->link) { + printf("%s: No link.\n", phydev->dev->name); + return; + } + + clrbits_le32(&mac_regs->rgmii_ctrl, + PCH_GBE_RGMII_RATE_2_5M | PCH_GBE_CRS_SEL); + clrbits_le32(&mac_regs->mode, + PCH_GBE_MODE_GMII_ETHER | PCH_GBE_MODE_FULL_DUPLEX); + + switch (phydev->speed) { + case 1000: + setbits_le32(&mac_regs->rgmii_ctrl, PCH_GBE_RGMII_RATE_125M); + setbits_le32(&mac_regs->mode, PCH_GBE_MODE_GMII_ETHER); + break; + case 100: + setbits_le32(&mac_regs->rgmii_ctrl, PCH_GBE_RGMII_RATE_25M); + setbits_le32(&mac_regs->mode, PCH_GBE_MODE_MII_ETHER); + break; + case 10: + setbits_le32(&mac_regs->rgmii_ctrl, PCH_GBE_RGMII_RATE_2_5M); + setbits_le32(&mac_regs->mode, PCH_GBE_MODE_MII_ETHER); + break; + } + + if (phydev->duplex) { + setbits_le32(&mac_regs->rgmii_ctrl, PCH_GBE_CRS_SEL); + setbits_le32(&mac_regs->mode, PCH_GBE_MODE_FULL_DUPLEX); + } + + printf("Speed: %d, %s duplex\n", phydev->speed, + (phydev->duplex) ? "full" : "half"); + + return; +} + +static int pch_gbe_init(struct eth_device *dev, bd_t *bis) +{ + struct pch_gbe_priv *priv = dev->priv; + struct pch_gbe_regs *mac_regs = priv->mac_regs; + + if (pch_gbe_reset(dev)) + return -1; + + pch_gbe_rx_descs_init(dev); + pch_gbe_tx_descs_init(dev); + + /* Enable frame bursting */ + writel(PCH_GBE_MODE_FR_BST, &mac_regs->mode); + /* Disable TCP/IP accelerator */ + writel(PCH_GBE_RX_TCPIPACC_OFF, &mac_regs->tcpip_acc); + /* Disable RX flow control */ + writel(0, &mac_regs->rx_fctrl); + /* Configure RX/TX mode */ + writel(PCH_GBE_RH_ALM_EMP_16 | PCH_GBE_RH_ALM_FULL_16 | + PCH_GBE_RH_RD_TRG_32, &mac_regs->rx_mode); + writel(PCH_GBE_TM_TH_TX_STRT_32 | PCH_GBE_TM_TH_ALM_EMP_16 | + PCH_GBE_TM_TH_ALM_FULL_32 | PCH_GBE_TM_ST_AND_FD | + PCH_GBE_TM_SHORT_PKT, &mac_regs->tx_mode); + + /* Start up the PHY */ + if (phy_startup(priv->phydev)) { + printf("Could not initialize PHY %s\n", + priv->phydev->dev->name); + return -1; + } + + pch_gbe_adjust_link(mac_regs, priv->phydev); + + if (!priv->phydev->link) + return -1; + + /* Enable TX & RX */ + writel(PCH_GBE_RX_DMA_EN | PCH_GBE_TX_DMA_EN, &mac_regs->dma_ctrl); + writel(PCH_GBE_MRE_MAC_RX_EN, &mac_regs->mac_rx_en); + + return 0; +} + +static void pch_gbe_halt(struct eth_device *dev) +{ + struct pch_gbe_priv *priv = dev->priv; + + pch_gbe_reset(dev); + + phy_shutdown(priv->phydev); +} + +static int pch_gbe_send(struct eth_device *dev, void *packet, int length) +{ + struct pch_gbe_priv *priv = dev->priv; + struct pch_gbe_regs *mac_regs = priv->mac_regs; + struct pch_gbe_tx_desc *tx_head, *tx_desc; + u16 frame_ctrl = 0; + u32 int_st; + ulong start; + + tx_head = &priv->tx_desc[0]; + tx_desc = &priv->tx_desc[priv->tx_idx]; + + if (length < 64) + frame_ctrl |= PCH_GBE_TXD_CTRL_APAD; + + tx_desc->buffer_addr = pci_phys_to_mem(priv->bdf, (u32)packet); + tx_desc->length = length; + tx_desc->tx_words_eob = length + 3; + tx_desc->tx_frame_ctrl = frame_ctrl; + tx_desc->dma_status = 0; + tx_desc->gbec_status = 0; + + /* Test the wrap-around condition */ + if (++priv->tx_idx >= PCH_GBE_DESC_NUM) + priv->tx_idx = 0; + + writel(pci_phys_to_mem(priv->bdf, (u32)(tx_head + priv->tx_idx)), + &mac_regs->tx_dsc_sw_p); + + start = get_timer(0); + while (get_timer(start) < PCH_GBE_TIMEOUT) { + int_st = readl(&mac_regs->int_st); + if (int_st & PCH_GBE_INT_TX_CMPLT) + return 0; + + udelay(10); + } + + debug("pch_gbe: sent failed\n"); + return -ETIME; +} + +static int pch_gbe_recv(struct eth_device *dev) +{ + struct pch_gbe_priv *priv = dev->priv; + struct pch_gbe_regs *mac_regs = priv->mac_regs; + struct pch_gbe_rx_desc *rx_head, *rx_desc; + u32 hw_desc, buffer_addr, length; + int rx_swp; + + rx_head = &priv->rx_desc[0]; + rx_desc = &priv->rx_desc[priv->rx_idx]; + + readl(&mac_regs->int_st); + hw_desc = readl(&mac_regs->rx_dsc_hw_p_hld); + + /* Just return if not receiving any packet */ + if ((u32)rx_desc == hw_desc) + return 0; + + buffer_addr = pci_mem_to_phys(priv->bdf, rx_desc->buffer_addr); + length = rx_desc->rx_words_eob - 3 - ETH_FCS_LEN; + NetReceive((uchar *)buffer_addr, length); + + /* Test the wrap-around condition */ + if (++priv->rx_idx >= PCH_GBE_DESC_NUM) + priv->rx_idx = 0; + rx_swp = priv->rx_idx; + if (++rx_swp >= PCH_GBE_DESC_NUM) + rx_swp = 0; + + writel(pci_phys_to_mem(priv->bdf, (u32)(rx_head + rx_swp)), + &mac_regs->rx_dsc_sw_p); + + return length; +} + +static int pch_gbe_mdio_ready(struct pch_gbe_regs *mac_regs) +{ + ulong start = get_timer(0); + + while (get_timer(start) < PCH_GBE_TIMEOUT) { + if (readl(&mac_regs->miim) & PCH_GBE_MIIM_OPER_READY) + return 0; + + udelay(10); + } + + return -ETIME; +} + +static int pch_gbe_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) +{ + struct pch_gbe_regs *mac_regs = bus->priv; + u32 miim; + + if (pch_gbe_mdio_ready(mac_regs)) + return -ETIME; + + miim = (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) | + (reg << PCH_GBE_MIIM_REG_ADDR_SHIFT) | + PCH_GBE_MIIM_OPER_READ; + writel(miim, &mac_regs->miim); + + if (pch_gbe_mdio_ready(mac_regs)) + return -ETIME; + + return readl(&mac_regs->miim) & 0xffff; +} + +static int pch_gbe_mdio_write(struct mii_dev *bus, int addr, int devad, + int reg, u16 val) +{ + struct pch_gbe_regs *mac_regs = bus->priv; + u32 miim; + + if (pch_gbe_mdio_ready(mac_regs)) + return -ETIME; + + miim = (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) | + (reg << PCH_GBE_MIIM_REG_ADDR_SHIFT) | + PCH_GBE_MIIM_OPER_WRITE | val; + writel(miim, &mac_regs->miim); + + if (pch_gbe_mdio_ready(mac_regs)) + return -ETIME; + else + return 0; +} + +static int pch_gbe_mdio_init(char *name, struct pch_gbe_regs *mac_regs) +{ + struct mii_dev *bus; + + bus = mdio_alloc(); + if (!bus) { + debug("pch_gbe: failed to allocate MDIO bus\n"); + return -ENOMEM; + } + + bus->read = pch_gbe_mdio_read; + bus->write = pch_gbe_mdio_write; + sprintf(bus->name, name); + + bus->priv = (void *)mac_regs; + + return mdio_register(bus); +} + +static int pch_gbe_phy_init(struct eth_device *dev) +{ + struct pch_gbe_priv *priv = dev->priv; + struct phy_device *phydev; + int mask = 0xffffffff; + + phydev = phy_find_by_mask(priv->bus, mask, priv->interface); + if (!phydev) { + printf("pch_gbe: cannot find the phy\n"); + return -1; + } + + phy_connect_dev(phydev, dev); + + phydev->supported &= PHY_GBIT_FEATURES; + phydev->advertising = phydev->supported; + + priv->phydev = phydev; + phy_config(phydev); + + return 1; +} + +int pch_gbe_register(bd_t *bis) +{ + struct eth_device *dev; + struct pch_gbe_priv *priv; + pci_dev_t devno; + u32 iobase; + + devno = pci_find_devices(supported, 0); + if (devno == -1) + return -ENODEV; + + dev = (struct eth_device *)malloc(sizeof(*dev)); + if (!dev) + return -ENOMEM; + memset(dev, 0, sizeof(*dev)); + + /* + * The priv structure contains the descriptors and frame buffers which + * need a strict buswidth alignment (64 bytes) + */ + priv = (struct pch_gbe_priv *)memalign(PCH_GBE_ALIGN_SIZE, + sizeof(*priv)); + if (!priv) { + free(dev); + return -ENOMEM; + } + memset(priv, 0, sizeof(*priv)); + + dev->priv = priv; + priv->dev = dev; + priv->bdf = devno; + + pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase); + iobase &= PCI_BASE_ADDRESS_MEM_MASK; + iobase = pci_mem_to_phys(devno, iobase); + + dev->iobase = iobase; + priv->mac_regs = (struct pch_gbe_regs *)iobase; + + sprintf(dev->name, "pch_gbe.%x", iobase); + + /* Read MAC address from SROM and initialize dev->enetaddr with it */ + pch_gbe_mac_read(priv->mac_regs, dev->enetaddr); + + dev->init = pch_gbe_init; + dev->halt = pch_gbe_halt; + dev->send = pch_gbe_send; + dev->recv = pch_gbe_recv; + + eth_register(dev); + + priv->interface = PHY_INTERFACE_MODE_RGMII; + pch_gbe_mdio_init(dev->name, priv->mac_regs); + priv->bus = miiphy_get_dev_by_name(dev->name); + + return pch_gbe_phy_init(dev); +} diff --git a/drivers/net/pch_gbe.h b/drivers/net/pch_gbe.h new file mode 100644 index 0000000..11329d4 --- /dev/null +++ b/drivers/net/pch_gbe.h @@ -0,0 +1,300 @@ +/* + * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> + * + * Intel Platform Controller Hub EG20T (codename Topcliff) GMAC Driver + * Adapted from linux drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _PCH_GBE_H_ +#define _PCH_GBE_H_ + +#define PCH_GBE_TIMEOUT (3 * CONFIG_SYS_HZ) + +#define PCH_GBE_DESC_NUM 4 +#define PCH_GBE_ALIGN_SIZE 64 + +/* + * Topcliff GBE MAC supports receiving ethernet frames with normal frame size + * (64-1518 bytes) as well as up to 10318 bytes, however it does not have a + * register bit to turn off receiving 'jumbo frame', so we have to allocate + * our own buffer to store the received frames instead of using U-Boot's own. + */ +#define PCH_GBE_RX_FRAME_LEN ROUND(10318, PCH_GBE_ALIGN_SIZE) + +/* Interrupt Status */ +/* Interrupt Status Hold */ +/* Interrupt Enable */ +#define PCH_GBE_INT_RX_DMA_CMPLT 0x00000001 +#define PCH_GBE_INT_RX_VALID 0x00000002 +#define PCH_GBE_INT_RX_FRAME_ERR 0x00000004 +#define PCH_GBE_INT_RX_FIFO_ERR 0x00000008 +#define PCH_GBE_INT_RX_DMA_ERR 0x00000010 +#define PCH_GBE_INT_RX_DSC_EMP 0x00000020 +#define PCH_GBE_INT_TX_CMPLT 0x00000100 +#define PCH_GBE_INT_TX_DMA_CMPLT 0x00000200 +#define PCH_GBE_INT_TX_FIFO_ERR 0x00000400 +#define PCH_GBE_INT_TX_DMA_ERR 0x00000800 +#define PCH_GBE_INT_PAUSE_CMPLT 0x00001000 +#define PCH_GBE_INT_MIIM_CMPLT 0x00010000 +#define PCH_GBE_INT_PHY_INT 0x00100000 +#define PCH_GBE_INT_WOL_DET 0x01000000 +#define PCH_GBE_INT_TCPIP_ERR 0x10000000 + +/* Mode */ +#define PCH_GBE_MODE_MII_ETHER 0x00000000 +#define PCH_GBE_MODE_GMII_ETHER 0x80000000 +#define PCH_GBE_MODE_HALF_DUPLEX 0x00000000 +#define PCH_GBE_MODE_FULL_DUPLEX 0x40000000 +#define PCH_GBE_MODE_FR_BST 0x04000000 + +/* Reset */ +#define PCH_GBE_ALL_RST 0x80000000 +#define PCH_GBE_TX_RST 0x00008000 +#define PCH_GBE_RX_RST 0x00004000 + +/* TCP/IP Accelerator Control */ +#define PCH_GBE_EX_LIST_EN 0x00000008 +#define PCH_GBE_RX_TCPIPACC_OFF 0x00000004 +#define PCH_GBE_TX_TCPIPACC_EN 0x00000002 +#define PCH_GBE_RX_TCPIPACC_EN 0x00000001 + +/* MAC RX Enable */ +#define PCH_GBE_MRE_MAC_RX_EN 0x00000001 + +/* RX Flow Control */ +#define PCH_GBE_FL_CTRL_EN 0x80000000 + +/* RX Mode */ +#define PCH_GBE_ADD_FIL_EN 0x80000000 +#define PCH_GBE_MLT_FIL_EN 0x40000000 +#define PCH_GBE_RH_ALM_EMP_4 0x00000000 +#define PCH_GBE_RH_ALM_EMP_8 0x00004000 +#define PCH_GBE_RH_ALM_EMP_16 0x00008000 +#define PCH_GBE_RH_ALM_EMP_32 0x0000c000 +#define PCH_GBE_RH_ALM_FULL_4 0x00000000 +#define PCH_GBE_RH_ALM_FULL_8 0x00001000 +#define PCH_GBE_RH_ALM_FULL_16 0x00002000 +#define PCH_GBE_RH_ALM_FULL_32 0x00003000 +#define PCH_GBE_RH_RD_TRG_4 0x00000000 +#define PCH_GBE_RH_RD_TRG_8 0x00000200 +#define PCH_GBE_RH_RD_TRG_16 0x00000400 +#define PCH_GBE_RH_RD_TRG_32 0x00000600 +#define PCH_GBE_RH_RD_TRG_64 0x00000800 +#define PCH_GBE_RH_RD_TRG_128 0x00000a00 +#define PCH_GBE_RH_RD_TRG_256 0x00000c00 +#define PCH_GBE_RH_RD_TRG_512 0x00000e00 + +/* TX Mode */ +#define PCH_GBE_TM_NO_RTRY 0x80000000 +#define PCH_GBE_TM_LONG_PKT 0x40000000 +#define PCH_GBE_TM_ST_AND_FD 0x20000000 +#define PCH_GBE_TM_SHORT_PKT 0x10000000 +#define PCH_GBE_TM_LTCOL_RETX 0x08000000 +#define PCH_GBE_TM_TH_TX_STRT_4 0x00000000 +#define PCH_GBE_TM_TH_TX_STRT_8 0x00004000 +#define PCH_GBE_TM_TH_TX_STRT_16 0x00008000 +#define PCH_GBE_TM_TH_TX_STRT_32 0x0000c000 +#define PCH_GBE_TM_TH_ALM_EMP_4 0x00000000 +#define PCH_GBE_TM_TH_ALM_EMP_8 0x00000800 +#define PCH_GBE_TM_TH_ALM_EMP_16 0x00001000 +#define PCH_GBE_TM_TH_ALM_EMP_32 0x00001800 +#define PCH_GBE_TM_TH_ALM_EMP_64 0x00002000 +#define PCH_GBE_TM_TH_ALM_EMP_128 0x00002800 +#define PCH_GBE_TM_TH_ALM_EMP_256 0x00003000 +#define PCH_GBE_TM_TH_ALM_EMP_512 0x00003800 +#define PCH_GBE_TM_TH_ALM_FULL_4 0x00000000 +#define PCH_GBE_TM_TH_ALM_FULL_8 0x00000200 +#define PCH_GBE_TM_TH_ALM_FULL_16 0x00000400 +#define PCH_GBE_TM_TH_ALM_FULL_32 0x00000600 + +/* MAC Address Mask */ +#define PCH_GBE_BUSY 0x80000000 + +/* MIIM */ +#define PCH_GBE_MIIM_OPER_WRITE 0x04000000 +#define PCH_GBE_MIIM_OPER_READ 0x00000000 +#define PCH_GBE_MIIM_OPER_READY 0x04000000 +#define PCH_GBE_MIIM_PHY_ADDR_SHIFT 21 +#define PCH_GBE_MIIM_REG_ADDR_SHIFT 16 + +/* RGMII Control */ +#define PCH_GBE_CRS_SEL 0x00000010 +#define PCH_GBE_RGMII_RATE_125M 0x00000000 +#define PCH_GBE_RGMII_RATE_25M 0x00000008 +#define PCH_GBE_RGMII_RATE_2_5M 0x0000000c +#define PCH_GBE_RGMII_MODE_GMII 0x00000000 +#define PCH_GBE_RGMII_MODE_RGMII 0x00000002 +#define PCH_GBE_CHIP_TYPE_EXTERNAL 0x00000000 +#define PCH_GBE_CHIP_TYPE_INTERNAL 0x00000001 + +/* DMA Control */ +#define PCH_GBE_RX_DMA_EN 0x00000002 +#define PCH_GBE_TX_DMA_EN 0x00000001 + +/* Receive Descriptor bit definitions */ +#define PCH_GBE_RXD_ACC_STAT_BCAST 0x00000400 +#define PCH_GBE_RXD_ACC_STAT_MCAST 0x00000200 +#define PCH_GBE_RXD_ACC_STAT_UCAST 0x00000100 +#define PCH_GBE_RXD_ACC_STAT_TCPIPOK 0x000000c0 +#define PCH_GBE_RXD_ACC_STAT_IPOK 0x00000080 +#define PCH_GBE_RXD_ACC_STAT_TCPOK 0x00000040 +#define PCH_GBE_RXD_ACC_STAT_IP6ERR 0x00000020 +#define PCH_GBE_RXD_ACC_STAT_OFLIST 0x00000010 +#define PCH_GBE_RXD_ACC_STAT_TYPEIP 0x00000008 +#define PCH_GBE_RXD_ACC_STAT_MACL 0x00000004 +#define PCH_GBE_RXD_ACC_STAT_PPPOE 0x00000002 +#define PCH_GBE_RXD_ACC_STAT_VTAGT 0x00000001 +#define PCH_GBE_RXD_GMAC_STAT_PAUSE 0x0200 +#define PCH_GBE_RXD_GMAC_STAT_MARBR 0x0100 +#define PCH_GBE_RXD_GMAC_STAT_MARMLT 0x0080 +#define PCH_GBE_RXD_GMAC_STAT_MARIND 0x0040 +#define PCH_GBE_RXD_GMAC_STAT_MARNOTMT 0x0020 +#define PCH_GBE_RXD_GMAC_STAT_TLONG 0x0010 +#define PCH_GBE_RXD_GMAC_STAT_TSHRT 0x0008 +#define PCH_GBE_RXD_GMAC_STAT_NOTOCTAL 0x0004 +#define PCH_GBE_RXD_GMAC_STAT_NBLERR 0x0002 +#define PCH_GBE_RXD_GMAC_STAT_CRCERR 0x0001 + +/* Transmit Descriptor bit definitions */ +#define PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF 0x0008 +#define PCH_GBE_TXD_CTRL_ITAG 0x0004 +#define PCH_GBE_TXD_CTRL_ICRC 0x0002 +#define PCH_GBE_TXD_CTRL_APAD 0x0001 +#define PCH_GBE_TXD_WORDS_SHIFT 2 +#define PCH_GBE_TXD_GMAC_STAT_CMPLT 0x2000 +#define PCH_GBE_TXD_GMAC_STAT_ABT 0x1000 +#define PCH_GBE_TXD_GMAC_STAT_EXCOL 0x0800 +#define PCH_GBE_TXD_GMAC_STAT_SNGCOL 0x0400 +#define PCH_GBE_TXD_GMAC_STAT_MLTCOL 0x0200 +#define PCH_GBE_TXD_GMAC_STAT_CRSER 0x0100 +#define PCH_GBE_TXD_GMAC_STAT_TLNG 0x0080 +#define PCH_GBE_TXD_GMAC_STAT_TSHRT 0x0040 +#define PCH_GBE_TXD_GMAC_STAT_LTCOL 0x0020 +#define PCH_GBE_TXD_GMAC_STAT_TFUNDFLW 0x0010 + +/** + * struct pch_gbe_rx_desc - Receive Descriptor + * @buffer_addr: RX Frame Buffer Address + * @tcp_ip_status: TCP/IP Accelerator Status + * @rx_words_eob: RX word count and Byte position + * @gbec_status: GMAC Status + * @dma_status: DMA Status + * @reserved1: Reserved + * @reserved2: Reserved + */ +struct pch_gbe_rx_desc { + u32 buffer_addr; + u32 tcp_ip_status; + u16 rx_words_eob; + u16 gbec_status; + u8 dma_status; + u8 reserved1; + u16 reserved2; +}; + +/** + * struct pch_gbe_tx_desc - Transmit Descriptor + * @buffer_addr: TX Frame Buffer Address + * @length: Data buffer length + * @reserved1: Reserved + * @tx_words_eob: TX word count and Byte position + * @tx_frame_ctrl: TX Frame Control + * @dma_status: DMA Status + * @reserved2: Reserved + * @gbec_status: GMAC Status + */ +struct pch_gbe_tx_desc { + u32 buffer_addr; + u16 length; + u16 reserved1; + u16 tx_words_eob; + u16 tx_frame_ctrl; + u8 dma_status; + u8 reserved2; + u16 gbec_status; +}; + +/** + * pch_gbe_regs_mac_adr - structure holding values of mac address registers + * + * @high Denotes the 1st to 4th byte from the initial of MAC address + * @low Denotes the 5th to 6th byte from the initial of MAC address + */ +struct pch_gbe_regs_mac_adr { + u32 high; + u32 low; +}; + +/** + * pch_gbe_regs - structure holding values of MAC registers + */ +struct pch_gbe_regs { + u32 int_st; + u32 int_en; + u32 mode; + u32 reset; + u32 tcpip_acc; + u32 ex_list; + u32 int_st_hold; + u32 phy_int_ctrl; + u32 mac_rx_en; + u32 rx_fctrl; + u32 pause_req; + u32 rx_mode; + u32 tx_mode; + u32 rx_fifo_st; + u32 tx_fifo_st; + u32 tx_fid; + u32 tx_result; + u32 pause_pkt1; + u32 pause_pkt2; + u32 pause_pkt3; + u32 pause_pkt4; + u32 pause_pkt5; + u32 reserve[2]; + struct pch_gbe_regs_mac_adr mac_adr[16]; + u32 addr_mask; + u32 miim; + u32 mac_addr_load; + u32 rgmii_st; + u32 rgmii_ctrl; + u32 reserve3[3]; + u32 dma_ctrl; + u32 reserve4[3]; + u32 rx_dsc_base; + u32 rx_dsc_size; + u32 rx_dsc_hw_p; + u32 rx_dsc_hw_p_hld; + u32 rx_dsc_sw_p; + u32 reserve5[3]; + u32 tx_dsc_base; + u32 tx_dsc_size; + u32 tx_dsc_hw_p; + u32 tx_dsc_hw_p_hld; + u32 tx_dsc_sw_p; + u32 reserve6[3]; + u32 rx_dma_st; + u32 tx_dma_st; + u32 reserve7[2]; + u32 wol_st; + u32 wol_ctrl; + u32 wol_addr_mask; +}; + +struct pch_gbe_priv { + struct pch_gbe_rx_desc rx_desc[PCH_GBE_DESC_NUM]; + struct pch_gbe_tx_desc tx_desc[PCH_GBE_DESC_NUM]; + char rx_buff[PCH_GBE_DESC_NUM][PCH_GBE_RX_FRAME_LEN]; + struct eth_device *dev; + struct phy_device *phydev; + struct mii_dev *bus; + struct pch_gbe_regs *mac_regs; + pci_dev_t bdf; + u32 interface; + int rx_idx; + int tx_idx; +}; + +#endif /* _PCH_GBE_H_ */ diff --git a/drivers/power/axp209.c b/drivers/power/axp209.c index 4565398..f8c9b77 100644 --- a/drivers/power/axp209.c +++ b/drivers/power/axp209.c @@ -119,7 +119,7 @@ int axp209_set_ldo3(int mvolt) if (mvolt == -1) cfg = 0x80; /* determined by LDO3IN pin */ else - cfg = axp209_mvolt_to_cfg(mvolt, 700, 2275, 25); + cfg = axp209_mvolt_to_cfg(mvolt, 700, 3500, 25); return axp209_write(AXP209_LDO3_VOLTAGE, cfg); } diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c index 3fc7104..2de3737 100644 --- a/drivers/serial/serial-uclass.c +++ b/drivers/serial/serial-uclass.c @@ -16,8 +16,6 @@ #include <dm/lists.h> #include <dm/device-internal.h> -#include <ns16550.h> - DECLARE_GLOBAL_DATA_PTR; /* diff --git a/drivers/serial/serial_arc.c b/drivers/serial/serial_arc.c index 2ddbf32..54e596c 100644 --- a/drivers/serial/serial_arc.c +++ b/drivers/serial/serial_arc.c @@ -8,6 +8,7 @@ */ #include <common.h> +#include <dm.h> #include <serial.h> DECLARE_GLOBAL_DATA_PTR; @@ -23,21 +24,23 @@ struct arc_serial_regs { unsigned int baudh; }; + +struct arc_serial_platdata { + struct arc_serial_regs *reg; + unsigned int uartclk; +}; + /* Bit definitions of STATUS register */ #define UART_RXEMPTY (1 << 5) #define UART_OVERFLOW_ERR (1 << 1) #define UART_TXEMPTY (1 << 7) -struct arc_serial_regs *regs; - -static void arc_serial_setbrg(void) +static int arc_serial_setbrg(struct udevice *dev, int baudrate) { - int arc_console_baud; + struct arc_serial_platdata *plat = dev->platdata; + struct arc_serial_regs *const regs = plat->reg; + int arc_console_baud = gd->cpu_clk / (baudrate * 4) - 1; - if (!gd->baudrate) - gd->baudrate = CONFIG_BAUDRATE; - - arc_console_baud = gd->cpu_clk / (gd->baudrate * 4) - 1; writeb(arc_console_baud & 0xff, ®s->baudl); #ifdef CONFIG_ARC @@ -56,34 +59,49 @@ static void arc_serial_setbrg(void) #else writeb((arc_console_baud & 0xff00) >> 8, ®s->baudh); #endif -} -static int arc_serial_init(void) -{ - regs = (struct arc_serial_regs *)CONFIG_ARC_UART_BASE; - serial_setbrg(); return 0; } -static void arc_serial_putc(const char c) +static int arc_serial_putc(struct udevice *dev, const char c) { + struct arc_serial_platdata *plat = dev->platdata; + struct arc_serial_regs *const regs = plat->reg; + if (c == '\n') - arc_serial_putc('\r'); + arc_serial_putc(dev, '\r'); while (!(readb(®s->status) & UART_TXEMPTY)) ; writeb(c, ®s->data); + + return 0; } -static int arc_serial_tstc(void) +static int arc_serial_tstc(struct arc_serial_regs *const regs) { return !(readb(®s->status) & UART_RXEMPTY); } -static int arc_serial_getc(void) +static int arc_serial_pending(struct udevice *dev, bool input) +{ + struct arc_serial_platdata *plat = dev->platdata; + struct arc_serial_regs *const regs = plat->reg; + uint32_t status = readb(®s->status); + + if (input) + return status & UART_RXEMPTY ? 0 : 1; + else + return status & UART_TXEMPTY ? 0 : 1; +} + +static int arc_serial_getc(struct udevice *dev) { - while (!arc_serial_tstc()) + struct arc_serial_platdata *plat = dev->platdata; + struct arc_serial_regs *const regs = plat->reg; + + while (!arc_serial_tstc(regs)) ; /* Check for overflow errors */ @@ -93,23 +111,42 @@ static int arc_serial_getc(void) return readb(®s->data) & 0xFF; } -static struct serial_device arc_serial_drv = { - .name = "arc_serial", - .start = arc_serial_init, - .stop = NULL, - .setbrg = arc_serial_setbrg, - .putc = arc_serial_putc, - .puts = default_serial_puts, - .getc = arc_serial_getc, - .tstc = arc_serial_tstc, -}; - -void arc_serial_initialize(void) +static int arc_serial_probe(struct udevice *dev) { - serial_register(&arc_serial_drv); + return 0; } -__weak struct serial_device *default_serial_console(void) +static const struct dm_serial_ops arc_serial_ops = { + .putc = arc_serial_putc, + .pending = arc_serial_pending, + .getc = arc_serial_getc, + .setbrg = arc_serial_setbrg, +}; + +static const struct udevice_id arc_serial_ids[] = { + { .compatible = "snps,arc-uart" }, + { } +}; + +static int arc_serial_ofdata_to_platdata(struct udevice *dev) { - return &arc_serial_drv; + struct arc_serial_platdata *plat = dev_get_platdata(dev); + DECLARE_GLOBAL_DATA_PTR; + + plat->reg = (struct arc_serial_regs *)fdtdec_get_addr(gd->fdt_blob, + dev->of_offset, "reg"); + plat->uartclk = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "clock-frequency", 0); + + return 0; } + +U_BOOT_DRIVER(serial_arc) = { + .name = "serial_arc", + .id = UCLASS_SERIAL, + .of_match = arc_serial_ids, + .ofdata_to_platdata = arc_serial_ofdata_to_platdata, + .probe = arc_serial_probe, + .ops = &arc_serial_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/spi/cf_qspi.c b/drivers/spi/cf_qspi.c index 6b85633..834c5bd 100644 --- a/drivers/spi/cf_qspi.c +++ b/drivers/spi/cf_qspi.c @@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR; #define clamp(x, low, high) (min(max(low, x), high)) -#define to_cf_qspi_slave(s) container_of(s, struct cf_qspi_slave, s) +#define to_cf_qspi_slave(s) container_of(s, struct cf_qspi_slave, slave) struct cf_qspi_slave { struct spi_slave slave; /* Specific bus:cs ID for each device */ diff --git a/drivers/spi/cf_spi.c b/drivers/spi/cf_spi.c index 879a809..6ce1101 100644 --- a/drivers/spi/cf_spi.c +++ b/drivers/spi/cf_spi.c @@ -20,13 +20,6 @@ struct cf_spi_slave { int charbit; }; -int cfspi_xfer(struct spi_slave *slave, uint bitlen, const void *dout, - void *din, ulong flags); -struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave, uint mode); -void cfspi_init(void); -void cfspi_tx(u32 ctrl, u16 data); -u16 cfspi_rx(void); - extern void cfspi_port_conf(void); extern int cfspi_claim_bus(uint bus, uint cs); extern void cfspi_release_bus(uint bus, uint cs); @@ -46,7 +39,12 @@ DECLARE_GLOBAL_DATA_PTR; #define SPI_MODE_MOD 0x00200000 #define SPI_DBLRATE 0x00100000 -void cfspi_init(void) +static inline struct cf_spi_slave *to_cf_spi_slave(struct spi_slave *slave) +{ + return container_of(slave, struct cf_spi_slave, slave); +} + +static void cfspi_init(void) { volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; @@ -84,7 +82,7 @@ void cfspi_init(void) #endif } -void cfspi_tx(u32 ctrl, u16 data) +static void cfspi_tx(u32 ctrl, u16 data) { volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; @@ -93,7 +91,7 @@ void cfspi_tx(u32 ctrl, u16 data) dspi->tfr = (ctrl | data); } -u16 cfspi_rx(void) +static u16 cfspi_rx(void) { volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; @@ -102,10 +100,10 @@ u16 cfspi_rx(void) return (dspi->rfr & 0xFFFF); } -int cfspi_xfer(struct spi_slave *slave, uint bitlen, const void *dout, - void *din, ulong flags) +static int cfspi_xfer(struct spi_slave *slave, uint bitlen, const void *dout, + void *din, ulong flags) { - struct cf_spi_slave *cfslave = (struct cf_spi_slave *)slave; + struct cf_spi_slave *cfslave = to_cf_spi_slave(slave); u16 *spi_rd16 = NULL, *spi_wr16 = NULL; u8 *spi_rd = NULL, *spi_wr = NULL; static u32 ctrl = 0; @@ -176,7 +174,8 @@ int cfspi_xfer(struct spi_slave *slave, uint bitlen, const void *dout, return 0; } -struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave, uint mode) +static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave, + uint mode) { /* * bit definition for mode: @@ -326,7 +325,9 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, void spi_free_slave(struct spi_slave *slave) { - free(slave); + struct cf_spi_slave *cfslave = to_cf_spi_slave(slave); + + free(cfslave); } int spi_claim_bus(struct spi_slave *slave) diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c index 0ec5b9d..bf18362 100644 --- a/drivers/spi/davinci_spi.c +++ b/drivers/spi/davinci_spi.c @@ -32,9 +32,6 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, if (!ds) return NULL; - ds->slave.bus = bus; - ds->slave.cs = cs; - switch (bus) { case SPI0_BUS: ds->regs = (struct davinci_spi_regs *)SPI0_BASE; diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c index 2624844..8f5c0fc 100644 --- a/drivers/spi/designware_spi.c +++ b/drivers/spi/designware_spi.c @@ -164,13 +164,13 @@ static void spi_hw_init(struct dw_spi_priv *priv) if (!priv->fifo_len) { u32 fifo; - for (fifo = 2; fifo <= 256; fifo++) { + for (fifo = 1; fifo < 256; fifo++) { dw_writew(priv, DW_SPI_TXFLTR, fifo); if (fifo != dw_readw(priv, DW_SPI_TXFLTR)) break; } - priv->fifo_len = (fifo == 2) ? 0 : fifo - 1; + priv->fifo_len = (fifo == 1) ? 0 : fifo; dw_writew(priv, DW_SPI_TXFLTR, 0); } debug("%s: fifo_len=%d\n", __func__, priv->fifo_len); diff --git a/drivers/spi/ftssp010_spi.c b/drivers/spi/ftssp010_spi.c index 267e4d8..c7d6480 100644 --- a/drivers/spi/ftssp010_spi.c +++ b/drivers/spi/ftssp010_spi.c @@ -431,7 +431,9 @@ free_out: void spi_free_slave(struct spi_slave *slave) { - free(slave); + struct ftssp010_spi *chip = to_ftssp010_spi(slave); + + free(chip); } int spi_claim_bus(struct spi_slave *slave) diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index 857b604..3356c0f 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -109,10 +109,17 @@ static void ti_spi_setup_spi_register(struct ti_qspi_slave *qslave) slave->op_mode_rx = 8; #endif +#ifdef CONFIG_QSPI_QUAD_SUPPORT + memval |= (QSPI_CMD_READ_QUAD | QSPI_SETUP0_NUM_A_BYTES | + QSPI_SETUP0_NUM_D_BYTES_8_BITS | + QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE | + QSPI_NUM_DUMMY_BITS); +#else memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES | QSPI_SETUP0_NUM_D_BYTES_NO_BITS | QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE | QSPI_NUM_DUMMY_BITS; +#endif writel(memval, &qslave->base->setup0); } diff --git a/drivers/usb/gadget/ether.c b/drivers/usb/gadget/ether.c index ba442d5..8f03a6b 100644 --- a/drivers/usb/gadget/ether.c +++ b/drivers/usb/gadget/ether.c @@ -68,7 +68,6 @@ unsigned packet_received, packet_sent; #define ETH_ZLEN 60 /* Min. octets in frame sans FCS */ #define ETH_DATA_LEN 1500 /* Max. octets in payload */ #define ETH_FRAME_LEN PKTSIZE_ALIGN /* Max. octets in frame sans FCS */ -#define ETH_FCS_LEN 4 /* Octets in the FCS */ #define DRIVER_DESC "Ethernet Gadget" /* Based on linux 2.6.27 version */ diff --git a/drivers/usb/gadget/rndis.c b/drivers/usb/gadget/rndis.c index 404a7b9..62c9b2e 100644 --- a/drivers/usb/gadget/rndis.c +++ b/drivers/usb/gadget/rndis.c @@ -43,7 +43,6 @@ #define ETH_ZLEN 60 /* Min. octets in frame sans FCS */ #define ETH_DATA_LEN 1500 /* Max. octets in payload */ #define ETH_FRAME_LEN PKTSIZE_ALIGN /* Max. octets in frame sans FCS */ -#define ETH_FCS_LEN 4 /* Octets in the FCS */ #define ENOTSUPP 524 /* Operation is not supported */ diff --git a/drivers/usb/musb-new/musb_uboot.c b/drivers/usb/musb-new/musb_uboot.c index 6e58ddf..51fb3fd 100644 --- a/drivers/usb/musb-new/musb_uboot.c +++ b/drivers/usb/musb-new/musb_uboot.c @@ -1,5 +1,8 @@ #include <common.h> #include <watchdog.h> +#ifdef CONFIG_ARCH_SUNXI +#include <asm/arch/usbc.h> +#endif #include <asm/errno.h> #include <linux/usb/ch9.h> #include <linux/usb/gadget.h> @@ -186,8 +189,19 @@ void usb_reset_root_port(void) power &= 0xf0; musb_writeb(mbase, MUSB_POWER, MUSB_POWER_RESET | power); mdelay(50); +#ifdef CONFIG_ARCH_SUNXI + /* + * sunxi phy has a bug and it will wrongly detect high speed squelch + * when clearing reset on low-speed devices, temporary disable + * squelch detection to work around this. + */ + sunxi_usbc_enable_squelch_detect(0, 0); +#endif power = musb_readb(mbase, MUSB_POWER); musb_writeb(mbase, MUSB_POWER, ~MUSB_POWER_RESET & power); +#ifdef CONFIG_ARCH_SUNXI + sunxi_usbc_enable_squelch_detect(0, 1); +#endif host->isr(0, host); host_speed = (musb_readb(mbase, MUSB_POWER) & MUSB_POWER_HSMODE) ? USB_SPEED_HIGH : diff --git a/drivers/video/exynos_fb.c b/drivers/video/exynos_fb.c index c5d7330..8f3b826 100644 --- a/drivers/video/exynos_fb.c +++ b/drivers/video/exynos_fb.c @@ -19,6 +19,7 @@ #include <asm/arch/mipi_dsim.h> #include <asm/arch/dp_info.h> #include <asm/arch/system.h> +#include <asm/gpio.h> #include <asm-generic/errno.h> #include "exynos_fb.h" @@ -102,6 +103,10 @@ __weak int exynos_lcd_misc_init(vidinfo_t *vid) static void lcd_panel_on(vidinfo_t *vid) { + struct gpio_desc pwm_out_gpio; + struct gpio_desc bl_en_gpio; + unsigned int node; + udelay(vid->init_delay); exynos_backlight_reset(); @@ -121,6 +126,22 @@ static void lcd_panel_on(vidinfo_t *vid) exynos_backlight_on(1); +#ifdef CONFIG_OF_CONTROL + node = fdtdec_next_compatible(gd->fdt_blob, 0, + COMPAT_SAMSUNG_EXYNOS_FIMD); + if (node <= 0) { + debug("FIMD: Can't get device node for FIMD\n"); + return; + } + gpio_request_by_name_nodev(gd->fdt_blob, node, "samsung,pwm-out-gpio", + 0, &pwm_out_gpio, + GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + + gpio_request_by_name_nodev(gd->fdt_blob, node, "samsung,bl-en-gpio", 0, + &bl_en_gpio, + GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + +#endif exynos_cfg_ldo(); exynos_enable_ldo(1); diff --git a/drivers/video/parade.c b/drivers/video/parade.c index 0f543f6..ae50971 100644 --- a/drivers/video/parade.c +++ b/drivers/video/parade.c @@ -12,6 +12,7 @@ #include <common.h> #include <i2c.h> #include <fdtdec.h> +#include <asm/gpio.h> /* * Initialization of the chip is a process of writing certaing values into @@ -180,6 +181,8 @@ static int parade_write_regs(int base_addr, const struct reg_data *table) int parade_init(const void *blob) { + struct gpio_desc rst_gpio; + struct gpio_desc slp_gpio; int bus, old_bus; int parent; int node; @@ -201,6 +204,14 @@ int parade_init(const void *blob) return -1; } + gpio_request_by_name_nodev(blob, node, "sleep-gpio", 0, &slp_gpio, + GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + + mdelay(10); + + gpio_request_by_name_nodev(blob, node, "reset-gpio", 0, &rst_gpio, + GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + bus = i2c_get_bus_num_fdt(parent); old_bus = i2c_get_bus_num(); diff --git a/drivers/watchdog/imx_watchdog.c b/drivers/watchdog/imx_watchdog.c index d5993b4..1d18d4b 100644 --- a/drivers/watchdog/imx_watchdog.c +++ b/drivers/watchdog/imx_watchdog.c @@ -20,7 +20,6 @@ struct watchdog_regs { #define WCR_WDE 0x04 /* WDOG enable */ #define WCR_WDT 0x08 #define WCR_SRS 0x10 -#define WCR_WDW 0x80 #define SET_WCR_WT(x) (x << 8) #ifdef CONFIG_IMX_WATCHDOG @@ -47,7 +46,7 @@ void hw_watchdog_init(void) #endif timeout = (CONFIG_WATCHDOG_TIMEOUT_MSECS / 500) - 1; writew(WCR_WDZST | WCR_WDBG | WCR_WDE | WCR_WDT | WCR_SRS | - WCR_WDW | SET_WCR_WT(timeout), &wdog->wcr); + SET_WCR_WT(timeout), &wdog->wcr); hw_watchdog_reset(); } #endif |