Merge branch 'master' of git://git.denx.de/u-boot

14 files changed, 1358 insertions, 136 deletions

diff --git a/drivers/fpga/spartan2.c b/drivers/fpga/spartan2.c
index f5ba7fc..d745334 100644
--- a/drivers/fpga/spartan2.c
+++ b/drivers/fpga/spartan2.c
@@ -260,8 +260,6 @@ static int Spartan2_sp_load (Xilinx_desc * desc, void *buf, size_t bsize)
 		ts = get_timer (0);		/* get current time */
 		ret_val = FPGA_SUCCESS;
 		while ((*fn->done) (cookie) == FPGA_FAIL) {
-			/* XXX - we should have a check in here somewhere to
-			 * make sure we aren't busy forever... */
 
 			CONFIG_FPGA_DELAY ();
 			(*fn->clk) (FALSE, TRUE, cookie);	/* Deassert the clock pin */
@@ -276,23 +274,18 @@ static int Spartan2_sp_load (Xilinx_desc * desc, void *buf, size_t bsize)
 			}
 		}
 
-		if (ret_val == FPGA_SUCCESS) {
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
-			puts ("Done.\n");
-#endif
-		}
 		/*
 		 * Run the post configuration function if there is one.
 		 */
-		if (*fn->post) {
+		if (*fn->post)
 			(*fn->post) (cookie);
-		}
 
-		else {
 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+		if (ret_val == FPGA_SUCCESS)
+			puts ("Done.\n");
+		else
 			puts ("Fail.\n");
 #endif
-		}
 
 	} else {
 		printf ("%s: NULL Interface function table!\n", __FUNCTION__);
@@ -412,8 +405,10 @@ static int Spartan2_sp_reloc (Xilinx_desc * desc, ulong reloc_offset)
 			addr = (ulong) (fn->abort) + reloc_offset;
 			fn_r->abort = (Xilinx_abort_fn) addr;
 
-			addr = (ulong) (fn->post) + reloc_offset;
-			fn_r->post = (Xilinx_post_fn) addr;
+			if (fn->post) {
+				addr = (ulong) (fn->post) + reloc_offset;
+				fn_r->post = (Xilinx_post_fn) addr;
+			}
 
 			fn_r->relocated = TRUE;
 
@@ -541,8 +536,6 @@ static int Spartan2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize)
 		(*fn->wr) (TRUE, TRUE, cookie);
 
 		while (! (*fn->done) (cookie)) {
-			/* XXX - we should have a check in here somewhere to
-			 * make sure we aren't busy forever... */
 
 			CONFIG_FPGA_DELAY ();
 			(*fn->clk) (FALSE, TRUE, cookie);	/* Deassert the clock pin */
@@ -562,17 +555,14 @@ static int Spartan2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize)
 		/*
 		 * Run the post configuration function if there is one.
 		 */
-		if (*fn->post) {
+		if (*fn->post)
 			(*fn->post) (cookie);
-		}
 
 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
-		if (ret_val == FPGA_SUCCESS) {
+		if (ret_val == FPGA_SUCCESS)
 			puts ("Done.\n");
-		}
-		else {
+		else
 			puts ("Fail.\n");
-		}
 #endif
 
 	} else {
diff --git a/drivers/fpga/spartan3.c b/drivers/fpga/spartan3.c
index 9ce41f1..8bb2449 100644
--- a/drivers/fpga/spartan3.c
+++ b/drivers/fpga/spartan3.c
@@ -281,23 +281,18 @@ static int Spartan3_sp_load (Xilinx_desc * desc, void *buf, size_t bsize)
 			}
 		}
 
-		if (ret_val == FPGA_SUCCESS) {
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
-			puts ("Done.\n");
-#endif
-		}
 		/*
 		 * Run the post configuration function if there is one.
 		 */
-		if (*fn->post) {
+		if (*fn->post)
 			(*fn->post) (cookie);
-		}
 
-		else {
 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+		if (ret_val == FPGA_SUCCESS)
+			puts ("Done.\n");
+		else
 			puts ("Fail.\n");
 #endif
-		}
 
 	} else {
 		printf ("%s: NULL Interface function table!\n", __FUNCTION__);
@@ -567,17 +562,14 @@ static int Spartan3_ss_load (Xilinx_desc * desc, void *buf, size_t bsize)
 		/*
 		 * Run the post configuration function if there is one.
 		 */
-		if (*fn->post) {
+		if (*fn->post)
 			(*fn->post) (cookie);
-		}
 
 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
-		if (ret_val == FPGA_SUCCESS) {
+		if (ret_val == FPGA_SUCCESS)
 			puts ("Done.\n");
-		}
-		else {
+		else
 			puts ("Fail.\n");
-		}
 #endif
 
 	} else {
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 6aa24f5..1b0af12 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -30,6 +30,7 @@ COBJS-$(CONFIG_ATMEL_MCI) += atmel_mci.o
 COBJS-$(CONFIG_BFIN_SDH) += bfin_sdh.o
 COBJS-$(CONFIG_OMAP3_MMC) += omap3_mmc.o
 COBJS-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o
+COBJS-$(CONFIG_PXA_MMC) += pxa_mmc.o
 
 COBJS	:= $(COBJS-y)
 SRCS	:= $(COBJS:.o=.c)
diff --git a/drivers/mmc/omap3_mmc.c b/drivers/mmc/omap3_mmc.c
index 0148702..e90db7e 100644
--- a/drivers/mmc/omap3_mmc.c
+++ b/drivers/mmc/omap3_mmc.c
@@ -28,6 +28,8 @@
 #include <mmc.h>
 #include <part.h>
 #include <i2c.h>
+#include <asm/io.h>
+#include <asm/arch/mmc.h>
 
 const unsigned short mmc_transspeed_val[15][4] = {
 	{CLKD(10, 1), CLKD(10, 10), CLKD(10, 100), CLKD(10, 1000)},
@@ -49,6 +51,7 @@ const unsigned short mmc_transspeed_val[15][4] = {
 
 mmc_card_data cur_card_data;
 static block_dev_desc_t mmc_blk_dev;
+static hsmmc_t *mmc_base = (hsmmc_t *)OMAP_HSMMC_BASE;
 
 block_dev_desc_t *mmc_get_dev(int dev)
 {
@@ -59,55 +62,49 @@ void twl4030_mmc_config(void)
 {
 	unsigned char data;
 
-	data = 0x20;
-	i2c_write(0x4B, 0x82, 1, &data, 1);
-	data = 0x2;
-	i2c_write(0x4B, 0x85, 1, &data, 1);
+	data = DEV_GRP_P1;
+	i2c_write(PWRMGT_ADDR_ID4, VMMC1_DEV_GRP, 1, &data, 1);
+	data = VMMC1_VSEL_30;
+	i2c_write(PWRMGT_ADDR_ID4, VMMC1_DEDICATED, 1, &data, 1);
 }
 
 unsigned char mmc_board_init(void)
 {
-	unsigned int value = 0;
+	t2_t *t2_base = (t2_t *)T2_BASE;
 
 	twl4030_mmc_config();
 
-	value = CONTROL_PBIAS_LITE;
-	CONTROL_PBIAS_LITE = value | (1 << 2) | (1 << 1) | (1 << 9);
+	writel(readl(&t2_base->pbias_lite) | PBIASLITEPWRDNZ1 |
+		PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
+		&t2_base->pbias_lite);
 
-	value = CONTROL_DEV_CONF0;
-	CONTROL_DEV_CONF0 = value | (1 << 24);
+	writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
+		&t2_base->devconf0);
 
 	return 1;
 }
 
 void mmc_init_stream(void)
 {
-	volatile unsigned int mmc_stat;
+	writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
 
-	OMAP_HSMMC_CON |= INIT_INITSTREAM;
+	writel(MMC_CMD0, &mmc_base->cmd);
+	while (!(readl(&mmc_base->stat) & CC_MASK));
 
-	OMAP_HSMMC_CMD = MMC_CMD0;
-	do {
-		mmc_stat = OMAP_HSMMC_STAT;
-	} while (!(mmc_stat & CC_MASK));
-
-	OMAP_HSMMC_STAT = CC_MASK;
+	writel(CC_MASK, &mmc_base->stat);
 
-	OMAP_HSMMC_CMD = MMC_CMD0;
-	do {
-		mmc_stat = OMAP_HSMMC_STAT;
-	} while (!(mmc_stat & CC_MASK));
+	writel(MMC_CMD0, &mmc_base->cmd);
+	while (!(readl(&mmc_base->stat) & CC_MASK));
 
-	OMAP_HSMMC_STAT = OMAP_HSMMC_STAT;
-	OMAP_HSMMC_CON &= ~INIT_INITSTREAM;
+	writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
 }
 
 unsigned char mmc_clock_config(unsigned int iclk, unsigned short clk_div)
 {
 	unsigned int val;
 
-	mmc_reg_out(OMAP_HSMMC_SYSCTL, (ICE_MASK | DTO_MASK | CEN_MASK),
-		    (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
+	mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
+			(ICE_STOP | DTO_15THDTO | CEN_DISABLE));
 
 	switch (iclk) {
 	case CLK_INITSEQ:
@@ -122,12 +119,12 @@ unsigned char mmc_clock_config(unsigned int iclk, unsigned short clk_div)
 	default:
 		return 0;
 	}
-	mmc_reg_out(OMAP_HSMMC_SYSCTL,
-		    ICE_MASK | CLKD_MASK, (val << CLKD_OFFSET) | ICE_OSCILLATE);
+	mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
+			(val << CLKD_OFFSET) | ICE_OSCILLATE);
 
-	while ((OMAP_HSMMC_SYSCTL & ICS_MASK) == ICS_NOTREADY) ;
+	while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY);
 
-	OMAP_HSMMC_SYSCTL |= CEN_ENABLE;
+	writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
 	return 1;
 }
 
@@ -137,59 +134,63 @@ unsigned char mmc_init_setup(void)
 
 	mmc_board_init();
 
-	OMAP_HSMMC_SYSCONFIG |= MMC_SOFTRESET;
-	while ((OMAP_HSMMC_SYSSTATUS & RESETDONE) == 0) ;
+	writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
+		&mmc_base->sysconfig);
+	while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0);
 
-	OMAP_HSMMC_SYSCTL |= SOFTRESETALL;
-	while ((OMAP_HSMMC_SYSCTL & SOFTRESETALL) != 0x0) ;
+	writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
+	while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0);
 
-	OMAP_HSMMC_HCTL = DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0;
-	OMAP_HSMMC_CAPA |= VS30_3V0SUP | VS18_1V8SUP;
+	writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
+	writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
+		&mmc_base->capa);
 
-	reg_val = OMAP_HSMMC_CON & RESERVED_MASK;
+	reg_val = readl(&mmc_base->con) & RESERVED_MASK;
 
-	OMAP_HSMMC_CON = CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH |
-		CDP_ACTIVEHIGH | MIT_CTO | DW8_1_4BITMODE | MODE_FUNC |
-		STR_BLOCK | HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN;
+	writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
+		MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
+		HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
 
 	mmc_clock_config(CLK_INITSEQ, 0);
-	OMAP_HSMMC_HCTL |= SDBP_PWRON;
+	writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
 
-	OMAP_HSMMC_IE = 0x307f0033;
+	writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE |
+		IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC,
+		&mmc_base->ie);
 
 	mmc_init_stream();
 	return 1;
 }
 
 unsigned char mmc_send_cmd(unsigned int cmd, unsigned int arg,
-			   unsigned int *response)
+				unsigned int *response)
 {
-	volatile unsigned int mmc_stat;
+	unsigned int mmc_stat;
 
-	while ((OMAP_HSMMC_PSTATE & DATI_MASK) == DATI_CMDDIS) ;
+	while ((readl(&mmc_base->pstate) & DATI_MASK) == DATI_CMDDIS);
 
-	OMAP_HSMMC_BLK = BLEN_512BYTESLEN | NBLK_STPCNT;
-	OMAP_HSMMC_STAT = 0xFFFFFFFF;
-	OMAP_HSMMC_ARG = arg;
-	OMAP_HSMMC_CMD = cmd | CMD_TYPE_NORMAL | CICE_NOCHECK |
-	    CCCE_NOCHECK | MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE |
-	    DE_DISABLE;
+	writel(BLEN_512BYTESLEN | NBLK_STPCNT, &mmc_base->blk);
+	writel(0xFFFFFFFF, &mmc_base->stat);
+	writel(arg, &mmc_base->arg);
+	writel(cmd | CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
+		MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE,
+		&mmc_base->cmd);
 
 	while (1) {
 		do {
-			mmc_stat = OMAP_HSMMC_STAT;
+			mmc_stat = readl(&mmc_base->stat);
 		} while (mmc_stat == 0);
 
 		if ((mmc_stat & ERRI_MASK) != 0)
 			return (unsigned char) mmc_stat;
 
 		if (mmc_stat & CC_MASK) {
-			OMAP_HSMMC_STAT = CC_MASK;
-			response[0] = OMAP_HSMMC_RSP10;
+			writel(CC_MASK, &mmc_base->stat);
+			response[0] = readl(&mmc_base->rsp10);
 			if ((cmd & RSP_TYPE_MASK) == RSP_TYPE_LGHT136) {
-				response[1] = OMAP_HSMMC_RSP32;
-				response[2] = OMAP_HSMMC_RSP54;
-				response[3] = OMAP_HSMMC_RSP76;
+				response[1] = readl(&mmc_base->rsp32);
+				response[2] = readl(&mmc_base->rsp54);
+				response[3] = readl(&mmc_base->rsp76);
 			}
 			break;
 		}
@@ -199,7 +200,7 @@ unsigned char mmc_send_cmd(unsigned int cmd, unsigned int arg,
 
 unsigned char mmc_read_data(unsigned int *output_buf)
 {
-	volatile unsigned int mmc_stat;
+	unsigned int mmc_stat;
 	unsigned int read_count = 0;
 
 	/*
@@ -207,7 +208,7 @@ unsigned char mmc_read_data(unsigned int *output_buf)
 	 */
 	while (1) {
 		do {
-			mmc_stat = OMAP_HSMMC_STAT;
+			mmc_stat = readl(&mmc_base->stat);
 		} while (mmc_stat == 0);
 
 		if ((mmc_stat & ERRI_MASK) != 0)
@@ -216,19 +217,22 @@ unsigned char mmc_read_data(unsigned int *output_buf)
 		if (mmc_stat & BRR_MASK) {
 			unsigned int k;
 
-			OMAP_HSMMC_STAT |= BRR_MASK;
+			writel(readl(&mmc_base->stat) | BRR_MASK,
+				&mmc_base->stat);
 			for (k = 0; k < MMCSD_SECTOR_SIZE / 4; k++) {
-				*output_buf = OMAP_HSMMC_DATA;
+				*output_buf = readl(&mmc_base->data);
 				output_buf++;
 				read_count += 4;
 			}
 		}
 
 		if (mmc_stat & BWR_MASK)
-			OMAP_HSMMC_STAT |= BWR_MASK;
+			writel(readl(&mmc_base->stat) | BWR_MASK,
+				&mmc_base->stat);
 
 		if (mmc_stat & TC_MASK) {
-			OMAP_HSMMC_STAT |= TC_MASK;
+			writel(readl(&mmc_base->stat) | TC_MASK,
+				&mmc_base->stat);
 			break;
 		}
 	}
@@ -272,8 +276,8 @@ unsigned char mmc_detect_card(mmc_card_data *mmc_card_cur)
 		mmc_card_cur->card_type = MMC_CARD;
 		ocr_value |= MMC_OCR_REG_ACCESS_MODE_SECTOR;
 		ret_cmd41 = MMC_CMD1;
-		OMAP_HSMMC_CON &= ~OD;
-		OMAP_HSMMC_CON |= OPENDRAIN;
+		writel(readl(&mmc_base->con) & ~OD, &mmc_base->con);
+		writel(readl(&mmc_base->con) | OPENDRAIN, &mmc_base->con);
 	}
 
 	argument = ocr_value;
@@ -341,8 +345,8 @@ unsigned char mmc_detect_card(mmc_card_data *mmc_card_cur)
 		mmc_card_cur->RCA = ((mmc_resp_r6 *) resp)->newpublishedrca;
 	}
 
-	OMAP_HSMMC_CON &= ~OD;
-	OMAP_HSMMC_CON |= NOOPENDRAIN;
+	writel(readl(&mmc_base->con) & ~OD, &mmc_base->con);
+	writel(readl(&mmc_base->con) | NOOPENDRAIN, &mmc_base->con);
 	return 1;
 }
 
@@ -517,11 +521,11 @@ unsigned long mmc_bread(int dev_num, unsigned long blknr, lbaint_t blkcnt,
 			void *dst)
 {
 	omap_mmc_read_sect(blknr, (blkcnt * MMCSD_SECTOR_SIZE), &cur_card_data,
-			   (unsigned long *) dst);
+				(unsigned long *) dst);
 	return 1;
 }
 
-int mmc_init(int verbose)
+int mmc_legacy_init(int verbose)
 {
 	if (configure_mmc(&cur_card_data) != 1)
 		return 1;
@@ -541,18 +545,3 @@ int mmc_init(int verbose)
 	fat_register_device(&mmc_blk_dev, 1);
 	return 0;
 }
-
-int mmc_read(ulong src, uchar *dst, int size)
-{
-	return 0;
-}
-
-int mmc_write(uchar *src, ulong dst, int size)
-{
-	return 0;
-}
-
-int mmc2info(ulong addr)
-{
-	return 0;
-}
diff --git a/drivers/mmc/pxa_mmc.c b/drivers/mmc/pxa_mmc.c
new file mode 100644
index 0000000..8225235
--- /dev/null
+++ b/drivers/mmc/pxa_mmc.c
@@ -0,0 +1,646 @@
+/*
+ * (C) Copyright 2003
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <mmc.h>
+#include <asm/errno.h>
+#include <asm/arch/hardware.h>
+#include <part.h>
+
+#include "pxa_mmc.h"
+
+extern int fat_register_device(block_dev_desc_t * dev_desc, int part_no);
+
+static block_dev_desc_t mmc_dev;
+
+block_dev_desc_t *mmc_get_dev(int dev)
+{
+	return ((block_dev_desc_t *) & mmc_dev);
+}
+
+/*
+ * FIXME needs to read cid and csd info to determine block size
+ * and other parameters
+ */
+static uchar mmc_buf[MMC_BLOCK_SIZE];
+static uchar spec_ver;
+static int mmc_ready = 0;
+static int wide = 0;
+
+static uint32_t *
+/****************************************************/
+mmc_cmd(ushort cmd, ushort argh, ushort argl, ushort cmdat)
+/****************************************************/
+{
+	static uint32_t resp[4], a, b, c;
+	ulong status;
+	int i;
+
+	debug("mmc_cmd %u 0x%04x 0x%04x 0x%04x\n", cmd, argh, argl,
+	      cmdat | wide);
+	MMC_STRPCL = MMC_STRPCL_STOP_CLK;
+	MMC_I_MASK = ~MMC_I_MASK_CLK_IS_OFF;
+	while (!(MMC_I_REG & MMC_I_REG_CLK_IS_OFF)) ;
+	MMC_CMD = cmd;
+	MMC_ARGH = argh;
+	MMC_ARGL = argl;
+	MMC_CMDAT = cmdat | wide;
+	MMC_I_MASK = ~MMC_I_MASK_END_CMD_RES;
+	MMC_STRPCL = MMC_STRPCL_START_CLK;
+	while (!(MMC_I_REG & MMC_I_REG_END_CMD_RES)) ;
+
+	status = MMC_STAT;
+	debug("MMC status 0x%08x\n", status);
+	if (status & MMC_STAT_TIME_OUT_RESPONSE) {
+		return 0;
+	}
+
+	/* Linux says:
+	 * Did I mention this is Sick.  We always need to
+	 * discard the upper 8 bits of the first 16-bit word.
+	 */
+	a = (MMC_RES & 0xffff);
+	for (i = 0; i < 4; i++) {
+		b = (MMC_RES & 0xffff);
+		c = (MMC_RES & 0xffff);
+		resp[i] = (a << 24) | (b << 8) | (c >> 8);
+		a = c;
+		debug("MMC resp[%d] = %#08x\n", i, resp[i]);
+	}
+
+	return resp;
+}
+
+int
+/****************************************************/
+mmc_block_read(uchar * dst, ulong src, ulong len)
+/****************************************************/
+{
+	ushort argh, argl;
+	ulong status;
+
+	if (len == 0) {
+		return 0;
+	}
+
+	debug("mmc_block_rd dst %lx src %lx len %d\n", (ulong) dst, src, len);
+
+	argh = len >> 16;
+	argl = len & 0xffff;
+
+	/* set block len */
+	mmc_cmd(MMC_CMD_SET_BLOCKLEN, argh, argl, MMC_CMDAT_R1);
+
+	/* send read command */
+	argh = src >> 16;
+	argl = src & 0xffff;
+	MMC_STRPCL = MMC_STRPCL_STOP_CLK;
+	MMC_RDTO = 0xffff;
+	MMC_NOB = 1;
+	MMC_BLKLEN = len;
+	mmc_cmd(MMC_CMD_READ_SINGLE_BLOCK, argh, argl,
+		MMC_CMDAT_R1 | MMC_CMDAT_READ | MMC_CMDAT_BLOCK |
+		MMC_CMDAT_DATA_EN);
+
+	MMC_I_MASK = ~MMC_I_MASK_RXFIFO_RD_REQ;
+	while (len) {
+		if (MMC_I_REG & MMC_I_REG_RXFIFO_RD_REQ) {
+#ifdef CONFIG_PXA27X
+			int i;
+			for (i = min(len, 32); i; i--) {
+				*dst++ = *((volatile uchar *)&MMC_RXFIFO);
+				len--;
+			}
+#else
+			*dst++ = MMC_RXFIFO;
+			len--;
+#endif
+		}
+		status = MMC_STAT;
+		if (status & MMC_STAT_ERRORS) {
+			printf("MMC_STAT error %lx\n", status);
+			return -1;
+		}
+	}
+	MMC_I_MASK = ~MMC_I_MASK_DATA_TRAN_DONE;
+	while (!(MMC_I_REG & MMC_I_REG_DATA_TRAN_DONE)) ;
+	status = MMC_STAT;
+	if (status & MMC_STAT_ERRORS) {
+		printf("MMC_STAT error %lx\n", status);
+		return -1;
+	}
+	return 0;
+}
+
+int
+/****************************************************/
+mmc_block_write(ulong dst, uchar * src, int len)
+/****************************************************/
+{
+	ushort argh, argl;
+	ulong status;
+
+	if (len == 0) {
+		return 0;
+	}
+
+	debug("mmc_block_wr dst %lx src %lx len %d\n", dst, (ulong) src, len);
+
+	argh = len >> 16;
+	argl = len & 0xffff;
+
+	/* set block len */
+	mmc_cmd(MMC_CMD_SET_BLOCKLEN, argh, argl, MMC_CMDAT_R1);
+
+	/* send write command */
+	argh = dst >> 16;
+	argl = dst & 0xffff;
+	MMC_STRPCL = MMC_STRPCL_STOP_CLK;
+	MMC_NOB = 1;
+	MMC_BLKLEN = len;
+	mmc_cmd(MMC_CMD_WRITE_SINGLE_BLOCK, argh, argl,
+		MMC_CMDAT_R1 | MMC_CMDAT_WRITE | MMC_CMDAT_BLOCK |
+		MMC_CMDAT_DATA_EN);
+
+	MMC_I_MASK = ~MMC_I_MASK_TXFIFO_WR_REQ;
+	while (len) {
+		if (MMC_I_REG & MMC_I_REG_TXFIFO_WR_REQ) {
+			int i, bytes = min(32, len);
+
+			for (i = 0; i < bytes; i++) {
+				MMC_TXFIFO = *src++;
+			}
+			if (bytes < 32) {
+				MMC_PRTBUF = MMC_PRTBUF_BUF_PART_FULL;
+			}
+			len -= bytes;
+		}
+		status = MMC_STAT;
+		if (status & MMC_STAT_ERRORS) {
+			printf("MMC_STAT error %lx\n", status);
+			return -1;
+		}
+	}
+	MMC_I_MASK = ~MMC_I_MASK_DATA_TRAN_DONE;
+	while (!(MMC_I_REG & MMC_I_REG_DATA_TRAN_DONE)) ;
+	MMC_I_MASK = ~MMC_I_MASK_PRG_DONE;
+	while (!(MMC_I_REG & MMC_I_REG_PRG_DONE)) ;
+	status = MMC_STAT;
+	if (status & MMC_STAT_ERRORS) {
+		printf("MMC_STAT error %lx\n", status);
+		return -1;
+	}
+	return 0;
+}
+
+int
+/****************************************************/
+pxa_mmc_read(long src, uchar * dst, int size)
+/****************************************************/
+{
+	ulong end, part_start, part_end, part_len, aligned_start, aligned_end;
+	ulong mmc_block_size, mmc_block_address;
+
+	if (size == 0) {
+		return 0;
+	}
+
+	if (!mmc_ready) {
+		printf("Please initial the MMC first\n");
+		return -1;
+	}
+
+	mmc_block_size = MMC_BLOCK_SIZE;
+	mmc_block_address = ~(mmc_block_size - 1);
+
+	src -= CONFIG_SYS_MMC_BASE;
+	end = src + size;
+	part_start = ~mmc_block_address & src;
+	part_end = ~mmc_block_address & end;
+	aligned_start = mmc_block_address & src;
+	aligned_end = mmc_block_address & end;
+
+	/* all block aligned accesses */
+	debug
+	    ("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
+	     src, (ulong) dst, end, part_start, part_end, aligned_start,
+	     aligned_end);
+	if (part_start) {
+		part_len = mmc_block_size - part_start;
+		debug
+		    ("ps src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
+		     src, (ulong) dst, end, part_start, part_end, aligned_start,
+		     aligned_end);
+		if ((mmc_block_read(mmc_buf, aligned_start, mmc_block_size)) <
+		    0) {
+			return -1;
+		}
+		memcpy(dst, mmc_buf + part_start, part_len);
+		dst += part_len;
+		src += part_len;
+	}
+	debug
+	    ("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
+	     src, (ulong) dst, end, part_start, part_end, aligned_start,
+	     aligned_end);
+	for (; src < aligned_end; src += mmc_block_size, dst += mmc_block_size) {
+		debug
+		    ("al src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
+		     src, (ulong) dst, end, part_start, part_end, aligned_start,
+		     aligned_end);
+		if ((mmc_block_read((uchar *) (dst), src, mmc_block_size)) < 0) {
+			return -1;
+		}
+	}
+	debug
+	    ("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
+	     src, (ulong) dst, end, part_start, part_end, aligned_start,
+	     aligned_end);
+	if (part_end && src < end) {
+		debug
+		    ("pe src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
+		     src, (ulong) dst, end, part_start, part_end, aligned_start,
+		     aligned_end);
+		if ((mmc_block_read(mmc_buf, aligned_end, mmc_block_size)) < 0) {
+			return -1;
+		}
+		memcpy(dst, mmc_buf, part_end);
+	}
+	return 0;
+}
+
+int
+/****************************************************/
+pxa_mmc_write(uchar * src, ulong dst, int size)
+/****************************************************/
+{
+	ulong end, part_start, part_end, part_len, aligned_start, aligned_end;
+	ulong mmc_block_size, mmc_block_address;
+
+	if (size == 0) {
+		return 0;
+	}
+
+	if (!mmc_ready) {
+		printf("Please initial the MMC first\n");
+		return -1;
+	}
+
+	mmc_block_size = MMC_BLOCK_SIZE;
+	mmc_block_address = ~(mmc_block_size - 1);
+
+	dst -= CONFIG_SYS_MMC_BASE;
+	end = dst + size;
+	part_start = ~mmc_block_address & dst;
+	part_end = ~mmc_block_address & end;
+	aligned_start = mmc_block_address & dst;
+	aligned_end = mmc_block_address & end;
+
+	/* all block aligned accesses */
+	debug
+	    ("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
+	     src, (ulong) dst, end, part_start, part_end, aligned_start,
+	     aligned_end);
+	if (part_start) {
+		part_len = mmc_block_size - part_start;
+		debug
+		    ("ps src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
+		     (ulong) src, dst, end, part_start, part_end, aligned_start,
+		     aligned_end);
+		if ((mmc_block_read(mmc_buf, aligned_start, mmc_block_size)) <
+		    0) {
+			return -1;
+		}
+		memcpy(mmc_buf + part_start, src, part_len);
+		if ((mmc_block_write(aligned_start, mmc_buf, mmc_block_size)) <
+		    0) {
+			return -1;
+		}
+		dst += part_len;
+		src += part_len;
+	}
+	debug
+	    ("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
+	     src, (ulong) dst, end, part_start, part_end, aligned_start,
+	     aligned_end);
+	for (; dst < aligned_end; src += mmc_block_size, dst += mmc_block_size) {
+		debug
+		    ("al src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
+		     src, (ulong) dst, end, part_start, part_end, aligned_start,
+		     aligned_end);
+		if ((mmc_block_write(dst, (uchar *) src, mmc_block_size)) < 0) {
+			return -1;
+		}
+	}
+	debug
+	    ("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
+	     src, (ulong) dst, end, part_start, part_end, aligned_start,
+	     aligned_end);
+	if (part_end && dst < end) {
+		debug
+		    ("pe src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
+		     src, (ulong) dst, end, part_start, part_end, aligned_start,
+		     aligned_end);
+		if ((mmc_block_read(mmc_buf, aligned_end, mmc_block_size)) < 0) {
+			return -1;
+		}
+		memcpy(mmc_buf, src, part_end);
+		if ((mmc_block_write(aligned_end, mmc_buf, mmc_block_size)) < 0) {
+			return -1;
+		}
+	}
+	return 0;
+}
+
+static ulong
+/****************************************************/
+mmc_bread(int dev_num, ulong blknr, lbaint_t blkcnt, void *dst)
+/****************************************************/
+{
+	int mmc_block_size = MMC_BLOCK_SIZE;
+	ulong src = blknr * mmc_block_size + CONFIG_SYS_MMC_BASE;
+
+	pxa_mmc_read(src, (uchar *) dst, blkcnt * mmc_block_size);
+	return blkcnt;
+}
+
+#ifdef __GNUC__
+#define likely(x)       __builtin_expect(!!(x), 1)
+#define unlikely(x)     __builtin_expect(!!(x), 0)
+#else
+#define likely(x)	(x)
+#define unlikely(x)	(x)
+#endif
+
+#define UNSTUFF_BITS(resp,start,size)					\
+	({								\
+		const int __size = size;				\
+		const uint32_t __mask = (__size < 32 ? 1 << __size : 0) - 1;	\
+		const int32_t __off = 3 - ((start) / 32);			\
+		const int32_t __shft = (start) & 31;			\
+		uint32_t __res;						\
+									\
+		__res = resp[__off] >> __shft;				\
+		if (__size + __shft > 32)				\
+			__res |= resp[__off-1] << ((32 - __shft) % 32);	\
+		__res & __mask;						\
+	})
+
+/*
+ * Given the decoded CSD structure, decode the raw CID to our CID structure.
+ */
+static void mmc_decode_cid(uint32_t * resp)
+{
+	if (IF_TYPE_SD == mmc_dev.if_type) {
+		/*
+		 * SD doesn't currently have a version field so we will
+		 * have to assume we can parse this.
+		 */
+		sprintf((char *)mmc_dev.vendor,
+			"Man %02x OEM %c%c \"%c%c%c%c%c\" Date %02u/%04u",
+			UNSTUFF_BITS(resp, 120, 8), UNSTUFF_BITS(resp, 112, 8),
+			UNSTUFF_BITS(resp, 104, 8), UNSTUFF_BITS(resp, 96, 8),
+			UNSTUFF_BITS(resp, 88, 8), UNSTUFF_BITS(resp, 80, 8),
+			UNSTUFF_BITS(resp, 72, 8), UNSTUFF_BITS(resp, 64, 8),
+			UNSTUFF_BITS(resp, 8, 4), UNSTUFF_BITS(resp, 12,
+							       8) + 2000);
+		sprintf((char *)mmc_dev.revision, "%d.%d",
+			UNSTUFF_BITS(resp, 60, 4), UNSTUFF_BITS(resp, 56, 4));
+		sprintf((char *)mmc_dev.product, "%u",
+			UNSTUFF_BITS(resp, 24, 32));
+	} else {
+		/*
+		 * The selection of the format here is based upon published
+		 * specs from sandisk and from what people have reported.
+		 */
+		switch (spec_ver) {
+		case 0:	/* MMC v1.0 - v1.2 */
+		case 1:	/* MMC v1.4 */
+			sprintf((char *)mmc_dev.vendor,
+				"Man %02x%02x%02x \"%c%c%c%c%c%c%c\" Date %02u/%04u",
+				UNSTUFF_BITS(resp, 120, 8), UNSTUFF_BITS(resp,
+									 112,
+									 8),
+				UNSTUFF_BITS(resp, 104, 8), UNSTUFF_BITS(resp,
+									 96, 8),
+				UNSTUFF_BITS(resp, 88, 8), UNSTUFF_BITS(resp,
+									80, 8),
+				UNSTUFF_BITS(resp, 72, 8), UNSTUFF_BITS(resp,
+									64, 8),
+				UNSTUFF_BITS(resp, 56, 8), UNSTUFF_BITS(resp,
+									48, 8),
+				UNSTUFF_BITS(resp, 12, 4), UNSTUFF_BITS(resp, 8,
+									4) +
+				1997);
+			sprintf((char *)mmc_dev.revision, "%d.%d",
+				UNSTUFF_BITS(resp, 44, 4), UNSTUFF_BITS(resp,
+									40, 4));
+			sprintf((char *)mmc_dev.product, "%u",
+				UNSTUFF_BITS(resp, 16, 24));
+			break;
+
+		case 2:	/* MMC v2.0 - v2.2 */
+		case 3:	/* MMC v3.1 - v3.3 */
+		case 4:	/* MMC v4 */
+			sprintf((char *)mmc_dev.vendor,
+				"Man %02x OEM %04x \"%c%c%c%c%c%c\" Date %02u/%04u",
+				UNSTUFF_BITS(resp, 120, 8), UNSTUFF_BITS(resp,
+									 104,
+									 16),
+				UNSTUFF_BITS(resp, 96, 8), UNSTUFF_BITS(resp,
+									88, 8),
+				UNSTUFF_BITS(resp, 80, 8), UNSTUFF_BITS(resp,
+									72, 8),
+				UNSTUFF_BITS(resp, 64, 8), UNSTUFF_BITS(resp,
+									56, 8),
+				UNSTUFF_BITS(resp, 12, 4), UNSTUFF_BITS(resp, 8,
+									4) +
+				1997);
+			sprintf((char *)mmc_dev.product, "%u",
+				UNSTUFF_BITS(resp, 16, 32));
+			sprintf((char *)mmc_dev.revision, "N/A");
+			break;
+
+		default:
+			printf("MMC card has unknown MMCA version %d\n",
+			       spec_ver);
+			break;
+		}
+	}
+	printf("%s card.\nVendor: %s\nProduct: %s\nRevision: %s\n",
+	       (IF_TYPE_SD == mmc_dev.if_type) ? "SD" : "MMC", mmc_dev.vendor,
+	       mmc_dev.product, mmc_dev.revision);
+}
+
+/*
+ * Given a 128-bit response, decode to our card CSD structure.
+ */
+static void mmc_decode_csd(uint32_t * resp)
+{
+	unsigned int mult, csd_struct;
+
+	if (IF_TYPE_SD == mmc_dev.if_type) {
+		csd_struct = UNSTUFF_BITS(resp, 126, 2);
+		if (csd_struct != 0) {
+			printf("SD: unrecognised CSD structure version %d\n",
+			       csd_struct);
+			return;
+		}
+	} else {
+		/*
+		 * We only understand CSD structure v1.1 and v1.2.
+		 * v1.2 has extra information in bits 15, 11 and 10.
+		 */
+		csd_struct = UNSTUFF_BITS(resp, 126, 2);
+		if (csd_struct != 1 && csd_struct != 2) {
+			printf("MMC: unrecognised CSD structure version %d\n",
+			       csd_struct);
+			return;
+		}
+
+		spec_ver = UNSTUFF_BITS(resp, 122, 4);
+		mmc_dev.if_type = IF_TYPE_MMC;
+	}
+
+	mult = 1 << (UNSTUFF_BITS(resp, 47, 3) + 2);
+	mmc_dev.lba = (1 + UNSTUFF_BITS(resp, 62, 12)) * mult;
+	mmc_dev.blksz = 1 << UNSTUFF_BITS(resp, 80, 4);
+
+	/* FIXME: The following just makes assumes that's the partition type -- should really read it */
+	mmc_dev.part_type = PART_TYPE_DOS;
+	mmc_dev.dev = 0;
+	mmc_dev.lun = 0;
+	mmc_dev.type = DEV_TYPE_HARDDISK;
+	mmc_dev.removable = 0;
+	mmc_dev.block_read = mmc_bread;
+
+	printf("Detected: %lu blocks of %lu bytes (%luMB) ",
+		mmc_dev.lba,
+		mmc_dev.blksz,
+		mmc_dev.lba * mmc_dev.blksz / (1024 * 1024));
+}
+
+int
+/****************************************************/
+mmc_legacy_init(int verbose)
+/****************************************************/
+{
+	int retries, rc = -ENODEV;
+	uint32_t cid_resp[4];
+	uint32_t *resp;
+	uint16_t rca = 0;
+
+	/* Reset device interface type */
+	mmc_dev.if_type = IF_TYPE_UNKNOWN;
+
+#if defined (CONFIG_LUBBOCK) || (defined (CONFIG_GUMSTIX) && !defined(CONFIG_PXA27X))
+	set_GPIO_mode(GPIO6_MMCCLK_MD);
+	set_GPIO_mode(GPIO8_MMCCS0_MD);
+#endif
+	CKEN |= CKEN12_MMC;	/* enable MMC unit clock */
+
+	MMC_CLKRT = MMC_CLKRT_0_3125MHZ;
+	MMC_RESTO = MMC_RES_TO_MAX;
+	MMC_SPI = MMC_SPI_DISABLE;
+
+	/* reset */
+	mmc_cmd(MMC_CMD_GO_IDLE_STATE, 0, 0, MMC_CMDAT_INIT | MMC_CMDAT_R0);
+	udelay(200000);
+	retries = 3;
+	while (retries--) {
+		resp = mmc_cmd(MMC_CMD_APP_CMD, 0, 0, MMC_CMDAT_R1);
+		if (!(resp[0] & 0x00000020)) {	/* Card does not support APP_CMD */
+			debug("Card does not support APP_CMD\n");
+			break;
+		}
+
+		/* Select 3.2-3.3V and 3.3-3.4V */
+		resp = mmc_cmd(SD_CMD_APP_SEND_OP_COND, 0x0030, 0x0000,
+				MMC_CMDAT_R3 | (retries < 2 ? 0
+					: MMC_CMDAT_INIT));
+		if (resp[0] & 0x80000000) {
+			mmc_dev.if_type = IF_TYPE_SD;
+			debug("Detected SD card\n");
+			break;
+		}
+#ifdef CONFIG_PXA27X
+		udelay(10000);
+#else
+		udelay(200000);
+#endif
+	}
+
+	if (retries <= 0 || !(IF_TYPE_SD == mmc_dev.if_type)) {
+		debug("Failed to detect SD Card, trying MMC\n");
+		resp =
+		    mmc_cmd(MMC_CMD_SEND_OP_COND, 0x00ff, 0x8000, MMC_CMDAT_R3);
+
+		retries = 10;
+		while (retries-- && resp && !(resp[0] & 0x80000000)) {
+#ifdef CONFIG_PXA27X
+			udelay(10000);
+#else
+			udelay(200000);
+#endif
+			resp =
+			    mmc_cmd(MMC_CMD_SEND_OP_COND, 0x00ff, 0x8000,
+				    MMC_CMDAT_R3);
+		}
+	}
+
+	/* try to get card id */
+	resp =
+	    mmc_cmd(MMC_CMD_ALL_SEND_CID, 0, 0, MMC_CMDAT_R2 | MMC_CMDAT_BUSY);
+	if (resp) {
+		memcpy(cid_resp, resp, sizeof(cid_resp));
+
+		/* MMC exists, get CSD too */
+		resp = mmc_cmd(MMC_CMD_SET_RELATIVE_ADDR, 0, 0, MMC_CMDAT_R1);
+		if (IF_TYPE_SD == mmc_dev.if_type)
+			rca = ((resp[0] & 0xffff0000) >> 16);
+		resp = mmc_cmd(MMC_CMD_SEND_CSD, rca, 0, MMC_CMDAT_R2);
+		if (resp) {
+			mmc_decode_csd(resp);
+			rc = 0;
+			mmc_ready = 1;
+		}
+
+		mmc_decode_cid(cid_resp);
+	}
+
+	MMC_CLKRT = 0;		/* 20 MHz */
+	resp = mmc_cmd(MMC_CMD_SELECT_CARD, rca, 0, MMC_CMDAT_R1);
+
+#ifdef CONFIG_PXA27X
+	if (IF_TYPE_SD == mmc_dev.if_type) {
+		resp = mmc_cmd(MMC_CMD_APP_CMD, rca, 0, MMC_CMDAT_R1);
+		resp = mmc_cmd(SD_CMD_APP_SET_BUS_WIDTH, 0, 2, MMC_CMDAT_R1);
+		wide = MMC_CMDAT_SD_4DAT;
+	}
+#endif
+
+	fat_register_device(&mmc_dev, 1);	/* partitions start counting with 1 */
+
+	return rc;
+}
diff --git a/drivers/mmc/pxa_mmc.h b/drivers/mmc/pxa_mmc.h
new file mode 100644
index 0000000..6fa4268
--- /dev/null
+++ b/drivers/mmc/pxa_mmc.h
@@ -0,0 +1,138 @@
+/*
+ *  linux/drivers/mmc/mmc_pxa.h
+ *
+ *  Author: Vladimir Shebordaev, Igor Oblakov
+ *  Copyright:  MontaVista Software Inc.
+ *
+ *  $Id: mmc_pxa.h,v 0.3.1.6 2002/09/25 19:25:48 ted Exp ted $
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+#ifndef __MMC_PXA_P_H__
+#define __MMC_PXA_P_H__
+
+/* PXA-250 MMC controller registers */
+
+/* MMC_STRPCL */
+#define MMC_STRPCL_STOP_CLK		(0x0001UL)
+#define MMC_STRPCL_START_CLK		(0x0002UL)
+
+/* MMC_STAT */
+#define MMC_STAT_END_CMD_RES		(0x0001UL << 13)
+#define MMC_STAT_PRG_DONE		(0x0001UL << 12)
+#define MMC_STAT_DATA_TRAN_DONE		(0x0001UL << 11)
+#define MMC_STAT_CLK_EN			(0x0001UL << 8)
+#define MMC_STAT_RECV_FIFO_FULL		(0x0001UL << 7)
+#define MMC_STAT_XMIT_FIFO_EMPTY	(0x0001UL << 6)
+#define MMC_STAT_RES_CRC_ERROR		(0x0001UL << 5)
+#define MMC_STAT_SPI_READ_ERROR_TOKEN   (0x0001UL << 4)
+#define MMC_STAT_CRC_READ_ERROR		(0x0001UL << 3)
+#define MMC_STAT_CRC_WRITE_ERROR	(0x0001UL << 2)
+#define MMC_STAT_TIME_OUT_RESPONSE	(0x0001UL << 1)
+#define MMC_STAT_READ_TIME_OUT		(0x0001UL)
+
+#define MMC_STAT_ERRORS (MMC_STAT_RES_CRC_ERROR|MMC_STAT_SPI_READ_ERROR_TOKEN\
+	|MMC_STAT_CRC_READ_ERROR|MMC_STAT_TIME_OUT_RESPONSE\
+	|MMC_STAT_READ_TIME_OUT|MMC_STAT_CRC_WRITE_ERROR)
+
+/* MMC_CLKRT */
+#define MMC_CLKRT_20MHZ			(0x0000UL)
+#define MMC_CLKRT_10MHZ			(0x0001UL)
+#define MMC_CLKRT_5MHZ			(0x0002UL)
+#define MMC_CLKRT_2_5MHZ		(0x0003UL)
+#define MMC_CLKRT_1_25MHZ		(0x0004UL)
+#define MMC_CLKRT_0_625MHZ		(0x0005UL)
+#define MMC_CLKRT_0_3125MHZ		(0x0006UL)
+
+/* MMC_SPI */
+#define MMC_SPI_DISABLE			(0x00UL)
+#define MMC_SPI_EN			(0x01UL)
+#define MMC_SPI_CS_EN			(0x01UL << 2)
+#define MMC_SPI_CS_ADDRESS		(0x01UL << 3)
+#define MMC_SPI_CRC_ON			(0x01UL << 1)
+
+/* MMC_CMDAT */
+#define MMC_CMDAT_SD_4DAT		(0x0001UL << 8)
+#define MMC_CMDAT_MMC_DMA_EN		(0x0001UL << 7)
+#define MMC_CMDAT_INIT			(0x0001UL << 6)
+#define MMC_CMDAT_BUSY			(0x0001UL << 5)
+#define MMC_CMDAT_BCR			(0x0003UL << 5)
+#define MMC_CMDAT_STREAM		(0x0001UL << 4)
+#define MMC_CMDAT_BLOCK			(0x0000UL << 4)
+#define MMC_CMDAT_WRITE			(0x0001UL << 3)
+#define MMC_CMDAT_READ			(0x0000UL << 3)
+#define MMC_CMDAT_DATA_EN		(0x0001UL << 2)
+#define MMC_CMDAT_R0			(0)
+#define MMC_CMDAT_R1			(0x0001UL)
+#define MMC_CMDAT_R2			(0x0002UL)
+#define MMC_CMDAT_R3			(0x0003UL)
+
+/* MMC_RESTO */
+#define MMC_RES_TO_MAX			(0x007fUL) /* [6:0] */
+
+/* MMC_RDTO */
+#define MMC_READ_TO_MAX			(0x0ffffUL) /* [15:0] */
+
+/* MMC_BLKLEN */
+#define MMC_BLK_LEN_MAX			(0x03ffUL) /* [9:0] */
+
+/* MMC_PRTBUF */
+#define MMC_PRTBUF_BUF_PART_FULL	(0x01UL)
+#define MMC_PRTBUF_BUF_FULL		(0x00UL    )
+
+/* MMC_I_MASK */
+#define MMC_I_MASK_TXFIFO_WR_REQ	(0x01UL << 6)
+#define MMC_I_MASK_RXFIFO_RD_REQ	(0x01UL << 5)
+#define MMC_I_MASK_CLK_IS_OFF		(0x01UL << 4)
+#define MMC_I_MASK_STOP_CMD		(0x01UL << 3)
+#define MMC_I_MASK_END_CMD_RES		(0x01UL << 2)
+#define MMC_I_MASK_PRG_DONE		(0x01UL << 1)
+#define MMC_I_MASK_DATA_TRAN_DONE       (0x01UL)
+#define MMC_I_MASK_ALL			(0x07fUL)
+
+
+/* MMC_I_REG */
+#define MMC_I_REG_TXFIFO_WR_REQ		(0x01UL << 6)
+#define MMC_I_REG_RXFIFO_RD_REQ		(0x01UL << 5)
+#define MMC_I_REG_CLK_IS_OFF		(0x01UL << 4)
+#define MMC_I_REG_STOP_CMD		(0x01UL << 3)
+#define MMC_I_REG_END_CMD_RES		(0x01UL << 2)
+#define MMC_I_REG_PRG_DONE		(0x01UL << 1)
+#define MMC_I_REG_DATA_TRAN_DONE	(0x01UL)
+#define MMC_I_REG_ALL			(0x007fUL)
+
+/* MMC_CMD */
+#define MMC_CMD_INDEX_MAX		(0x006fUL)  /* [5:0] */
+#define CMD(x)  (x)
+
+#define MMC_DEFAULT_RCA			1
+
+#define MMC_BLOCK_SIZE			512
+#define MMC_MAX_BLOCK_SIZE		512
+
+#define MMC_R1_IDLE_STATE		0x01
+#define MMC_R1_ERASE_STATE		0x02
+#define MMC_R1_ILLEGAL_CMD		0x04
+#define MMC_R1_COM_CRC_ERR		0x08
+#define MMC_R1_ERASE_SEQ_ERR		0x01
+#define MMC_R1_ADDR_ERR			0x02
+#define MMC_R1_PARAM_ERR		0x04
+
+#define MMC_R1B_WP_ERASE_SKIP		0x0002
+#define MMC_R1B_ERR			0x0004
+#define MMC_R1B_CC_ERR			0x0008
+#define MMC_R1B_CARD_ECC_ERR		0x0010
+#define MMC_R1B_WP_VIOLATION		0x0020
+#define MMC_R1B_ERASE_PARAM		0x0040
+#define MMC_R1B_OOR			0x0080
+#define MMC_R1B_IDLE_STATE		0x0100
+#define MMC_R1B_ERASE_RESET		0x0200
+#define MMC_R1B_ILLEGAL_CMD		0x0400
+#define MMC_R1B_COM_CRC_ERR		0x0800
+#define MMC_R1B_ERASE_SEQ_ERR		0x1000
+#define MMC_R1B_ADDR_ERR		0x2000
+#define MMC_R1B_PARAM_ERR		0x4000
+
+#endif /* __MMC_PXA_P_H__ */
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 24edb27..5974d77 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -38,6 +38,7 @@ endif
 COBJS-$(CONFIG_DRIVER_NAND_BFIN) += bfin_nand.o
 COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o
 COBJS-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o
+COBJS-$(CONFIG_NAND_NOMADIK) += nomadik.o
 COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o
 COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o
 endif
diff --git a/drivers/mtd/nand/nomadik.c b/drivers/mtd/nand/nomadik.c
new file mode 100644
index 0000000..b76f4cb
--- /dev/null
+++ b/drivers/mtd/nand/nomadik.c
@@ -0,0 +1,221 @@
+/*
+ * (C) Copyright 2007 STMicroelectronics, <www.st.com>
+ * (C) Copyright 2009 Alessandro Rubini <rubini@unipv.it>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <nand.h>
+#include <asm/io.h>
+
+static inline int parity(int b) /* b is really a byte; returns 0 or ~0 */
+{
+	__asm__ __volatile__(
+		"eor   %0, %0, %0, lsr #4\n\t"
+		"eor   %0, %0, %0, lsr #2\n\t"
+		"eor   %0, %0, %0, lsr #1\n\t"
+		"ands  %0, %0, #1\n\t"
+		"subne %0, %0, #2\t"
+		: "=r" (b) : "0" (b));
+	return b;
+}
+
+/*
+ * This is the ECC routine used in hardware, according to the manual.
+ * HW claims to make the calculation but not the correction; so we must
+ * recalculate the bytes for a comparison.
+ */
+static int ecc512(const unsigned char *data, unsigned char *ecc)
+{
+	int gpar = 0;
+	int i, val, par;
+	int pbits = 0;		/* P8, P16, ... P2048 */
+	int pprime = 0;		/* P8', P16', ... P2048' */
+	int lowbits;		/* P1, P2, P4 and primes */
+
+	for (i = 0; i < 512; i++) {
+		par = parity((val = data[i]));
+		gpar ^= val;
+		pbits ^= (i & par);
+	}
+	/*
+	 * Ok, now gpar is global parity (xor of all bytes)
+	 * pbits are all the parity bits (non-prime ones)
+	 */
+	par = parity(gpar);
+	pprime = pbits ^ par;
+	/* Put low bits in the right position for ecc[2] (bits 7..2) */
+	lowbits = 0
+		| (parity(gpar & 0xf0) & 0x80)	/* P4  */
+		| (parity(gpar & 0x0f) & 0x40)	/* P4' */
+		| (parity(gpar & 0xcc) & 0x20)	/* P2  */
+		| (parity(gpar & 0x33) & 0x10)	/* P2' */
+		| (parity(gpar & 0xaa) & 0x08)	/* P1  */
+		| (parity(gpar & 0x55) & 0x04);	/* P1' */
+
+	ecc[2] = ~(lowbits | ((pbits & 0x100) >> 7) | ((pprime & 0x100) >> 8));
+	/* now intermix bits for ecc[1] (P1024..P128') and ecc[0] (P64..P8') */
+	ecc[1] = ~(    (pbits & 0x80) >> 0  | ((pprime & 0x80) >> 1)
+		    | ((pbits & 0x40) >> 1) | ((pprime & 0x40) >> 2)
+		    | ((pbits & 0x20) >> 2) | ((pprime & 0x20) >> 3)
+		    | ((pbits & 0x10) >> 3) | ((pprime & 0x10) >> 4));
+
+	ecc[0] = ~(    (pbits & 0x8) << 4  | ((pprime & 0x8) << 3)
+		    | ((pbits & 0x4) << 3) | ((pprime & 0x4) << 2)
+		    | ((pbits & 0x2) << 2) | ((pprime & 0x2) << 1)
+		    | ((pbits & 0x1) << 1) | ((pprime & 0x1) << 0));
+	return 0;
+}
+
+/* This is the method in the chip->ecc field */
+static int nomadik_ecc_calculate(struct mtd_info *mtd, const uint8_t *dat,
+				 uint8_t *ecc_code)
+{
+	return ecc512(dat, ecc_code);
+}
+
+static int nomadik_ecc_correct(struct mtd_info *mtd, uint8_t *dat,
+				uint8_t *r_ecc, uint8_t *c_ecc)
+{
+	struct nand_chip *chip = mtd->priv;
+	uint32_t r, c, d, diff; /*read, calculated, xor of them */
+
+	if (!memcmp(r_ecc, c_ecc, chip->ecc.bytes))
+		return 0;
+
+	/* Reorder the bytes into ascending-order 24 bits -- see manual */
+	r = r_ecc[2] << 22 | r_ecc[1] << 14 | r_ecc[0] << 6 | r_ecc[2] >> 2;
+	c = c_ecc[2] << 22 | c_ecc[1] << 14 | c_ecc[0] << 6 | c_ecc[2] >> 2;
+	diff = (r ^ c) & ((1<<24)-1); /* use 24 bits only */
+
+	/* If 12 bits are different, one per pair, it's correctable */
+	if (((diff | (diff>>1)) & 0x555555) == 0x555555) {
+		int bit = ((diff & 2) >> 1)
+			| ((diff & 0x8) >> 2) | ((diff & 0x20) >> 3);
+		int byte;
+
+		d = diff >> 6; /* remove bit-order info */
+		byte =  ((d & 2) >> 1)
+			| ((d & 0x8) >> 2) | ((d & 0x20) >> 3)
+			| ((d & 0x80) >> 4) | ((d & 0x200) >> 5)
+			| ((d & 0x800) >> 6) | ((d & 0x2000) >> 7)
+			| ((d & 0x8000) >> 8) | ((d & 0x20000) >> 9);
+		/* correct the single bit */
+		dat[byte] ^= 1<<bit;
+		return 0;
+	}
+	/* If 1 bit only differs, it's one bit error in ECC, ignore */
+	if ((diff ^ (1 << (ffs(diff) - 1))) == 0)
+		return 0;
+	/* Otherwise, uncorrectable */
+	return -1;
+}
+
+static void nomadik_ecc_hwctl(struct mtd_info *mtd, int mode)
+{ /* mandatory in the structure but not used here */ }
+
+
+/* This is the layout used by older installations, we keep compatible */
+struct nand_ecclayout nomadik_ecc_layout = {
+	.eccbytes = 3 * 4,
+	.eccpos = { /* each subpage has 16 bytes: pos 2,3,4 hosts ECC */
+		0x02, 0x03, 0x04,
+		0x12, 0x13, 0x14,
+		0x22, 0x23, 0x24,
+		0x32, 0x33, 0x34},
+	.oobfree = { {0x08, 0x08}, {0x18, 0x08}, {0x28, 0x08}, {0x38, 0x08} },
+};
+
+#define MASK_ALE	(1 << 24)	/* our ALE is AD21 */
+#define MASK_CLE	(1 << 23)	/* our CLE is AD22 */
+
+/* This is copied from the AT91SAM9 devices (Stelian Pop, Lead Tech Design) */
+static void nomadik_nand_hwcontrol(struct mtd_info *mtd,
+				   int cmd, unsigned int ctrl)
+{
+	struct nand_chip *this = mtd->priv;
+	u32 pcr0 = readl(REG_FSMC_PCR0);
+
+	if (ctrl & NAND_CTRL_CHANGE) {
+		ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
+		IO_ADDR_W &= ~(MASK_ALE | MASK_CLE);
+
+		if (ctrl & NAND_CLE)
+			IO_ADDR_W |= MASK_CLE;
+		if (ctrl & NAND_ALE)
+			IO_ADDR_W |= MASK_ALE;
+
+		if (ctrl & NAND_NCE)
+			writel(pcr0 | 0x4, REG_FSMC_PCR0);
+		else
+			writel(pcr0 & ~0x4, REG_FSMC_PCR0);
+
+		this->IO_ADDR_W = (void *) IO_ADDR_W;
+		this->IO_ADDR_R = (void *) IO_ADDR_W;
+	}
+
+	if (cmd != NAND_CMD_NONE)
+		writeb(cmd, this->IO_ADDR_W);
+}
+
+/* Returns 1 when ready; upper layers timeout at 20ms with timer routines */
+static int nomadik_nand_ready(struct mtd_info *mtd)
+{
+	return 1; /* The ready bit is handled in hardware */
+}
+
+/* Copy a buffer 32bits at a time: faster than defualt method which is 8bit */
+static void nomadik_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+{
+	int i;
+	struct nand_chip *chip = mtd->priv;
+	u32 *p = (u32 *) buf;
+
+	len >>= 2;
+	writel(0, REG_FSMC_ECCR0);
+	for (i = 0; i < len; i++)
+		p[i] = readl(chip->IO_ADDR_R);
+}
+
+int board_nand_init(struct nand_chip *chip)
+{
+	/* Set up the FSMC_PCR0 for nand access*/
+	writel(0x0000004a, REG_FSMC_PCR0);
+	/* Set up FSMC_PMEM0, FSMC_PATT0 with timing data for access */
+	writel(0x00020401, REG_FSMC_PMEM0);
+	writel(0x00020404, REG_FSMC_PATT0);
+
+	chip->options = NAND_COPYBACK |	NAND_CACHEPRG | NAND_NO_PADDING;
+	chip->cmd_ctrl = nomadik_nand_hwcontrol;
+	chip->dev_ready = nomadik_nand_ready;
+	/* The chip allows 32bit reads, so avoid the default 8bit copy */
+	chip->read_buf = nomadik_nand_read_buf;
+
+	/* ECC: follow the hardware-defined rulse, but do it in sw */
+	chip->ecc.mode = NAND_ECC_HW;
+	chip->ecc.bytes = 3;
+	chip->ecc.size = 512;
+	chip->ecc.layout = &nomadik_ecc_layout;
+	chip->ecc.calculate = nomadik_ecc_calculate;
+	chip->ecc.hwctl = nomadik_ecc_hwctl;
+	chip->ecc.correct = nomadik_ecc_correct;
+
+	return 0;
+}
diff --git a/drivers/net/dnet.c b/drivers/net/dnet.c
index efac746..bfe87fa 100644
--- a/drivers/net/dnet.c
+++ b/drivers/net/dnet.c
@@ -393,4 +393,3 @@ int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr)
 
 	return 0;
 }
-
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index b6fd0d7..d0efd73 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -25,13 +25,14 @@ include $(TOPDIR)/config.mk
 
 LIB	:= $(obj)libserial.a
 
+COBJS-$(CONFIG_ARM_DCC) += arm_dcc.o
 COBJS-$(CONFIG_ATMEL_USART) += atmel_usart.o
 COBJS-$(CONFIG_MCFUART) += mcfuart.o
 COBJS-$(CONFIG_NS9750_UART) += ns9750_serial.o
-COBJS-y += ns16550.o
+COBJS-$(CONFIG_SYS_NS16550) += ns16550.o
 COBJS-$(CONFIG_DRIVER_S3C4510_UART) += s3c4510b_uart.o
 COBJS-$(CONFIG_S3C64XX) += s3c64xx.o
-COBJS-y += serial.o
+COBJS-$(CONFIG_SYS_NS16550_SERIAL) += serial.o
 COBJS-$(CONFIG_IXP_SERIAL) += serial_ixp.o
 COBJS-$(CONFIG_MAX3100_SERIAL) += serial_max3100.o
 COBJS-$(CONFIG_PL010_SERIAL) += serial_pl01x.o
diff --git a/drivers/serial/arm_dcc.c b/drivers/serial/arm_dcc.c
new file mode 100644
index 0000000..5a7fb6b
--- /dev/null
+++ b/drivers/serial/arm_dcc.c
@@ -0,0 +1,226 @@
+/*
+ * Copyright (C) 2004-2007 ARM Limited.
+ * Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ * As a special exception, if other files instantiate templates or use macros
+ * or inline functions from this file, or you compile this file and link it
+ * with other works to produce a work based on this file, this file does not
+ * by itself cause the resulting work to be covered by the GNU General Public
+ * License. However the source code for this file must still be made available
+ * in accordance with section (3) of the GNU General Public License.
+
+ * This exception does not invalidate any other reasons why a work based on
+ * this file might be covered by the GNU General Public License.
+ */
+
+#include <common.h>
+#include <devices.h>
+
+#define DCC_ARM9_RBIT	(1 << 0)
+#define DCC_ARM9_WBIT	(1 << 1)
+#define DCC_ARM11_RBIT	(1 << 30)
+#define DCC_ARM11_WBIT	(1 << 29)
+
+#define read_core_id(x)	do {						\
+		__asm__ ("mrc p15, 0, %0, c0, c0, 0\n" : "=r" (x));	\
+		x = (x >> 4) & 0xFFF;					\
+		} while (0);
+
+/*
+ * ARM9
+ */
+#define write_arm9_dcc(x)	\
+		__asm__ volatile ("mcr p14, 0, %0, c1, c0, 0\n" : : "r" (x))
+
+#define read_arm9_dcc(x)	\
+		__asm__ volatile ("mrc p14, 0, %0, c1, c0, 0\n" : "=r" (x))
+
+#define status_arm9_dcc(x)	\
+		__asm__ volatile ("mrc p14, 0, %0, c0, c0, 0\n" : "=r" (x))
+
+#define can_read_arm9_dcc(x)	do {	\
+		status_arm9_dcc(x);	\
+		x &= DCC_ARM9_RBIT;	\
+		} while (0);
+
+#define can_write_arm9_dcc(x)	do {	\
+		status_arm9_dcc(x);	\
+		x &= DCC_ARM9_WBIT;	\
+		x = (x == 0);		\
+		} while (0);
+
+/*
+ * ARM11
+ */
+#define write_arm11_dcc(x)	\
+		__asm__ volatile ("mcr p14, 0, %0, c0, c5, 0\n" : : "r" (x))
+
+#define read_arm11_dcc(x)	\
+		__asm__ volatile ("mrc p14, 0, %0, c0, c5, 0\n" : "=r" (x))
+
+#define status_arm11_dcc(x)	\
+		__asm__ volatile ("mrc p14, 0, %0, c0, c1, 0\n" : "=r" (x))
+
+#define can_read_arm11_dcc(x)	do {	\
+		status_arm11_dcc(x);	\
+		x &= DCC_ARM11_RBIT;	\
+		} while (0);
+
+#define can_write_arm11_dcc(x)	do {	\
+		status_arm11_dcc(x);	\
+		x &= DCC_ARM11_WBIT;	\
+		x = (x == 0);		\
+		} while (0);
+
+#define TIMEOUT_COUNT 0x4000000
+
+static enum {
+	arm9_and_earlier,
+	arm11_and_later
+} arm_type = arm9_and_earlier;
+
+#ifndef CONFIG_ARM_DCC_MULTI
+#define arm_dcc_init serial_init
+void serial_setbrg(void) {}
+#define arm_dcc_getc serial_getc
+#define arm_dcc_putc serial_putc
+#define arm_dcc_puts serial_puts
+#define arm_dcc_tstc serial_tstc
+#endif
+
+int arm_dcc_init(void)
+{
+	register unsigned int id;
+
+	read_core_id(id);
+
+	if (id >= 0xb00)
+		arm_type = arm11_and_later;
+	else
+		arm_type = arm9_and_earlier;
+
+	return 0;
+}
+
+int arm_dcc_getc(void)
+{
+	int ch;
+	register unsigned int reg;
+
+	switch (arm_type) {
+	case arm11_and_later:
+		do {
+			can_read_arm11_dcc(reg);
+		} while (!reg);
+		read_arm11_dcc(ch);
+		break;
+
+	case arm9_and_earlier:
+	default:
+		do {
+			can_read_arm9_dcc(reg);
+		} while (!reg);
+		read_arm9_dcc(ch);
+		break;
+	}
+
+	return ch;
+}
+
+void arm_dcc_putc(char ch)
+{
+	register unsigned int reg;
+	unsigned int timeout_count = TIMEOUT_COUNT;
+
+	switch (arm_type) {
+	case arm11_and_later:
+		while (--timeout_count) {
+			can_write_arm11_dcc(reg);
+			if (reg)
+				break;
+		}
+		if (timeout_count == 0)
+			return;
+		else
+			write_arm11_dcc(ch);
+		break;
+
+	case arm9_and_earlier:
+	default:
+		while (--timeout_count) {
+			can_write_arm9_dcc(reg);
+			if (reg)
+				break;
+		}
+		if (timeout_count == 0)
+			return;
+		else
+			write_arm9_dcc(ch);
+		break;
+	}
+}
+
+void arm_dcc_puts(const char *s)
+{
+	while (*s)
+		arm_dcc_putc(*s++);
+}
+
+int arm_dcc_tstc(void)
+{
+	register unsigned int reg;
+
+	switch (arm_type) {
+	case arm11_and_later:
+		can_read_arm11_dcc(reg);
+		break;
+	case arm9_and_earlier:
+	default:
+		can_read_arm9_dcc(reg);
+		break;
+	}
+
+	return reg;
+}
+
+#ifdef CONFIG_ARM_DCC_MULTI
+static device_t arm_dcc_dev;
+
+int drv_arm_dcc_init(void)
+{
+	int rc;
+
+	/* Device initialization */
+	memset(&arm_dcc_dev, 0, sizeof(arm_dcc_dev));
+
+	strcpy(arm_dcc_dev.name, "dcc");
+	arm_dcc_dev.ext = 0;	/* No extensions */
+	arm_dcc_dev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_OUTPUT;
+	arm_dcc_dev.tstc = arm_dcc_tstc;	/* 'tstc' function */
+	arm_dcc_dev.getc = arm_dcc_getc;	/* 'getc' function */
+	arm_dcc_dev.putc = arm_dcc_putc;	/* 'putc' function */
+	arm_dcc_dev.puts = arm_dcc_puts;	/* 'puts' function */
+
+	rc = device_register(&arm_dcc_dev);
+
+	if (rc == 0) {
+		arm_dcc_init();
+		return 1;
+	}
+
+	return 0;
+}
+#endif
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 1b347e9..397f5df 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -5,9 +5,6 @@
  */
 
 #include <config.h>
-
-#ifdef CONFIG_SYS_NS16550
-
 #include <ns16550.h>
 
 #define LCRVAL LCR_8N1					/* 8 data, 1 stop, no parity */
@@ -36,7 +33,7 @@ void NS16550_init (NS16550_t com_port, int baud_divisor)
 #else
 	com_port->mdr1 = 0;	/* /16 is proper to hit 115200 with 48MHz */
 #endif
-#endif
+#endif /* CONFIG_OMAP */
 }
 
 #ifndef CONFIG_NS16550_MIN_FUNCTIONS
@@ -80,4 +77,3 @@ int NS16550_tstc (NS16550_t com_port)
 }
 
 #endif /* CONFIG_NS16550_MIN_FUNCTIONS */
-#endif
diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c
index bce7548..966df9a 100644
--- a/drivers/serial/serial.c
+++ b/drivers/serial/serial.c
@@ -23,8 +23,6 @@
 
 #include <common.h>
 
-#ifdef CONFIG_SYS_NS16550_SERIAL
-
 #include <ns16550.h>
 #ifdef CONFIG_NS87308
 #include <ns87308.h>
@@ -328,5 +326,3 @@ DECLARE_ESERIAL_FUNCTIONS(4);
 struct serial_device eserial4_device =
 	INIT_ESERIAL_STRUCTURE(4,"eserial3","EUART4");
 #endif /* CONFIG_SERIAL_MULTI */
-
-#endif
diff --git a/drivers/usb/r8a66597-hcd.c b/drivers/usb/r8a66597-hcd.c
index 288f41a..db611b6 100644
--- a/drivers/usb/r8a66597-hcd.c
+++ b/drivers/usb/r8a66597-hcd.c
@@ -36,12 +36,37 @@ static unsigned short vif = CONFIG_R8A66597_LDRV;
 static unsigned short endian = CONFIG_R8A66597_ENDIAN;
 static struct r8a66597 gr8a66597;
 
-static void set_devadd_reg(struct r8a66597 *r8a66597, u8 r8a66597_address,
-			   u16 usbspd, u8 upphub, u8 hubport, int port)
+static void get_hub_data(struct usb_device *dev, u16 *hub_devnum, u16 *hubport)
 {
-	u16 val;
+	int i;
+
+	*hub_devnum = 0;
+	*hubport = 0;
+
+	/* check a device connected to root_hub */
+	if ((dev->parent && dev->parent->devnum == 1) ||
+	    (dev->devnum == 1))
+		return;
+
+	for (i = 0; i < USB_MAXCHILDREN; i++) {
+		if (dev->parent->children[i] == dev) {
+			*hub_devnum = (u8)dev->parent->devnum;
+			*hubport = i;
+			return;
+		}
+	}
+
+	printf("get_hub_data error.\n");
+}
+
+static void set_devadd(struct r8a66597 *r8a66597, u8 r8a66597_address,
+			struct usb_device *dev, int port)
+{
+	u16 val, usbspd, upphub, hubport;
 	unsigned long devadd_reg = get_devadd_addr(r8a66597_address);
 
+	get_hub_data(dev, &upphub, &hubport);
+	usbspd = r8a66597->speed;
 	val = (upphub << 11) | (hubport << 8) | (usbspd << 6) | (port & 0x0001);
 	r8a66597_write(r8a66597, val, devadd_reg);
 }
@@ -818,7 +843,7 @@ int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
 	R8A66597_DPRINT("pipe = %08x, buffer = %p, len = %d, devnum = %d\n",
 			pipe, buffer, transfer_len, dev->devnum);
 
-	set_devadd_reg(r8a66597, dev->devnum, r8a66597->speed, 0, 0, 0);
+	set_devadd(r8a66597, dev->devnum, dev, 0);
 
 	pipe_buffer_setting(r8a66597, dev, pipe);
 
@@ -854,13 +879,14 @@ int submit_control_msg(struct usb_device *dev, unsigned long pipe,
 						setup);
 
 	R8A66597_DPRINT("%s: setup\n", __func__);
-	set_devadd_reg(r8a66597, r8a66597_address, r8a66597->speed, 0, 0, 0);
+	set_devadd(r8a66597, r8a66597_address, dev, 0);
 
 	if (send_setup_packet(r8a66597, dev, setup) < 0) {
 		printf("setup packet send error\n");
 		return -1;
 	}
 
+	dev->act_len = 0;
 	if (usb_pipein(pipe))
 		if (receive_control_packet(r8a66597, dev, buffer,
 						transfer_len) < 0)