Add support for eTSEC 3 & 4 on 8548 CDS

* Added support for using eTSEC 3 and eTSEC 4 on the 8548 CDS.
  This will only work on rev 1.3 boards (but doesn't break older boards)
* Cleaned up some comments to reflect the expanded role of tsec
  in other systems

2 files changed, 76 insertions, 10 deletions

diff --git a/drivers/tsec.c b/drivers/tsec.c
index 7ec565c..bfc49c4 100644
--- a/drivers/tsec.c
+++ b/drivers/tsec.c
@@ -44,9 +44,7 @@ struct tsec_info_struct {
 
 /* The tsec_info structure contains 3 values which the
  * driver uses to determine how to operate a given ethernet
- * device.  For now, the structure is initialized with the
- * knowledge that all current implementations have 2 TSEC
- * devices, and one FEC.  The information needed is:
+ * device. The information needed is:
  *  phyaddr - The address of the PHY which is attached to
  *	the given device.
  *
@@ -56,18 +54,16 @@ struct tsec_info_struct {
  *
  *  phyregidx - This variable specifies which ethernet device
  *	controls the MII Management registers which are connected
- *	to the PHY.  For 8540/8560, only TSEC1 (index 0) has
+ *	to the PHY.  For now, only TSEC1 (index 0) has
  *	access to the PHYs, so all of the entries have "0".
  *
  * The values specified in the table are taken from the board's
  * config file in include/configs/.  When implementing a new
  * board with ethernet capability, it is necessary to define:
- *   TSEC1_PHY_ADDR
- *   TSEC1_PHYIDX
- *   TSEC2_PHY_ADDR
- *   TSEC2_PHYIDX
+ *   TSECn_PHY_ADDR
+ *   TSECn_PHYIDX
  *
- * and for 8560:
+ * for n = 1,2,3, etc.  And for FEC:
  *   FEC_PHY_ADDR
  *   FEC_PHYIDX
  */
@@ -91,7 +87,7 @@ static struct tsec_info_struct tsec_info[] = {
 	{ 0, 0, 0},
 #    endif
 #    if defined(CONFIG_MPC85XX_TSEC4) || defined(CONFIG_MPC83XX_TSEC4)
-	{TSEC4_PHY_ADDR, TSEC_REDUCED, TSEC4_PHYIDX},
+	{TSEC4_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC4_PHYIDX},
 #    else
 	{ 0, 0, 0},
 #    endif
@@ -805,6 +801,58 @@ struct phy_info phy_info_M88E1111S = {
 	},
 };
 
+static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv)
+{
+	unsigned int temp;
+	uint mii_data = read_phy_reg(priv, mii_reg);
+
+
+	/* Setting MIIM_88E1145_PHY_EXT_CR */
+	if (priv->flags & TSEC_REDUCED)
+		return mii_data |
+			MIIM_M88E1145_RGMII_RX_DELAY |
+			MIIM_M88E1145_RGMII_TX_DELAY;
+	else
+		return mii_data;
+}
+
+static struct phy_info phy_info_M88E1145 = {
+	0x01410cd,
+	"Marvell 88E1145",
+	4,
+	(struct phy_cmd[]) { /* config */
+		/* Errata E0, E1 */
+		{29, 0x001b, NULL},
+		{30, 0x418f, NULL},
+		{29, 0x0016, NULL},
+		{30, 0xa2da, NULL},
+
+		/* Reset and configure the PHY */
+		{MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
+		{MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
+		{MIIM_ANAR, MIIM_ANAR_INIT, NULL},
+		{MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO, NULL},
+		{MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode},
+		{MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
+		{MIIM_CONTROL, MIIM_CONTROL_INIT, NULL},
+		{miim_end,}
+	},
+	(struct phy_cmd[]) { /* startup */
+		/* Status is read once to clear old link state */
+		{MIIM_STATUS, miim_read, NULL},
+		/* Auto-negotiate */
+		{MIIM_STATUS, miim_read, &mii_parse_sr},
+		{MIIM_88E1111_PHY_LED_CONTROL, MIIM_88E1111_PHY_LED_DIRECT, NULL},
+		/* Read the Status */
+		{MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr},
+		{miim_end,}
+	},
+	(struct phy_cmd[]) { /* shutdown */
+		{miim_end,}
+	},
+};
+
+
 struct phy_info phy_info_cis8204 = {
 	0x3f11,
 	"Cicada Cis8204",
@@ -999,6 +1047,7 @@ struct phy_info *phy_info[] = {
 	&phy_info_cis8204,
 	&phy_info_M88E1011S,
 	&phy_info_M88E1111S,
+	&phy_info_M88E1145,
 	&phy_info_dm9161,
 	&phy_info_lxt971,
 	&phy_info_dp83865,
diff --git a/drivers/tsec.h b/drivers/tsec.h
index b55b299..0bfca3a 100644
--- a/drivers/tsec.h
+++ b/drivers/tsec.h
@@ -142,6 +142,23 @@
 #define MIIM_88E1011_PHYSTAT_SPDDONE	0x0800
 #define MIIM_88E1011_PHYSTAT_LINK	0x0400
 
+#define MIIM_88E1011_PHY_SCR		0x10
+#define MIIM_88E1011_PHY_MDI_X_AUTO	0x0060
+
+/* 88E1111 PHY LED Control Register */
+#define MIIM_88E1111_PHY_LED_CONTROL   24
+#define MIIM_88E1111_PHY_LED_DIRECT    0x4100
+#define MIIM_88E1111_PHY_LED_COMBINE   0x411C
+
+/* 88E1145 Extended PHY Specific Control Register */
+#define MIIM_88E1145_PHY_EXT_CR 20
+#define MIIM_M88E1145_RGMII_RX_DELAY	0x0080
+#define MIIM_M88E1145_RGMII_TX_DELAY	0x0002
+
+#define MIIM_88E1145_PHY_PAGE   29
+#define MIIM_88E1145_PHY_CAL_OV 30
+
+
 /* DM9161 Control register values */
 #define MIIM_DM9161_CR_STOP	0x0400
 #define MIIM_DM9161_CR_RSTAN	0x1200