diff options
| author | Marcel Ziswiler <marcel@ziswiler.com> | 2014-10-21 14:26:36 +0200 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2014-10-27 17:54:10 -0400 |
| commit | 17da7120249bfdef877f46be5bbcb3cc01212eb9 (patch) | |
| tree | 2a77ad151420d6af144253aac8437ebd9879f5a9 /drivers | |
| parent | b265d0c45902990cb9fedf8080094b07c877d500 (diff) | |
| download | u-boot-imx-17da7120249bfdef877f46be5bbcb3cc01212eb9.zip u-boot-imx-17da7120249bfdef877f46be5bbcb3cc01212eb9.tar.gz u-boot-imx-17da7120249bfdef877f46be5bbcb3cc01212eb9.tar.bz2 | |
e1000: fix sw fw sync on igb i210/i211
I finally had a look at the datasheet and spotted an additional
register address difference between regular E1000 and i210/i211 chips.
This patch fixes this and now successfully works on programmed
i210/i211 as well as unprogrammed i211.
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/net/e1000.c | 6 | ||||
| -rw-r--r-- | drivers/net/e1000.h | 1 |
2 files changed, 5 insertions, 2 deletions
diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index b092867..798c8aa 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -1112,7 +1112,10 @@ e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask) if (e1000_get_hw_eeprom_semaphore(hw)) return -E1000_ERR_SWFW_SYNC; - swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); + if (hw->mac_type == e1000_igb) + swfw_sync = E1000_READ_REG(hw, I210_SW_FW_SYNC); + else + swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); if (!(swfw_sync & (fwmask | swmask))) break; @@ -4429,7 +4432,6 @@ e1000_phy_hw_reset(struct e1000_hw *hw) if (hw->mac_type >= e1000_82571) mdelay(10); - } else { /* Read the Extended Device Control Register, assert the PHY_RESET_DIR * bit to put the PHY into reset. Then, take it out of reset. diff --git a/drivers/net/e1000.h b/drivers/net/e1000.h index b025ecc..6d110eb 100644 --- a/drivers/net/e1000.h +++ b/drivers/net/e1000.h @@ -2497,6 +2497,7 @@ struct e1000_hw { #define ICH_GFPREG_BASE_MASK 0x1FFF #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF +#define E1000_I210_SW_FW_SYNC 0x5B50 /* Software-Firmware Synchronization - RW */ #define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */ /* SPI EEPROM Status Register */ |