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| author | York Sun <yorksun@freescale.com> | 2014-12-08 15:30:55 -0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-01-23 22:29:13 -0600 |
| commit | dda3b610eee9dcd433627202584ded417327dd51 (patch) | |
| tree | de7d6037e6730f3fd9bc2baa086dd74f449d0fd6 /drivers | |
| parent | 37b608a52dcb13312a4f7ccea199cd6bac76d298 (diff) | |
| download | u-boot-imx-dda3b610eee9dcd433627202584ded417327dd51.zip u-boot-imx-dda3b610eee9dcd433627202584ded417327dd51.tar.gz u-boot-imx-dda3b610eee9dcd433627202584ded417327dd51.tar.bz2 | |
arm/ls1021a: Add workaround for DDR erratum A008378
Internal memory controller counters can reach a bad state after
training in DDR4 mode if accumulated ECC or DBI mode is eanbled.
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/ddr/fsl/fsl_ddr_gen4.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c index a3c01e7..4eef047 100644 --- a/drivers/ddr/fsl/fsl_ddr_gen4.c +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c @@ -171,6 +171,14 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, ddr_out32(&ddr->debug[i], regs->debug[i]); } } +#ifdef CONFIG_SYS_FSL_ERRATUM_A008378 + /* Erratum applies when accumulated ECC is used, or DBI is enabled */ +#define IS_ACC_ECC_EN(v) ((v) & 0x4) +#define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2) + if (IS_ACC_ECC_EN(regs->ddr_sdram_cfg) || + IS_DBI(regs->ddr_sdram_cfg_3)) + ddr_setbits32(ddr->debug[28], 0x9 << 20); +#endif /* * For RDIMMs, JEDEC spec requires clocks to be stable before reset is |