fpga: xilinx: Avoid CamelCase for in Xilinx_desc

No functional changes.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

5 files changed, 47 insertions, 47 deletions

diff --git a/drivers/fpga/spartan2.c b/drivers/fpga/spartan2.c
index bd31709..0796729 100644
--- a/drivers/fpga/spartan2.c
+++ b/drivers/fpga/spartan2.c
@@ -31,17 +31,17 @@
 #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100	/* 10 ms */
 #endif
 
-static int spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize);
-static int spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
-/* static int spartan2_sp_info(Xilinx_desc *desc ); */
+static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize);
+static int spartan2_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize);
+/* static int spartan2_sp_info(xilinx_desc *desc ); */
 
-static int spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize);
-static int spartan2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
-/* static int spartan2_ss_info(Xilinx_desc *desc ); */
+static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize);
+static int spartan2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize);
+/* static int spartan2_ss_info(xilinx_desc *desc ); */
 
 /* ------------------------------------------------------------------------- */
 /* Spartan-II Generic Implementation */
-int spartan2_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+int spartan2_load(xilinx_desc *desc, const void *buf, size_t bsize)
 {
 	int ret_val = FPGA_FAIL;
 
@@ -64,7 +64,7 @@ int spartan2_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 	return ret_val;
 }
 
-int spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+int spartan2_dump(xilinx_desc *desc, const void *buf, size_t bsize)
 {
 	int ret_val = FPGA_FAIL;
 
@@ -87,7 +87,7 @@ int spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
 	return ret_val;
 }
 
-int spartan2_info(Xilinx_desc *desc)
+int spartan2_info(xilinx_desc *desc)
 {
 	return FPGA_SUCCESS;
 }
@@ -96,7 +96,7 @@ int spartan2_info(Xilinx_desc *desc)
 /* ------------------------------------------------------------------------- */
 /* Spartan-II Slave Parallel Generic Implementation */
 
-static int spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
 {
 	int ret_val = FPGA_FAIL;	/* assume the worst */
 	xilinx_spartan2_slave_parallel_fns *fn = desc->iface_fns;
@@ -248,7 +248,7 @@ static int spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 	return ret_val;
 }
 
-static int spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan2_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize)
 {
 	int ret_val = FPGA_FAIL;	/* assume the worst */
 	xilinx_spartan2_slave_parallel_fns *fn = desc->iface_fns;
@@ -296,7 +296,7 @@ static int spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
 
 /* ------------------------------------------------------------------------- */
 
-static int spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
 {
 	int ret_val = FPGA_FAIL;	/* assume the worst */
 	xilinx_spartan2_slave_serial_fns *fn = desc->iface_fns;
@@ -439,7 +439,7 @@ static int spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 	return ret_val;
 }
 
-static int spartan2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize)
 {
 	/* Readback is only available through the Slave Parallel and         */
 	/* boundary-scan interfaces.                                         */
diff --git a/drivers/fpga/spartan3.c b/drivers/fpga/spartan3.c
index e40abbf..1304b4c 100644
--- a/drivers/fpga/spartan3.c
+++ b/drivers/fpga/spartan3.c
@@ -35,17 +35,17 @@
 #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100	/* 10 ms */
 #endif
 
-static int spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize);
-static int spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
-/* static int spartan3_sp_info(Xilinx_desc *desc ); */
+static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize);
+static int spartan3_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize);
+/* static int spartan3_sp_info(xilinx_desc *desc ); */
 
-static int spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize);
-static int spartan3_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
-/* static int spartan3_ss_info(Xilinx_desc *desc); */
+static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize);
+static int spartan3_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize);
+/* static int spartan3_ss_info(xilinx_desc *desc); */
 
 /* ------------------------------------------------------------------------- */
 /* Spartan-II Generic Implementation */
-int spartan3_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+int spartan3_load(xilinx_desc *desc, const void *buf, size_t bsize)
 {
 	int ret_val = FPGA_FAIL;
 
@@ -68,7 +68,7 @@ int spartan3_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 	return ret_val;
 }
 
-int spartan3_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+int spartan3_dump(xilinx_desc *desc, const void *buf, size_t bsize)
 {
 	int ret_val = FPGA_FAIL;
 
@@ -91,7 +91,7 @@ int spartan3_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
 	return ret_val;
 }
 
-int spartan3_info(Xilinx_desc *desc)
+int spartan3_info(xilinx_desc *desc)
 {
 	return FPGA_SUCCESS;
 }
@@ -100,7 +100,7 @@ int spartan3_info(Xilinx_desc *desc)
 /* ------------------------------------------------------------------------- */
 /* Spartan-II Slave Parallel Generic Implementation */
 
-static int spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
 {
 	int ret_val = FPGA_FAIL;	/* assume the worst */
 	xilinx_spartan3_slave_parallel_fns *fn = desc->iface_fns;
@@ -254,7 +254,7 @@ static int spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 	return ret_val;
 }
 
-static int spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan3_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize)
 {
 	int ret_val = FPGA_FAIL;	/* assume the worst */
 	xilinx_spartan3_slave_parallel_fns *fn = desc->iface_fns;
@@ -302,7 +302,7 @@ static int spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
 
 /* ------------------------------------------------------------------------- */
 
-static int spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
 {
 	int ret_val = FPGA_FAIL;	/* assume the worst */
 	xilinx_spartan3_slave_serial_fns *fn = desc->iface_fns;
@@ -457,7 +457,7 @@ static int spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 	return ret_val;
 }
 
-static int spartan3_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan3_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize)
 {
 	/* Readback is only available through the Slave Parallel and         */
 	/* boundary-scan interfaces.                                         */
diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c
index 1cd9046..a582bf2 100644
--- a/drivers/fpga/virtex2.c
+++ b/drivers/fpga/virtex2.c
@@ -84,13 +84,13 @@
 #define CONFIG_SYS_FPGA_WAIT_CONFIG	CONFIG_SYS_HZ/5	/* 200 ms */
 #endif
 
-static int virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize);
-static int virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
+static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize);
+static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize);
 
-static int virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize);
-static int virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
+static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize);
+static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize);
 
-int virtex2_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize)
 {
 	int ret_val = FPGA_FAIL;
 
@@ -112,7 +112,7 @@ int virtex2_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 	return ret_val;
 }
 
-int virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+int virtex2_dump(xilinx_desc *desc, const void *buf, size_t bsize)
 {
 	int ret_val = FPGA_FAIL;
 
@@ -134,7 +134,7 @@ int virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
 	return ret_val;
 }
 
-int virtex2_info(Xilinx_desc *desc)
+int virtex2_info(xilinx_desc *desc)
 {
 	return FPGA_SUCCESS;
 }
@@ -153,7 +153,7 @@ int virtex2_info(Xilinx_desc *desc)
  *    INIT_B and DONE lines.  If both are high, configuration has
  *    succeeded. Congratulations!
  */
-static int virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
 {
 	int ret_val = FPGA_FAIL;
 	xilinx_virtex2_slave_selectmap_fns *fn = desc->iface_fns;
@@ -352,7 +352,7 @@ static int virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 /*
  * Read the FPGA configuration data
  */
-static int virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize)
 {
 	int ret_val = FPGA_FAIL;
 	xilinx_virtex2_slave_selectmap_fns *fn = desc->iface_fns;
@@ -404,13 +404,13 @@ static int virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
 	return ret_val;
 }
 
-static int virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
 {
 	printf ("%s: Slave Serial Loading is unsupported\n", __FUNCTION__);
 	return FPGA_FAIL;
 }
 
-static int virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize)
 {
 	printf ("%s: Slave Serial Dumping is unsupported\n", __FUNCTION__);
 	return FPGA_FAIL;
diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c
index 6953535..b0e9cb3 100644
--- a/drivers/fpga/xilinx.c
+++ b/drivers/fpga/xilinx.c
@@ -31,7 +31,7 @@
 #endif
 
 /* Local Static Functions */
-static int xilinx_validate (Xilinx_desc * desc, char *fn);
+static int xilinx_validate(xilinx_desc *desc, char *fn);
 
 /* ------------------------------------------------------------------------- */
 
@@ -43,7 +43,7 @@ int fpga_loadbitstream(int devnum, char *fpgadata, size_t size)
 	unsigned char *dataptr;
 	unsigned int i;
 	const fpga_desc *desc;
-	Xilinx_desc *xdesc;
+	xilinx_desc *xdesc;
 
 	dataptr = (unsigned char *)fpgadata;
 	/* Find out fpga_description */
@@ -94,7 +94,7 @@ int fpga_loadbitstream(int devnum, char *fpgadata, size_t size)
 			return FPGA_FAIL;
 		}
 	} else {
-		printf("%s: Please fill correct device ID to Xilinx_desc\n",
+		printf("%s: Please fill correct device ID to xilinx_desc\n",
 		       __func__);
 	}
 	printf("  part number = \"%s\"\n", buffer);
@@ -141,7 +141,7 @@ int fpga_loadbitstream(int devnum, char *fpgadata, size_t size)
 	return fpga_load(devnum, dataptr, swapsize);
 }
 
-int xilinx_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+int xilinx_load(xilinx_desc *desc, const void *buf, size_t bsize)
 {
 	int ret_val = FPGA_FAIL;	/* assume a failure */
 
@@ -198,7 +198,7 @@ int xilinx_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 	return ret_val;
 }
 
-int xilinx_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize)
 {
 	int ret_val = FPGA_FAIL;	/* assume a failure */
 
@@ -255,7 +255,7 @@ int xilinx_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
 	return ret_val;
 }
 
-int xilinx_info (Xilinx_desc * desc)
+int xilinx_info(xilinx_desc *desc)
 {
 	int ret_val = FPGA_FAIL;
 
@@ -369,7 +369,7 @@ int xilinx_info (Xilinx_desc * desc)
 
 /* ------------------------------------------------------------------------- */
 
-static int xilinx_validate (Xilinx_desc * desc, char *fn)
+static int xilinx_validate(xilinx_desc *desc, char *fn)
 {
 	int ret_val = false;
 
diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c
index 923a158..b4d0e22 100644
--- a/drivers/fpga/zynqpl.c
+++ b/drivers/fpga/zynqpl.c
@@ -36,7 +36,7 @@
 #define CONFIG_SYS_FPGA_PROG_TIME	(CONFIG_SYS_HZ * 4) /* 4 s */
 #endif
 
-int zynq_info(Xilinx_desc *desc)
+int zynq_info(xilinx_desc *desc)
 {
 	return FPGA_SUCCESS;
 }
@@ -153,7 +153,7 @@ static void *check_data(u8 *buf, size_t bsize, u32 *swap)
 }
 
 
-int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize)
 {
 	unsigned long ts; /* Timestamp */
 	u32 partialbit = 0;
@@ -358,7 +358,7 @@ int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 	return FPGA_SUCCESS;
 }
 
-int zynq_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+int zynq_dump(xilinx_desc *desc, const void *buf, size_t bsize)
 {
 	return FPGA_FAIL;
 }