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authorFelix Radensky <felix@embedded-sol.com>2010-06-28 01:57:39 +0300
committerWolfgang Denk <wd@denx.de>2010-06-29 23:03:23 +0200
commitc987f4753b0afadb38acd7e61df7ba11e8a0203f (patch)
tree319f90bd75fcc28742fb6b76b5bb30dfc3316709 /drivers
parentd3bee08332fbc9cc5b6dc22ecd34050a85d44d0a (diff)
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tsec: Fix eTSEC2 link problem on P2020RDB
On P2020RDB eTSEC2 is connected to Vitesse VSC8221 PHY via SGMII. Current TBI PHY settings for SGMII mode cause link problems on this platform, link never comes up. Fix this by making TBI PHY settings configurable and add a working configuration for P2020RDB. Signed-off-by: Felix Radensky <felix@embedded-sol.com> Acked-by: Andy Fleming <afleming@freescale.com> Acked-by: Peter Tyser <ptyser@xes-inc.com> Tested-by: Peter Tyser <ptyser@xes-inc.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/tsec.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index 3e4c3bd..5fa6f61 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -281,12 +281,16 @@ static uint tsec_local_mdio_read(volatile tsec_mdio_t *phyregs,
| TBIANA_FULL_DUPLEX \
)
-/* Force the TBI PHY into 1000Mbps full duplex when in SGMII mode */
+/* By default force the TBI PHY into 1000Mbps full duplex when in SGMII mode */
+#ifndef CONFIG_TSEC_TBICR_SETTINGS
#define TBICR_SETTINGS ( \
TBICR_PHY_RESET \
| TBICR_FULL_DUPLEX \
| TBICR_SPEED1_SET \
)
+#else
+#define TBICR_SETTINGS CONFIG_TSEC_TBICR_SETTINGS
+#endif /* CONFIG_TSEC_TBICR_SETTINGS */
/* Configure the TBI for SGMII operation */
static void tsec_configure_serdes(struct tsec_private *priv)