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| author | Roy Zang <tie-fei.zang@freescale.com> | 2013-03-25 07:33:23 +0000 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2013-05-14 16:00:28 -0500 |
| commit | 1e501f913667a5ce8ed139410ec71bc50c306a1c (patch) | |
| tree | a24d669838997236c2423b1fe3e4a037d95cfb9f /drivers | |
| parent | 97c7fe61b84bf836ccf3d9aac624d4241f6e3b4c (diff) | |
| download | u-boot-imx-1e501f913667a5ce8ed139410ec71bc50c306a1c.zip u-boot-imx-1e501f913667a5ce8ed139410ec71bc50c306a1c.tar.gz u-boot-imx-1e501f913667a5ce8ed139410ec71bc50c306a1c.tar.bz2 | |
T4/USB: Add USB 2.0 UTMI dual phy support
T4240 internal UTMI phy is different comparing to previous UTMI PHY
in P3041.
This patch adds USB 2.0 UTMI Dual PHY new memory map and enable it for
T4240.
The phy timing is very sensitive and moving the phy enable code to
cpu_init.c will not work.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/usb/host/ehci-fsl.c | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index f54b408..77c41f3 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -89,6 +89,27 @@ int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) if (!strcmp(phy_type, "utmi")) { #if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY) +#if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE) + ccsr_usb_phy_t *usb_phy = + (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; + setbits_be32(&usb_phy->pllprg[1], + CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN | + CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN | + CONFIG_SYS_FSL_USB_PLLPRG2_MFI | + CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN); + setbits_be32(&usb_phy->port1.ctrl, + CONFIG_SYS_FSL_USB_CTRL_PHY_EN); + setbits_be32(&usb_phy->port1.drvvbuscfg, + CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN); + setbits_be32(&usb_phy->port1.pwrfltcfg, + CONFIG_SYS_FSL_USB_PWRFLT_CR_EN); + setbits_be32(&usb_phy->port2.ctrl, + CONFIG_SYS_FSL_USB_CTRL_PHY_EN); + setbits_be32(&usb_phy->port2.drvvbuscfg, + CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN); + setbits_be32(&usb_phy->port2.pwrfltcfg, + CONFIG_SYS_FSL_USB_PWRFLT_CR_EN); +#endif setbits_be32(&ehci->control, PHY_CLK_SEL_UTMI); setbits_be32(&ehci->control, UTMI_PHY_EN); udelay(1000); /* delay required for PHY Clk to appear */ |