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author | Tom Rini <trini@ti.com> | 2014-01-20 07:51:22 -0500 |
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committer | Tom Rini <trini@ti.com> | 2014-01-20 07:51:22 -0500 |
commit | 55ca99f8940e230366cadd522702fac9f962e904 (patch) | |
tree | d767ca262f9d015df4b1c18aa80468a97fccdc5c /drivers | |
parent | 4641c211f6e37454c30770521c4de79c725036b0 (diff) | |
parent | dccacbe01968f9e682cb1dc9b7d43c831897cbec (diff) | |
download | u-boot-imx-55ca99f8940e230366cadd522702fac9f962e904.zip u-boot-imx-55ca99f8940e230366cadd522702fac9f962e904.tar.gz u-boot-imx-55ca99f8940e230366cadd522702fac9f962e904.tar.bz2 |
Merge branch 'master' of git://git.denx.de/u-boot-i2c
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/i2c/designware_i2c.c | 38 | ||||
-rw-r--r-- | drivers/i2c/fti2c010.c | 4 | ||||
-rw-r--r-- | drivers/i2c/i2c_core.c | 2 | ||||
-rw-r--r-- | drivers/i2c/rcar_i2c.c | 6 |
4 files changed, 45 insertions, 5 deletions
diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c index cb2ac04..9ed9295 100644 --- a/drivers/i2c/designware_i2c.c +++ b/drivers/i2c/designware_i2c.c @@ -266,6 +266,25 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) { unsigned long start_time_rx; +#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW + /* + * EEPROM chips that implement "address overflow" are ones + * like Catalyst 24WC04/08/16 which has 9/10/11 bits of + * address and the extra bits end up in the "chip address" + * bit slots. This makes a 24WC08 (1Kbyte) chip look like + * four 256 byte chips. + * + * Note that we consider the length of the address field to + * still be one byte because the extra address bits are + * hidden in the chip address. + */ + chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); + addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8)); + + debug("%s: fix addr_overflow: chip %02x addr %02x\n", __func__, chip, + addr); +#endif + if (check_params(addr, alen, buffer, len)) return 1; @@ -307,6 +326,25 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) int nb = len; unsigned long start_time_tx; +#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW + /* + * EEPROM chips that implement "address overflow" are ones + * like Catalyst 24WC04/08/16 which has 9/10/11 bits of + * address and the extra bits end up in the "chip address" + * bit slots. This makes a 24WC08 (1Kbyte) chip look like + * four 256 byte chips. + * + * Note that we consider the length of the address field to + * still be one byte because the extra address bits are + * hidden in the chip address. + */ + chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); + addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8)); + + debug("%s: fix addr_overflow: chip %02x addr %02x\n", __func__, chip, + addr); +#endif + if (check_params(addr, alen, buffer, len)) return 1; diff --git a/drivers/i2c/fti2c010.c b/drivers/i2c/fti2c010.c index fb9fa35..68d9a42 100644 --- a/drivers/i2c/fti2c010.c +++ b/drivers/i2c/fti2c010.c @@ -201,7 +201,7 @@ static int fti2c010_read(struct i2c_adapter *adap, struct fti2c010_chip *chip = chip_list + adap->hwadapnr; struct fti2c010_regs *regs = chip->regs; int ret, pos; - uchar paddr[4]; + uchar paddr[4] = { 0 }; to_i2c_addr(paddr, addr, alen); @@ -263,7 +263,7 @@ static int fti2c010_write(struct i2c_adapter *adap, struct fti2c010_chip *chip = chip_list + adap->hwadapnr; struct fti2c010_regs *regs = chip->regs; int ret, pos; - uchar paddr[4]; + uchar paddr[4] = { 0 }; to_i2c_addr(paddr, addr, alen); diff --git a/drivers/i2c/i2c_core.c b/drivers/i2c/i2c_core.c index e1767f4..18d6736 100644 --- a/drivers/i2c/i2c_core.c +++ b/drivers/i2c/i2c_core.c @@ -349,7 +349,7 @@ unsigned int i2c_set_bus_speed(unsigned int speed) return 0; ret = I2C_ADAP->set_bus_speed(I2C_ADAP, speed); if (gd->flags & GD_FLG_RELOC) - I2C_ADAP->speed = ret; + I2C_ADAP->speed = (ret == 0) ? speed : 0; return ret; } diff --git a/drivers/i2c/rcar_i2c.c b/drivers/i2c/rcar_i2c.c index ba2cadb..50cebd6 100644 --- a/drivers/i2c/rcar_i2c.c +++ b/drivers/i2c/rcar_i2c.c @@ -119,11 +119,13 @@ rcar_i2c_raw_read(struct rcar_i2c *dev, u8 chip, uint addr) /* set slave address, receive */ writel((chip << 1) | 1, &dev->icmar); + /* clear status */ + writel(0, &dev->icmsr); /* start master receive */ writel(MCR_MDBS | MCR_MIE | MCR_ESG, &dev->icmcr); - while ((readl(&dev->icmsr) & (MSR_MAT | MSR_MDE)) - != (MSR_MAT | MSR_MDE)) + while ((readl(&dev->icmsr) & (MSR_MAT | MSR_MDR)) + != (MSR_MAT | MSR_MDR)) udelay(10); /* clear ESG */ |