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| author | Liu Ying <Ying.Liu@freescale.com> | 2013-06-07 09:24:16 +0800 |
|---|---|---|
| committer | Liu Ying <Ying.Liu@freescale.com> | 2013-06-17 08:41:58 +0800 |
| commit | 7ef2b6342676be01cb3a5656919292ce935c5082 (patch) | |
| tree | 52a17092814e2369234a2ae3f1f3df76150814ff /drivers | |
| parent | 56f7baefe24f20c9e7b134bd8c904d08ee9e7a70 (diff) | |
| download | u-boot-imx-7ef2b6342676be01cb3a5656919292ce935c5082.zip u-boot-imx-7ef2b6342676be01cb3a5656919292ce935c5082.tar.gz u-boot-imx-7ef2b6342676be01cb3a5656919292ce935c5082.tar.bz2 | |
ENGR00267118-2 IPU disp:Align setting with kernel
To align with kernel display setting so that we may
avoid a blank interval during smooth UI transition
from uboot to Android desktop on LVDS0(LVDS1 is OK).
The code change refers to the following CR:
"ENGR00214565 MX6x, IPUv3: Display lack last horizontal
pixel"
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/video/ipu_disp.c | 17 |
1 files changed, 10 insertions, 7 deletions
diff --git a/drivers/video/ipu_disp.c b/drivers/video/ipu_disp.c index b9281ff..fef538e 100644 --- a/drivers/video/ipu_disp.c +++ b/drivers/video/ipu_disp.c @@ -51,6 +51,7 @@ struct dp_csc_param_t { }; #define SYNC_WAVE 0 +#define NULL_WAVE (-1) /* DC display ID assignments */ #define DC_DISP_ID_SYNC(di) (di) @@ -567,12 +568,12 @@ void ipu_dc_init(int dc_chan, int di, unsigned char interlaced) ipu_dc_link_event(dc_chan, DC_EVT_NL, 2, 3); ipu_dc_link_event(dc_chan, DC_EVT_EOL, 3, 2); ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA, - 4, 1); + 1, 1); } else { ipu_dc_link_event(dc_chan, DC_EVT_NL, 5, 3); ipu_dc_link_event(dc_chan, DC_EVT_EOL, 6, 2); ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA, - 7, 1); + 12, 1); } } ipu_dc_link_event(dc_chan, DC_EVT_NF, 0, 0); @@ -1208,12 +1209,14 @@ int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk, /* Init template microcode */ if (disp) { ipu_dc_write_tmpl(2, WROD(0), 0, map, SYNC_WAVE, 8, 5, 1); - ipu_dc_write_tmpl(3, WROD(0), 0, map, SYNC_WAVE, 4, 5, 1); - ipu_dc_write_tmpl(4, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1); + ipu_dc_write_tmpl(3, WROD(0), 0, map, SYNC_WAVE, 4, 5, 0); + ipu_dc_write_tmpl(4, WRG, 0, map, NULL_WAVE, 0, 0, 1); + ipu_dc_write_tmpl(1, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1); } else { - ipu_dc_write_tmpl(5, WROD(0), 0, map, SYNC_WAVE, 8, 5, 1); - ipu_dc_write_tmpl(6, WROD(0), 0, map, SYNC_WAVE, 4, 5, 1); - ipu_dc_write_tmpl(7, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1); + ipu_dc_write_tmpl(5, WROD(0), 0, map, SYNC_WAVE, 8, 5, 1); + ipu_dc_write_tmpl(6, WROD(0), 0, map, SYNC_WAVE, 4, 5, 0); + ipu_dc_write_tmpl(7, WRG, 0, map, NULL_WAVE, 0, 0, 1); + ipu_dc_write_tmpl(12, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1); } if (sig.Hsync_pol) |