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author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-01-19 13:55:28 +0900 |
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committer | Simon Glass <sjg@chromium.org> | 2016-01-21 19:46:47 -0700 |
commit | b21e20b255a02393727c93b1927a381ce3008fa4 (patch) | |
tree | d965a28a41a19863a08066dbe4abc9d60787315f /drivers | |
parent | 6905f4d3c7be46fed4859f51f0a8f9a1107c22e7 (diff) | |
download | u-boot-imx-b21e20b255a02393727c93b1927a381ce3008fa4.zip u-boot-imx-b21e20b255a02393727c93b1927a381ce3008fa4.tar.gz u-boot-imx-b21e20b255a02393727c93b1927a381ce3008fa4.tar.bz2 |
clk: add fixed rate clock driver
This commit intends to implement "fixed-clock" as in Linux.
(drivers/clk/clk-fixed-rate.c in Linux)
If you need a very simple clock to just provide fixed clock rate
like a crystal oscillator, you do not have to write a new driver.
This driver can support it.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/clk/Makefile | 2 | ||||
-rw-r--r-- | drivers/clk/clk_fixed_rate.c | 57 |
2 files changed, 58 insertions, 1 deletions
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 4a6a4a8..8aa81f4 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -5,7 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-$(CONFIG_CLK) += clk-uclass.o +obj-$(CONFIG_CLK) += clk-uclass.o clk_fixed_rate.o obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o obj-$(CONFIG_SANDBOX) += clk_sandbox.o diff --git a/drivers/clk/clk_fixed_rate.c b/drivers/clk/clk_fixed_rate.c new file mode 100644 index 0000000..8beda9c --- /dev/null +++ b/drivers/clk/clk_fixed_rate.c @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <clk.h> +#include <dm/device.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct clk_fixed_rate { + unsigned long fixed_rate; +}; + +#define to_clk_fixed_rate(dev) ((struct clk_fixed_rate *)dev_get_platdata(dev)) + +static ulong clk_fixed_rate_get_rate(struct udevice *dev) +{ + return to_clk_fixed_rate(dev)->fixed_rate; +} + +static ulong clk_fixed_rate_get_periph_rate(struct udevice *dev, int periph) +{ + return clk_fixed_rate_get_rate(dev); +} + +const struct clk_ops clk_fixed_rate_ops = { + .get_rate = clk_fixed_rate_get_rate, + .get_periph_rate = clk_fixed_rate_get_periph_rate, +}; + +static int clk_fixed_rate_ofdata_to_platdata(struct udevice *dev) +{ + to_clk_fixed_rate(dev)->fixed_rate = + fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "clock-frequency", 0); + + return 0; +} + +static const struct udevice_id clk_fixed_rate_match[] = { + { + .compatible = "fixed-clock", + }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(clk_fixed_rate) = { + .name = "fixed_rate_clock", + .id = UCLASS_CLK, + .of_match = clk_fixed_rate_match, + .ofdata_to_platdata = clk_fixed_rate_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct clk_fixed_rate), + .ops = &clk_fixed_rate_ops, +}; |