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authorWolfgang Denk <wd@denx.de>2010-05-21 22:22:23 +0200
committerWolfgang Denk <wd@denx.de>2010-05-21 22:22:23 +0200
commit8a452c2c17bc284e3f91b8ed4aec9d2b9b342df7 (patch)
tree95d411f913fa4634df6ba86ce7af4bbbe98a92c0 /drivers
parent445093d175b06226549680b6894923bb0f5e50fa (diff)
parent03af5abd85637d27e96fb999ce6e3992293570b0 (diff)
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Merge branch 'master' of git://git.denx.de/u-boot-imx
Diffstat (limited to 'drivers')
-rw-r--r--drivers/misc/Makefile1
-rw-r--r--drivers/misc/fsl_pmic.c200
-rw-r--r--drivers/rtc/mc13783-rtc.c72
-rw-r--r--drivers/spi/mxc_spi.c231
-rw-r--r--drivers/video/mx3fb.c47
5 files changed, 458 insertions, 93 deletions
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index f6df60f..96aa331 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -31,6 +31,7 @@ COBJS-$(CONFIG_FSL_LAW) += fsl_law.o
COBJS-$(CONFIG_NS87308) += ns87308.o
COBJS-$(CONFIG_STATUS_LED) += status_led.o
COBJS-$(CONFIG_TWL4030_LED) += twl4030_led.o
+COBJS-$(CONFIG_FSL_PMIC) += fsl_pmic.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff --git a/drivers/misc/fsl_pmic.c b/drivers/misc/fsl_pmic.c
new file mode 100644
index 0000000..87f0aed
--- /dev/null
+++ b/drivers/misc/fsl_pmic.c
@@ -0,0 +1,200 @@
+/*
+ * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <spi.h>
+#include <asm/errno.h>
+#include <linux/types.h>
+#include <fsl_pmic.h>
+
+static struct spi_slave *slave;
+
+struct spi_slave *pmic_spi_probe(void)
+{
+ return spi_setup_slave(CONFIG_FSL_PMIC_BUS,
+ CONFIG_FSL_PMIC_CS,
+ CONFIG_FSL_PMIC_CLK,
+ CONFIG_FSL_PMIC_MODE);
+}
+
+void pmic_spi_free(struct spi_slave *slave)
+{
+ if (slave)
+ spi_free_slave(slave);
+}
+
+u32 pmic_reg(u32 reg, u32 val, u32 write)
+{
+ u32 pmic_tx, pmic_rx;
+
+ if (!slave) {
+ slave = pmic_spi_probe();
+
+ if (!slave)
+ return -1;
+ }
+
+ if (reg > 63 || write > 1) {
+ printf("<reg num> = %d is invalid. Should be less then 63\n",
+ reg);
+ return -1;
+ }
+
+ if (spi_claim_bus(slave))
+ return -1;
+
+ pmic_tx = (write << 31) | (reg << 25) | (val & 0x00FFFFFF);
+
+ if (spi_xfer(slave, 4 << 3, &pmic_tx, &pmic_rx,
+ SPI_XFER_BEGIN | SPI_XFER_END)) {
+ spi_release_bus(slave);
+ return -1;
+ }
+
+ if (write) {
+ pmic_tx &= ~(1 << 31);
+ if (spi_xfer(slave, 4 << 3, &pmic_tx, &pmic_rx,
+ SPI_XFER_BEGIN | SPI_XFER_END)) {
+ spi_release_bus(slave);
+ return -1;
+ }
+ }
+
+ spi_release_bus(slave);
+ return pmic_rx;
+}
+
+void pmic_reg_write(u32 reg, u32 value)
+{
+ pmic_reg(reg, value, 1);
+}
+
+u32 pmic_reg_read(u32 reg)
+{
+ return pmic_reg(reg, 0, 0);
+}
+
+void pmic_show_pmic_info(void)
+{
+ u32 rev_id;
+
+ rev_id = pmic_reg_read(REG_IDENTIFICATION);
+ printf("PMIC ID: 0x%08x [Rev: ", rev_id);
+ switch (rev_id & 0x1F) {
+ case 0x1:
+ puts("1.0");
+ break;
+ case 0x9:
+ puts("1.1");
+ break;
+ case 0xA:
+ puts("1.2");
+ break;
+ case 0x10:
+ puts("2.0");
+ break;
+ case 0x11:
+ puts("2.1");
+ break;
+ case 0x18:
+ puts("3.0");
+ break;
+ case 0x19:
+ puts("3.1");
+ break;
+ case 0x1A:
+ puts("3.2");
+ break;
+ case 0x2:
+ puts("3.2A");
+ break;
+ case 0x1B:
+ puts("3.3");
+ break;
+ case 0x1D:
+ puts("3.5");
+ break;
+ default:
+ puts("unknown");
+ break;
+ }
+ puts("]\n");
+}
+
+static void pmic_dump(int numregs)
+{
+ u32 val;
+ int i;
+
+ pmic_show_pmic_info();
+ for (i = 0; i < numregs; i++) {
+ val = pmic_reg_read(i);
+ if (!(i % 8))
+ printf ("\n0x%02x: ", i);
+ printf("%08x ", val);
+ }
+ puts("\n");
+}
+
+int do_pmic(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ char *cmd;
+ int nregs;
+ u32 val;
+
+ /* at least two arguments please */
+ if (argc < 2) {
+ cmd_usage(cmdtp);
+ return 1;
+ }
+
+ cmd = argv[1];
+ if (strcmp(cmd, "dump") == 0) {
+ if (argc < 3) {
+ cmd_usage(cmdtp);
+ return 1;
+ }
+ nregs = simple_strtoul(argv[2], NULL, 16);
+ pmic_dump(nregs);
+ return 0;
+ }
+ if (strcmp(cmd, "write") == 0) {
+ if (argc < 4) {
+ cmd_usage(cmdtp);
+ return 1;
+ }
+ nregs = simple_strtoul(argv[2], NULL, 16);
+ val = simple_strtoul(argv[3], NULL, 16);
+ pmic_reg_write(nregs, val);
+ return 0;
+ }
+ /* No subcommand found */
+ return 1;
+}
+
+U_BOOT_CMD(
+ pmic, CONFIG_SYS_MAXARGS, 1, do_pmic,
+ "Freescale PMIC (Atlas)",
+ "dump [numregs] dump registers\n"
+ "pmic write <reg> <value> - write register"
+);
diff --git a/drivers/rtc/mc13783-rtc.c b/drivers/rtc/mc13783-rtc.c
index 416f50d..4e18f80 100644
--- a/drivers/rtc/mc13783-rtc.c
+++ b/drivers/rtc/mc13783-rtc.c
@@ -23,53 +23,30 @@
#include <common.h>
#include <rtc.h>
#include <spi.h>
-
-static struct spi_slave *slave;
+#include <fsl_pmic.h>
int rtc_get(struct rtc_time *rtc)
{
u32 day1, day2, time;
- u32 reg;
- int err, tim, i = 0;
-
- if (!slave) {
- /* FIXME: Verify the max SCK rate */
- slave = spi_setup_slave(CONFIG_MC13783_SPI_BUS,
- CONFIG_MC13783_SPI_CS, 1000000,
- SPI_MODE_2 | SPI_CS_HIGH);
- if (!slave)
- return -1;
- }
-
- if (spi_claim_bus(slave))
- return -1;
+ int tim, i = 0;
do {
- reg = 0x2c000000;
- err = spi_xfer(slave, 32, (uchar *)&reg, (uchar *)&day1,
- SPI_XFER_BEGIN | SPI_XFER_END);
-
- if (err)
- return err;
-
- reg = 0x28000000;
- err = spi_xfer(slave, 32, (uchar *)&reg, (uchar *)&time,
- SPI_XFER_BEGIN | SPI_XFER_END);
+ day1 = pmic_reg_read(REG_RTC_DAY);
+ if (day1 < 0)
+ return -1;
- if (err)
- return err;
+ time = pmic_reg_read(REG_RTC_TIME);
+ if (time < 0)
+ return -1;
- reg = 0x2c000000;
- err = spi_xfer(slave, 32, (uchar *)&reg, (uchar *)&day2,
- SPI_XFER_BEGIN | SPI_XFER_END);
+ day2 = pmic_reg_read(REG_RTC_DAY);
+ if (day2 < 0)
+ return -1;
- if (err)
- return err;
} while (day1 != day2 && i++ < 3);
- spi_release_bus(slave);
-
tim = day1 * 86400 + time;
+
to_tm(tim, rtc);
rtc->tm_yday = 0;
@@ -80,34 +57,15 @@ int rtc_get(struct rtc_time *rtc)
int rtc_set(struct rtc_time *rtc)
{
- u32 time, day, reg;
-
- if (!slave) {
- /* FIXME: Verify the max SCK rate */
- slave = spi_setup_slave(CONFIG_MC13783_SPI_BUS,
- CONFIG_MC13783_SPI_CS, 1000000,
- SPI_MODE_2 | SPI_CS_HIGH);
- if (!slave)
- return -1;
- }
+ u32 time, day;
time = mktime(rtc->tm_year, rtc->tm_mon, rtc->tm_mday,
rtc->tm_hour, rtc->tm_min, rtc->tm_sec);
day = time / 86400;
time %= 86400;
- if (spi_claim_bus(slave))
- return -1;
-
- reg = 0x2c000000 | day | 0x80000000;
- spi_xfer(slave, 32, (uchar *)&reg, (uchar *)&day,
- SPI_XFER_BEGIN | SPI_XFER_END);
-
- reg = 0x28000000 | time | 0x80000000;
- spi_xfer(slave, 32, (uchar *)&reg, (uchar *)&time,
- SPI_XFER_BEGIN | SPI_XFER_END);
-
- spi_release_bus(slave);
+ pmic_reg_write(REG_RTC_DAY, day);
+ pmic_reg_write(REG_RTC_TIME, time);
return 0;
}
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index 3a45200..e15a63c 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -31,7 +31,7 @@
#error "i.MX27 CSPI not supported due to drastic differences in register definisions" \
"See linux mxc_spi driver from Freescale for details."
-#else
+#elif defined(CONFIG_MX31)
#include <asm/arch/mx31.h>
@@ -56,6 +56,9 @@
#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24)
#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8)
#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16)
+#define MXC_CSPICTRL_TC (1 << 8)
+#define MXC_CSPICTRL_RXOVF (1 << 6)
+#define MXC_CSPICTRL_MAXBITS 0x1f
#define MXC_CSPIPERIOD_32KHZ (1 << 15)
@@ -65,12 +68,63 @@ static unsigned long spi_bases[] = {
0x53f84000,
};
+#define OUT MX31_GPIO_DIRECTION_OUT
+#define mxc_gpio_direction mx31_gpio_direction
+#define mxc_gpio_set mx31_gpio_set
+#elif defined(CONFIG_MX51)
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+
+#define MXC_CSPIRXDATA 0x00
+#define MXC_CSPITXDATA 0x04
+#define MXC_CSPICTRL 0x08
+#define MXC_CSPICON 0x0C
+#define MXC_CSPIINT 0x10
+#define MXC_CSPIDMA 0x14
+#define MXC_CSPISTAT 0x18
+#define MXC_CSPIPERIOD 0x1C
+#define MXC_CSPIRESET 0x00
+#define MXC_CSPICTRL_EN (1 << 0)
+#define MXC_CSPICTRL_MODE (1 << 1)
+#define MXC_CSPICTRL_XCH (1 << 2)
+#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
+#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
+#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
+#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
+#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
+#define MXC_CSPICTRL_MAXBITS 0xfff
+#define MXC_CSPICTRL_TC (1 << 7)
+#define MXC_CSPICTRL_RXOVF (1 << 6)
+
+#define MXC_CSPIPERIOD_32KHZ (1 << 15)
+
+/* Bit position inside CTRL register to be associated with SS */
+#define MXC_CSPICTRL_CHAN 18
+
+/* Bit position inside CON register to be associated with SS */
+#define MXC_CSPICON_POL 4
+#define MXC_CSPICON_PHA 0
+#define MXC_CSPICON_SSPOL 12
+
+static unsigned long spi_bases[] = {
+ CSPI1_BASE_ADDR,
+ CSPI2_BASE_ADDR,
+ CSPI3_BASE_ADDR,
+};
+#define mxc_gpio_direction(gpio, dir) (0)
+#define mxc_gpio_set(gpio, value) {}
+#define OUT 1
+#else
+#error "Unsupported architecture"
#endif
struct mxc_spi_slave {
struct spi_slave slave;
unsigned long base;
u32 ctrl_reg;
+#if defined(CONFIG_MX51)
+ u32 cfg_reg;
+#endif
int gpio;
};
@@ -89,34 +143,161 @@ static inline void reg_write(unsigned long addr, u32 val)
*(volatile unsigned long*)addr = val;
}
+void spi_cs_activate(struct spi_slave *slave)
+{
+ struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
+ if (mxcs->gpio > 0)
+ mxc_gpio_set(mxcs->gpio, mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
+ if (mxcs->gpio > 0)
+ mxc_gpio_set(mxcs->gpio,
+ !(mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL));
+}
+
+#ifdef CONFIG_MX51
+static s32 spi_cfg(struct mxc_spi_slave *mxcs, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
+ s32 pre_div = 0, post_div = 0, i, reg_ctrl, reg_config;
+ u32 ss_pol = 0, sclkpol = 0, sclkpha = 0;
+
+ if (max_hz == 0) {
+ printf("Error: desired clock is 0\n");
+ return -1;
+ }
+
+ reg_ctrl = reg_read(mxcs->base + MXC_CSPICTRL);
+
+ /* Reset spi */
+ reg_write(mxcs->base + MXC_CSPICTRL, 0);
+ reg_write(mxcs->base + MXC_CSPICTRL, (reg_ctrl | 0x1));
+
+ /*
+ * The following computation is taken directly from Freescale's code.
+ */
+ if (clk_src > max_hz) {
+ pre_div = clk_src / max_hz;
+ if (pre_div > 16) {
+ post_div = pre_div / 16;
+ pre_div = 15;
+ }
+ if (post_div != 0) {
+ for (i = 0; i < 16; i++) {
+ if ((1 << i) >= post_div)
+ break;
+ }
+ if (i == 16) {
+ printf("Error: no divider for the freq: %d\n",
+ max_hz);
+ return -1;
+ }
+ post_div = i;
+ }
+ }
+
+ debug("pre_div = %d, post_div=%d\n", pre_div, post_div);
+ reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) |
+ MXC_CSPICTRL_SELCHAN(cs);
+ reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) |
+ MXC_CSPICTRL_PREDIV(pre_div);
+ reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) |
+ MXC_CSPICTRL_POSTDIV(post_div);
+
+ /* always set to master mode */
+ reg_ctrl |= 1 << (cs + 4);
+
+ /* We need to disable SPI before changing registers */
+ reg_ctrl &= ~MXC_CSPICTRL_EN;
+
+ if (mode & SPI_CS_HIGH)
+ ss_pol = 1;
+
+ if (!(mode & SPI_CPOL))
+ sclkpol = 1;
+
+ if (mode & SPI_CPHA)
+ sclkpha = 1;
+
+ reg_config = reg_read(mxcs->base + MXC_CSPICON);
+
+ /*
+ * Configuration register setup
+ * The MX51 has support different setup for each SS
+ */
+ reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) |
+ (ss_pol << (cs + MXC_CSPICON_SSPOL));
+ reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) |
+ (sclkpol << (cs + MXC_CSPICON_POL));
+ reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) |
+ (sclkpha << (cs + MXC_CSPICON_PHA));
+
+ debug("reg_ctrl = 0x%x\n", reg_ctrl);
+ reg_write(mxcs->base + MXC_CSPICTRL, reg_ctrl);
+ debug("reg_config = 0x%x\n", reg_config);
+ reg_write(mxcs->base + MXC_CSPICON, reg_config);
+
+ /* save config register and control register */
+ mxcs->ctrl_reg = reg_ctrl;
+ mxcs->cfg_reg = reg_config;
+
+ /* clear interrupt reg */
+ reg_write(mxcs->base + MXC_CSPIINT, 0);
+ reg_write(mxcs->base + MXC_CSPISTAT,
+ MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
+
+ return 0;
+}
+#endif
+
static u32 spi_xchg_single(struct spi_slave *slave, u32 data, int bitlen,
unsigned long flags)
{
struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
- unsigned int cfg_reg = reg_read(mxcs->base + MXC_CSPICTRL);
- mxcs->ctrl_reg = (mxcs->ctrl_reg & ~MXC_CSPICTRL_BITCOUNT(31)) |
+ if (flags & SPI_XFER_BEGIN)
+ spi_cs_activate(slave);
+
+ mxcs->ctrl_reg = (mxcs->ctrl_reg &
+ ~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) |
MXC_CSPICTRL_BITCOUNT(bitlen - 1);
- if (cfg_reg != mxcs->ctrl_reg)
- reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg);
+ reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg | MXC_CSPICTRL_EN);
+#ifdef CONFIG_MX51
+ reg_write(mxcs->base + MXC_CSPICON, mxcs->cfg_reg);
+#endif
- if (mxcs->gpio > 0 && (flags & SPI_XFER_BEGIN))
- mx31_gpio_set(mxcs->gpio, mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL);
+ /* Clear interrupt register */
+ reg_write(mxcs->base + MXC_CSPISTAT,
+ MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
+ debug("Sending SPI 0x%x\n", data);
reg_write(mxcs->base + MXC_CSPITXDATA, data);
- reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg | MXC_CSPICTRL_XCH);
+ /* FIFO is written, now starts the transfer setting the XCH bit */
+ reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg |
+ MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH);
- while (reg_read(mxcs->base + MXC_CSPICTRL) & MXC_CSPICTRL_XCH)
+ /* Wait until the TC (Transfer completed) bit is set */
+ while ((reg_read(mxcs->base + MXC_CSPISTAT) & MXC_CSPICTRL_TC) == 0)
;
- if (mxcs->gpio > 0 && (flags & SPI_XFER_END)) {
- mx31_gpio_set(mxcs->gpio,
- !(mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL));
- }
+ /* Transfer completed, clear any pending request */
+ reg_write(mxcs->base + MXC_CSPISTAT,
+ MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
+
+ data = reg_read(mxcs->base + MXC_CSPIRXDATA);
+ debug("SPI Rx: 0x%x\n", data);
+
+ if (flags & SPI_XFER_END)
+ spi_cs_deactivate(slave);
+
+ return data;
- return reg_read(mxcs->base + MXC_CSPIRXDATA);
}
int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
@@ -176,7 +357,7 @@ static int decode_cs(struct mxc_spi_slave *mxcs, unsigned int cs)
if (cs > 3) {
mxcs->gpio = cs >> 8;
cs &= 3;
- ret = mx31_gpio_direction(mxcs->gpio, MX31_GPIO_DIRECTION_OUT);
+ ret = mxc_gpio_direction(mxcs->gpio, OUT);
if (ret) {
printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio);
return -EINVAL;
@@ -210,6 +391,20 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
cs = ret;
+ mxcs->slave.bus = bus;
+ mxcs->slave.cs = cs;
+ mxcs->base = spi_bases[bus];
+
+#ifdef CONFIG_MX51
+ /* Can be used for i.MX31 too ? */
+ ctrl_reg = 0;
+ ret = spi_cfg(mxcs, cs, max_hz, mode);
+ if (ret) {
+ printf("mxc_spi: cannot setup SPI controller\n");
+ free(mxcs);
+ return NULL;
+ }
+#else
ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) |
MXC_CSPICTRL_BITCOUNT(31) |
MXC_CSPICTRL_DATARATE(7) | /* FIXME: calculate data rate */
@@ -222,12 +417,8 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
ctrl_reg |= MXC_CSPICTRL_POL;
if (mode & SPI_CS_HIGH)
ctrl_reg |= MXC_CSPICTRL_SSPOL;
-
- mxcs->slave.bus = bus;
- mxcs->slave.cs = cs;
- mxcs->base = spi_bases[bus];
mxcs->ctrl_reg = ctrl_reg;
-
+#endif
return &mxcs->slave;
}
diff --git a/drivers/video/mx3fb.c b/drivers/video/mx3fb.c
index 99a595e..7f04b49 100644
--- a/drivers/video/mx3fb.c
+++ b/drivers/video/mx3fb.c
@@ -56,22 +56,7 @@ void lcd_panel_disable(void)
#define msleep(a) udelay(a * 1000)
-#ifndef CONFIG_DISPLAY_VBEST_VGG322403
-#define XRES 240
-#define YRES 320
-#define PANEL_TYPE IPU_PANEL_TFT
-#define PIXEL_CLK 185925
-#define PIXEL_FMT IPU_PIX_FMT_RGB666
-#define H_START_WIDTH 9 /* left_margin */
-#define H_SYNC_WIDTH 1 /* hsync_len */
-#define H_END_WIDTH (16 + 1) /* right_margin + hsync_len */
-#define V_START_WIDTH 7 /* upper_margin */
-#define V_SYNC_WIDTH 1 /* vsync_len */
-#define V_END_WIDTH (9 + 1) /* lower_margin + vsync_len */
-#define SIG_POL (DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL)
-#define IF_CONF 0
-#define IF_CLK_DIV 0x175
-#else /* Display Vbest VGG322403 */
+#if defined(CONFIG_DISPLAY_VBEST_VGG322403)
#define XRES 320
#define YRES 240
#define PANEL_TYPE IPU_PANEL_TFT
@@ -86,6 +71,36 @@ void lcd_panel_disable(void)
#define SIG_POL (DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL)
#define IF_CONF 0
#define IF_CLK_DIV 0x175
+#elif defined(CONFIG_DISPLAY_COM57H5M10XRC)
+#define XRES 640
+#define YRES 480
+#define PANEL_TYPE IPU_PANEL_TFT
+#define PIXEL_CLK 40000
+#define PIXEL_FMT IPU_PIX_FMT_RGB666
+#define H_START_WIDTH 120 /* left_margin */
+#define H_SYNC_WIDTH 30 /* hsync_len */
+#define H_END_WIDTH (10 + 30) /* right_margin + hsync_len */
+#define V_START_WIDTH 35 /* upper_margin */
+#define V_SYNC_WIDTH 3 /* vsync_len */
+#define V_END_WIDTH (7 + 3) /* lower_margin + vsync_len */
+#define SIG_POL (DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL)
+#define IF_CONF 0
+#define IF_CLK_DIV 0x175
+#else
+#define XRES 240
+#define YRES 320
+#define PANEL_TYPE IPU_PANEL_TFT
+#define PIXEL_CLK 185925
+#define PIXEL_FMT IPU_PIX_FMT_RGB666
+#define H_START_WIDTH 9 /* left_margin */
+#define H_SYNC_WIDTH 1 /* hsync_len */
+#define H_END_WIDTH (16 + 1) /* right_margin + hsync_len */
+#define V_START_WIDTH 7 /* upper_margin */
+#define V_SYNC_WIDTH 1 /* vsync_len */
+#define V_END_WIDTH (9 + 1) /* lower_margin + vsync_len */
+#define SIG_POL (DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL)
+#define IF_CONF 0
+#define IF_CLK_DIV 0x175
#endif
#define LCD_COLOR_IPU LCD_COLOR16