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authorDmitry Lifshitz <lifshitz@compulab.co.il>2014-12-15 16:02:55 +0200
committerTom Rini <trini@ti.com>2015-01-05 15:13:46 -0500
commit6b68888a3385ca5abc0ee647873052720e8bffe3 (patch)
treeca01cf421f5e008fc9c82cc721f96f7396a6c380 /drivers
parent2a10f8b9480f7ff0b365130669f3c172bfefece9 (diff)
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ahci: introduce ahci_reset()
Extract controller reset code from ahci_host_init() into separate ahci_reset(). Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il> Reviewed-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/block/ahci.c47
1 files changed, 30 insertions, 17 deletions
diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c
index c9a3beb..12ed5e3 100644
--- a/drivers/block/ahci.c
+++ b/drivers/block/ahci.c
@@ -137,6 +137,33 @@ static void sunxi_dma_init(volatile u8 *port_mmio)
}
#endif
+int ahci_reset(u32 base)
+{
+ int i = 1000;
+ u32 host_ctl_reg = base + HOST_CTL;
+ u32 tmp = readl(host_ctl_reg); /* global controller reset */
+
+ if ((tmp & HOST_RESET) == 0)
+ writel_with_flush(tmp | HOST_RESET, host_ctl_reg);
+
+ /*
+ * reset must complete within 1 second, or
+ * the hardware should be considered fried.
+ */
+ do {
+ udelay(1000);
+ tmp = readl(host_ctl_reg);
+ i--;
+ } while ((i > 0) && (tmp & HOST_RESET));
+
+ if (i == 0) {
+ printf("controller reset failed (0x%x)\n", tmp);
+ return -1;
+ }
+
+ return 0;
+}
+
static int ahci_host_init(struct ahci_probe_ent *probe_ent)
{
#ifndef CONFIG_SCSI_AHCI_PLAT
@@ -156,23 +183,9 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent)
cap_save &= ((1 << 28) | (1 << 17));
cap_save |= (1 << 27); /* Staggered Spin-up. Not needed. */
- /* global controller reset */
- tmp = readl(mmio + HOST_CTL);
- if ((tmp & HOST_RESET) == 0)
- writel_with_flush(tmp | HOST_RESET, mmio + HOST_CTL);
-
- /* reset must complete within 1 second, or
- * the hardware should be considered fried.
- */
- i = 1000;
- do {
- udelay(1000);
- tmp = readl(mmio + HOST_CTL);
- if (!i--) {
- debug("controller reset failed (0x%x)\n", tmp);
- return -1;
- }
- } while (tmp & HOST_RESET);
+ ret = ahci_reset(probe_ent->mmio_base);
+ if (ret)
+ return ret;
writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL);
writel(cap_save, mmio + HOST_CAP);