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authorStefano Babic <sbabic@denx.de>2015-11-12 17:13:26 +0100
committerStefano Babic <sbabic@denx.de>2015-11-12 17:13:26 +0100
commit5f5620ab2679608f94b3a77e51c77d0a770103bd (patch)
treeec983c06d2f62384909968bb870add121b8a1502 /drivers
parent78e9ca52edaab74ad645d719676ff4c24d2f462c (diff)
parent038be18fd95aa6283eafb85ceabc0b880976424b (diff)
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Merge git://git.denx.de/u-boot
Diffstat (limited to 'drivers')
-rw-r--r--drivers/Kconfig2
-rw-r--r--drivers/Makefile5
-rw-r--r--drivers/adc/Kconfig30
-rw-r--r--drivers/adc/Makefile10
-rw-r--r--drivers/adc/adc-uclass.c409
-rw-r--r--drivers/adc/exynos-adc.c145
-rw-r--r--drivers/adc/sandbox.c174
-rw-r--r--drivers/bios_emulator/Makefile4
-rw-r--r--drivers/crypto/fsl/desc_constr.h26
-rw-r--r--drivers/crypto/fsl/fsl_hash.c8
-rw-r--r--drivers/crypto/fsl/jr.c86
-rw-r--r--drivers/crypto/fsl/jr.h7
-rw-r--r--drivers/ddr/fsl/Makefile4
-rw-r--r--drivers/ddr/fsl/ctrl_regs.c2
-rw-r--r--drivers/dfu/dfu_sf.c4
-rw-r--r--drivers/i2c/mxc_i2c.c4
-rw-r--r--drivers/input/cros_ec_keyb.c2
-rw-r--r--drivers/input/keyboard.c2
-rw-r--r--drivers/input/tegra-kbc.c2
-rw-r--r--drivers/memory/Makefile2
-rw-r--r--drivers/misc/altera_sysid.c4
-rw-r--r--drivers/misc/fsl_debug_server.c1
-rw-r--r--drivers/mmc/Makefile1
-rw-r--r--drivers/mmc/atmel_sdhci.c40
-rw-r--r--drivers/mmc/fsl_esdhc.c19
-rw-r--r--drivers/mmc/gen_atmel_mci.c60
-rw-r--r--drivers/mmc/s5p_sdhci.c14
-rw-r--r--drivers/mmc/sdhci.c20
-rw-r--r--drivers/mtd/Kconfig32
-rw-r--r--drivers/mtd/Makefile2
-rw-r--r--drivers/mtd/altera_qspi.c273
-rw-r--r--drivers/mtd/cfi_flash.c78
-rw-r--r--drivers/mtd/mtd-uclass.c21
-rw-r--r--drivers/mtd/mtdcore.c2
-rw-r--r--drivers/mtd/spi/sf_internal.h12
-rw-r--r--drivers/mtd/spi/sf_ops.c180
-rw-r--r--drivers/mtd/spi/sf_probe.c13
-rw-r--r--drivers/mtd/ubi/build.c2
-rw-r--r--drivers/net/altera_tse.c265
-rw-r--r--drivers/net/altera_tse.h314
-rw-r--r--drivers/net/fm/Makefile1
-rw-r--r--drivers/net/fm/dtsec.c2
-rw-r--r--drivers/net/fm/eth.c195
-rw-r--r--drivers/net/fm/fm.c31
-rw-r--r--drivers/net/fm/fm.h14
-rw-r--r--drivers/net/fm/init.c10
-rw-r--r--drivers/net/fm/ls1043.c119
-rw-r--r--drivers/net/fm/tgec.c2
-rw-r--r--drivers/net/fm/tgec_phy.c2
-rw-r--r--drivers/net/ldpaa_eth/ldpaa_eth.c15
-rw-r--r--drivers/net/ldpaa_eth/ls2085a.c2
-rw-r--r--drivers/net/netconsole.c2
-rw-r--r--drivers/pci/pcie_layerscape.c4
-rw-r--r--drivers/pinctrl/Makefile4
-rw-r--r--drivers/pinctrl/uniphier/Makefile4
-rw-r--r--drivers/power/pmic/Kconfig14
-rw-r--r--drivers/power/pmic/Makefile1
-rw-r--r--drivers/power/pmic/s2mps11.c62
-rw-r--r--drivers/power/regulator/regulator-uclass.c7
-rw-r--r--drivers/rtc/Makefile2
-rw-r--r--drivers/rtc/ds1307.c34
-rw-r--r--drivers/serial/Kconfig7
-rw-r--r--drivers/serial/altera_jtag_uart.c33
-rw-r--r--drivers/serial/altera_uart.c23
-rw-r--r--drivers/serial/serial-uclass.c30
-rw-r--r--drivers/serial/serial_zynq.c203
-rw-r--r--drivers/soc/Makefile2
-rw-r--r--drivers/soc/keystone/Makefile4
-rw-r--r--drivers/spi/altera_spi.c4
-rw-r--r--drivers/spi/cadence_qspi.c33
-rw-r--r--drivers/spi/cadence_qspi.h1
-rw-r--r--drivers/timer/altera_timer.c14
-rw-r--r--drivers/usb/dwc3/Makefile4
-rw-r--r--drivers/usb/dwc3/core.c7
-rw-r--r--drivers/usb/dwc3/ep0.c10
-rw-r--r--drivers/usb/dwc3/gadget.c10
-rw-r--r--drivers/usb/dwc3/io.h4
-rw-r--r--drivers/usb/gadget/f_thor.c2
-rw-r--r--drivers/usb/gadget/udc/Makefile3
-rw-r--r--drivers/usb/gadget/udc/udc-core.c2
-rw-r--r--drivers/usb/host/ohci-hcd.c1
-rw-r--r--drivers/usb/musb-new/Makefile2
-rw-r--r--drivers/video/atmel_hlcdfb.c4
-rw-r--r--drivers/video/cfb_console.c3
84 files changed, 2638 insertions, 576 deletions
diff --git a/drivers/Kconfig b/drivers/Kconfig
index ba88b5e..c481e93 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -4,6 +4,8 @@ source "drivers/core/Kconfig"
# types of drivers sorted in alphabetical order
+source "drivers/adc/Kconfig"
+
source "drivers/block/Kconfig"
source "drivers/clk/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index 4f49bfd..c9031f2 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -1,3 +1,7 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
obj-$(CONFIG_$(SPL_)DM) += core/
obj-$(CONFIG_$(SPL_)CLK) += clk/
obj-$(CONFIG_$(SPL_)LED) += led/
@@ -35,6 +39,7 @@ obj-$(CONFIG_SPL_SATA_SUPPORT) += block/
else
+obj-y += adc/
obj-$(CONFIG_DM_DEMO) += demo/
obj-$(CONFIG_BIOSEMU) += bios_emulator/
obj-y += block/
diff --git a/drivers/adc/Kconfig b/drivers/adc/Kconfig
new file mode 100644
index 0000000..e5335f7
--- /dev/null
+++ b/drivers/adc/Kconfig
@@ -0,0 +1,30 @@
+config ADC
+ bool "Enable ADC drivers using Driver Model"
+ help
+ This enables ADC API for drivers, which allows driving ADC features
+ by single and multi-channel methods for:
+ - start/stop/get data for conversion of a single-channel selected by
+ a number or multi-channels selected by a bitmask
+ - get data mask (ADC resolution)
+ ADC reference Voltage supply options:
+ - methods for get Vdd/Vss reference Voltage values with polarity
+ - support supply's phandle with auto-enable
+ - supply polarity setting in fdt
+
+config ADC_EXYNOS
+ bool "Enable Exynos 54xx ADC driver"
+ help
+ This enables basic driver for Exynos ADC compatible with Exynos54xx.
+ It provides:
+ - 10 analog input channels
+ - 12-bit resolution
+ - 600 KSPS of sample rate
+
+config ADC_SANDBOX
+ bool "Enable Sandbox ADC test driver"
+ help
+ This enables driver for Sandbox ADC device emulation.
+ It provides:
+ - 4 analog input channels
+ - 16-bit resolution
+ - single and multi-channel conversion mode
diff --git a/drivers/adc/Makefile b/drivers/adc/Makefile
new file mode 100644
index 0000000..cebf26d
--- /dev/null
+++ b/drivers/adc/Makefile
@@ -0,0 +1,10 @@
+#
+# Copyright (C) 2015 Samsung Electronics
+# Przemyslaw Marczak <p.marczak@samsung.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_ADC) += adc-uclass.o
+obj-$(CONFIG_ADC_EXYNOS) += exynos-adc.o
+obj-$(CONFIG_ADC_SANDBOX) += sandbox.o
diff --git a/drivers/adc/adc-uclass.c b/drivers/adc/adc-uclass.c
new file mode 100644
index 0000000..9233fcd
--- /dev/null
+++ b/drivers/adc/adc-uclass.c
@@ -0,0 +1,409 @@
+/*
+ * Copyright (C) 2015 Samsung Electronics
+ * Przemyslaw Marczak <p.marczak@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <dm.h>
+#include <dm/lists.h>
+#include <dm/device-internal.h>
+#include <dm/uclass-internal.h>
+#include <adc.h>
+#include <power/regulator.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define ADC_UCLASS_PLATDATA_SIZE sizeof(struct adc_uclass_platdata)
+#define CHECK_NUMBER true
+#define CHECK_MASK (!CHECK_NUMBER)
+
+/* TODO: add support for timer uclass (for early calls) */
+#ifdef CONFIG_SANDBOX_ARCH
+#define sdelay(x) udelay(x)
+#else
+extern void sdelay(unsigned long loops);
+#endif
+
+static int check_channel(struct udevice *dev, int value, bool number_or_mask,
+ const char *caller_function)
+{
+ struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
+ unsigned mask = number_or_mask ? (1 << value) : value;
+
+ /* For the real ADC hardware, some ADC channels can be inactive.
+ * For example if device has 4 analog channels, and only channels
+ * 1-st and 3-rd are valid, then channel mask is: 0b1010, so request
+ * with mask 0b1110 should return an error.
+ */
+ if ((uc_pdata->channel_mask >= mask) && (uc_pdata->channel_mask & mask))
+ return 0;
+
+ printf("Error in %s/%s().\nWrong channel selection for device: %s\n",
+ __FILE__, caller_function, dev->name);
+
+ return -EINVAL;
+}
+
+static int adc_supply_enable(struct udevice *dev)
+{
+ struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
+ const char *supply_type;
+ int ret = 0;
+
+ if (uc_pdata->vdd_supply) {
+ supply_type = "vdd";
+ ret = regulator_set_enable(uc_pdata->vdd_supply, true);
+ }
+
+ if (!ret && uc_pdata->vss_supply) {
+ supply_type = "vss";
+ ret = regulator_set_enable(uc_pdata->vss_supply, true);
+ }
+
+ if (ret)
+ error("%s: can't enable %s-supply!", dev->name, supply_type);
+
+ return ret;
+}
+
+int adc_data_mask(struct udevice *dev, unsigned int *data_mask)
+{
+ struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
+
+ if (!uc_pdata)
+ return -ENOSYS;
+
+ *data_mask = uc_pdata->data_mask;
+ return 0;
+}
+
+int adc_stop(struct udevice *dev)
+{
+ const struct adc_ops *ops = dev_get_driver_ops(dev);
+
+ if (!ops->stop)
+ return -ENOSYS;
+
+ return ops->stop(dev);
+}
+
+int adc_start_channel(struct udevice *dev, int channel)
+{
+ const struct adc_ops *ops = dev_get_driver_ops(dev);
+ int ret;
+
+ if (!ops->start_channel)
+ return -ENOSYS;
+
+ ret = check_channel(dev, channel, CHECK_NUMBER, __func__);
+ if (ret)
+ return ret;
+
+ ret = adc_supply_enable(dev);
+ if (ret)
+ return ret;
+
+ return ops->start_channel(dev, channel);
+}
+
+int adc_start_channels(struct udevice *dev, unsigned int channel_mask)
+{
+ const struct adc_ops *ops = dev_get_driver_ops(dev);
+ int ret;
+
+ if (!ops->start_channels)
+ return -ENOSYS;
+
+ ret = check_channel(dev, channel_mask, CHECK_MASK, __func__);
+ if (ret)
+ return ret;
+
+ ret = adc_supply_enable(dev);
+ if (ret)
+ return ret;
+
+ return ops->start_channels(dev, channel_mask);
+}
+
+int adc_channel_data(struct udevice *dev, int channel, unsigned int *data)
+{
+ struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
+ const struct adc_ops *ops = dev_get_driver_ops(dev);
+ unsigned int timeout_us = uc_pdata->data_timeout_us;
+ int ret;
+
+ if (!ops->channel_data)
+ return -ENOSYS;
+
+ ret = check_channel(dev, channel, CHECK_NUMBER, __func__);
+ if (ret)
+ return ret;
+
+ do {
+ ret = ops->channel_data(dev, channel, data);
+ if (!ret || ret != -EBUSY)
+ break;
+
+ /* TODO: use timer uclass (for early calls). */
+ sdelay(5);
+ } while (timeout_us--);
+
+ return ret;
+}
+
+int adc_channels_data(struct udevice *dev, unsigned int channel_mask,
+ struct adc_channel *channels)
+{
+ struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
+ unsigned int timeout_us = uc_pdata->multidata_timeout_us;
+ const struct adc_ops *ops = dev_get_driver_ops(dev);
+ int ret;
+
+ if (!ops->channels_data)
+ return -ENOSYS;
+
+ ret = check_channel(dev, channel_mask, CHECK_MASK, __func__);
+ if (ret)
+ return ret;
+
+ do {
+ ret = ops->channels_data(dev, channel_mask, channels);
+ if (!ret || ret != -EBUSY)
+ break;
+
+ /* TODO: use timer uclass (for early calls). */
+ sdelay(5);
+ } while (timeout_us--);
+
+ return ret;
+}
+
+int adc_channel_single_shot(const char *name, int channel, unsigned int *data)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_name(UCLASS_ADC, name, &dev);
+ if (ret)
+ return ret;
+
+ ret = adc_start_channel(dev, channel);
+ if (ret)
+ return ret;
+
+ ret = adc_channel_data(dev, channel, data);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int _adc_channels_single_shot(struct udevice *dev,
+ unsigned int channel_mask,
+ struct adc_channel *channels)
+{
+ unsigned int data;
+ int channel, ret;
+
+ for (channel = 0; channel <= ADC_MAX_CHANNEL; channel++) {
+ /* Check channel bit. */
+ if (!((channel_mask >> channel) & 0x1))
+ continue;
+
+ ret = adc_start_channel(dev, channel);
+ if (ret)
+ return ret;
+
+ ret = adc_channel_data(dev, channel, &data);
+ if (ret)
+ return ret;
+
+ channels->id = channel;
+ channels->data = data;
+ channels++;
+ }
+
+ return 0;
+}
+
+int adc_channels_single_shot(const char *name, unsigned int channel_mask,
+ struct adc_channel *channels)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_name(UCLASS_ADC, name, &dev);
+ if (ret)
+ return ret;
+
+ ret = adc_start_channels(dev, channel_mask);
+ if (ret)
+ goto try_manual;
+
+ ret = adc_channels_data(dev, channel_mask, channels);
+ if (ret)
+ return ret;
+
+ return 0;
+
+try_manual:
+ if (ret != -ENOSYS)
+ return ret;
+
+ return _adc_channels_single_shot(dev, channel_mask, channels);
+}
+
+static int adc_vdd_platdata_update(struct udevice *dev)
+{
+ struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
+ int ret;
+
+ /* Warning!
+ * This function can't return supply device before its bind.
+ * Please pay attention to proper fdt scan sequence. If ADC device
+ * will bind before its supply regulator device, then the below 'get'
+ * will return an error.
+ */
+ ret = device_get_supply_regulator(dev, "vdd-supply",
+ &uc_pdata->vdd_supply);
+ if (ret)
+ return ret;
+
+ ret = regulator_get_value(uc_pdata->vdd_supply);
+ if (ret < 0)
+ return ret;
+
+ uc_pdata->vdd_microvolts = ret;
+
+ return 0;
+}
+
+static int adc_vss_platdata_update(struct udevice *dev)
+{
+ struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
+ int ret;
+
+ ret = device_get_supply_regulator(dev, "vss-supply",
+ &uc_pdata->vss_supply);
+ if (ret)
+ return ret;
+
+ ret = regulator_get_value(uc_pdata->vss_supply);
+ if (ret < 0)
+ return ret;
+
+ uc_pdata->vss_microvolts = ret;
+
+ return 0;
+}
+
+int adc_vdd_value(struct udevice *dev, int *uV)
+{
+ struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
+ int ret, value_sign = uc_pdata->vdd_polarity_negative ? -1 : 1;
+
+ if (!uc_pdata->vdd_supply)
+ goto nodev;
+
+ /* Update the regulator Value. */
+ ret = adc_vdd_platdata_update(dev);
+ if (ret)
+ return ret;
+nodev:
+ if (uc_pdata->vdd_microvolts == -ENODATA)
+ return -ENODATA;
+
+ *uV = uc_pdata->vdd_microvolts * value_sign;
+
+ return 0;
+}
+
+int adc_vss_value(struct udevice *dev, int *uV)
+{
+ struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
+ int ret, value_sign = uc_pdata->vss_polarity_negative ? -1 : 1;
+
+ if (!uc_pdata->vss_supply)
+ goto nodev;
+
+ /* Update the regulator Value. */
+ ret = adc_vss_platdata_update(dev);
+ if (ret)
+ return ret;
+nodev:
+ if (uc_pdata->vss_microvolts == -ENODATA)
+ return -ENODATA;
+
+ *uV = uc_pdata->vss_microvolts * value_sign;
+
+ return 0;
+}
+
+static int adc_vdd_platdata_set(struct udevice *dev)
+{
+ struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
+ int ret, offset = dev->of_offset;
+ const void *fdt = gd->fdt_blob;
+ char *prop;
+
+ prop = "vdd-polarity-negative";
+ uc_pdata->vdd_polarity_negative = fdtdec_get_bool(fdt, offset, prop);
+
+ ret = adc_vdd_platdata_update(dev);
+ if (ret != -ENOENT)
+ return ret;
+
+ /* No vdd-supply phandle. */
+ prop = "vdd-microvolts";
+ uc_pdata->vdd_microvolts = fdtdec_get_int(fdt, offset, prop, -ENODATA);
+
+ return 0;
+}
+
+static int adc_vss_platdata_set(struct udevice *dev)
+{
+ struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
+ int ret, offset = dev->of_offset;
+ const void *fdt = gd->fdt_blob;
+ char *prop;
+
+ prop = "vss-polarity-negative";
+ uc_pdata->vss_polarity_negative = fdtdec_get_bool(fdt, offset, prop);
+
+ ret = adc_vss_platdata_update(dev);
+ if (ret != -ENOENT)
+ return ret;
+
+ /* No vss-supply phandle. */
+ prop = "vss-microvolts";
+ uc_pdata->vss_microvolts = fdtdec_get_int(fdt, offset, prop, -ENODATA);
+
+ return 0;
+}
+
+static int adc_pre_probe(struct udevice *dev)
+{
+ int ret;
+
+ /* Set ADC VDD platdata: polarity, uV, regulator (phandle). */
+ ret = adc_vdd_platdata_set(dev);
+ if (ret)
+ error("%s: Can't update Vdd. Error: %d", dev->name, ret);
+
+ /* Set ADC VSS platdata: polarity, uV, regulator (phandle). */
+ ret = adc_vss_platdata_set(dev);
+ if (ret)
+ error("%s: Can't update Vss. Error: %d", dev->name, ret);
+
+ return 0;
+}
+
+UCLASS_DRIVER(adc) = {
+ .id = UCLASS_ADC,
+ .name = "adc",
+ .pre_probe = adc_pre_probe,
+ .per_device_platdata_auto_alloc_size = ADC_UCLASS_PLATDATA_SIZE,
+};
diff --git a/drivers/adc/exynos-adc.c b/drivers/adc/exynos-adc.c
new file mode 100644
index 0000000..534e68d
--- /dev/null
+++ b/drivers/adc/exynos-adc.c
@@ -0,0 +1,145 @@
+/*
+ * Copyright (C) 2015 Samsung Electronics
+ * Przemyslaw Marczak <p.marczak@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <errno.h>
+#include <dm.h>
+#include <adc.h>
+#include <asm/arch/adc.h>
+
+struct exynos_adc_priv {
+ int active_channel;
+ struct exynos_adc_v2 *regs;
+};
+
+int exynos_adc_channel_data(struct udevice *dev, int channel,
+ unsigned int *data)
+{
+ struct exynos_adc_priv *priv = dev_get_priv(dev);
+ struct exynos_adc_v2 *regs = priv->regs;
+
+ if (channel != priv->active_channel) {
+ error("Requested channel is not active!");
+ return -EINVAL;
+ }
+
+ if (ADC_V2_GET_STATUS_FLAG(readl(&regs->status)) != FLAG_CONV_END)
+ return -EBUSY;
+
+ *data = readl(&regs->dat) & ADC_V2_DAT_MASK;
+
+ return 0;
+}
+
+int exynos_adc_start_channel(struct udevice *dev, int channel)
+{
+ struct exynos_adc_priv *priv = dev_get_priv(dev);
+ struct exynos_adc_v2 *regs = priv->regs;
+ unsigned int cfg;
+
+ /* Choose channel */
+ cfg = readl(&regs->con2);
+ cfg &= ~ADC_V2_CON2_CHAN_SEL_MASK;
+ cfg |= ADC_V2_CON2_CHAN_SEL(channel);
+ writel(cfg, &regs->con2);
+
+ /* Start conversion */
+ cfg = readl(&regs->con1);
+ writel(cfg | ADC_V2_CON1_STC_EN, &regs->con1);
+
+ priv->active_channel = channel;
+
+ return 0;
+}
+
+int exynos_adc_stop(struct udevice *dev)
+{
+ struct exynos_adc_priv *priv = dev_get_priv(dev);
+ struct exynos_adc_v2 *regs = priv->regs;
+ unsigned int cfg;
+
+ /* Stop conversion */
+ cfg = readl(&regs->con1);
+ cfg |= ~ADC_V2_CON1_STC_EN;
+
+ writel(cfg, &regs->con1);
+
+ priv->active_channel = -1;
+
+ return 0;
+}
+
+int exynos_adc_probe(struct udevice *dev)
+{
+ struct exynos_adc_priv *priv = dev_get_priv(dev);
+ struct exynos_adc_v2 *regs = priv->regs;
+ unsigned int cfg;
+
+ /* Check HW version */
+ if (readl(&regs->version) != ADC_V2_VERSION) {
+ error("This driver supports only ADC v2!");
+ return -ENXIO;
+ }
+
+ /* ADC Reset */
+ writel(ADC_V2_CON1_SOFT_RESET, &regs->con1);
+
+ /* Disable INT - will read status only */
+ writel(0x0, &regs->int_en);
+
+ /* CON2 - set conversion parameters */
+ cfg = ADC_V2_CON2_C_TIME(3); /* Conversion times: (1 << 3) = 8 */
+ cfg |= ADC_V2_CON2_OSEL(OSEL_BINARY);
+ cfg |= ADC_V2_CON2_ESEL(ESEL_ADC_EVAL_TIME_20CLK);
+ cfg |= ADC_V2_CON2_HIGHF(HIGHF_CONV_RATE_600KSPS);
+ writel(cfg, &regs->con2);
+
+ priv->active_channel = -1;
+
+ return 0;
+}
+
+int exynos_adc_ofdata_to_platdata(struct udevice *dev)
+{
+ struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
+ struct exynos_adc_priv *priv = dev_get_priv(dev);
+
+ priv->regs = (struct exynos_adc_v2 *)dev_get_addr(dev);
+ if (priv->regs == (struct exynos_adc_v2 *)FDT_ADDR_T_NONE) {
+ error("Dev: %s - can't get address!", dev->name);
+ return -ENODATA;
+ }
+
+ uc_pdata->data_mask = ADC_V2_DAT_MASK;
+ uc_pdata->data_format = ADC_DATA_FORMAT_BIN;
+ uc_pdata->data_timeout_us = ADC_V2_CONV_TIMEOUT_US;
+
+ /* Mask available channel bits: [0:9] */
+ uc_pdata->channel_mask = (2 << ADC_V2_MAX_CHANNEL) - 1;
+
+ return 0;
+}
+
+static const struct adc_ops exynos_adc_ops = {
+ .start_channel = exynos_adc_start_channel,
+ .channel_data = exynos_adc_channel_data,
+ .stop = exynos_adc_stop,
+};
+
+static const struct udevice_id exynos_adc_ids[] = {
+ { .compatible = "samsung,exynos-adc-v2" },
+ { }
+};
+
+U_BOOT_DRIVER(exynos_adc) = {
+ .name = "exynos-adc",
+ .id = UCLASS_ADC,
+ .of_match = exynos_adc_ids,
+ .ops = &exynos_adc_ops,
+ .probe = exynos_adc_probe,
+ .ofdata_to_platdata = exynos_adc_ofdata_to_platdata,
+ .priv_auto_alloc_size = sizeof(struct exynos_adc_priv),
+};
diff --git a/drivers/adc/sandbox.c b/drivers/adc/sandbox.c
new file mode 100644
index 0000000..3718922
--- /dev/null
+++ b/drivers/adc/sandbox.c
@@ -0,0 +1,174 @@
+/*
+ * Copyright (C) 2015 Samsung Electronics
+ * Przemyslaw Marczak <p.marczak@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <errno.h>
+#include <dm.h>
+#include <adc.h>
+#include <sandbox-adc.h>
+
+/**
+ * struct sandbox_adc_priv - sandbox ADC device's operation status and data
+ *
+ * @conversion_status - conversion status: ACTIVE (started) / INACTIVE (stopped)
+ * @conversion_mode - conversion mode: single or multi-channel
+ * @active_channel - active channel number, valid for single channel mode
+ * data[] - channels data
+ */
+struct sandbox_adc_priv {
+ int conversion_status;
+ int conversion_mode;
+ int active_channel_mask;
+ unsigned int data[4];
+};
+
+int sandbox_adc_start_channel(struct udevice *dev, int channel)
+{
+ struct sandbox_adc_priv *priv = dev_get_priv(dev);
+
+ /* Set single-channel mode */
+ priv->conversion_mode = SANDBOX_ADC_MODE_SINGLE_CHANNEL;
+ /* Select channel */
+ priv->active_channel_mask = 1 << channel;
+ /* Start conversion */
+ priv->conversion_status = SANDBOX_ADC_ACTIVE;
+
+ return 0;
+}
+
+int sandbox_adc_start_channels(struct udevice *dev, unsigned int channel_mask)
+{
+ struct sandbox_adc_priv *priv = dev_get_priv(dev);
+
+ /* Set single-channel mode */
+ priv->conversion_mode = SANDBOX_ADC_MODE_MULTI_CHANNEL;
+ /* Select channel */
+ priv->active_channel_mask = channel_mask;
+ /* Start conversion */
+ priv->conversion_status = SANDBOX_ADC_ACTIVE;
+
+ return 0;
+}
+
+int sandbox_adc_channel_data(struct udevice *dev, int channel,
+ unsigned int *data)
+{
+ struct sandbox_adc_priv *priv = dev_get_priv(dev);
+
+ /* For single-channel conversion mode, check if channel was selected */
+ if ((priv->conversion_mode == SANDBOX_ADC_MODE_SINGLE_CHANNEL) &&
+ !(priv->active_channel_mask & (1 << channel))) {
+ error("Request for an inactive channel!");
+ return -EINVAL;
+ }
+
+ /* The conversion must be started before reading the data */
+ if (priv->conversion_status == SANDBOX_ADC_INACTIVE)
+ return -EIO;
+
+ *data = priv->data[channel];
+
+ return 0;
+}
+
+int sandbox_adc_channels_data(struct udevice *dev, unsigned int channel_mask,
+ struct adc_channel *channels)
+{
+ struct sandbox_adc_priv *priv = dev_get_priv(dev);
+ int i;
+
+ /* Return error for single-channel conversion mode */
+ if (priv->conversion_mode == SANDBOX_ADC_MODE_SINGLE_CHANNEL) {
+ error("ADC in single-channel mode!");
+ return -EPERM;
+ }
+ /* Check channel selection */
+ if (!(priv->active_channel_mask & channel_mask)) {
+ error("Request for an inactive channel!");
+ return -EINVAL;
+ }
+ /* The conversion must be started before reading the data */
+ if (priv->conversion_status == SANDBOX_ADC_INACTIVE)
+ return -EIO;
+
+ for (i = 0; i < SANDBOX_ADC_CHANNELS; i++) {
+ if (!((channel_mask >> i) & 0x1))
+ continue;
+
+ channels->data = priv->data[i];
+ channels->id = i;
+ channels++;
+ }
+
+ return 0;
+}
+
+int sandbox_adc_stop(struct udevice *dev)
+{
+ struct sandbox_adc_priv *priv = dev_get_priv(dev);
+
+ /* Start conversion */
+ priv->conversion_status = SANDBOX_ADC_INACTIVE;
+
+ return 0;
+}
+
+int sandbox_adc_probe(struct udevice *dev)
+{
+ struct sandbox_adc_priv *priv = dev_get_priv(dev);
+
+ /* Stop conversion */
+ priv->conversion_status = SANDBOX_ADC_INACTIVE;
+ /* Set single-channel mode */
+ priv->conversion_mode = SANDBOX_ADC_MODE_SINGLE_CHANNEL;
+ /* Deselect all channels */
+ priv->active_channel_mask = 0;
+
+ /* Set sandbox test data */
+ priv->data[0] = SANDBOX_ADC_CHANNEL0_DATA;
+ priv->data[1] = SANDBOX_ADC_CHANNEL1_DATA;
+ priv->data[2] = SANDBOX_ADC_CHANNEL2_DATA;
+ priv->data[3] = SANDBOX_ADC_CHANNEL3_DATA;
+
+ return 0;
+}
+
+int sandbox_adc_ofdata_to_platdata(struct udevice *dev)
+{
+ struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
+
+ uc_pdata->data_mask = SANDBOX_ADC_DATA_MASK;
+ uc_pdata->data_format = ADC_DATA_FORMAT_BIN;
+ uc_pdata->data_timeout_us = 0;
+
+ /* Mask available channel bits: [0:3] */
+ uc_pdata->channel_mask = (1 << SANDBOX_ADC_CHANNELS) - 1;
+
+ return 0;
+}
+
+static const struct adc_ops sandbox_adc_ops = {
+ .start_channel = sandbox_adc_start_channel,
+ .start_channels = sandbox_adc_start_channels,
+ .channel_data = sandbox_adc_channel_data,
+ .channels_data = sandbox_adc_channels_data,
+ .stop = sandbox_adc_stop,
+};
+
+static const struct udevice_id sandbox_adc_ids[] = {
+ { .compatible = "sandbox,adc" },
+ { }
+};
+
+U_BOOT_DRIVER(sandbox_adc) = {
+ .name = "sandbox-adc",
+ .id = UCLASS_ADC,
+ .of_match = sandbox_adc_ids,
+ .ops = &sandbox_adc_ops,
+ .probe = sandbox_adc_probe,
+ .ofdata_to_platdata = sandbox_adc_ofdata_to_platdata,
+ .priv_auto_alloc_size = sizeof(struct sandbox_adc_priv),
+};
diff --git a/drivers/bios_emulator/Makefile b/drivers/bios_emulator/Makefile
index 2ba43ac..0a28074 100644
--- a/drivers/bios_emulator/Makefile
+++ b/drivers/bios_emulator/Makefile
@@ -1,3 +1,7 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
X86DIR = x86emu
obj-y = atibios.o biosemu.o besys.o bios.o \
diff --git a/drivers/crypto/fsl/desc_constr.h b/drivers/crypto/fsl/desc_constr.h
index f9cae91..2559ccd 100644
--- a/drivers/crypto/fsl/desc_constr.h
+++ b/drivers/crypto/fsl/desc_constr.h
@@ -36,6 +36,23 @@
LDST_SRCDST_WORD_DECOCTRL | \
(LDOFF_ENABLE_AUTO_NFIFO << LDST_OFFSET_SHIFT))
+#ifdef CONFIG_PHYS_64BIT
+union ptr_addr_t {
+ u64 m_whole;
+ struct {
+#ifdef CONFIG_SYS_FSL_SEC_LE
+ u32 low;
+ u32 high;
+#elif defined(CONFIG_SYS_FSL_SEC_BE)
+ u32 high;
+ u32 low;
+#else
+#error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined
+#endif
+ } m_halfs;
+};
+#endif
+
static inline int desc_len(u32 *desc)
{
return *desc & HDR_DESCLEN_MASK;
@@ -65,7 +82,16 @@ static inline void append_ptr(u32 *desc, dma_addr_t ptr)
{
dma_addr_t *offset = (dma_addr_t *)desc_end(desc);
+#ifdef CONFIG_PHYS_64BIT
+ /* The Position of low and high part of 64 bit address
+ * will depend on the endianness of CAAM Block */
+ union ptr_addr_t ptr_addr;
+ ptr_addr.m_halfs.high = (u32)(ptr >> 32);
+ ptr_addr.m_halfs.low = (u32)ptr;
+ *offset = ptr_addr.m_whole;
+#else
*offset = ptr;
+#endif
(*desc) += CAAM_PTR_SZ / CAAM_CMD_SZ;
}
diff --git a/drivers/crypto/fsl/fsl_hash.c b/drivers/crypto/fsl/fsl_hash.c
index c298404..887e88c 100644
--- a/drivers/crypto/fsl/fsl_hash.c
+++ b/drivers/crypto/fsl/fsl_hash.c
@@ -84,7 +84,7 @@ static int caam_hash_update(void *hash_ctx, const void *buf,
enum caam_hash_algos caam_algo)
{
uint32_t final = 0;
- dma_addr_t addr = virt_to_phys((void *)buf);
+ phys_addr_t addr = virt_to_phys((void *)buf);
struct sha_ctx *ctx = hash_ctx;
if (ctx->sg_num >= MAX_SG_32) {
@@ -93,11 +93,11 @@ static int caam_hash_update(void *hash_ctx, const void *buf,
}
#ifdef CONFIG_PHYS_64BIT
- ctx->sg_tbl[ctx->sg_num].addr_hi = addr >> 32;
+ sec_out32(&ctx->sg_tbl[ctx->sg_num].addr_hi, (uint32_t)(addr >> 32));
#else
- ctx->sg_tbl[ctx->sg_num].addr_hi = 0x0;
+ sec_out32(&ctx->sg_tbl[ctx->sg_num].addr_hi, 0x0);
#endif
- ctx->sg_tbl[ctx->sg_num].addr_lo = addr;
+ sec_out32(&ctx->sg_tbl[ctx->sg_num].addr_lo, (uint32_t)addr);
sec_out32(&ctx->sg_tbl[ctx->sg_num].len_flag,
(size & SG_ENTRY_LENGTH_MASK));
diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
index 17392c9..f63eacb 100644
--- a/drivers/crypto/fsl/jr.c
+++ b/drivers/crypto/fsl/jr.c
@@ -11,6 +11,7 @@
#include "fsl_sec.h"
#include "jr.h"
#include "jobdesc.h"
+#include "desc_constr.h"
#define CIRC_CNT(head, tail, size) (((head) - (tail)) & (size - 1))
#define CIRC_SPACE(head, tail, size) CIRC_CNT((tail), (head) + 1, (size))
@@ -154,19 +155,35 @@ static int jr_hw_reset(void)
/* -1 --- error, can't enqueue -- no space available */
static int jr_enqueue(uint32_t *desc_addr,
- void (*callback)(uint32_t desc, uint32_t status, void *arg),
+ void (*callback)(uint32_t status, void *arg),
void *arg)
{
struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
int head = jr.head;
- dma_addr_t desc_phys_addr = virt_to_phys(desc_addr);
+ uint32_t desc_word;
+ int length = desc_len(desc_addr);
+ int i;
+#ifdef CONFIG_PHYS_64BIT
+ uint32_t *addr_hi, *addr_lo;
+#endif
+
+ /* The descriptor must be submitted to SEC block as per endianness
+ * of the SEC Block.
+ * So, if the endianness of Core and SEC block is different, each word
+ * of the descriptor will be byte-swapped.
+ */
+ for (i = 0; i < length; i++) {
+ desc_word = desc_addr[i];
+ sec_out32((uint32_t *)&desc_addr[i], desc_word);
+ }
+
+ phys_addr_t desc_phys_addr = virt_to_phys(desc_addr);
if (sec_in32(&regs->irsa) == 0 ||
CIRC_SPACE(jr.head, jr.tail, jr.size) <= 0)
return -1;
jr.info[head].desc_phys_addr = desc_phys_addr;
- jr.info[head].desc_addr = (uint32_t)desc_addr;
jr.info[head].callback = (void *)callback;
jr.info[head].arg = arg;
jr.info[head].op_done = 0;
@@ -177,9 +194,29 @@ static int jr_enqueue(uint32_t *desc_addr,
ARCH_DMA_MINALIGN);
flush_dcache_range(start, end);
- jr.input_ring[head] = desc_phys_addr;
+#ifdef CONFIG_PHYS_64BIT
+ /* Write the 64 bit Descriptor address on Input Ring.
+ * The 32 bit hign and low part of the address will
+ * depend on endianness of SEC block.
+ */
+#ifdef CONFIG_SYS_FSL_SEC_LE
+ addr_lo = (uint32_t *)(&jr.input_ring[head]);
+ addr_hi = (uint32_t *)(&jr.input_ring[head]) + 1;
+#elif defined(CONFIG_SYS_FSL_SEC_BE)
+ addr_hi = (uint32_t *)(&jr.input_ring[head]);
+ addr_lo = (uint32_t *)(&jr.input_ring[head]) + 1;
+#endif /* ifdef CONFIG_SYS_FSL_SEC_LE */
+
+ sec_out32(addr_hi, (uint32_t)(desc_phys_addr >> 32));
+ sec_out32(addr_lo, (uint32_t)(desc_phys_addr));
+
+#else
+ /* Write the 32 bit Descriptor address on Input Ring. */
+ sec_out32(&jr.input_ring[head], desc_phys_addr);
+#endif /* ifdef CONFIG_PHYS_64BIT */
+
start = (unsigned long)&jr.input_ring[head] & ~(ARCH_DMA_MINALIGN - 1);
- end = ALIGN(start + sizeof(dma_addr_t), ARCH_DMA_MINALIGN);
+ end = ALIGN(start + sizeof(phys_addr_t), ARCH_DMA_MINALIGN);
flush_dcache_range(start, end);
jr.head = (head + 1) & (jr.size - 1);
@@ -195,8 +232,13 @@ static int jr_dequeue(void)
int head = jr.head;
int tail = jr.tail;
int idx, i, found;
- void (*callback)(uint32_t desc, uint32_t status, void *arg);
+ void (*callback)(uint32_t status, void *arg);
void *arg = NULL;
+#ifdef CONFIG_PHYS_64BIT
+ uint32_t *addr_hi, *addr_lo;
+#else
+ uint32_t *addr;
+#endif
while (sec_in32(&regs->orsf) && CIRC_CNT(jr.head, jr.tail, jr.size)) {
unsigned long start = (unsigned long)jr.output_ring &
@@ -208,14 +250,34 @@ static int jr_dequeue(void)
found = 0;
- dma_addr_t op_desc = jr.output_ring[jr.tail].desc;
- uint32_t status = jr.output_ring[jr.tail].status;
- uint32_t desc_virt;
+ phys_addr_t op_desc;
+ #ifdef CONFIG_PHYS_64BIT
+ /* Read the 64 bit Descriptor address from Output Ring.
+ * The 32 bit hign and low part of the address will
+ * depend on endianness of SEC block.
+ */
+ #ifdef CONFIG_SYS_FSL_SEC_LE
+ addr_lo = (uint32_t *)(&jr.output_ring[jr.tail].desc);
+ addr_hi = (uint32_t *)(&jr.output_ring[jr.tail].desc) + 1;
+ #elif defined(CONFIG_SYS_FSL_SEC_BE)
+ addr_hi = (uint32_t *)(&jr.output_ring[jr.tail].desc);
+ addr_lo = (uint32_t *)(&jr.output_ring[jr.tail].desc) + 1;
+ #endif /* ifdef CONFIG_SYS_FSL_SEC_LE */
+
+ op_desc = ((u64)sec_in32(addr_hi) << 32) |
+ ((u64)sec_in32(addr_lo));
+
+ #else
+ /* Read the 32 bit Descriptor address from Output Ring. */
+ addr = (uint32_t *)&jr.output_ring[jr.tail].desc;
+ op_desc = sec_in32(addr);
+ #endif /* ifdef CONFIG_PHYS_64BIT */
+
+ uint32_t status = sec_in32(&jr.output_ring[jr.tail].status);
for (i = 0; CIRC_CNT(head, tail + i, jr.size) >= 1; i++) {
idx = (tail + i) & (jr.size - 1);
if (op_desc == jr.info[idx].desc_phys_addr) {
- desc_virt = jr.info[idx].desc_addr;
found = 1;
break;
}
@@ -244,13 +306,13 @@ static int jr_dequeue(void)
sec_out32(&regs->orjr, 1);
jr.info[idx].op_done = 0;
- callback(desc_virt, status, arg);
+ callback(status, arg);
}
return 0;
}
-static void desc_done(uint32_t desc, uint32_t status, void *arg)
+static void desc_done(uint32_t status, void *arg)
{
struct result *x = arg;
x->status = status;
diff --git a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h
index 1526060..5899696 100644
--- a/drivers/crypto/fsl/jr.h
+++ b/drivers/crypto/fsl/jr.h
@@ -37,14 +37,13 @@
#define JQ_ENQ_ERR -3
struct op_ring {
- dma_addr_t desc;
+ phys_addr_t desc;
uint32_t status;
} __packed;
struct jr_info {
- void (*callback)(dma_addr_t desc, uint32_t status, void *arg);
- dma_addr_t desc_phys_addr;
- uint32_t desc_addr;
+ void (*callback)(uint32_t status, void *arg);
+ phys_addr_t desc_phys_addr;
uint32_t desc_len;
uint32_t op_done;
void *arg;
diff --git a/drivers/ddr/fsl/Makefile b/drivers/ddr/fsl/Makefile
index df66c07..01ea862 100644
--- a/drivers/ddr/fsl/Makefile
+++ b/drivers/ddr/fsl/Makefile
@@ -1,9 +1,7 @@
#
# Copyright 2008-2014 Freescale Semiconductor, Inc.
#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License
-# Version 2 as published by the Free Software Foundation.
+# SPDX-License-Identifier: GPL-2.0
#
obj-$(CONFIG_SYS_FSL_DDR1) += main.o util.o ctrl_regs.o options.o \
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index 8367c95..8543679 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -858,7 +858,7 @@ static void set_ddr_sdram_cfg_2(const unsigned int ctrl_num,
break;
}
}
-
+ sr_ie = popts->self_refresh_interrupt_en;
num_pr = 1; /* Make this configurable */
/*
diff --git a/drivers/dfu/dfu_sf.c b/drivers/dfu/dfu_sf.c
index 7646c6b..9702eee 100644
--- a/drivers/dfu/dfu_sf.c
+++ b/drivers/dfu/dfu_sf.c
@@ -115,8 +115,10 @@ static struct spi_flash *parse_dev(char *devstr)
int dfu_fill_entity_sf(struct dfu_entity *dfu, char *devstr, char *s)
{
char *st;
+ char *devstr_bkup = strdup(devstr);
- dfu->data.sf.dev = parse_dev(devstr);
+ dfu->data.sf.dev = parse_dev(devstr_bkup);
+ free(devstr_bkup);
if (!dfu->data.sf.dev)
return -ENODEV;
diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index 0f977d7..fa4c82f 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -523,8 +523,8 @@ static int bus_i2c_write(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
#endif
static struct mxc_i2c_bus mxc_i2c_buses[] = {
-#if defined(CONFIG_LS102XA) || defined(CONFIG_FSL_LSCH3) || \
- defined(CONFIG_VF610)
+#if defined(CONFIG_LS102XA) || defined(CONFIG_VF610) || \
+ defined(CONFIG_FSL_LAYERSCAPE)
{ 0, I2C1_BASE_ADDR, I2C_QUIRK_FLAG },
{ 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG },
{ 2, I2C3_BASE_ADDR, I2C_QUIRK_FLAG },
diff --git a/drivers/input/cros_ec_keyb.c b/drivers/input/cros_ec_keyb.c
index a31aa77..dd150ee 100644
--- a/drivers/input/cros_ec_keyb.c
+++ b/drivers/input/cros_ec_keyb.c
@@ -258,7 +258,7 @@ int drv_keyboard_init(void)
memset(&dev, '\0', sizeof(dev));
strcpy(dev.name, "cros-ec-keyb");
- dev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
+ dev.flags = DEV_FLAGS_INPUT;
dev.getc = kbd_getc;
dev.tstc = kbd_tstc;
dev.start = cros_ec_init_keyboard;
diff --git a/drivers/input/keyboard.c b/drivers/input/keyboard.c
index be0f333..ca3886a 100644
--- a/drivers/input/keyboard.c
+++ b/drivers/input/keyboard.c
@@ -274,7 +274,7 @@ int kbd_init (void)
return -1;
memset (&kbddev, 0, sizeof(kbddev));
strcpy(kbddev.name, DEVNAME);
- kbddev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
+ kbddev.flags = DEV_FLAGS_INPUT;
kbddev.getc = kbd_getc ;
kbddev.tstc = kbd_testc ;
diff --git a/drivers/input/tegra-kbc.c b/drivers/input/tegra-kbc.c
index c9c9fac..6b88db4 100644
--- a/drivers/input/tegra-kbc.c
+++ b/drivers/input/tegra-kbc.c
@@ -358,7 +358,7 @@ int drv_keyboard_init(void)
memset(&dev, '\0', sizeof(dev));
strcpy(dev.name, "tegra-kbc");
- dev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
+ dev.flags = DEV_FLAGS_INPUT;
dev.getc = kbd_getc;
dev.tstc = kbd_tstc;
dev.start = init_tegra_keyboard;
diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile
index 9bfb9c7..6124e38 100644
--- a/drivers/memory/Makefile
+++ b/drivers/memory/Makefile
@@ -1 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
obj-$(CONFIG_TI_AEMIF) += ti-aemif.o
diff --git a/drivers/misc/altera_sysid.c b/drivers/misc/altera_sysid.c
index 249b273..737520f 100644
--- a/drivers/misc/altera_sysid.c
+++ b/drivers/misc/altera_sysid.c
@@ -87,8 +87,8 @@ static const struct misc_ops altera_sysid_ops = {
};
static const struct udevice_id altera_sysid_ids[] = {
- { .compatible = "altr,sysid-1.0", },
- { }
+ { .compatible = "altr,sysid-1.0" },
+ {}
};
U_BOOT_DRIVER(altera_sysid) = {
diff --git a/drivers/misc/fsl_debug_server.c b/drivers/misc/fsl_debug_server.c
index a592891..98d9fbe 100644
--- a/drivers/misc/fsl_debug_server.c
+++ b/drivers/misc/fsl_debug_server.c
@@ -8,7 +8,6 @@
#include <errno.h>
#include <asm/io.h>
#include <asm/system.h>
-#include <asm/arch-fsl-lsch3/immap_lsch3.h>
#include <fsl-mc/fsl_mc.h>
#include <fsl_debug_server.h>
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 99d0295..5d35705 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -8,6 +8,7 @@
obj-$(CONFIG_DM_MMC) += mmc-uclass.o
obj-$(CONFIG_ARM_PL180_MMCI) += arm_pl180_mmci.o
+obj-$(CONFIG_ATMEL_SDHCI) += atmel_sdhci.o
obj-$(CONFIG_BCM2835_SDHCI) += bcm2835_sdhci.o
obj-$(CONFIG_BFIN_SDH) += bfin_sdh.o
obj-$(CONFIG_DAVINCI_MMC) += davinci_mmc.o
diff --git a/drivers/mmc/atmel_sdhci.c b/drivers/mmc/atmel_sdhci.c
new file mode 100644
index 0000000..24b68b6
--- /dev/null
+++ b/drivers/mmc/atmel_sdhci.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2015 Atmel Corporation
+ * Wenyou.Yang <wenyou.yang@atmel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <sdhci.h>
+#include <asm/arch/clk.h>
+
+#define ATMEL_SDHC_MIN_FREQ 400000
+
+int atmel_sdhci_init(void *regbase, u32 id)
+{
+ struct sdhci_host *host;
+ u32 max_clk, min_clk = ATMEL_SDHC_MIN_FREQ;
+
+ host = (struct sdhci_host *)calloc(1, sizeof(struct sdhci_host));
+ if (!host) {
+ printf("%s: sdhci_host calloc failed\n", __func__);
+ return -ENOMEM;
+ }
+
+ host->name = "atmel_sdhci";
+ host->ioaddr = regbase;
+ host->quirks = 0;
+ host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
+ max_clk = at91_get_periph_generated_clk(id);
+ if (!max_clk) {
+ printf("%s: Failed to get the proper clock\n", __func__);
+ free(host);
+ return -ENODEV;
+ }
+
+ add_sdhci(host, max_clk, min_clk);
+
+ return 0;
+}
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 0b37002..c5054d6 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -106,7 +106,8 @@ static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
xfertyp |= XFERTYP_RSPTYP_48;
#if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) || \
- defined(CONFIG_LS102XA) || defined(CONFIG_LS2085A)
+ defined(CONFIG_LS102XA) || defined(CONFIG_FSL_LAYERSCAPE) || \
+ defined(CONFIG_PPC_T4160)
if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
xfertyp |= XFERTYP_CMDTYP_ABORT;
#endif
@@ -184,7 +185,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
int timeout;
struct fsl_esdhc_cfg *cfg = mmc->priv;
struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
-#ifdef CONFIG_LS2085A
+#ifdef CONFIG_FSL_LAYERSCAPE
dma_addr_t addr;
#endif
uint wml_value;
@@ -197,7 +198,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
-#ifdef CONFIG_LS2085A
+#ifdef CONFIG_FSL_LAYERSCAPE
addr = virt_to_phys((void *)(data->dest));
if (upper_32_bits(addr))
printf("Error found for upper 32 bits\n");
@@ -223,7 +224,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
wml_value << 16);
#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
-#ifdef CONFIG_LS2085A
+#ifdef CONFIG_FSL_LAYERSCAPE
addr = virt_to_phys((void *)(data->src));
if (upper_32_bits(addr))
printf("Error found for upper 32 bits\n");
@@ -277,7 +278,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
static void check_and_invalidate_dcache_range
(struct mmc_cmd *cmd,
struct mmc_data *data) {
-#ifdef CONFIG_LS2085A
+#ifdef CONFIG_FSL_LAYERSCAPE
unsigned start = 0;
#else
unsigned start = (unsigned)data->dest ;
@@ -285,7 +286,7 @@ static void check_and_invalidate_dcache_range
unsigned size = roundup(ARCH_DMA_MINALIGN,
data->blocks*data->blocksize);
unsigned end = start+size ;
-#ifdef CONFIG_LS2085A
+#ifdef CONFIG_FSL_LAYERSCAPE
dma_addr_t addr;
addr = virt_to_phys((void *)(data->dest));
@@ -747,8 +748,14 @@ void mmc_adapter_card_type_ident(void)
switch (card_id) {
case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45:
+ value = QIXIS_READ(brdcfg[5]);
+ value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7);
+ QIXIS_WRITE(brdcfg[5], value);
break;
case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY:
+ value = QIXIS_READ(pwr_ctl[1]);
+ value |= QIXIS_EVDD_BY_SDHC_VS;
+ QIXIS_WRITE(pwr_ctl[1], value);
break;
case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44:
value = QIXIS_READ(brdcfg[5]);
diff --git a/drivers/mmc/gen_atmel_mci.c b/drivers/mmc/gen_atmel_mci.c
index 45bcffb..da870c6 100644
--- a/drivers/mmc/gen_atmel_mci.c
+++ b/drivers/mmc/gen_atmel_mci.c
@@ -32,7 +32,11 @@
# define MCI_BUS 0
#endif
-static int initialized = 0;
+struct atmel_mci_priv {
+ struct mmc_config cfg;
+ struct atmel_mci *mci;
+ unsigned int initialized:1;
+};
/* Read Atmel MCI IP version */
static unsigned int atmel_mci_get_version(struct atmel_mci *mci)
@@ -48,14 +52,15 @@ static unsigned int atmel_mci_get_version(struct atmel_mci *mci)
*/
static void dump_cmd(u32 cmdr, u32 arg, u32 status, const char* msg)
{
- printf("gen_atmel_mci: CMDR %08x (%2u) ARGR %08x (SR: %08x) %s\n",
- cmdr, cmdr&0x3F, arg, status, msg);
+ debug("gen_atmel_mci: CMDR %08x (%2u) ARGR %08x (SR: %08x) %s\n",
+ cmdr, cmdr & 0x3F, arg, status, msg);
}
/* Setup for MCI Clock and Block Size */
static void mci_set_mode(struct mmc *mmc, u32 hz, u32 blklen)
{
- atmel_mci_t *mci = mmc->priv;
+ struct atmel_mci_priv *priv = mmc->priv;
+ atmel_mci_t *mci = priv->mci;
u32 bus_hz = get_mci_clk_rate();
u32 clkdiv = 255;
unsigned int version = atmel_mci_get_version(mci);
@@ -73,16 +78,16 @@ static void mci_set_mode(struct mmc *mmc, u32 hz, u32 blklen)
clkodd = clkdiv & 1;
clkdiv >>= 1;
- printf("mci: setting clock %u Hz, block size %u\n",
- bus_hz / (clkdiv * 2 + clkodd + 2), blklen);
+ debug("mci: setting clock %u Hz, block size %u\n",
+ bus_hz / (clkdiv * 2 + clkodd + 2), blklen);
} else {
/* find clkdiv yielding a rate <= than requested */
for (clkdiv = 0; clkdiv < 255; clkdiv++) {
if ((bus_hz / (clkdiv + 1) / 2) <= hz)
break;
}
- printf("mci: setting clock %u Hz, block size %u\n",
- (bus_hz / (clkdiv + 1)) / 2, blklen);
+ debug("mci: setting clock %u Hz, block size %u\n",
+ (bus_hz / (clkdiv + 1)) / 2, blklen);
}
}
@@ -113,7 +118,9 @@ static void mci_set_mode(struct mmc *mmc, u32 hz, u32 blklen)
if (mmc->card_caps & mmc->cfg->host_caps & MMC_MODE_HS)
writel(MMCI_BIT(HSMODE), &mci->cfg);
- initialized = 1;
+ udelay(50);
+
+ priv->initialized = 1;
}
/* Return the CMDR with flags for a given command and data packet */
@@ -196,12 +203,13 @@ io_fail:
static int
mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
{
- atmel_mci_t *mci = mmc->priv;
+ struct atmel_mci_priv *priv = mmc->priv;
+ atmel_mci_t *mci = priv->mci;
u32 cmdr;
u32 error_flags = 0;
u32 status;
- if (!initialized) {
+ if (!priv->initialized) {
puts ("MCI not initialized!\n");
return COMM_ERR;
}
@@ -321,7 +329,8 @@ mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
/* Entered into mmc structure during driver init */
static void mci_set_ios(struct mmc *mmc)
{
- atmel_mci_t *mci = mmc->priv;
+ struct atmel_mci_priv *priv = mmc->priv;
+ atmel_mci_t *mci = priv->mci;
int bus_width = mmc->bus_width;
unsigned int version = atmel_mci_get_version(mci);
int busw;
@@ -357,7 +366,8 @@ static void mci_set_ios(struct mmc *mmc)
/* Entered into mmc structure during driver init */
static int mci_init(struct mmc *mmc)
{
- atmel_mci_t *mci = mmc->priv;
+ struct atmel_mci_priv *priv = mmc->priv;
+ atmel_mci_t *mci = priv->mci;
/* Initialize controller */
writel(MMCI_BIT(SWRST), &mci->cr); /* soft reset */
@@ -391,22 +401,24 @@ int atmel_mci_init(void *regs)
{
struct mmc *mmc;
struct mmc_config *cfg;
- struct atmel_mci *mci;
+ struct atmel_mci_priv *priv;
unsigned int version;
- cfg = malloc(sizeof(*cfg));
- if (cfg == NULL)
- return -1;
- memset(cfg, 0, sizeof(*cfg));
+ priv = calloc(1, sizeof(*priv));
+ if (!priv)
+ return -ENOMEM;
- mci = (struct atmel_mci *)regs;
+ cfg = &priv->cfg;
cfg->name = "mci";
cfg->ops = &atmel_mci_ops;
+ priv->mci = (struct atmel_mci *)regs;
+ priv->initialized = 0;
+
/* need to be able to pass these in on a board by board basis */
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
- version = atmel_mci_get_version(mci);
+ version = atmel_mci_get_version(priv->mci);
if ((version & 0xf00) >= 0x300) {
cfg->host_caps = MMC_MODE_8BIT;
cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
@@ -423,13 +435,13 @@ int atmel_mci_init(void *regs)
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
- mmc = mmc_create(cfg, regs);
+ mmc = mmc_create(cfg, priv);
if (mmc == NULL) {
- free(cfg);
- return -1;
+ free(priv);
+ return -ENODEV;
}
- /* NOTE: possibly leaking the cfg structure */
+ /* NOTE: possibly leaking the priv structure */
return 0;
}
diff --git a/drivers/mmc/s5p_sdhci.c b/drivers/mmc/s5p_sdhci.c
index 15ecfee..44353c7 100644
--- a/drivers/mmc/s5p_sdhci.c
+++ b/drivers/mmc/s5p_sdhci.c
@@ -106,6 +106,12 @@ static int do_sdhci_init(struct sdhci_host *host)
flag = host->bus_width == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE;
dev_id = host->index + PERIPH_ID_SDMMC0;
+ ret = exynos_pinmux_config(dev_id, flag);
+ if (ret) {
+ printf("external SD not configured\n");
+ return ret;
+ }
+
if (dm_gpio_is_valid(&host->pwr_gpio)) {
dm_gpio_set_value(&host->pwr_gpio, 1);
ret = exynos_pinmux_config(dev_id, flag);
@@ -121,12 +127,6 @@ static int do_sdhci_init(struct sdhci_host *host)
debug("no SD card detected (%d)\n", ret);
return -ENODEV;
}
-
- ret = exynos_pinmux_config(dev_id, flag);
- if (ret) {
- printf("external SD not configured\n");
- return ret;
- }
}
return s5p_sdhci_core_init(host);
@@ -193,7 +193,7 @@ static int process_nodes(const void *blob, int node_list[], int count)
}
ret = do_sdhci_init(host);
- if (ret) {
+ if (ret && ret != -ENODEV) {
printf("%s: failed to initialize dev %d (%d)\n", __func__, i, ret);
failed++;
}
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index d89e302..02d71b9 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -286,9 +286,25 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
{
struct sdhci_host *host = mmc->priv;
- unsigned int div, clk, timeout;
+ unsigned int div, clk, timeout, reg;
- sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
+ /* Wait max 20 ms */
+ timeout = 200;
+ while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
+ (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
+ if (timeout == 0) {
+ printf("%s: Timeout to wait cmd & data inhibit\n",
+ __func__);
+ return -1;
+ }
+
+ timeout--;
+ udelay(100);
+ }
+
+ reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
+ reg &= ~SDHCI_CLOCK_CARD_EN;
+ sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL);
if (clock == 0)
return 0;
diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig
index 59278d1..c58841e 100644
--- a/drivers/mtd/Kconfig
+++ b/drivers/mtd/Kconfig
@@ -1,3 +1,35 @@
+menu "MTD Support"
+
+config MTD
+ bool "Enable Driver Model for MTD drivers"
+ depends on DM
+ help
+ Enable driver model for Memory Technology Devices (MTD), such as
+ flash, RAM and similar chips, often used for solid state file
+ systems on embedded devices.
+
+config CFI_FLASH
+ bool "Enable Driver Model for CFI Flash driver"
+ depends on MTD
+ help
+ The Common Flash Interface specification was developed by Intel,
+ AMD and other flash manufactures. It provides a universal method
+ for probing the capabilities of flash devices. If you wish to
+ support any device that is CFI-compliant, you need to enable this
+ option. Visit <http://www.amd.com/products/nvd/overview/cfi.html>
+ for more information on CFI.
+
+config ALTERA_QSPI
+ bool "Altera Generic Quad SPI Controller"
+ depends on MTD
+ help
+ This enables access to Altera EPCQ/EPCS flash chips using the
+ Altera Generic Quad SPI Controller. The controller converts SPI
+ NOR flash to parallel flash interface. Please find details on the
+ "Embedded Peripherals IP User Guide" of Altera.
+
+endmenu
+
source "drivers/mtd/nand/Kconfig"
source "drivers/mtd/spi/Kconfig"
diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile
index a623f4c..7f018a4 100644
--- a/drivers/mtd/Makefile
+++ b/drivers/mtd/Makefile
@@ -8,8 +8,10 @@
ifneq (,$(findstring y,$(CONFIG_MTD_DEVICE)$(CONFIG_CMD_NAND)$(CONFIG_CMD_ONENAND)$(CONFIG_CMD_SF)))
obj-y += mtdcore.o mtd_uboot.o
endif
+obj-$(CONFIG_MTD) += mtd-uclass.o
obj-$(CONFIG_MTD_PARTITIONS) += mtdpart.o
obj-$(CONFIG_MTD_CONCAT) += mtdconcat.o
+obj-$(CONFIG_ALTERA_QSPI) += altera_qspi.o
obj-$(CONFIG_HAS_DATAFLASH) += at45.o
obj-$(CONFIG_FLASH_CFI_DRIVER) += cfi_flash.o
obj-$(CONFIG_FLASH_CFI_MTD) += cfi_mtd.o
diff --git a/drivers/mtd/altera_qspi.c b/drivers/mtd/altera_qspi.c
new file mode 100644
index 0000000..1826dc8
--- /dev/null
+++ b/drivers/mtd/altera_qspi.c
@@ -0,0 +1,273 @@
+/*
+ * Copyright (C) 2015 Thomas Chou <thomas@wytron.com.tw>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdt_support.h>
+#include <flash.h>
+#include <mtd.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * The QUADSPI_MEM_OP register is used to do memory protect and erase operations
+ */
+#define QUADSPI_MEM_OP_BULK_ERASE 0x00000001
+#define QUADSPI_MEM_OP_SECTOR_ERASE 0x00000002
+#define QUADSPI_MEM_OP_SECTOR_PROTECT 0x00000003
+
+/*
+ * The QUADSPI_ISR register is used to determine whether an invalid write or
+ * erase operation trigerred an interrupt
+ */
+#define QUADSPI_ISR_ILLEGAL_ERASE BIT(0)
+#define QUADSPI_ISR_ILLEGAL_WRITE BIT(1)
+
+struct altera_qspi_regs {
+ u32 rd_status;
+ u32 rd_sid;
+ u32 rd_rdid;
+ u32 mem_op;
+ u32 isr;
+ u32 imr;
+ u32 chip_select;
+};
+
+struct altera_qspi_platdata {
+ struct altera_qspi_regs *regs;
+ void *base;
+ unsigned long size;
+};
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* FLASH chips info */
+
+void flash_print_info(flash_info_t *info)
+{
+ printf("Altera QSPI flash Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+}
+
+int flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+ struct mtd_info *mtd = info->mtd;
+ struct erase_info instr;
+ int ret;
+
+ memset(&instr, 0, sizeof(instr));
+ instr.addr = mtd->erasesize * s_first;
+ instr.len = mtd->erasesize * (s_last + 1 - s_first);
+ ret = mtd_erase(mtd, &instr);
+ if (ret)
+ return ERR_NOT_ERASED;
+
+ return 0;
+}
+
+int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+ struct mtd_info *mtd = info->mtd;
+ struct udevice *dev = mtd->dev;
+ struct altera_qspi_platdata *pdata = dev_get_platdata(dev);
+ ulong base = (ulong)pdata->base;
+ loff_t to = addr - base;
+ size_t retlen;
+ int ret;
+
+ ret = mtd_write(mtd, to, cnt, &retlen, src);
+ if (ret)
+ return ERR_NOT_ERASED;
+
+ return 0;
+}
+
+unsigned long flash_init(void)
+{
+ struct udevice *dev;
+
+ /* probe every MTD device */
+ for (uclass_first_device(UCLASS_MTD, &dev);
+ dev;
+ uclass_next_device(&dev)) {
+ }
+
+ return flash_info[0].size;
+}
+
+static int altera_qspi_erase(struct mtd_info *mtd, struct erase_info *instr)
+{
+ struct udevice *dev = mtd->dev;
+ struct altera_qspi_platdata *pdata = dev_get_platdata(dev);
+ struct altera_qspi_regs *regs = pdata->regs;
+ size_t addr = instr->addr;
+ size_t len = instr->len;
+ size_t end = addr + len;
+ u32 sect;
+ u32 stat;
+
+ instr->state = MTD_ERASING;
+ addr &= ~(mtd->erasesize - 1); /* get lower aligned address */
+ while (addr < end) {
+ sect = addr / mtd->erasesize;
+ sect <<= 8;
+ sect |= QUADSPI_MEM_OP_SECTOR_ERASE;
+ debug("erase %08x\n", sect);
+ writel(sect, &regs->mem_op);
+ stat = readl(&regs->isr);
+ if (stat & QUADSPI_ISR_ILLEGAL_ERASE) {
+ /* erase failed, sector might be protected */
+ debug("erase %08x fail %x\n", sect, stat);
+ writel(stat, &regs->isr); /* clear isr */
+ instr->state = MTD_ERASE_FAILED;
+ return -EIO;
+ }
+ addr += mtd->erasesize;
+ }
+ instr->state = MTD_ERASE_DONE;
+ mtd_erase_callback(instr);
+
+ return 0;
+}
+
+static int altera_qspi_read(struct mtd_info *mtd, loff_t from, size_t len,
+ size_t *retlen, u_char *buf)
+{
+ struct udevice *dev = mtd->dev;
+ struct altera_qspi_platdata *pdata = dev_get_platdata(dev);
+
+ memcpy_fromio(buf, pdata->base + from, len);
+ *retlen = len;
+
+ return 0;
+}
+
+static int altera_qspi_write(struct mtd_info *mtd, loff_t to, size_t len,
+ size_t *retlen, const u_char *buf)
+{
+ struct udevice *dev = mtd->dev;
+ struct altera_qspi_platdata *pdata = dev_get_platdata(dev);
+ struct altera_qspi_regs *regs = pdata->regs;
+ u32 stat;
+
+ memcpy_toio(pdata->base + to, buf, len);
+ /* check whether write triggered a illegal write interrupt */
+ stat = readl(&regs->isr);
+ if (stat & QUADSPI_ISR_ILLEGAL_WRITE) {
+ /* write failed, sector might be protected */
+ debug("write fail %x\n", stat);
+ writel(stat, &regs->isr); /* clear isr */
+ return -EIO;
+ }
+ *retlen = len;
+
+ return 0;
+}
+
+static void altera_qspi_sync(struct mtd_info *mtd)
+{
+}
+
+static int altera_qspi_probe(struct udevice *dev)
+{
+ struct altera_qspi_platdata *pdata = dev_get_platdata(dev);
+ struct altera_qspi_regs *regs = pdata->regs;
+ unsigned long base = (unsigned long)pdata->base;
+ struct mtd_info *mtd;
+ flash_info_t *flash = &flash_info[0];
+ u32 rdid;
+ int i;
+
+ rdid = readl(&regs->rd_rdid);
+ debug("rdid %x\n", rdid);
+
+ mtd = dev_get_uclass_priv(dev);
+ mtd->dev = dev;
+ mtd->name = "nor0";
+ mtd->type = MTD_NORFLASH;
+ mtd->flags = MTD_CAP_NORFLASH;
+ mtd->size = 1 << ((rdid & 0xff) - 6);
+ mtd->writesize = 1;
+ mtd->writebufsize = mtd->writesize;
+ mtd->_erase = altera_qspi_erase;
+ mtd->_read = altera_qspi_read;
+ mtd->_write = altera_qspi_write;
+ mtd->_sync = altera_qspi_sync;
+ mtd->numeraseregions = 0;
+ mtd->erasesize = 0x10000;
+ if (add_mtd_device(mtd))
+ return -ENOMEM;
+
+ flash->mtd = mtd;
+ flash->size = mtd->size;
+ flash->sector_count = mtd->size / mtd->erasesize;
+ flash->flash_id = rdid;
+ flash->start[0] = base;
+ for (i = 1; i < flash->sector_count; i++)
+ flash->start[i] = flash->start[i - 1] + mtd->erasesize;
+ gd->bd->bi_flashstart = base;
+
+ return 0;
+}
+
+static int altera_qspi_ofdata_to_platdata(struct udevice *dev)
+{
+ struct altera_qspi_platdata *pdata = dev_get_platdata(dev);
+ void *blob = (void *)gd->fdt_blob;
+ int node = dev->of_offset;
+ const char *list, *end;
+ const fdt32_t *cell;
+ void *base;
+ unsigned long addr, size;
+ int parent, addrc, sizec;
+ int len, idx;
+
+ /*
+ * decode regs. there are multiple reg tuples, and they need to
+ * match with reg-names.
+ */
+ parent = fdt_parent_offset(blob, node);
+ of_bus_default_count_cells(blob, parent, &addrc, &sizec);
+ list = fdt_getprop(blob, node, "reg-names", &len);
+ if (!list)
+ return -ENOENT;
+ end = list + len;
+ cell = fdt_getprop(blob, node, "reg", &len);
+ if (!cell)
+ return -ENOENT;
+ idx = 0;
+ while (list < end) {
+ addr = fdt_translate_address((void *)blob,
+ node, cell + idx);
+ size = fdt_addr_to_cpu(cell[idx + addrc]);
+ base = ioremap(addr, size);
+ len = strlen(list);
+ if (strcmp(list, "avl_csr") == 0) {
+ pdata->regs = base;
+ } else if (strcmp(list, "avl_mem") == 0) {
+ pdata->base = base;
+ pdata->size = size;
+ }
+ idx += addrc + sizec;
+ list += (len + 1);
+ }
+
+ return 0;
+}
+
+static const struct udevice_id altera_qspi_ids[] = {
+ { .compatible = "altr,quadspi-1.0" },
+ {}
+};
+
+U_BOOT_DRIVER(altera_qspi) = {
+ .name = "altera_qspi",
+ .id = UCLASS_MTD,
+ .of_match = altera_qspi_ids,
+ .ofdata_to_platdata = altera_qspi_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct altera_qspi_platdata),
+ .probe = altera_qspi_probe,
+};
diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c
index fc7a878..e3cb598 100644
--- a/drivers/mtd/cfi_flash.c
+++ b/drivers/mtd/cfi_flash.c
@@ -18,6 +18,9 @@
/* #define DEBUG */
#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdt_support.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/byteorder.h>
@@ -47,6 +50,8 @@
* reading and writing ... (yes there is such a Hardware).
*/
+DECLARE_GLOBAL_DATA_PTR;
+
static uint flash_offset_cfi[2] = { FLASH_OFFSET_CFI, FLASH_OFFSET_CFI_ALT };
#ifdef CONFIG_FLASH_CFI_MTD
static uint flash_verbose = 1;
@@ -87,10 +92,36 @@ static u16 cfi_flash_config_reg(int i)
int cfi_flash_num_flash_banks = CONFIG_SYS_MAX_FLASH_BANKS_DETECT;
#endif
+#ifdef CONFIG_CFI_FLASH /* for driver model */
+static void cfi_flash_init_dm(void)
+{
+ struct udevice *dev;
+
+ cfi_flash_num_flash_banks = 0;
+ /*
+ * The uclass_first_device() will probe the first device and
+ * uclass_next_device() will probe the rest if they exist. So
+ * that cfi_flash_probe() will get called assigning the base
+ * addresses that are available.
+ */
+ for (uclass_first_device(UCLASS_MTD, &dev);
+ dev;
+ uclass_next_device(&dev)) {
+ }
+}
+
+static phys_addr_t cfi_flash_base[CFI_MAX_FLASH_BANKS];
+
+phys_addr_t cfi_flash_bank_addr(int i)
+{
+ return cfi_flash_base[i];
+}
+#else
__weak phys_addr_t cfi_flash_bank_addr(int i)
{
return ((phys_addr_t [])CONFIG_SYS_FLASH_BANKS_LIST)[i];
}
+#endif
__weak unsigned long cfi_flash_bank_size(int i)
{
@@ -2322,6 +2353,10 @@ unsigned long flash_init (void)
getenv_f("unlock", s, sizeof(s));
#endif
+#ifdef CONFIG_CFI_FLASH /* for driver model */
+ cfi_flash_init_dm();
+#endif
+
/* Init: no FLASHes known */
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
@@ -2398,3 +2433,46 @@ unsigned long flash_init (void)
return (size);
}
+
+#ifdef CONFIG_CFI_FLASH /* for driver model */
+static int cfi_flash_probe(struct udevice *dev)
+{
+ void *blob = (void *)gd->fdt_blob;
+ int node = dev->of_offset;
+ const fdt32_t *cell;
+ phys_addr_t addr;
+ int parent, addrc, sizec;
+ int len, idx;
+
+ parent = fdt_parent_offset(blob, node);
+ of_bus_default_count_cells(blob, parent, &addrc, &sizec);
+ /* decode regs, there may be multiple reg tuples. */
+ cell = fdt_getprop(blob, node, "reg", &len);
+ if (!cell)
+ return -ENOENT;
+ idx = 0;
+ len /= sizeof(fdt32_t);
+ while (idx < len) {
+ addr = fdt_translate_address((void *)blob,
+ node, cell + idx);
+ cfi_flash_base[cfi_flash_num_flash_banks++] = addr;
+ idx += addrc + sizec;
+ }
+ gd->bd->bi_flashstart = cfi_flash_base[0];
+
+ return 0;
+}
+
+static const struct udevice_id cfi_flash_ids[] = {
+ { .compatible = "cfi-flash" },
+ { .compatible = "jedec-flash" },
+ {}
+};
+
+U_BOOT_DRIVER(cfi_flash) = {
+ .name = "cfi_flash",
+ .id = UCLASS_MTD,
+ .of_match = cfi_flash_ids,
+ .probe = cfi_flash_probe,
+};
+#endif /* CONFIG_CFI_FLASH */
diff --git a/drivers/mtd/mtd-uclass.c b/drivers/mtd/mtd-uclass.c
new file mode 100644
index 0000000..7b7c48e
--- /dev/null
+++ b/drivers/mtd/mtd-uclass.c
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2015 Thomas Chou <thomas@wytron.com.tw>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <mtd.h>
+
+/*
+ * Implement a MTD uclass which should include most flash drivers.
+ * The uclass private is pointed to mtd_info.
+ */
+
+UCLASS_DRIVER(mtd) = {
+ .id = UCLASS_MTD,
+ .name = "mtd",
+ .per_device_auto_alloc_size = sizeof(struct mtd_info),
+};
diff --git a/drivers/mtd/mtdcore.c b/drivers/mtd/mtdcore.c
index 2f2172b..e3f56e5 100644
--- a/drivers/mtd/mtdcore.c
+++ b/drivers/mtd/mtdcore.c
@@ -27,11 +27,11 @@
#include <linux/gfp.h>
#include <linux/slab.h>
#else
-#include <linux/compat.h>
#include <linux/err.h>
#include <ubi_uboot.h>
#endif
+#include <linux/log2.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 8a3e5ec..8793f18 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -105,6 +105,9 @@ enum spi_nor_option_flags {
#define STATUS_QEB_WINSPAN (1 << 1)
#define STATUS_QEB_MXIC (1 << 6)
#define STATUS_PEC (1 << 7)
+#define SR_BP0 BIT(2) /* Block protect 0 */
+#define SR_BP1 BIT(3) /* Block protect 1 */
+#define SR_BP2 BIT(4) /* Block protect 2 */
/* Flash timeout values */
#define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ)
@@ -173,6 +176,15 @@ int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs);
/* Program the status register */
int spi_flash_cmd_write_status(struct spi_flash *flash, u8 ws);
+/* Lock stmicro spi flash region */
+int stm_lock(struct spi_flash *flash, u32 ofs, size_t len);
+
+/* Unlock stmicro spi flash region */
+int stm_unlock(struct spi_flash *flash, u32 ofs, size_t len);
+
+/* Check if a stmicro spi flash region is completely locked */
+int stm_is_locked(struct spi_flash *flash, u32 ofs, size_t len);
+
/* Read the config register */
int spi_flash_cmd_read_config(struct spi_flash *flash, u8 *rc);
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index f2a9244..d832464 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -15,6 +15,7 @@
#include <spi_flash.h>
#include <watchdog.h>
#include <linux/compiler.h>
+#include <linux/log2.h>
#include "sf_internal.h"
@@ -267,6 +268,11 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
return -1;
}
+ if (flash->flash_is_locked(flash, offset, len) > 0) {
+ printf("offset 0x%x is protected and cannot be erased\n", offset);
+ return -EINVAL;
+ }
+
cmd[0] = flash->erase_cmd;
while (len) {
erase_addr = offset;
@@ -309,6 +315,11 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
page_size = flash->page_size;
+ if (flash->flash_is_locked(flash, offset, len) > 0) {
+ printf("offset 0x%x is protected and cannot be written\n", offset);
+ return -EINVAL;
+ }
+
cmd[0] = flash->write_cmd;
for (actual = 0; actual < len; actual += chunk_len) {
write_addr = offset;
@@ -565,3 +576,172 @@ int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len,
return ret;
}
#endif
+
+#ifdef CONFIG_SPI_FLASH_STMICRO
+static void stm_get_locked_range(struct spi_flash *flash, u8 sr, loff_t *ofs,
+ u32 *len)
+{
+ u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
+ int shift = ffs(mask) - 1;
+ int pow;
+
+ if (!(sr & mask)) {
+ /* No protection */
+ *ofs = 0;
+ *len = 0;
+ } else {
+ pow = ((sr & mask) ^ mask) >> shift;
+ *len = flash->size >> pow;
+ *ofs = flash->size - *len;
+ }
+}
+
+/*
+ * Return 1 if the entire region is locked, 0 otherwise
+ */
+static int stm_is_locked_sr(struct spi_flash *flash, u32 ofs, u32 len,
+ u8 sr)
+{
+ loff_t lock_offs;
+ u32 lock_len;
+
+ stm_get_locked_range(flash, sr, &lock_offs, &lock_len);
+
+ return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs);
+}
+
+/*
+ * Check if a region of the flash is (completely) locked. See stm_lock() for
+ * more info.
+ *
+ * Returns 1 if entire region is locked, 0 if any portion is unlocked, and
+ * negative on errors.
+ */
+int stm_is_locked(struct spi_flash *flash, u32 ofs, size_t len)
+{
+ int status;
+ u8 sr;
+
+ status = spi_flash_cmd_read_status(flash, &sr);
+ if (status < 0)
+ return status;
+
+ return stm_is_locked_sr(flash, ofs, len, sr);
+}
+
+/*
+ * Lock a region of the flash. Compatible with ST Micro and similar flash.
+ * Supports only the block protection bits BP{0,1,2} in the status register
+ * (SR). Does not support these features found in newer SR bitfields:
+ * - TB: top/bottom protect - only handle TB=0 (top protect)
+ * - SEC: sector/block protect - only handle SEC=0 (block protect)
+ * - CMP: complement protect - only support CMP=0 (range is not complemented)
+ *
+ * Sample table portion for 8MB flash (Winbond w25q64fw):
+ *
+ * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion
+ * --------------------------------------------------------------------------
+ * X | X | 0 | 0 | 0 | NONE | NONE
+ * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64
+ * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32
+ * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16
+ * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8
+ * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4
+ * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2
+ * X | X | 1 | 1 | 1 | 8 MB | ALL
+ *
+ * Returns negative on errors, 0 on success.
+ */
+int stm_lock(struct spi_flash *flash, u32 ofs, size_t len)
+{
+ u8 status_old, status_new;
+ u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
+ u8 shift = ffs(mask) - 1, pow, val;
+
+ spi_flash_cmd_read_status(flash, &status_old);
+
+ /* SPI NOR always locks to the end */
+ if (ofs + len != flash->size) {
+ /* Does combined region extend to end? */
+ if (!stm_is_locked_sr(flash, ofs + len, flash->size - ofs - len,
+ status_old))
+ return -EINVAL;
+ len = flash->size - ofs;
+ }
+
+ /*
+ * Need smallest pow such that:
+ *
+ * 1 / (2^pow) <= (len / size)
+ *
+ * so (assuming power-of-2 size) we do:
+ *
+ * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len))
+ */
+ pow = ilog2(flash->size) - ilog2(len);
+ val = mask - (pow << shift);
+ if (val & ~mask)
+ return -EINVAL;
+
+ /* Don't "lock" with no region! */
+ if (!(val & mask))
+ return -EINVAL;
+
+ status_new = (status_old & ~mask) | val;
+
+ /* Only modify protection if it will not unlock other areas */
+ if ((status_new & mask) <= (status_old & mask))
+ return -EINVAL;
+
+ spi_flash_cmd_write_status(flash, status_new);
+
+ return 0;
+}
+
+/*
+ * Unlock a region of the flash. See stm_lock() for more info
+ *
+ * Returns negative on errors, 0 on success.
+ */
+int stm_unlock(struct spi_flash *flash, u32 ofs, size_t len)
+{
+ uint8_t status_old, status_new;
+ u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
+ u8 shift = ffs(mask) - 1, pow, val;
+
+ spi_flash_cmd_read_status(flash, &status_old);
+
+ /* Cannot unlock; would unlock larger region than requested */
+ if (stm_is_locked_sr(flash, status_old, ofs - flash->erase_size,
+ flash->erase_size))
+ return -EINVAL;
+ /*
+ * Need largest pow such that:
+ *
+ * 1 / (2^pow) >= (len / size)
+ *
+ * so (assuming power-of-2 size) we do:
+ *
+ * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len))
+ */
+ pow = ilog2(flash->size) - order_base_2(flash->size - (ofs + len));
+ if (ofs + len == flash->size) {
+ val = 0; /* fully unlocked */
+ } else {
+ val = mask - (pow << shift);
+ /* Some power-of-two sizes are not supported */
+ if (val & ~mask)
+ return -EINVAL;
+ }
+
+ status_new = (status_old & ~mask) | val;
+
+ /* Only modify protection if it will not lock other areas */
+ if ((status_new & mask) >= (status_old & mask))
+ return -EINVAL;
+
+ spi_flash_cmd_write_status(flash, status_new);
+
+ return 0;
+}
+#endif /* CONFIG_SPI_FLASH_STMICRO */
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index c000c53..bc05d30 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -182,6 +182,19 @@ static int spi_flash_validate_params(struct spi_slave *spi, u8 *idcode,
flash->read = spi_flash_cmd_read_ops;
#endif
+ /* lock hooks are flash specific - assign them based on idcode0 */
+ switch (idcode[0]) {
+#ifdef CONFIG_SPI_FLASH_STMICRO
+ case SPI_FLASH_CFI_MFR_STMICRO:
+ flash->flash_lock = stm_lock;
+ flash->flash_unlock = stm_unlock;
+ flash->flash_is_locked = stm_is_locked;
+#endif
+ break;
+ default:
+ debug("SF: Lock ops not supported for %02x flash\n", idcode[0]);
+ }
+
/* Compute the flash size */
flash->shift = (flash->dual_flash & SF_DUAL_PARALLEL_FLASH) ? 1 : 0;
/*
diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c
index f0a3b67..f484e62 100644
--- a/drivers/mtd/ubi/build.c
+++ b/drivers/mtd/ubi/build.c
@@ -30,7 +30,7 @@
#include <linux/slab.h>
#include <linux/major.h>
#else
-#include <linux/compat.h>
+#include <linux/log2.h>
#endif
#include <linux/err.h>
#include <ubi_uboot.h>
diff --git a/drivers/net/altera_tse.c b/drivers/net/altera_tse.c
index 319983c..5692fe9 100644
--- a/drivers/net/altera_tse.c
+++ b/drivers/net/altera_tse.c
@@ -27,12 +27,12 @@ static inline void alt_sgdma_construct_descriptor(
struct alt_sgdma_descriptor *next,
void *read_addr,
void *write_addr,
- unsigned short length_or_eop,
+ u16 length_or_eop,
int generate_eop,
int read_fixed,
int write_fixed_or_sop)
{
- unsigned char val;
+ u8 val;
/*
* Mark the "next" descriptor as "not" owned by hardware. This prevents
@@ -100,7 +100,7 @@ static int alt_sgdma_wait_transfer(struct alt_sgdma_registers *regs)
static int alt_sgdma_start_transfer(struct alt_sgdma_registers *regs,
struct alt_sgdma_descriptor *desc)
{
- unsigned int val;
+ u32 val;
/* Point the controller at the descriptor */
writel(virt_to_phys(desc), &regs->next_descriptor_pointer);
@@ -121,7 +121,7 @@ static void tse_adjust_link(struct altera_tse_priv *priv,
struct phy_device *phydev)
{
struct alt_tse_mac *mac_dev = priv->mac_dev;
- unsigned int refvar;
+ u32 refvar;
if (!phydev->link) {
debug("%s: No link.\n", phydev->dev->name);
@@ -152,13 +152,11 @@ static void tse_adjust_link(struct altera_tse_priv *priv,
writel(refvar, &mac_dev->command_config);
}
-static int altera_tse_send(struct udevice *dev, void *packet, int length)
+static int altera_tse_send_sgdma(struct udevice *dev, void *packet, int length)
{
struct altera_tse_priv *priv = dev_get_priv(dev);
struct alt_sgdma_descriptor *tx_desc = priv->tx_desc;
- unsigned long tx_buf = (unsigned long)packet;
- flush_dcache_range(tx_buf, tx_buf + length);
alt_sgdma_construct_descriptor(
tx_desc,
tx_desc + 1,
@@ -178,7 +176,8 @@ static int altera_tse_send(struct udevice *dev, void *packet, int length)
return tx_desc->actual_bytes_transferred;
}
-static int altera_tse_recv(struct udevice *dev, int flags, uchar **packetp)
+static int altera_tse_recv_sgdma(struct udevice *dev, int flags,
+ uchar **packetp)
{
struct altera_tse_priv *priv = dev_get_priv(dev);
struct alt_sgdma_descriptor *rx_desc = priv->rx_desc;
@@ -186,6 +185,7 @@ static int altera_tse_recv(struct udevice *dev, int flags, uchar **packetp)
if (rx_desc->descriptor_status &
ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK) {
+ alt_sgdma_wait_transfer(priv->sgdma_rx);
packet_length = rx_desc->actual_bytes_transferred;
debug("recv %d bytes\n", packet_length);
*packetp = priv->rx_buf;
@@ -196,15 +196,12 @@ static int altera_tse_recv(struct udevice *dev, int flags, uchar **packetp)
return -EAGAIN;
}
-static int altera_tse_free_pkt(struct udevice *dev, uchar *packet,
- int length)
+static int altera_tse_free_pkt_sgdma(struct udevice *dev, uchar *packet,
+ int length)
{
struct altera_tse_priv *priv = dev_get_priv(dev);
struct alt_sgdma_descriptor *rx_desc = priv->rx_desc;
- unsigned long rx_buf = (unsigned long)priv->rx_buf;
- alt_sgdma_wait_transfer(priv->sgdma_rx);
- invalidate_dcache_range(rx_buf, rx_buf + PKTSIZE_ALIGN);
alt_sgdma_construct_descriptor(
rx_desc,
rx_desc + 1,
@@ -223,16 +220,33 @@ static int altera_tse_free_pkt(struct udevice *dev, uchar *packet,
return 0;
}
-static void altera_tse_stop(struct udevice *dev)
+static void altera_tse_stop_mac(struct altera_tse_priv *priv)
{
- struct altera_tse_priv *priv = dev_get_priv(dev);
struct alt_tse_mac *mac_dev = priv->mac_dev;
+ u32 status;
+ ulong ctime;
+
+ /* reset the mac */
+ writel(ALTERA_TSE_CMD_SW_RESET_MSK, &mac_dev->command_config);
+ ctime = get_timer(0);
+ while (1) {
+ status = readl(&mac_dev->command_config);
+ if (!(status & ALTERA_TSE_CMD_SW_RESET_MSK))
+ break;
+ if (get_timer(ctime) > ALT_TSE_SW_RESET_TIMEOUT) {
+ debug("Reset mac timeout\n");
+ break;
+ }
+ }
+}
+
+static void altera_tse_stop_sgdma(struct udevice *dev)
+{
+ struct altera_tse_priv *priv = dev_get_priv(dev);
struct alt_sgdma_registers *rx_sgdma = priv->sgdma_rx;
struct alt_sgdma_registers *tx_sgdma = priv->sgdma_tx;
struct alt_sgdma_descriptor *rx_desc = priv->rx_desc;
- unsigned int status;
int ret;
- ulong ctime;
/* clear rx desc & wait for sgdma to complete */
rx_desc->descriptor_control = 0;
@@ -247,26 +261,128 @@ static void altera_tse_stop(struct udevice *dev)
if (ret == -ETIMEDOUT)
writel(ALT_SGDMA_CONTROL_SOFTWARERESET_MSK,
&tx_sgdma->control);
+}
- /* reset the mac */
- writel(ALTERA_TSE_CMD_SW_RESET_MSK, &mac_dev->command_config);
+static void msgdma_reset(struct msgdma_csr *csr)
+{
+ u32 status;
+ ulong ctime;
+
+ /* Reset mSGDMA */
+ writel(MSGDMA_CSR_STAT_MASK, &csr->status);
+ writel(MSGDMA_CSR_CTL_RESET, &csr->control);
ctime = get_timer(0);
while (1) {
- status = readl(&mac_dev->command_config);
- if (!(status & ALTERA_TSE_CMD_SW_RESET_MSK))
+ status = readl(&csr->status);
+ if (!(status & MSGDMA_CSR_STAT_RESETTING))
break;
if (get_timer(ctime) > ALT_TSE_SW_RESET_TIMEOUT) {
- debug("Reset mac timeout\n");
+ debug("Reset msgdma timeout\n");
+ break;
+ }
+ }
+ /* Clear status */
+ writel(MSGDMA_CSR_STAT_MASK, &csr->status);
+}
+
+static u32 msgdma_wait(struct msgdma_csr *csr)
+{
+ u32 status;
+ ulong ctime;
+
+ /* Wait for the descriptor to complete */
+ ctime = get_timer(0);
+ while (1) {
+ status = readl(&csr->status);
+ if (!(status & MSGDMA_CSR_STAT_BUSY))
+ break;
+ if (get_timer(ctime) > ALT_TSE_SGDMA_BUSY_TIMEOUT) {
+ debug("sgdma timeout\n");
break;
}
}
+ /* Clear status */
+ writel(MSGDMA_CSR_STAT_MASK, &csr->status);
+
+ return status;
+}
+
+static int altera_tse_send_msgdma(struct udevice *dev, void *packet,
+ int length)
+{
+ struct altera_tse_priv *priv = dev_get_priv(dev);
+ struct msgdma_extended_desc *desc = priv->tx_desc;
+ u32 tx_buf = virt_to_phys(packet);
+ u32 status;
+
+ writel(tx_buf, &desc->read_addr_lo);
+ writel(0, &desc->read_addr_hi);
+ writel(0, &desc->write_addr_lo);
+ writel(0, &desc->write_addr_hi);
+ writel(length, &desc->len);
+ writel(0, &desc->burst_seq_num);
+ writel(MSGDMA_DESC_TX_STRIDE, &desc->stride);
+ writel(MSGDMA_DESC_CTL_TX_SINGLE, &desc->control);
+ status = msgdma_wait(priv->sgdma_tx);
+ debug("sent %d bytes, status %08x\n", length, status);
+
+ return 0;
+}
+
+static int altera_tse_recv_msgdma(struct udevice *dev, int flags,
+ uchar **packetp)
+{
+ struct altera_tse_priv *priv = dev_get_priv(dev);
+ struct msgdma_csr *csr = priv->sgdma_rx;
+ struct msgdma_response *resp = priv->rx_resp;
+ u32 level, length, status;
+
+ level = readl(&csr->resp_fill_level);
+ if (level & 0xffff) {
+ length = readl(&resp->bytes_transferred);
+ status = readl(&resp->status);
+ debug("recv %d bytes, status %08x\n", length, status);
+ *packetp = priv->rx_buf;
+
+ return length;
+ }
+
+ return -EAGAIN;
+}
+
+static int altera_tse_free_pkt_msgdma(struct udevice *dev, uchar *packet,
+ int length)
+{
+ struct altera_tse_priv *priv = dev_get_priv(dev);
+ struct msgdma_extended_desc *desc = priv->rx_desc;
+ u32 rx_buf = virt_to_phys(priv->rx_buf);
+
+ writel(0, &desc->read_addr_lo);
+ writel(0, &desc->read_addr_hi);
+ writel(rx_buf, &desc->write_addr_lo);
+ writel(0, &desc->write_addr_hi);
+ writel(PKTSIZE_ALIGN, &desc->len);
+ writel(0, &desc->burst_seq_num);
+ writel(MSGDMA_DESC_RX_STRIDE, &desc->stride);
+ writel(MSGDMA_DESC_CTL_RX_SINGLE, &desc->control);
+ debug("recv setup\n");
+
+ return 0;
+}
+
+static void altera_tse_stop_msgdma(struct udevice *dev)
+{
+ struct altera_tse_priv *priv = dev_get_priv(dev);
+
+ msgdma_reset(priv->sgdma_rx);
+ msgdma_reset(priv->sgdma_tx);
}
static int tse_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
{
struct altera_tse_priv *priv = bus->priv;
struct alt_tse_mac *mac_dev = priv->mac_dev;
- unsigned int value;
+ u32 value;
/* set mdio address */
writel(addr, &mac_dev->mdio_phy1_addr);
@@ -337,7 +453,7 @@ static int altera_tse_write_hwaddr(struct udevice *dev)
struct alt_tse_mac *mac_dev = priv->mac_dev;
struct eth_pdata *pdata = dev_get_platdata(dev);
u8 *hwaddr = pdata->enetaddr;
- unsigned int mac_lo, mac_hi;
+ u32 mac_lo, mac_hi;
mac_lo = (hwaddr[3] << 24) | (hwaddr[2] << 16) |
(hwaddr[1] << 8) | hwaddr[0];
@@ -358,11 +474,47 @@ static int altera_tse_write_hwaddr(struct udevice *dev)
return 0;
}
+static int altera_tse_send(struct udevice *dev, void *packet, int length)
+{
+ struct altera_tse_priv *priv = dev_get_priv(dev);
+ unsigned long tx_buf = (unsigned long)packet;
+
+ flush_dcache_range(tx_buf, tx_buf + length);
+
+ return priv->ops->send(dev, packet, length);
+}
+
+static int altera_tse_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+ struct altera_tse_priv *priv = dev_get_priv(dev);
+
+ return priv->ops->recv(dev, flags, packetp);
+}
+
+static int altera_tse_free_pkt(struct udevice *dev, uchar *packet,
+ int length)
+{
+ struct altera_tse_priv *priv = dev_get_priv(dev);
+ unsigned long rx_buf = (unsigned long)priv->rx_buf;
+
+ invalidate_dcache_range(rx_buf, rx_buf + PKTSIZE_ALIGN);
+
+ return priv->ops->free_pkt(dev, packet, length);
+}
+
+static void altera_tse_stop(struct udevice *dev)
+{
+ struct altera_tse_priv *priv = dev_get_priv(dev);
+
+ priv->ops->stop(dev);
+ altera_tse_stop_mac(priv);
+}
+
static int altera_tse_start(struct udevice *dev)
{
struct altera_tse_priv *priv = dev_get_priv(dev);
struct alt_tse_mac *mac_dev = priv->mac_dev;
- unsigned int val;
+ u32 val;
int ret;
/* need to create sgdma */
@@ -405,24 +557,45 @@ static int altera_tse_start(struct udevice *dev)
return 0;
}
+static const struct tse_ops tse_sgdma_ops = {
+ .send = altera_tse_send_sgdma,
+ .recv = altera_tse_recv_sgdma,
+ .free_pkt = altera_tse_free_pkt_sgdma,
+ .stop = altera_tse_stop_sgdma,
+};
+
+static const struct tse_ops tse_msgdma_ops = {
+ .send = altera_tse_send_msgdma,
+ .recv = altera_tse_recv_msgdma,
+ .free_pkt = altera_tse_free_pkt_msgdma,
+ .stop = altera_tse_stop_msgdma,
+};
+
static int altera_tse_probe(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct altera_tse_priv *priv = dev_get_priv(dev);
- const void *blob = gd->fdt_blob;
+ void *blob = (void *)gd->fdt_blob;
int node = dev->of_offset;
const char *list, *end;
const fdt32_t *cell;
void *base, *desc_mem = NULL;
unsigned long addr, size;
+ int parent, addrc, sizec;
int len, idx;
int ret;
+ priv->dma_type = dev_get_driver_data(dev);
+ if (priv->dma_type == ALT_SGDMA)
+ priv->ops = &tse_sgdma_ops;
+ else
+ priv->ops = &tse_msgdma_ops;
/*
- * decode regs, assume address-cells and size-cells are both one.
- * there are multiple reg tuples, and they need to match with
- * reg-names.
+ * decode regs. there are multiple reg tuples, and they need to
+ * match with reg-names.
*/
+ parent = fdt_parent_offset(blob, node);
+ of_bus_default_count_cells(blob, parent, &addrc, &sizec);
list = fdt_getprop(blob, node, "reg-names", &len);
if (!list)
return -ENOENT;
@@ -434,18 +607,24 @@ static int altera_tse_probe(struct udevice *dev)
while (list < end) {
addr = fdt_translate_address((void *)blob,
node, cell + idx);
- size = fdt_addr_to_cpu(cell[idx + 1]);
+ size = fdt_addr_to_cpu(cell[idx + addrc]);
base = ioremap(addr, size);
len = strlen(list);
if (strcmp(list, "control_port") == 0)
priv->mac_dev = base;
else if (strcmp(list, "rx_csr") == 0)
priv->sgdma_rx = base;
+ else if (strcmp(list, "rx_desc") == 0)
+ priv->rx_desc = base;
+ else if (strcmp(list, "rx_resp") == 0)
+ priv->rx_resp = base;
else if (strcmp(list, "tx_csr") == 0)
priv->sgdma_tx = base;
+ else if (strcmp(list, "tx_desc") == 0)
+ priv->tx_desc = base;
else if (strcmp(list, "s1") == 0)
desc_mem = base;
- idx += 2;
+ idx += addrc + sizec;
list += (len + 1);
}
/* decode fifo depth */
@@ -460,15 +639,18 @@ static int altera_tse_probe(struct udevice *dev)
priv->phyaddr = fdtdec_get_int(blob, addr,
"reg", 0);
/* init desc */
- len = sizeof(struct alt_sgdma_descriptor) * 4;
- if (!desc_mem) {
- desc_mem = dma_alloc_coherent(len, &addr);
- if (!desc_mem)
- return -ENOMEM;
+ if (priv->dma_type == ALT_SGDMA) {
+ len = sizeof(struct alt_sgdma_descriptor) * 4;
+ if (!desc_mem) {
+ desc_mem = dma_alloc_coherent(len, &addr);
+ if (!desc_mem)
+ return -ENOMEM;
+ }
+ memset(desc_mem, 0, len);
+ priv->tx_desc = desc_mem;
+ priv->rx_desc = priv->tx_desc +
+ 2 * sizeof(struct alt_sgdma_descriptor);
}
- memset(desc_mem, 0, len);
- priv->tx_desc = desc_mem;
- priv->rx_desc = priv->tx_desc + 2;
/* allocate recv packet buffer */
priv->rx_buf = malloc_cache_aligned(PKTSIZE_ALIGN);
if (!priv->rx_buf)
@@ -515,8 +697,9 @@ static const struct eth_ops altera_tse_ops = {
};
static const struct udevice_id altera_tse_ids[] = {
- { .compatible = "altr,tse-1.0", },
- { }
+ { .compatible = "altr,tse-msgdma-1.0", .data = ALT_MSGDMA },
+ { .compatible = "altr,tse-1.0", .data = ALT_SGDMA },
+ {}
};
U_BOOT_DRIVER(altera_tse) = {
diff --git a/drivers/net/altera_tse.h b/drivers/net/altera_tse.h
index 08c4f66..2b1af81 100644
--- a/drivers/net/altera_tse.h
+++ b/drivers/net/altera_tse.h
@@ -11,22 +11,18 @@
#ifndef _ALTERA_TSE_H_
#define _ALTERA_TSE_H_
-#define __packed_1_ __attribute__ ((packed, aligned(1)))
+#define __packed_1_ __packed __aligned(1)
-/* SGDMA Stuff */
-#define ALT_SGDMA_STATUS_ERROR_MSK (0x00000001)
-#define ALT_SGDMA_STATUS_EOP_ENCOUNTERED_MSK (0x00000002)
-#define ALT_SGDMA_STATUS_DESC_COMPLETED_MSK (0x00000004)
-#define ALT_SGDMA_STATUS_CHAIN_COMPLETED_MSK (0x00000008)
-#define ALT_SGDMA_STATUS_BUSY_MSK (0x00000010)
+/* dma type */
+#define ALT_SGDMA 0
+#define ALT_MSGDMA 1
-#define ALT_SGDMA_CONTROL_RUN_MSK (0x00000020)
-#define ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK (0x00000040)
-#define ALT_SGDMA_CONTROL_SOFTWARERESET_MSK (0x00010000)
+/* SGDMA Stuff */
+#define ALT_SGDMA_STATUS_BUSY_MSK BIT(4)
-#define ALTERA_TSE_SGDMA_INTR_MASK (ALT_SGDMA_CONTROL_IE_CHAIN_COMPLETED_MSK \
- | ALT_SGDMA_STATUS_DESC_COMPLETED_MSK \
- | ALT_SGDMA_CONTROL_IE_GLOBAL_MSK)
+#define ALT_SGDMA_CONTROL_RUN_MSK BIT(5)
+#define ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK BIT(6)
+#define ALT_SGDMA_CONTROL_SOFTWARERESET_MSK BIT(16)
/*
* Descriptor control bit masks & offsets
@@ -35,11 +31,10 @@
* The following bit-offsets are expressed relative to the LSB of
* the control register bitfield.
*/
-#define ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK (0x00000001)
-#define ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK (0x00000002)
-#define ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK (0x00000004)
-#define ALT_SGDMA_DESCRIPTOR_CONTROL_ATLANTIC_CHANNEL_MSK (0x00000008)
-#define ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK (0x00000080)
+#define ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK BIT(0)
+#define ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK BIT(1)
+#define ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK BIT(2)
+#define ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK BIT(7)
/*
* Descriptor status bit masks & offsets
@@ -48,15 +43,7 @@
* The following bit-offsets are expressed relative to the LSB of
* the status register bitfield.
*/
-#define ALT_SGDMA_DESCRIPTOR_STATUS_E_CRC_MSK (0x00000001)
-#define ALT_SGDMA_DESCRIPTOR_STATUS_E_PARITY_MSK (0x00000002)
-#define ALT_SGDMA_DESCRIPTOR_STATUS_E_OVERFLOW_MSK (0x00000004)
-#define ALT_SGDMA_DESCRIPTOR_STATUS_E_SYNC_MSK (0x00000008)
-#define ALT_SGDMA_DESCRIPTOR_STATUS_E_UEOP_MSK (0x00000010)
-#define ALT_SGDMA_DESCRIPTOR_STATUS_E_MEOP_MSK (0x00000020)
-#define ALT_SGDMA_DESCRIPTOR_STATUS_E_MSOP_MSK (0x00000040)
-#define ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK (0x00000080)
-#define ALT_SGDMA_DESCRIPTOR_STATUS_ERROR_MSK (0x0000007F)
+#define ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK BIT(7)
/*
* The SGDMA controller buffer descriptor allocates
@@ -71,70 +58,101 @@
*
*/
struct alt_sgdma_descriptor {
- unsigned int source; /* the address of data to be read. */
- unsigned int source_pad;
+ u32 source; /* the address of data to be read. */
+ u32 source_pad;
- unsigned int destination; /* the address to write data */
- unsigned int destination_pad;
+ u32 destination; /* the address to write data */
+ u32 destination_pad;
- unsigned int next; /* the next descriptor in the list. */
- unsigned int next_pad;
+ u32 next; /* the next descriptor in the list. */
+ u32 next_pad;
- unsigned short bytes_to_transfer; /* the number of bytes to transfer */
- unsigned char read_burst;
- unsigned char write_burst;
+ u16 bytes_to_transfer; /* the number of bytes to transfer */
+ u8 read_burst;
+ u8 write_burst;
- unsigned short actual_bytes_transferred;/* bytes transferred by DMA */
- unsigned char descriptor_status;
- unsigned char descriptor_control;
+ u16 actual_bytes_transferred;/* bytes transferred by DMA */
+ u8 descriptor_status;
+ u8 descriptor_control;
} __packed_1_;
/* SG-DMA Control/Status Slave registers map */
struct alt_sgdma_registers {
- unsigned int status;
- unsigned int status_pad[3];
- unsigned int control;
- unsigned int control_pad[3];
- unsigned int next_descriptor_pointer;
- unsigned int descriptor_pad[3];
+ u32 status;
+ u32 status_pad[3];
+ u32 control;
+ u32 control_pad[3];
+ u32 next_descriptor_pointer;
+ u32 descriptor_pad[3];
+};
+
+/* mSGDMA Stuff */
+
+/* mSGDMA extended descriptor format */
+struct msgdma_extended_desc {
+ u32 read_addr_lo; /* data buffer source address low bits */
+ u32 write_addr_lo; /* data buffer destination address low bits */
+ u32 len;
+ u32 burst_seq_num;
+ u32 stride;
+ u32 read_addr_hi; /* data buffer source address high bits */
+ u32 write_addr_hi; /* data buffer destination address high bits */
+ u32 control; /* characteristics of the transfer */
+};
+
+/* mSGDMA descriptor control field bit definitions */
+#define MSGDMA_DESC_CTL_GEN_SOP BIT(8)
+#define MSGDMA_DESC_CTL_GEN_EOP BIT(9)
+#define MSGDMA_DESC_CTL_END_ON_EOP BIT(12)
+#define MSGDMA_DESC_CTL_END_ON_LEN BIT(13)
+#define MSGDMA_DESC_CTL_GO BIT(31)
+
+/* Tx buffer control flags */
+#define MSGDMA_DESC_CTL_TX_SINGLE (MSGDMA_DESC_CTL_GEN_SOP | \
+ MSGDMA_DESC_CTL_GEN_EOP | \
+ MSGDMA_DESC_CTL_GO)
+
+#define MSGDMA_DESC_CTL_RX_SINGLE (MSGDMA_DESC_CTL_END_ON_EOP | \
+ MSGDMA_DESC_CTL_END_ON_LEN | \
+ MSGDMA_DESC_CTL_GO)
+
+/* mSGDMA extended descriptor stride definitions */
+#define MSGDMA_DESC_TX_STRIDE 0x00010001
+#define MSGDMA_DESC_RX_STRIDE 0x00010001
+
+/* mSGDMA dispatcher control and status register map */
+struct msgdma_csr {
+ u32 status; /* Read/Clear */
+ u32 control; /* Read/Write */
+ u32 rw_fill_level;
+ u32 resp_fill_level; /* bit 15:0 */
+ u32 rw_seq_num;
+ u32 pad[3]; /* reserved */
+};
+
+/* mSGDMA CSR status register bit definitions */
+#define MSGDMA_CSR_STAT_BUSY BIT(0)
+#define MSGDMA_CSR_STAT_RESETTING BIT(6)
+#define MSGDMA_CSR_STAT_MASK 0x3FF
+
+/* mSGDMA CSR control register bit definitions */
+#define MSGDMA_CSR_CTL_RESET BIT(1)
+
+/* mSGDMA response register map */
+struct msgdma_response {
+ u32 bytes_transferred;
+ u32 status;
};
/* TSE Stuff */
-#define ALTERA_TSE_CMD_TX_ENA_MSK (0x00000001)
-#define ALTERA_TSE_CMD_RX_ENA_MSK (0x00000002)
-#define ALTERA_TSE_CMD_XON_GEN_MSK (0x00000004)
-#define ALTERA_TSE_CMD_ETH_SPEED_MSK (0x00000008)
-#define ALTERA_TSE_CMD_PROMIS_EN_MSK (0x00000010)
-#define ALTERA_TSE_CMD_PAD_EN_MSK (0x00000020)
-#define ALTERA_TSE_CMD_CRC_FWD_MSK (0x00000040)
-#define ALTERA_TSE_CMD_PAUSE_FWD_MSK (0x00000080)
-#define ALTERA_TSE_CMD_PAUSE_IGNORE_MSK (0x00000100)
-#define ALTERA_TSE_CMD_TX_ADDR_INS_MSK (0x00000200)
-#define ALTERA_TSE_CMD_HD_ENA_MSK (0x00000400)
-#define ALTERA_TSE_CMD_EXCESS_COL_MSK (0x00000800)
-#define ALTERA_TSE_CMD_LATE_COL_MSK (0x00001000)
-#define ALTERA_TSE_CMD_SW_RESET_MSK (0x00002000)
-#define ALTERA_TSE_CMD_MHASH_SEL_MSK (0x00004000)
-#define ALTERA_TSE_CMD_LOOPBACK_MSK (0x00008000)
-/* Bits (18:16) = address select */
-#define ALTERA_TSE_CMD_TX_ADDR_SEL_MSK (0x00070000)
-#define ALTERA_TSE_CMD_MAGIC_ENA_MSK (0x00080000)
-#define ALTERA_TSE_CMD_SLEEP_MSK (0x00100000)
-#define ALTERA_TSE_CMD_WAKEUP_MSK (0x00200000)
-#define ALTERA_TSE_CMD_XOFF_GEN_MSK (0x00400000)
-#define ALTERA_TSE_CMD_CNTL_FRM_ENA_MSK (0x00800000)
-#define ALTERA_TSE_CMD_NO_LENGTH_CHECK_MSK (0x01000000)
-#define ALTERA_TSE_CMD_ENA_10_MSK (0x02000000)
-#define ALTERA_TSE_CMD_RX_ERR_DISC_MSK (0x04000000)
-/* Bits (30..27) reserved */
-#define ALTERA_TSE_CMD_CNT_RESET_MSK (0x80000000)
-
-#define ALTERA_TSE_TX_CMD_STAT_TX_SHIFT16 (0x00040000)
-#define ALTERA_TSE_TX_CMD_STAT_OMIT_CRC (0x00020000)
-
-#define ALTERA_TSE_RX_CMD_STAT_RX_SHIFT16 (0x02000000)
+#define ALTERA_TSE_CMD_TX_ENA_MSK BIT(0)
+#define ALTERA_TSE_CMD_RX_ENA_MSK BIT(1)
+#define ALTERA_TSE_CMD_ETH_SPEED_MSK BIT(3)
+#define ALTERA_TSE_CMD_HD_ENA_MSK BIT(10)
+#define ALTERA_TSE_CMD_SW_RESET_MSK BIT(13)
+#define ALTERA_TSE_CMD_ENA_10_MSK BIT(25)
#define ALT_TSE_SW_RESET_TIMEOUT (3 * CONFIG_SYS_HZ)
#define ALT_TSE_SGDMA_BUSY_TIMEOUT (3 * CONFIG_SYS_HZ)
@@ -142,116 +160,72 @@ struct alt_sgdma_registers {
/* MAC register Space */
struct alt_tse_mac {
- unsigned int megacore_revision;
- unsigned int scratch_pad;
- unsigned int command_config;
- unsigned int mac_addr_0;
- unsigned int mac_addr_1;
- unsigned int max_frame_length;
- unsigned int pause_quanta;
- unsigned int rx_sel_empty_threshold;
- unsigned int rx_sel_full_threshold;
- unsigned int tx_sel_empty_threshold;
- unsigned int tx_sel_full_threshold;
- unsigned int rx_almost_empty_threshold;
- unsigned int rx_almost_full_threshold;
- unsigned int tx_almost_empty_threshold;
- unsigned int tx_almost_full_threshold;
- unsigned int mdio_phy0_addr;
- unsigned int mdio_phy1_addr;
-
- /* only if 100/1000 BaseX PCS, reserved otherwise */
- unsigned int reservedx44[5];
-
- unsigned int reg_read_access_status;
- unsigned int min_tx_ipg_length;
-
- /* IEEE 802.3 oEntity Managed Object Support */
- unsigned int aMACID_1; /*The MAC addresses */
- unsigned int aMACID_2;
- unsigned int aFramesTransmittedOK;
- unsigned int aFramesReceivedOK;
- unsigned int aFramesCheckSequenceErrors;
- unsigned int aAlignmentErrors;
- unsigned int aOctetsTransmittedOK;
- unsigned int aOctetsReceivedOK;
-
- /* IEEE 802.3 oPausedEntity Managed Object Support */
- unsigned int aTxPAUSEMACCtrlFrames;
- unsigned int aRxPAUSEMACCtrlFrames;
-
- /* IETF MIB (MIB-II) Object Support */
- unsigned int ifInErrors;
- unsigned int ifOutErrors;
- unsigned int ifInUcastPkts;
- unsigned int ifInMulticastPkts;
- unsigned int ifInBroadcastPkts;
- unsigned int ifOutDiscards;
- unsigned int ifOutUcastPkts;
- unsigned int ifOutMulticastPkts;
- unsigned int ifOutBroadcastPkts;
-
- /* IETF RMON MIB Object Support */
- unsigned int etherStatsDropEvent;
- unsigned int etherStatsOctets;
- unsigned int etherStatsPkts;
- unsigned int etherStatsUndersizePkts;
- unsigned int etherStatsOversizePkts;
- unsigned int etherStatsPkts64Octets;
- unsigned int etherStatsPkts65to127Octets;
- unsigned int etherStatsPkts128to255Octets;
- unsigned int etherStatsPkts256to511Octets;
- unsigned int etherStatsPkts512to1023Octets;
- unsigned int etherStatsPkts1024to1518Octets;
-
- unsigned int etherStatsPkts1519toXOctets;
- unsigned int etherStatsJabbers;
- unsigned int etherStatsFragments;
-
- unsigned int reservedxE4;
+ u32 megacore_revision;
+ u32 scratch_pad;
+ u32 command_config;
+ u32 mac_addr_0;
+ u32 mac_addr_1;
+ u32 max_frame_length;
+ u32 pause_quanta;
+ u32 rx_sel_empty_threshold;
+ u32 rx_sel_full_threshold;
+ u32 tx_sel_empty_threshold;
+ u32 tx_sel_full_threshold;
+ u32 rx_almost_empty_threshold;
+ u32 rx_almost_full_threshold;
+ u32 tx_almost_empty_threshold;
+ u32 tx_almost_full_threshold;
+ u32 mdio_phy0_addr;
+ u32 mdio_phy1_addr;
+
+ u32 reserved1[0x29];
/*FIFO control register. */
- unsigned int tx_cmd_stat;
- unsigned int rx_cmd_stat;
+ u32 tx_cmd_stat;
+ u32 rx_cmd_stat;
- unsigned int ipaccTxConf;
- unsigned int ipaccRxConf;
- unsigned int ipaccRxStat;
- unsigned int ipaccRxStatSum;
-
- /*Multicast address resolution table */
- unsigned int hash_table[64];
+ u32 reserved2[0x44];
/*Registers 0 to 31 within PHY device 0/1 */
- unsigned int mdio_phy0[0x20];
- unsigned int mdio_phy1[0x20];
+ u32 mdio_phy0[0x20];
+ u32 mdio_phy1[0x20];
/*4 Supplemental MAC Addresses */
- unsigned int supp_mac_addr_0_0;
- unsigned int supp_mac_addr_0_1;
- unsigned int supp_mac_addr_1_0;
- unsigned int supp_mac_addr_1_1;
- unsigned int supp_mac_addr_2_0;
- unsigned int supp_mac_addr_2_1;
- unsigned int supp_mac_addr_3_0;
- unsigned int supp_mac_addr_3_1;
-
- unsigned int reservedx320[56];
+ u32 supp_mac_addr_0_0;
+ u32 supp_mac_addr_0_1;
+ u32 supp_mac_addr_1_0;
+ u32 supp_mac_addr_1_1;
+ u32 supp_mac_addr_2_0;
+ u32 supp_mac_addr_2_1;
+ u32 supp_mac_addr_3_0;
+ u32 supp_mac_addr_3_1;
+
+ u32 reserved3[0x38];
+};
+
+struct tse_ops {
+ int (*send)(struct udevice *dev, void *packet, int length);
+ int (*recv)(struct udevice *dev, int flags, uchar **packetp);
+ int (*free_pkt)(struct udevice *dev, uchar *packet, int length);
+ void (*stop)(struct udevice *dev);
};
struct altera_tse_priv {
struct alt_tse_mac *mac_dev;
- struct alt_sgdma_registers *sgdma_rx;
- struct alt_sgdma_registers *sgdma_tx;
+ void *sgdma_rx;
+ void *sgdma_tx;
unsigned int rx_fifo_depth;
unsigned int tx_fifo_depth;
- struct alt_sgdma_descriptor *rx_desc;
- struct alt_sgdma_descriptor *tx_desc;
+ void *rx_desc;
+ void *tx_desc;
+ void *rx_resp;
unsigned char *rx_buf;
unsigned int phyaddr;
unsigned int interface;
struct phy_device *phydev;
struct mii_dev *bus;
+ const struct tse_ops *ops;
+ int dma_type;
};
#endif /* _ALTERA_TSE_H_ */
diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile
index d052fcb..a3c9f99 100644
--- a/drivers/net/fm/Makefile
+++ b/drivers/net/fm/Makefile
@@ -37,3 +37,4 @@ obj-$(CONFIG_PPC_T4160) += t4240.o
obj-$(CONFIG_PPC_T4080) += t4240.o
obj-$(CONFIG_PPC_B4420) += b4860.o
obj-$(CONFIG_PPC_B4860) += b4860.o
+obj-$(CONFIG_LS1043A) += ls1043.o
diff --git a/drivers/net/fm/dtsec.c b/drivers/net/fm/dtsec.c
index 8d3dc0e..b339a84 100644
--- a/drivers/net/fm/dtsec.c
+++ b/drivers/net/fm/dtsec.c
@@ -7,7 +7,7 @@
#include <common.h>
#include <asm/types.h>
#include <asm/io.h>
-#include <asm/fsl_dtsec.h>
+#include <fsl_dtsec.h>
#include <fsl_mdio.h>
#include <phy.h>
diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index 6702f5a..eb8e936 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -13,8 +13,8 @@
#include <fsl_mdio.h>
#include <miiphy.h>
#include <phy.h>
-#include <asm/fsl_dtsec.h>
-#include <asm/fsl_tgec.h>
+#include <fsl_dtsec.h>
+#include <fsl_tgec.h>
#include <fsl_memac.h>
#include "fm.h"
@@ -41,28 +41,35 @@ static void dtsec_configure_serdes(struct fm_eth *priv)
bus.priv = priv->mac->phyregs;
bool sgmii_2500 = (priv->enet_if ==
PHY_INTERFACE_MODE_SGMII_2500) ? true : false;
+ int i = 0;
+qsgmii_loop:
/* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */
value = PHY_SGMII_IF_MODE_SGMII;
if (!sgmii_2500)
value |= PHY_SGMII_IF_MODE_AN;
- memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x14, value);
+ memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x14, value);
/* Dev ability according to SGMII specification */
value = PHY_SGMII_DEV_ABILITY_SGMII;
- memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x4, value);
+ memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x4, value);
/* Adjust link timer for SGMII -
1.6 ms in units of 8 ns = 2 * 10^5 = 0x30d40 */
- memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x13, 0x3);
- memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x12, 0xd40);
+ memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x13, 0x3);
+ memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x12, 0xd40);
/* Restart AN */
value = PHY_SGMII_CR_DEF_VAL;
if (!sgmii_2500)
value |= PHY_SGMII_CR_RESET_AN;
- memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0, value);
+ memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0, value);
+
+ if ((priv->enet_if == PHY_INTERFACE_MODE_QSGMII) && (i < 3)) {
+ i++;
+ goto qsgmii_loop;
+ }
#else
struct dtsec *regs = priv->mac->base;
struct tsec_mii_mng *phyregs = priv->mac->phyregs;
@@ -91,10 +98,12 @@ static void dtsec_init_phy(struct eth_device *dev)
#endif
if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII ||
+ fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII ||
fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500)
dtsec_configure_serdes(fm_eth);
}
+#ifdef CONFIG_PHYLIB
static int tgec_is_fibre(struct eth_device *dev)
{
struct fm_eth *fm = dev->priv;
@@ -105,15 +114,16 @@ static int tgec_is_fibre(struct eth_device *dev)
return hwconfig_arg_cmp(phyopt, "xfi");
}
#endif
+#endif
static u16 muram_readw(u16 *addr)
{
- u32 base = (u32)addr & ~0x3;
- u32 val32 = *(u32 *)base;
+ ulong base = (ulong)addr & ~0x3UL;
+ u32 val32 = in_be32((void *)base);
int byte_pos;
u16 ret;
- byte_pos = (u32)addr & 0x3;
+ byte_pos = (ulong)addr & 0x3UL;
if (byte_pos)
ret = (u16)(val32 & 0x0000ffff);
else
@@ -124,18 +134,18 @@ static u16 muram_readw(u16 *addr)
static void muram_writew(u16 *addr, u16 val)
{
- u32 base = (u32)addr & ~0x3;
- u32 org32 = *(u32 *)base;
+ ulong base = (ulong)addr & ~0x3UL;
+ u32 org32 = in_be32((void *)base);
u32 val32;
int byte_pos;
- byte_pos = (u32)addr & 0x3;
+ byte_pos = (ulong)addr & 0x3UL;
if (byte_pos)
val32 = (org32 & 0xffff0000) | val;
else
val32 = (org32 & 0x0000ffff) | ((u32)val << 16);
- *(u32 *)base = val32;
+ out_be32((void *)base, val32);
}
static void bmi_rx_port_disable(struct fm_bmi_rx_port *rx_port)
@@ -199,6 +209,8 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth)
u32 pram_page_offset;
void *rx_bd_ring_base;
void *rx_buf_pool;
+ u32 bd_ring_base_lo, bd_ring_base_hi;
+ u32 buf_lo, buf_hi;
struct fm_port_bd *rxbd;
struct fm_port_qd *rxqd;
struct fm_bmi_rx_port *bmi_rx_port = fm_eth->rx_port;
@@ -207,16 +219,21 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth)
/* alloc global parameter ram at MURAM */
pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index,
FM_PRAM_SIZE, FM_PRAM_ALIGN);
+ if (!pram) {
+ printf("%s: No muram for Rx global parameter\n", __func__);
+ return -ENOMEM;
+ }
+
fm_eth->rx_pram = pram;
/* parameter page offset to MURAM */
- pram_page_offset = (u32)pram - fm_muram_base(fm_eth->fm_index);
+ pram_page_offset = (void *)pram - fm_muram_base(fm_eth->fm_index);
/* enable global mode- snooping data buffers and BDs */
- pram->mode = PRAM_MODE_GLOBAL;
+ out_be32(&pram->mode, PRAM_MODE_GLOBAL);
/* init the Rx queue descriptor pionter */
- pram->rxqd_ptr = pram_page_offset + 0x20;
+ out_be32(&pram->rxqd_ptr, pram_page_offset + 0x20);
/* set the max receive buffer length, power of 2 */
muram_writew(&pram->mrblr, MAX_RXBUF_LOG2);
@@ -225,15 +242,18 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth)
rx_bd_ring_base = malloc(sizeof(struct fm_port_bd)
* RX_BD_RING_SIZE);
if (!rx_bd_ring_base)
- return 0;
+ return -ENOMEM;
+
memset(rx_bd_ring_base, 0, sizeof(struct fm_port_bd)
* RX_BD_RING_SIZE);
/* alloc Rx buffer from main memory */
rx_buf_pool = malloc(MAX_RXBUF_LEN * RX_BD_RING_SIZE);
if (!rx_buf_pool)
- return 0;
+ return -ENOMEM;
+
memset(rx_buf_pool, 0, MAX_RXBUF_LEN * RX_BD_RING_SIZE);
+ debug("%s: rx_buf_pool = %p\n", __func__, rx_buf_pool);
/* save them to fm_eth */
fm_eth->rx_bd_ring = rx_bd_ring_base;
@@ -243,18 +263,24 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth)
/* init Rx BDs ring */
rxbd = (struct fm_port_bd *)rx_bd_ring_base;
for (i = 0; i < RX_BD_RING_SIZE; i++) {
- rxbd->status = RxBD_EMPTY;
- rxbd->len = 0;
- rxbd->buf_ptr_hi = 0;
- rxbd->buf_ptr_lo = (u32)rx_buf_pool + i * MAX_RXBUF_LEN;
+ muram_writew(&rxbd->status, RxBD_EMPTY);
+ muram_writew(&rxbd->len, 0);
+ buf_hi = upper_32_bits(virt_to_phys(rx_buf_pool +
+ i * MAX_RXBUF_LEN));
+ buf_lo = lower_32_bits(virt_to_phys(rx_buf_pool +
+ i * MAX_RXBUF_LEN));
+ muram_writew(&rxbd->buf_ptr_hi, (u16)buf_hi);
+ out_be32(&rxbd->buf_ptr_lo, buf_lo);
rxbd++;
}
/* set the Rx queue descriptor */
rxqd = &pram->rxqd;
muram_writew(&rxqd->gen, 0);
- muram_writew(&rxqd->bd_ring_base_hi, 0);
- rxqd->bd_ring_base_lo = (u32)rx_bd_ring_base;
+ bd_ring_base_hi = upper_32_bits(virt_to_phys(rx_bd_ring_base));
+ bd_ring_base_lo = lower_32_bits(virt_to_phys(rx_bd_ring_base));
+ muram_writew(&rxqd->bd_ring_base_hi, (u16)bd_ring_base_hi);
+ out_be32(&rxqd->bd_ring_base_lo, bd_ring_base_lo);
muram_writew(&rxqd->bd_ring_size, sizeof(struct fm_port_bd)
* RX_BD_RING_SIZE);
muram_writew(&rxqd->offset_in, 0);
@@ -263,7 +289,7 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth)
/* set IM parameter ram pointer to Rx Frame Queue ID */
out_be32(&bmi_rx_port->fmbm_rfqid, pram_page_offset);
- return 1;
+ return 0;
}
static int fm_eth_tx_port_parameter_init(struct fm_eth *fm_eth)
@@ -271,6 +297,7 @@ static int fm_eth_tx_port_parameter_init(struct fm_eth *fm_eth)
struct fm_port_global_pram *pram;
u32 pram_page_offset;
void *tx_bd_ring_base;
+ u32 bd_ring_base_lo, bd_ring_base_hi;
struct fm_port_bd *txbd;
struct fm_port_qd *txqd;
struct fm_bmi_tx_port *bmi_tx_port = fm_eth->tx_port;
@@ -279,22 +306,27 @@ static int fm_eth_tx_port_parameter_init(struct fm_eth *fm_eth)
/* alloc global parameter ram at MURAM */
pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index,
FM_PRAM_SIZE, FM_PRAM_ALIGN);
+ if (!pram) {
+ printf("%s: No muram for Tx global parameter\n", __func__);
+ return -ENOMEM;
+ }
fm_eth->tx_pram = pram;
/* parameter page offset to MURAM */
- pram_page_offset = (u32)pram - fm_muram_base(fm_eth->fm_index);
+ pram_page_offset = (void *)pram - fm_muram_base(fm_eth->fm_index);
/* enable global mode- snooping data buffers and BDs */
- pram->mode = PRAM_MODE_GLOBAL;
+ out_be32(&pram->mode, PRAM_MODE_GLOBAL);
/* init the Tx queue descriptor pionter */
- pram->txqd_ptr = pram_page_offset + 0x40;
+ out_be32(&pram->txqd_ptr, pram_page_offset + 0x40);
/* alloc Tx buffer descriptors from main memory */
tx_bd_ring_base = malloc(sizeof(struct fm_port_bd)
* TX_BD_RING_SIZE);
if (!tx_bd_ring_base)
- return 0;
+ return -ENOMEM;
+
memset(tx_bd_ring_base, 0, sizeof(struct fm_port_bd)
* TX_BD_RING_SIZE);
/* save it to fm_eth */
@@ -304,16 +336,19 @@ static int fm_eth_tx_port_parameter_init(struct fm_eth *fm_eth)
/* init Tx BDs ring */
txbd = (struct fm_port_bd *)tx_bd_ring_base;
for (i = 0; i < TX_BD_RING_SIZE; i++) {
- txbd->status = TxBD_LAST;
- txbd->len = 0;
- txbd->buf_ptr_hi = 0;
- txbd->buf_ptr_lo = 0;
+ muram_writew(&txbd->status, TxBD_LAST);
+ muram_writew(&txbd->len, 0);
+ muram_writew(&txbd->buf_ptr_hi, 0);
+ out_be32(&txbd->buf_ptr_lo, 0);
+ txbd++;
}
/* set the Tx queue decriptor */
txqd = &pram->txqd;
- muram_writew(&txqd->bd_ring_base_hi, 0);
- txqd->bd_ring_base_lo = (u32)tx_bd_ring_base;
+ bd_ring_base_hi = upper_32_bits(virt_to_phys(tx_bd_ring_base));
+ bd_ring_base_lo = lower_32_bits(virt_to_phys(tx_bd_ring_base));
+ muram_writew(&txqd->bd_ring_base_hi, (u16)bd_ring_base_hi);
+ out_be32(&txqd->bd_ring_base_lo, bd_ring_base_lo);
muram_writew(&txqd->bd_ring_size, sizeof(struct fm_port_bd)
* TX_BD_RING_SIZE);
muram_writew(&txqd->offset_in, 0);
@@ -322,29 +357,35 @@ static int fm_eth_tx_port_parameter_init(struct fm_eth *fm_eth)
/* set IM parameter ram pointer to Tx Confirmation Frame Queue ID */
out_be32(&bmi_tx_port->fmbm_tcfqid, pram_page_offset);
- return 1;
+ return 0;
}
static int fm_eth_init(struct fm_eth *fm_eth)
{
+ int ret;
- if (!fm_eth_rx_port_parameter_init(fm_eth))
- return 0;
+ ret = fm_eth_rx_port_parameter_init(fm_eth);
+ if (ret)
+ return ret;
- if (!fm_eth_tx_port_parameter_init(fm_eth))
- return 0;
+ ret = fm_eth_tx_port_parameter_init(fm_eth);
+ if (ret)
+ return ret;
- return 1;
+ return 0;
}
static int fm_eth_startup(struct fm_eth *fm_eth)
{
struct fsl_enet_mac *mac;
+ int ret;
+
mac = fm_eth->mac;
/* Rx/TxBDs, Rx/TxQDs, Rx buff and parameter ram init */
- if (!fm_eth_init(fm_eth))
- return 0;
+ ret = fm_eth_init(fm_eth);
+ if (ret)
+ return ret;
/* setup the MAC controller */
mac->init_mac(mac);
@@ -359,7 +400,7 @@ static int fm_eth_startup(struct fm_eth *fm_eth)
/* init bmi tx port, IM mode and disable */
bmi_tx_port_init(fm_eth->tx_port);
- return 1;
+ return 0;
}
static void fmc_tx_port_graceful_stop_enable(struct fm_eth *fm_eth)
@@ -368,7 +409,7 @@ static void fmc_tx_port_graceful_stop_enable(struct fm_eth *fm_eth)
pram = fm_eth->tx_pram;
/* graceful stop transmission of frames */
- pram->mode |= PRAM_MODE_GRACEFUL_STOP;
+ setbits_be32(&pram->mode, PRAM_MODE_GRACEFUL_STOP);
sync();
}
@@ -378,7 +419,7 @@ static void fmc_tx_port_graceful_stop_disable(struct fm_eth *fm_eth)
pram = fm_eth->tx_pram;
/* re-enable transmission of frames */
- pram->mode &= ~PRAM_MODE_GRACEFUL_STOP;
+ clrbits_be32(&pram->mode, PRAM_MODE_GRACEFUL_STOP);
sync();
}
@@ -452,8 +493,10 @@ static void fm_eth_halt(struct eth_device *dev)
/* disable bmi Rx port */
bmi_rx_port_disable(fm_eth->rx_port);
+#ifdef CONFIG_PHYLIB
if (fm_eth->phydev)
phy_shutdown(fm_eth->phydev);
+#endif
}
static int fm_eth_send(struct eth_device *dev, void *buf, int len)
@@ -469,19 +512,20 @@ static int fm_eth_send(struct eth_device *dev, void *buf, int len)
txbd = fm_eth->cur_txbd;
/* find one empty TxBD */
- for (i = 0; txbd->status & TxBD_READY; i++) {
+ for (i = 0; muram_readw(&txbd->status) & TxBD_READY; i++) {
udelay(100);
if (i > 0x1000) {
- printf("%s: Tx buffer not ready\n", dev->name);
+ printf("%s: Tx buffer not ready, txbd->status = 0x%x\n",
+ dev->name, muram_readw(&txbd->status));
return 0;
}
}
/* setup TxBD */
- txbd->buf_ptr_hi = 0;
- txbd->buf_ptr_lo = (u32)buf;
- txbd->len = len;
+ muram_writew(&txbd->buf_ptr_hi, (u16)upper_32_bits(virt_to_phys(buf)));
+ out_be32(&txbd->buf_ptr_lo, lower_32_bits(virt_to_phys(buf)));
+ muram_writew(&txbd->len, len);
sync();
- txbd->status = TxBD_READY | TxBD_LAST;
+ muram_writew(&txbd->status, TxBD_READY | TxBD_LAST);
sync();
/* update TxQD, let RISC to send the packet */
@@ -493,10 +537,11 @@ static int fm_eth_send(struct eth_device *dev, void *buf, int len)
sync();
/* wait for buffer to be transmitted */
- for (i = 0; txbd->status & TxBD_READY; i++) {
+ for (i = 0; muram_readw(&txbd->status) & TxBD_READY; i++) {
udelay(100);
if (i > 0x10000) {
- printf("%s: Tx error\n", dev->name);
+ printf("%s: Tx error, txbd->status = 0x%x\n",
+ dev->name, muram_readw(&txbd->status));
return 0;
}
}
@@ -518,6 +563,7 @@ static int fm_eth_recv(struct eth_device *dev)
struct fm_port_global_pram *pram;
struct fm_port_bd *rxbd, *rxbd_base;
u16 status, len;
+ u32 buf_lo, buf_hi;
u8 *data;
u16 offset_out;
int ret = 1;
@@ -525,12 +571,14 @@ static int fm_eth_recv(struct eth_device *dev)
fm_eth = (struct fm_eth *)dev->priv;
pram = fm_eth->rx_pram;
rxbd = fm_eth->cur_rxbd;
- status = rxbd->status;
+ status = muram_readw(&rxbd->status);
while (!(status & RxBD_EMPTY)) {
if (!(status & RxBD_ERROR)) {
- data = (u8 *)rxbd->buf_ptr_lo;
- len = rxbd->len;
+ buf_hi = muram_readw(&rxbd->buf_ptr_hi);
+ buf_lo = in_be32(&rxbd->buf_ptr_lo);
+ data = (u8 *)((ulong)(buf_hi << 16) << 16 | buf_lo);
+ len = muram_readw(&rxbd->len);
net_process_received_packet(data, len);
} else {
printf("%s: Rx error\n", dev->name);
@@ -538,8 +586,8 @@ static int fm_eth_recv(struct eth_device *dev)
}
/* clear the RxBDs */
- rxbd->status = RxBD_EMPTY;
- rxbd->len = 0;
+ muram_writew(&rxbd->status, RxBD_EMPTY);
+ muram_writew(&rxbd->len, 0);
sync();
/* advance RxBD */
@@ -548,7 +596,7 @@ static int fm_eth_recv(struct eth_device *dev)
if (rxbd >= (rxbd_base + RX_BD_RING_SIZE))
rxbd = rxbd_base;
/* read next status */
- status = rxbd->status;
+ status = muram_readw(&rxbd->status);
/* update RxQD */
offset_out = muram_readw(&pram->rxqd.offset_out);
@@ -601,7 +649,7 @@ static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg)
/* alloc mac controller */
mac = malloc(sizeof(struct fsl_enet_mac));
if (!mac)
- return 0;
+ return -ENOMEM;
memset(mac, 0, sizeof(struct fsl_enet_mac));
/* save the mac to fm_eth struct */
@@ -616,19 +664,21 @@ static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg)
init_tgec(mac, base, phyregs, MAX_RXBUF_LEN);
#endif
- return 1;
+ return 0;
}
static int init_phy(struct eth_device *dev)
{
struct fm_eth *fm_eth = dev->priv;
+#ifdef CONFIG_PHYLIB
struct phy_device *phydev = NULL;
u32 supported;
+#endif
-#ifdef CONFIG_PHYLIB
if (fm_eth->type == FM_ETH_1G_E)
dtsec_init_phy(dev);
+#ifdef CONFIG_PHYLIB
if (fm_eth->bus) {
phydev = phy_connect(fm_eth->bus, fm_eth->phyaddr, dev,
fm_eth->enet_if);
@@ -669,17 +719,18 @@ int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info)
struct eth_device *dev;
struct fm_eth *fm_eth;
int i, num = info->num;
+ int ret;
/* alloc eth device */
dev = (struct eth_device *)malloc(sizeof(struct eth_device));
if (!dev)
- return 0;
+ return -ENOMEM;
memset(dev, 0, sizeof(struct eth_device));
/* alloc the FMan ethernet private struct */
fm_eth = (struct fm_eth *)malloc(sizeof(struct fm_eth));
if (!fm_eth)
- return 0;
+ return -ENOMEM;
memset(fm_eth, 0, sizeof(struct fm_eth));
/* save off some things we need from the info struct */
@@ -694,8 +745,9 @@ int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info)
fm_eth->max_rx_len = MAX_RXBUF_LEN;
/* init global mac structure */
- if (!fm_eth_init_mac(fm_eth, reg))
- return 0;
+ ret = fm_eth_init_mac(fm_eth, reg);
+ if (ret)
+ return ret;
/* keep same as the manual, we call FMAN1, FMAN2, DTSEC1, DTSEC2, etc */
if (fm_eth->type == FM_ETH_1G_E)
@@ -716,8 +768,9 @@ int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info)
fm_eth->enet_if = info->enet_if;
/* startup the FM im */
- if (!fm_eth_startup(fm_eth))
- return 0;
+ ret = fm_eth_startup(fm_eth);
+ if (ret)
+ return ret;
init_phy(dev);
@@ -726,5 +779,5 @@ int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info)
dev->enetaddr[i] = 0;
eth_register(dev);
- return 1;
+ return 0;
}
diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c
index 400e9dd..df5db72 100644
--- a/drivers/net/fm/fm.c
+++ b/drivers/net/fm/fm.c
@@ -22,21 +22,22 @@
struct fm_muram muram[CONFIG_SYS_NUM_FMAN];
-u32 fm_muram_base(int fm_idx)
+void *fm_muram_base(int fm_idx)
{
return muram[fm_idx].base;
}
-u32 fm_muram_alloc(int fm_idx, u32 size, u32 align)
+void *fm_muram_alloc(int fm_idx, size_t size, ulong align)
{
- u32 ret;
- u32 align_mask, off;
- u32 save;
+ void *ret;
+ ulong align_mask;
+ size_t off;
+ void *save;
align_mask = align - 1;
save = muram[fm_idx].alloc;
- off = save & align_mask;
+ off = (ulong)save & align_mask;
if (off != 0)
muram[fm_idx].alloc += (align - off);
off = size & align_mask;
@@ -45,6 +46,7 @@ u32 fm_muram_alloc(int fm_idx, u32 size, u32 align)
if ((muram[fm_idx].alloc + size) >= muram[fm_idx].top) {
muram[fm_idx].alloc = save;
printf("%s: run out of ram.\n", __func__);
+ return NULL;
}
ret = muram[fm_idx].alloc;
@@ -56,7 +58,7 @@ u32 fm_muram_alloc(int fm_idx, u32 size, u32 align)
static void fm_init_muram(int fm_idx, void *reg)
{
- u32 base = (u32)reg;
+ void *base = reg;
muram[fm_idx].base = base;
muram[fm_idx].size = CONFIG_SYS_FM_MURAM_SIZE;
@@ -80,11 +82,11 @@ static void fm_upload_ucode(int fm_idx, struct fm_imem *imem,
out_be32(&imem->iadd, IRAM_IADD_AIE);
/* write microcode to IRAM */
for (i = 0; i < size / 4; i++)
- out_be32(&imem->idata, ucode[i]);
+ out_be32(&imem->idata, (be32_to_cpu(ucode[i])));
/* verify if the writing is over */
out_be32(&imem->iadd, 0);
- while ((in_be32(&imem->idata) != ucode[0]) && --timeout)
+ while ((in_be32(&imem->idata) != be32_to_cpu(ucode[0])) && --timeout)
;
if (!timeout)
printf("Fman%u: microcode upload timeout\n", fm_idx + 1);
@@ -177,14 +179,15 @@ static int fman_upload_firmware(int fm_idx,
const struct qe_microcode *ucode = &firmware->microcode[i];
/* Upload a microcode if it's present */
- if (ucode->code_offset) {
+ if (be32_to_cpu(ucode->code_offset)) {
u32 ucode_size;
u32 *code;
printf("Fman%u: Uploading microcode version %u.%u.%u\n",
fm_idx + 1, ucode->major, ucode->minor,
ucode->revision);
- code = (void *)firmware + ucode->code_offset;
- ucode_size = sizeof(u32) * ucode->count;
+ code = (void *)firmware +
+ be32_to_cpu(ucode->code_offset);
+ ucode_size = sizeof(u32) * be32_to_cpu(ucode->count);
fm_upload_ucode(fm_idx, fm_imem, code, ucode_size);
}
}
@@ -255,7 +258,9 @@ static void fm_init_fpm(struct fm_fpm *fpm)
static int fm_init_bmi(int fm_idx, struct fm_bmi_common *bmi)
{
int blk, i, port_id;
- u32 val, offset, base;
+ u32 val;
+ size_t offset;
+ void *base;
/* alloc free buffer pool in MURAM */
base = fm_muram_alloc(fm_idx, FM_FREE_POOL_SIZE, FM_FREE_POOL_ALIGN);
diff --git a/drivers/net/fm/fm.h b/drivers/net/fm/fm.h
index a9691c6..fa9bc9f 100644
--- a/drivers/net/fm/fm.h
+++ b/drivers/net/fm/fm.h
@@ -10,7 +10,7 @@
#include <common.h>
#include <phy.h>
#include <fm_eth.h>
-#include <asm/fsl_fman.h>
+#include <fsl_fman.h>
/* Port ID */
#define OH_PORT_ID_BASE 0x01
@@ -26,10 +26,10 @@
#define MIIM_TIMEOUT 0xFFFF
struct fm_muram {
- u32 base;
- u32 top;
- u32 size;
- u32 alloc;
+ void *base;
+ void *top;
+ size_t size;
+ void *alloc;
};
#define FM_MURAM_RES_SIZE 0x01000
@@ -95,8 +95,8 @@ struct fm_port_global_pram {
#endif
#define FM_FREE_POOL_ALIGN 256
-u32 fm_muram_alloc(int fm_idx, u32 size, u32 align);
-u32 fm_muram_base(int fm_idx);
+void *fm_muram_alloc(int fm_idx, size_t size, ulong align);
+void *fm_muram_base(int fm_idx);
int fm_init_common(int index, struct ccsr_fman *reg);
int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info);
phy_interface_t fman_port_enet_if(enum fm_port port);
diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c
index b3ff4c5..3a1de59 100644
--- a/drivers/net/fm/init.c
+++ b/drivers/net/fm/init.c
@@ -1,13 +1,17 @@
/*
- * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011-2015 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <errno.h>
#include <common.h>
#include <asm/io.h>
-#include <asm/fsl_serdes.h>
#include <fsl_mdio.h>
+#ifdef CONFIG_FSL_LAYERSCAPE
+#include <asm/arch/fsl_serdes.h>
+#else
+#include <asm/fsl_serdes.h>
+#endif
#include "fm.h"
@@ -153,7 +157,9 @@ void fm_disable_port(enum fm_port port)
return;
fm_info[i].enabled = 0;
+#ifndef CONFIG_SYS_FMAN_V3
fman_disable_port(port);
+#endif
}
void fm_enable_port(enum fm_port port)
diff --git a/drivers/net/fm/ls1043.c b/drivers/net/fm/ls1043.c
new file mode 100644
index 0000000..cf2cc95
--- /dev/null
+++ b/drivers/net/fm/ls1043.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <phy.h>
+#include <fm_eth.h>
+#include <asm/io.h>
+#include <asm/arch/fsl_serdes.h>
+
+#define FSL_CHASSIS2_RCWSR13_EC1 0xe0000000 /* bits 416..418 */
+#define FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII 0x00000000
+#define FSL_CHASSIS2_RCWSR13_EC1_GPIO 0x20000000
+#define FSL_CHASSIS2_RCWSR13_EC1_FTM 0xa0000000
+#define FSL_CHASSIS2_RCWSR13_EC2 0x1c000000 /* bits 419..421 */
+#define FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII 0x00000000
+#define FSL_CHASSIS2_RCWSR13_EC2_GPIO 0x04000000
+#define FSL_CHASSIS2_RCWSR13_EC2_1588 0x08000000
+#define FSL_CHASSIS2_RCWSR13_EC2_FTM 0x14000000
+
+u32 port_to_devdisr[] = {
+ [FM1_DTSEC1] = FSL_CHASSIS2_DEVDISR2_DTSEC1_1,
+ [FM1_DTSEC2] = FSL_CHASSIS2_DEVDISR2_DTSEC1_2,
+ [FM1_DTSEC3] = FSL_CHASSIS2_DEVDISR2_DTSEC1_3,
+ [FM1_DTSEC4] = FSL_CHASSIS2_DEVDISR2_DTSEC1_4,
+ [FM1_DTSEC5] = FSL_CHASSIS2_DEVDISR2_DTSEC1_5,
+ [FM1_DTSEC6] = FSL_CHASSIS2_DEVDISR2_DTSEC1_6,
+ [FM1_DTSEC9] = FSL_CHASSIS2_DEVDISR2_DTSEC1_9,
+ [FM1_DTSEC10] = FSL_CHASSIS2_DEVDISR2_DTSEC1_10,
+ [FM1_10GEC1] = FSL_CHASSIS2_DEVDISR2_10GEC1_1,
+ [FM1_10GEC2] = FSL_CHASSIS2_DEVDISR2_10GEC1_2,
+ [FM1_10GEC3] = FSL_CHASSIS2_DEVDISR2_10GEC1_3,
+ [FM1_10GEC4] = FSL_CHASSIS2_DEVDISR2_10GEC1_4,
+};
+
+static int is_device_disabled(enum fm_port port)
+{
+ struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ u32 devdisr2 = in_be32(&gur->devdisr2);
+
+ return port_to_devdisr[port] & devdisr2;
+}
+
+void fman_disable_port(enum fm_port port)
+{
+ struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+
+ setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
+}
+
+phy_interface_t fman_port_enet_if(enum fm_port port)
+{
+ struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
+
+ if (is_device_disabled(port)) {
+ printf("%s:%d: port(%d) is disabled\n", __func__,
+ __LINE__, port);
+ return PHY_INTERFACE_MODE_NONE;
+ }
+
+ if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC9)))
+ return PHY_INTERFACE_MODE_XGMII;
+
+ if ((port == FM1_DTSEC9) && (is_serdes_configured(XFI_FM1_MAC9)))
+ return PHY_INTERFACE_MODE_NONE;
+
+ if (port == FM1_DTSEC3)
+ if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC1) ==
+ FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII) {
+ printf("%s:%d: port(FM1_DTSEC3) is OK\n",
+ __func__, __LINE__);
+ return PHY_INTERFACE_MODE_RGMII;
+ }
+ if (port == FM1_DTSEC4)
+ if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC2) ==
+ FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII) {
+ printf("%s:%d: port(FM1_DTSEC4) is OK\n",
+ __func__, __LINE__);
+ return PHY_INTERFACE_MODE_RGMII;
+ }
+
+ /* handle SGMII */
+ switch (port) {
+ case FM1_DTSEC1:
+ case FM1_DTSEC2:
+ if ((port == FM1_DTSEC2) &&
+ is_serdes_configured(SGMII_2500_FM1_DTSEC2))
+ return PHY_INTERFACE_MODE_SGMII_2500;
+ case FM1_DTSEC5:
+ case FM1_DTSEC6:
+ case FM1_DTSEC9:
+ if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
+ return PHY_INTERFACE_MODE_SGMII;
+ else if ((port == FM1_DTSEC9) &&
+ is_serdes_configured(SGMII_2500_FM1_DTSEC9))
+ return PHY_INTERFACE_MODE_SGMII_2500;
+ break;
+ default:
+ break;
+ }
+
+ /* handle QSGMII */
+ switch (port) {
+ case FM1_DTSEC1:
+ case FM1_DTSEC2:
+ case FM1_DTSEC5:
+ case FM1_DTSEC6:
+ /* only MAC 1,2,5,6 available for QSGMII */
+ if (is_serdes_configured(QSGMII_FM1_A))
+ return PHY_INTERFACE_MODE_QSGMII;
+ break;
+ default:
+ break;
+ }
+
+ return PHY_INTERFACE_MODE_NONE;
+}
diff --git a/drivers/net/fm/tgec.c b/drivers/net/fm/tgec.c
index 5017123..8d4622f 100644
--- a/drivers/net/fm/tgec.c
+++ b/drivers/net/fm/tgec.c
@@ -12,7 +12,7 @@
#include <phy.h>
#include <asm/types.h>
#include <asm/io.h>
-#include <asm/fsl_tgec.h>
+#include <fsl_tgec.h>
#include "fm.h"
diff --git a/drivers/net/fm/tgec_phy.c b/drivers/net/fm/tgec_phy.c
index 095f00c..24cb17b 100644
--- a/drivers/net/fm/tgec_phy.c
+++ b/drivers/net/fm/tgec_phy.c
@@ -9,7 +9,7 @@
#include <miiphy.h>
#include <phy.h>
#include <asm/io.h>
-#include <asm/fsl_tgec.h>
+#include <fsl_tgec.h>
#include <fm_eth.h>
/*
diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.c b/drivers/net/ldpaa_eth/ldpaa_eth.c
index 4de7586..99acb7a 100644
--- a/drivers/net/ldpaa_eth/ldpaa_eth.c
+++ b/drivers/net/ldpaa_eth/ldpaa_eth.c
@@ -220,7 +220,6 @@ static int ldpaa_eth_open(struct eth_device *net_dev, bd_t *bd)
{
struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv;
struct dpni_queue_attr rx_queue_attr;
- uint8_t mac_addr[6];
int err;
if (net_dev->state == ETH_STATE_ACTIVE)
@@ -240,21 +239,13 @@ static int ldpaa_eth_open(struct eth_device *net_dev, bd_t *bd)
if (err)
goto err_bind;
- err = dpni_get_primary_mac_addr(dflt_mc_io, MC_CMD_NO_FLAGS,
- priv->dpni_handle, mac_addr);
+ err = dpni_add_mac_addr(dflt_mc_io, MC_CMD_NO_FLAGS,
+ priv->dpni_handle, net_dev->enetaddr);
if (err) {
- printf("dpni_get_primary_mac_addr() failed\n");
+ printf("dpni_add_mac_addr() failed\n");
return err;
}
- memcpy(net_dev->enetaddr, mac_addr, 0x6);
-
- /* setup the MAC address */
- if (net_dev->enetaddr[0] & 0x01) {
- printf("%s: MacAddress is multcast address\n", __func__);
- return 1;
- }
-
#ifdef CONFIG_PHYLIB
/* TODO Check this path */
err = phy_startup(priv->phydev);
diff --git a/drivers/net/ldpaa_eth/ls2085a.c b/drivers/net/ldpaa_eth/ls2085a.c
index 6b7960a..93ed4f1 100644
--- a/drivers/net/ldpaa_eth/ls2085a.c
+++ b/drivers/net/ldpaa_eth/ls2085a.c
@@ -7,9 +7,7 @@
#include <phy.h>
#include <fsl-mc/ldpaa_wriop.h>
#include <asm/io.h>
-#include <asm/arch-fsl-lsch3/immap_lsch3.h>
#include <asm/arch/fsl_serdes.h>
-#include <fsl-mc/ldpaa_wriop.h>
u32 dpmac_to_devdisr[] = {
[WRIOP1_DPMAC1] = FSL_CHASSIS3_DEVDISR2_DPMAC1,
diff --git a/drivers/net/netconsole.c b/drivers/net/netconsole.c
index bf972dc..3500047 100644
--- a/drivers/net/netconsole.c
+++ b/drivers/net/netconsole.c
@@ -330,7 +330,7 @@ int drv_nc_init(void)
memset(&dev, 0, sizeof(dev));
strcpy(dev.name, "nc");
- dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
+ dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT;
dev.start = nc_stdio_start;
dev.putc = nc_stdio_putc;
dev.puts = nc_stdio_puts;
diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index 2f24a6a..4cee038 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -11,7 +11,9 @@
#include <asm/io.h>
#include <errno.h>
#include <malloc.h>
-#include <asm/arch-fsl-lsch3/fdt.h>
+#ifdef CONFIG_FSL_LAYERSCAPE
+#include <asm/arch/fdt.h>
+#endif
#ifndef CONFIG_SYS_PCI_MEMORY_BUS
#define CONFIG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index e56a17f..70d25dc 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -1,3 +1,7 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
obj-y += pinctrl-uclass.o
obj-$(CONFIG_$(SPL_)PINCTRL_GENERIC) += pinctrl-generic.o
diff --git a/drivers/pinctrl/uniphier/Makefile b/drivers/pinctrl/uniphier/Makefile
index e215b10..c5cdd84 100644
--- a/drivers/pinctrl/uniphier/Makefile
+++ b/drivers/pinctrl/uniphier/Makefile
@@ -1,3 +1,7 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
obj-$(CONFIG_PINCTRL_UNIPHIER_CORE) += pinctrl-uniphier-core.o
obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_LD4) += pinctrl-ph1-ld4.o
diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig
index 547fd1a..fb29843 100644
--- a/drivers/power/pmic/Kconfig
+++ b/drivers/power/pmic/Kconfig
@@ -33,6 +33,20 @@ config DM_PMIC_MAX77686
This config enables implementation of driver-model pmic uclass features
for PMIC MAX77686. The driver implements read/write operations.
+config PMIC_S2MPS11
+ bool "Enable Driver Model for PMIC Samsung S2MPS11"
+ depends on DM_PMIC
+ ---help---
+ The Samsung S2MPS11 PMIC provides:
+ - 38 adjustable LDO regulators
+ - 9 High-Efficiency Buck Converters
+ - 1 BuckBoost Converter
+ - RTC with two alarms
+ - Backup battery charger
+ - I2C Configuration Interface
+ This driver provides access to I/O interface only.
+ Binding info: doc/device-tree-bindings/pmic/s2mps11.txt
+
config DM_PMIC_SANDBOX
bool "Enable Driver Model for emulated Sandbox PMIC "
depends on DM_PMIC
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index 00fde71..91e78f8 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -8,6 +8,7 @@
obj-$(CONFIG_DM_PMIC) += pmic-uclass.o
obj-$(CONFIG_DM_PMIC_MAX77686) += max77686.o
obj-$(CONFIG_DM_PMIC_PFUZE100) += pfuze100.o
+obj-$(CONFIG_PMIC_S2MPS11) += s2mps11.o
obj-$(CONFIG_DM_PMIC_SANDBOX) += sandbox.o i2c_pmic_emul.o
obj-$(CONFIG_PMIC_ACT8846) += act8846.o
obj-$(CONFIG_PMIC_TPS65090) += tps65090.o
diff --git a/drivers/power/pmic/s2mps11.c b/drivers/power/pmic/s2mps11.c
new file mode 100644
index 0000000..9d83059
--- /dev/null
+++ b/drivers/power/pmic/s2mps11.c
@@ -0,0 +1,62 @@
+/*
+ * Copyright (C) 2015 Samsung Electronics
+ * Przemyslaw Marczak <p.marczak@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <errno.h>
+#include <dm.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <power/s2mps11.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int s2mps11_reg_count(struct udevice *dev)
+{
+ return S2MPS11_REG_COUNT;
+}
+
+static int s2mps11_write(struct udevice *dev, uint reg, const uint8_t *buff,
+ int len)
+{
+ int ret;
+
+ ret = dm_i2c_write(dev, reg, buff, len);
+ if (ret)
+ error("write error to device: %p register: %#x!", dev, reg);
+
+ return ret;
+}
+
+static int s2mps11_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
+{
+ int ret;
+
+ ret = dm_i2c_read(dev, reg, buff, len);
+ if (ret)
+ error("read error from device: %p register: %#x!", dev, reg);
+
+ return ret;
+}
+
+static struct dm_pmic_ops s2mps11_ops = {
+ .reg_count = s2mps11_reg_count,
+ .read = s2mps11_read,
+ .write = s2mps11_write,
+};
+
+static const struct udevice_id s2mps11_ids[] = {
+ { .compatible = "samsung,s2mps11-pmic" },
+ { }
+};
+
+U_BOOT_DRIVER(pmic_s2mps11) = {
+ .name = "s2mps11_pmic",
+ .id = UCLASS_PMIC,
+ .of_match = s2mps11_ids,
+ .ops = &s2mps11_ops,
+};
diff --git a/drivers/power/regulator/regulator-uclass.c b/drivers/power/regulator/regulator-uclass.c
index a5170df..4241a4c 100644
--- a/drivers/power/regulator/regulator-uclass.c
+++ b/drivers/power/regulator/regulator-uclass.c
@@ -138,6 +138,13 @@ int regulator_get_by_devname(const char *devname, struct udevice **devp)
return uclass_get_device_by_name(UCLASS_REGULATOR, devname, devp);
}
+int device_get_supply_regulator(struct udevice *dev, const char *supply_name,
+ struct udevice **devp)
+{
+ return uclass_get_device_by_phandle(UCLASS_REGULATOR, dev,
+ supply_name, devp);
+}
+
int regulator_autoset(struct udevice *dev)
{
struct dm_regulator_uclass_platdata *uc_pdata;
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 3092de1..fc38a3f 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -4,7 +4,6 @@
#
# SPDX-License-Identifier: GPL-2.0+
#
-
#ccflags-y += -DDEBUG
obj-$(CONFIG_DM_RTC) += rtc-uclass.o
@@ -37,6 +36,7 @@ obj-$(CONFIG_RTC_M48T35A) += m48t35ax.o
obj-$(CONFIG_RTC_MAX6900) += max6900.o
obj-$(CONFIG_RTC_MC13XXX) += mc13xxx-rtc.o
obj-$(CONFIG_RTC_MC146818) += mc146818.o
+obj-$(CONFIG_RTC_MCP79411) += ds1307.o
obj-$(CONFIG_MCFRTC) += mcfrtc.o
obj-$(CONFIG_RTC_MK48T59) += mk48t59.o
obj-$(CONFIG_RTC_MPC5200) += mpc5xxx.o
diff --git a/drivers/rtc/ds1307.c b/drivers/rtc/ds1307.c
index 03ab1a8..3be1da6 100644
--- a/drivers/rtc/ds1307.c
+++ b/drivers/rtc/ds1307.c
@@ -58,6 +58,10 @@
#define RTC_CTL_BIT_SQWE 0x10 /* Square Wave Enable */
#define RTC_CTL_BIT_OUT 0x80 /* Output Control */
+/* MCP7941X-specific bits */
+#define MCP7941X_BIT_ST 0x80
+#define MCP7941X_BIT_VBATEN 0x08
+
static uchar rtc_read (uchar reg);
static void rtc_write (uchar reg, uchar val);
@@ -69,6 +73,9 @@ int rtc_get (struct rtc_time *tmp)
int rel = 0;
uchar sec, min, hour, mday, wday, mon, year;
+#ifdef CONFIG_RTC_MCP79411
+read_rtc:
+#endif
sec = rtc_read (RTC_SEC_REG_ADDR);
min = rtc_read (RTC_MIN_REG_ADDR);
hour = rtc_read (RTC_HR_REG_ADDR);
@@ -81,6 +88,7 @@ int rtc_get (struct rtc_time *tmp)
"hr: %02x min: %02x sec: %02x\n",
year, mon, mday, wday, hour, min, sec);
+#ifdef CONFIG_RTC_DS1307
if (sec & RTC_SEC_BIT_CH) {
printf ("### Warning: RTC oscillator has stopped\n");
/* clear the CH flag */
@@ -88,6 +96,23 @@ int rtc_get (struct rtc_time *tmp)
rtc_read (RTC_SEC_REG_ADDR) & ~RTC_SEC_BIT_CH);
rel = -1;
}
+#endif
+
+#ifdef CONFIG_RTC_MCP79411
+ /* make sure that the backup battery is enabled */
+ if (!(wday & MCP7941X_BIT_VBATEN)) {
+ rtc_write(RTC_DAY_REG_ADDR,
+ wday | MCP7941X_BIT_VBATEN);
+ }
+
+ /* clock halted? turn it on, so clock can tick. */
+ if (!(sec & MCP7941X_BIT_ST)) {
+ rtc_write(RTC_SEC_REG_ADDR, MCP7941X_BIT_ST);
+ printf("Started RTC\n");
+ goto read_rtc;
+ }
+#endif
+
tmp->tm_sec = bcd2bin (sec & 0x7F);
tmp->tm_min = bcd2bin (min & 0x7F);
@@ -121,11 +146,20 @@ int rtc_set (struct rtc_time *tmp)
rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100));
rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon));
+#ifdef CONFIG_RTC_MCP79411
+ rtc_write (RTC_DAY_REG_ADDR,
+ bin2bcd (tmp->tm_wday + 1) | MCP7941X_BIT_VBATEN);
+#else
rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday + 1));
+#endif
rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday));
rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour));
rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min));
+#ifdef CONFIG_RTC_MCP79411
+ rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec) | MCP7941X_BIT_ST);
+#else
rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec));
+#endif
return 0;
}
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 53b4e1b..d462244 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -91,6 +91,13 @@ config DEBUG_UART_S5P
will need to provide parameters to make this work. The driver will
be available until the real driver-model serial is running.
+config DEBUG_UART_ZYNQ
+ bool "Xilinx Zynq"
+ help
+ Select this to enable a debug UART using the serial_s5p driver. You
+ will need to provide parameters to make this work. The driver will
+ be available until the real driver-model serial is running.
+
endchoice
config DEBUG_UART_BASE
diff --git a/drivers/serial/altera_jtag_uart.c b/drivers/serial/altera_jtag_uart.c
index 39d4a4e..c77bea3 100644
--- a/drivers/serial/altera_jtag_uart.c
+++ b/drivers/serial/altera_jtag_uart.c
@@ -8,9 +8,20 @@
#include <common.h>
#include <dm.h>
#include <errno.h>
-#include <asm/io.h>
-#include <linux/compiler.h>
#include <serial.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* data register */
+#define ALTERA_JTAG_RVALID BIT(15) /* Read valid */
+
+/* control register */
+#define ALTERA_JTAG_AC BIT(10) /* activity indicator */
+#define ALTERA_JTAG_RRDY BIT(12) /* read available */
+#define ALTERA_JTAG_WSPACE(d) ((d) >> 16) /* Write space avail */
+/* Write fifo size. FIXME: this should be extracted with sopc2dts */
+#define ALTERA_JTAG_WRITE_DEPTH 64
struct altera_jtaguart_regs {
u32 data; /* Data register */
@@ -21,18 +32,6 @@ struct altera_jtaguart_platdata {
struct altera_jtaguart_regs *regs;
};
-/* data register */
-#define ALTERA_JTAG_RVALID (1<<15) /* Read valid */
-
-/* control register */
-#define ALTERA_JTAG_AC (1 << 10) /* activity indicator */
-#define ALTERA_JTAG_RRDY (1 << 12) /* read available */
-#define ALTERA_JTAG_WSPACE(d) ((d)>>16) /* Write space avail */
-/* Write fifo size. FIXME: this should be extracted with sopc2dts */
-#define ALTERA_JTAG_WRITE_DEPTH 64
-
-DECLARE_GLOBAL_DATA_PTR;
-
static int altera_jtaguart_setbrg(struct udevice *dev, int baudrate)
{
return 0;
@@ -112,8 +111,8 @@ static const struct dm_serial_ops altera_jtaguart_ops = {
};
static const struct udevice_id altera_jtaguart_ids[] = {
- { .compatible = "altr,juart-1.0", },
- { }
+ { .compatible = "altr,juart-1.0" },
+ {}
};
U_BOOT_DRIVER(altera_jtaguart) = {
@@ -131,7 +130,7 @@ U_BOOT_DRIVER(altera_jtaguart) = {
#include <debug_uart.h>
-void debug_uart_init(void)
+static inline void _debug_uart_init(void)
{
}
diff --git a/drivers/serial/altera_uart.c b/drivers/serial/altera_uart.c
index 4ff9fe2..5d76c33 100644
--- a/drivers/serial/altera_uart.c
+++ b/drivers/serial/altera_uart.c
@@ -8,9 +8,15 @@
#include <common.h>
#include <dm.h>
#include <errno.h>
-#include <asm/io.h>
-#include <linux/compiler.h>
#include <serial.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* status register */
+#define ALTERA_UART_TMT BIT(5) /* tx empty */
+#define ALTERA_UART_TRDY BIT(6) /* tx ready */
+#define ALTERA_UART_RRDY BIT(7) /* rx ready */
struct altera_uart_regs {
u32 rxdata; /* Rx data reg */
@@ -26,13 +32,6 @@ struct altera_uart_platdata {
unsigned int uartclk;
};
-/* status register */
-#define ALTERA_UART_TMT (1 << 5) /* tx empty */
-#define ALTERA_UART_TRDY (1 << 6) /* tx ready */
-#define ALTERA_UART_RRDY (1 << 7) /* rx ready */
-
-DECLARE_GLOBAL_DATA_PTR;
-
static int altera_uart_setbrg(struct udevice *dev, int baudrate)
{
struct altera_uart_platdata *plat = dev->platdata;
@@ -106,8 +105,8 @@ static const struct dm_serial_ops altera_uart_ops = {
};
static const struct udevice_id altera_uart_ids[] = {
- { .compatible = "altr,uart-1.0", },
- { }
+ { .compatible = "altr,uart-1.0" },
+ {}
};
U_BOOT_DRIVER(altera_uart) = {
@@ -125,7 +124,7 @@ U_BOOT_DRIVER(altera_uart) = {
#include <debug_uart.h>
-void debug_uart_init(void)
+static inline void _debug_uart_init(void)
{
struct altera_uart_regs *regs = (void *)CONFIG_DEBUG_UART_BASE;
u32 div;
diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c
index 55011cc..842f78b 100644
--- a/drivers/serial/serial-uclass.c
+++ b/drivers/serial/serial-uclass.c
@@ -29,14 +29,34 @@ static const unsigned long baudrate_table[] = CONFIG_SYS_BAUDRATE_TABLE;
static void serial_find_console_or_panic(void)
{
+ const void *blob = gd->fdt_blob;
struct udevice *dev;
int node;
- if (CONFIG_IS_ENABLED(OF_CONTROL) && gd->fdt_blob) {
+ if (CONFIG_IS_ENABLED(OF_CONTROL) && blob) {
/* Check for a chosen console */
- node = fdtdec_get_chosen_node(gd->fdt_blob, "stdout-path");
+ node = fdtdec_get_chosen_node(blob, "stdout-path");
+ if (node < 0) {
+ const char *str, *p, *name;
+
+ /*
+ * Deal with things like
+ * stdout-path = "serial0:115200n8";
+ *
+ * We need to look up the alias and then follow it to
+ * the correct node.
+ */
+ str = fdtdec_get_chosen_prop(blob, "stdout-path");
+ if (str) {
+ p = strchr(str, ':');
+ name = fdt_get_alias_namelen(blob, str,
+ p ? p - str : strlen(str));
+ if (name)
+ node = fdt_path_offset(blob, name);
+ }
+ }
if (node < 0)
- node = fdt_path_offset(gd->fdt_blob, "console");
+ node = fdt_path_offset(blob, "console");
if (!uclass_get_device_by_of_offset(UCLASS_SERIAL, node,
&dev)) {
gd->cur_serial_dev = dev;
@@ -48,14 +68,14 @@ static void serial_find_console_or_panic(void)
* bind it anyway.
*/
if (node > 0 &&
- !lists_bind_fdt(gd->dm_root, gd->fdt_blob, node, &dev)) {
+ !lists_bind_fdt(gd->dm_root, blob, node, &dev)) {
if (!device_probe(dev)) {
gd->cur_serial_dev = dev;
return;
}
}
}
- if (!SPL_BUILD || !CONFIG_IS_ENABLED(OF_CONTROL) || !gd->fdt_blob) {
+ if (!SPL_BUILD || !CONFIG_IS_ENABLED(OF_CONTROL) || !blob) {
/*
* Try to use CONFIG_CONS_INDEX if available (it is numbered
* from 1!).
diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c
index 9d84290..88bebed 100644
--- a/drivers/serial/serial_zynq.c
+++ b/drivers/serial/serial_zynq.c
@@ -6,6 +6,9 @@
*/
#include <common.h>
+#include <debug_uart.h>
+#include <dm.h>
+#include <errno.h>
#include <fdtdec.h>
#include <watchdog.h>
#include <asm/io.h>
@@ -17,6 +20,7 @@
DECLARE_GLOBAL_DATA_PTR;
#define ZYNQ_UART_SR_TXFULL 0x00000010 /* TX FIFO full */
+#define ZYNQ_UART_SR_TXACTIVE (1 << 11) /* TX active */
#define ZYNQ_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
#define ZYNQ_UART_CR_TX_EN 0x00000010 /* TX enabled */
@@ -37,26 +41,21 @@ struct uart_zynq {
u32 baud_rate_divider; /* 0x34 - Baud Rate Divider [7:0] */
};
-static struct uart_zynq *uart_zynq_ports[2] = {
- [0] = (struct uart_zynq *)ZYNQ_SERIAL_BASEADDR0,
- [1] = (struct uart_zynq *)ZYNQ_SERIAL_BASEADDR1,
+struct zynq_uart_priv {
+ struct uart_zynq *regs;
};
/* Set up the baud rate in gd struct */
-static void uart_zynq_serial_setbrg(const int port)
+static void _uart_zynq_serial_setbrg(struct uart_zynq *regs,
+ unsigned long clock, unsigned long baud)
{
/* Calculation results. */
unsigned int calc_bauderror, bdiv, bgen;
unsigned long calc_baud = 0;
- unsigned long baud;
- unsigned long clock = get_uart_clk(port);
- struct uart_zynq *regs = uart_zynq_ports[port];
/* Covering case where input clock is so slow */
- if (clock < 1000000 && gd->baudrate > 4800)
- gd->baudrate = 4800;
-
- baud = gd->baudrate;
+ if (clock < 1000000 && baud > 4800)
+ baud = 4800;
/* master clock
* Baud rate = ------------------
@@ -88,133 +87,131 @@ static void uart_zynq_serial_setbrg(const int port)
}
/* Initialize the UART, with...some settings. */
-static int uart_zynq_serial_init(const int port)
+static void _uart_zynq_serial_init(struct uart_zynq *regs)
{
- struct uart_zynq *regs = uart_zynq_ports[port];
-
- if (!regs)
- return -1;
-
/* RX/TX enabled & reset */
writel(ZYNQ_UART_CR_TX_EN | ZYNQ_UART_CR_RX_EN | ZYNQ_UART_CR_TXRST | \
ZYNQ_UART_CR_RXRST, &regs->control);
writel(ZYNQ_UART_MR_PARITY_NONE, &regs->mode); /* 8 bit, no parity */
- uart_zynq_serial_setbrg(port);
-
- return 0;
}
-static void uart_zynq_serial_putc(const char c, const int port)
+static int _uart_zynq_serial_putc(struct uart_zynq *regs, const char c)
{
- struct uart_zynq *regs = uart_zynq_ports[port];
+ if (readl(&regs->channel_sts) & ZYNQ_UART_SR_TXFULL)
+ return -EAGAIN;
- while ((readl(&regs->channel_sts) & ZYNQ_UART_SR_TXFULL) != 0)
- WATCHDOG_RESET();
-
- if (c == '\n') {
- writel('\r', &regs->tx_rx_fifo);
- while ((readl(&regs->channel_sts) & ZYNQ_UART_SR_TXFULL) != 0)
- WATCHDOG_RESET();
- }
writel(c, &regs->tx_rx_fifo);
+
+ return 0;
}
-static void uart_zynq_serial_puts(const char *s, const int port)
+int zynq_serial_setbrg(struct udevice *dev, int baudrate)
{
- while (*s)
- uart_zynq_serial_putc(*s++, port);
+ struct zynq_uart_priv *priv = dev_get_priv(dev);
+ unsigned long clock = get_uart_clk(0);
+
+ _uart_zynq_serial_setbrg(priv->regs, clock, baudrate);
+
+ return 0;
}
-static int uart_zynq_serial_tstc(const int port)
+static int zynq_serial_probe(struct udevice *dev)
{
- struct uart_zynq *regs = uart_zynq_ports[port];
+ struct zynq_uart_priv *priv = dev_get_priv(dev);
+
+ _uart_zynq_serial_init(priv->regs);
- return (readl(&regs->channel_sts) & ZYNQ_UART_SR_RXEMPTY) == 0;
+ return 0;
}
-static int uart_zynq_serial_getc(const int port)
+static int zynq_serial_getc(struct udevice *dev)
{
- struct uart_zynq *regs = uart_zynq_ports[port];
+ struct zynq_uart_priv *priv = dev_get_priv(dev);
+ struct uart_zynq *regs = priv->regs;
+
+ if (readl(&regs->channel_sts) & ZYNQ_UART_SR_RXEMPTY)
+ return -EAGAIN;
- while (!uart_zynq_serial_tstc(port))
- WATCHDOG_RESET();
return readl(&regs->tx_rx_fifo);
}
-/* Multi serial device functions */
-#define DECLARE_PSSERIAL_FUNCTIONS(port) \
- static int uart_zynq##port##_init(void) \
- { return uart_zynq_serial_init(port); } \
- static void uart_zynq##port##_setbrg(void) \
- { return uart_zynq_serial_setbrg(port); } \
- static int uart_zynq##port##_getc(void) \
- { return uart_zynq_serial_getc(port); } \
- static int uart_zynq##port##_tstc(void) \
- { return uart_zynq_serial_tstc(port); } \
- static void uart_zynq##port##_putc(const char c) \
- { uart_zynq_serial_putc(c, port); } \
- static void uart_zynq##port##_puts(const char *s) \
- { uart_zynq_serial_puts(s, port); }
-
-/* Serial device descriptor */
-#define INIT_PSSERIAL_STRUCTURE(port, __name) { \
- .name = __name, \
- .start = uart_zynq##port##_init, \
- .stop = NULL, \
- .setbrg = uart_zynq##port##_setbrg, \
- .getc = uart_zynq##port##_getc, \
- .tstc = uart_zynq##port##_tstc, \
- .putc = uart_zynq##port##_putc, \
- .puts = uart_zynq##port##_puts, \
-}
+static int zynq_serial_putc(struct udevice *dev, const char ch)
+{
+ struct zynq_uart_priv *priv = dev_get_priv(dev);
-DECLARE_PSSERIAL_FUNCTIONS(0);
-static struct serial_device uart_zynq_serial0_device =
- INIT_PSSERIAL_STRUCTURE(0, "ttyPS0");
-DECLARE_PSSERIAL_FUNCTIONS(1);
-static struct serial_device uart_zynq_serial1_device =
- INIT_PSSERIAL_STRUCTURE(1, "ttyPS1");
+ return _uart_zynq_serial_putc(priv->regs, ch);
+}
-#if CONFIG_IS_ENABLED(OF_CONTROL)
-__weak struct serial_device *default_serial_console(void)
+static int zynq_serial_pending(struct udevice *dev, bool input)
{
- const void *blob = gd->fdt_blob;
- int node;
- unsigned int base_addr;
+ struct zynq_uart_priv *priv = dev_get_priv(dev);
+ struct uart_zynq *regs = priv->regs;
- node = fdt_path_offset(blob, "serial0");
- if (node < 0)
- return NULL;
+ if (input)
+ return !(readl(&regs->channel_sts) & ZYNQ_UART_SR_RXEMPTY);
+ else
+ return !!(readl(&regs->channel_sts) & ZYNQ_UART_SR_TXACTIVE);
+}
- base_addr = fdtdec_get_addr(blob, node, "reg");
- if (base_addr == FDT_ADDR_T_NONE)
- return NULL;
+static int zynq_serial_ofdata_to_platdata(struct udevice *dev)
+{
+ struct zynq_uart_priv *priv = dev_get_priv(dev);
+ fdt_addr_t addr;
- if (base_addr == ZYNQ_SERIAL_BASEADDR0)
- return &uart_zynq_serial0_device;
+ addr = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg");
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
- if (base_addr == ZYNQ_SERIAL_BASEADDR1)
- return &uart_zynq_serial1_device;
+ priv->regs = (struct uart_zynq *)addr;
- return NULL;
+ return 0;
}
-#else
-__weak struct serial_device *default_serial_console(void)
+
+static const struct dm_serial_ops zynq_serial_ops = {
+ .putc = zynq_serial_putc,
+ .pending = zynq_serial_pending,
+ .getc = zynq_serial_getc,
+ .setbrg = zynq_serial_setbrg,
+};
+
+static const struct udevice_id zynq_serial_ids[] = {
+ { .compatible = "xlnx,xuartps" },
+ { .compatible = "cdns,uart-r1p8" },
+ { }
+};
+
+U_BOOT_DRIVER(serial_s5p) = {
+ .name = "serial_zynq",
+ .id = UCLASS_SERIAL,
+ .of_match = zynq_serial_ids,
+ .ofdata_to_platdata = zynq_serial_ofdata_to_platdata,
+ .priv_auto_alloc_size = sizeof(struct zynq_uart_priv),
+ .probe = zynq_serial_probe,
+ .ops = &zynq_serial_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+#ifdef CONFIG_DEBUG_UART_ZYNQ
+
+#include <debug_uart.h>
+
+void _debug_uart_init(void)
{
-#if defined(CONFIG_ZYNQ_SERIAL_UART0)
- if (uart_zynq_ports[0])
- return &uart_zynq_serial0_device;
-#endif
-#if defined(CONFIG_ZYNQ_SERIAL_UART1)
- if (uart_zynq_ports[1])
- return &uart_zynq_serial1_device;
-#endif
- return NULL;
+ struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE;
+
+ _uart_zynq_serial_init(regs);
+ _uart_zynq_serial_setbrg(regs, CONFIG_DEBUG_UART_CLOCK,
+ CONFIG_BAUDRATE);
}
-#endif
-void zynq_serial_initialize(void)
+static inline void _debug_uart_putc(int ch)
{
- serial_register(&uart_zynq_serial0_device);
- serial_register(&uart_zynq_serial1_device);
+ struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE;
+
+ while (_uart_zynq_serial_putc(regs, ch) == -EAGAIN)
+ WATCHDOG_RESET();
}
+
+DEBUG_UART_FUNCS
+
+#endif
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index 3d4baa5..99345eb 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -1,5 +1,7 @@
#
# Makefile for the U-boot SOC specific device drivers.
#
+# SPDX-License-Identifier: GPL-2.0+
+#
obj-$(CONFIG_ARCH_KEYSTONE) += keystone/
diff --git a/drivers/soc/keystone/Makefile b/drivers/soc/keystone/Makefile
index c000eca..1334fa4 100644
--- a/drivers/soc/keystone/Makefile
+++ b/drivers/soc/keystone/Makefile
@@ -1 +1,5 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
obj-$(CONFIG_TI_KEYSTONE_SERDES) += keystone_serdes.o
diff --git a/drivers/spi/altera_spi.c b/drivers/spi/altera_spi.c
index e49949b..3e09592 100644
--- a/drivers/spi/altera_spi.c
+++ b/drivers/spi/altera_spi.c
@@ -193,8 +193,8 @@ static const struct dm_spi_ops altera_spi_ops = {
};
static const struct udevice_id altera_spi_ids[] = {
- { .compatible = "altr,spi-1.0", },
- { }
+ { .compatible = "altr,spi-1.0" },
+ {}
};
U_BOOT_DRIVER(altera_spi) = {
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index 34a0f46..4f7fd52 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -37,9 +37,8 @@ static int cadence_spi_write_speed(struct udevice *bus, uint hz)
}
/* Calibration sequence to determine the read data capture delay register */
-static int spi_calibration(struct udevice *bus)
+static int spi_calibration(struct udevice *bus, uint hz)
{
- struct cadence_spi_platdata *plat = bus->platdata;
struct cadence_spi_priv *priv = dev_get_priv(bus);
void *base = priv->regbase;
u8 opcode_rdid = 0x9F;
@@ -64,7 +63,7 @@ static int spi_calibration(struct udevice *bus)
}
/* use back the intended clock and find low range */
- cadence_spi_write_speed(bus, plat->max_hz);
+ cadence_spi_write_speed(bus, hz);
for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) {
/* Disable QSPI */
cadence_qspi_apb_controller_disable(base);
@@ -111,7 +110,7 @@ static int spi_calibration(struct udevice *bus)
(range_hi + range_lo) / 2, range_lo, range_hi);
/* just to ensure we do once only when speed or chip select change */
- priv->qspi_calibrated_hz = plat->max_hz;
+ priv->qspi_calibrated_hz = hz;
priv->qspi_calibrated_cs = spi_chip_select(bus);
return 0;
@@ -123,17 +122,25 @@ static int cadence_spi_set_speed(struct udevice *bus, uint hz)
struct cadence_spi_priv *priv = dev_get_priv(bus);
int err;
+ if (hz > plat->max_hz)
+ hz = plat->max_hz;
+
/* Disable QSPI */
cadence_qspi_apb_controller_disable(priv->regbase);
- cadence_spi_write_speed(bus, hz);
-
- /* Calibration required for different SCLK speed or chip select */
- if (priv->qspi_calibrated_hz != plat->max_hz ||
+ /*
+ * Calibration required for different current SCLK speed, requested
+ * SCLK speed or chip select
+ */
+ if (priv->previous_hz != hz ||
+ priv->qspi_calibrated_hz != hz ||
priv->qspi_calibrated_cs != spi_chip_select(bus)) {
- err = spi_calibration(bus);
+ err = spi_calibration(bus, hz);
if (err)
return err;
+
+ /* prevent calibration run when same as previous request */
+ priv->previous_hz = hz;
}
/* Enable QSPI */
@@ -291,10 +298,6 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus)
plat->regbase = (void *)data[0];
plat->ahbbase = (void *)data[2];
- /* Use 500KHz as a suitable default */
- plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
- 500000);
-
/* All other paramters are embedded in the child node */
subnode = fdt_first_subnode(blob, node);
if (subnode < 0) {
@@ -302,6 +305,10 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus)
return -ENODEV;
}
+ /* Use 500 KHz as a suitable default */
+ plat->max_hz = fdtdec_get_uint(blob, subnode, "spi-max-frequency",
+ 500000);
+
/* Read other parameters from DT */
plat->page_size = fdtdec_get_int(blob, subnode, "page-size", 256);
plat->block_size = fdtdec_get_int(blob, subnode, "block-size", 16);
diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h
index 98e57aa..2912e36 100644
--- a/drivers/spi/cadence_qspi.h
+++ b/drivers/spi/cadence_qspi.h
@@ -38,6 +38,7 @@ struct cadence_spi_priv {
int qspi_is_init;
unsigned int qspi_calibrated_hz;
unsigned int qspi_calibrated_cs;
+ unsigned int previous_hz;
};
/* Functions call declaration */
diff --git a/drivers/timer/altera_timer.c b/drivers/timer/altera_timer.c
index 2ef9ad6..46a598a 100644
--- a/drivers/timer/altera_timer.c
+++ b/drivers/timer/altera_timer.c
@@ -16,6 +16,11 @@
DECLARE_GLOBAL_DATA_PTR;
+/* control register */
+#define ALTERA_TIMER_CONT BIT(1) /* Continuous mode */
+#define ALTERA_TIMER_START BIT(2) /* Start timer */
+#define ALTERA_TIMER_STOP BIT(3) /* Stop timer */
+
struct altera_timer_regs {
u32 status; /* Timer status reg */
u32 control; /* Timer control reg */
@@ -30,11 +35,6 @@ struct altera_timer_platdata {
unsigned long clock_rate;
};
-/* control register */
-#define ALTERA_TIMER_CONT (1 << 1) /* Continuous mode */
-#define ALTERA_TIMER_START (1 << 2) /* Start timer */
-#define ALTERA_TIMER_STOP (1 << 3) /* Stop timer */
-
static int altera_timer_get_count(struct udevice *dev, unsigned long *count)
{
struct altera_timer_platdata *plat = dev->platdata;
@@ -88,8 +88,8 @@ static const struct timer_ops altera_timer_ops = {
};
static const struct udevice_id altera_timer_ids[] = {
- { .compatible = "altr,timer-1.0", },
- { }
+ { .compatible = "altr,timer-1.0" },
+ {}
};
U_BOOT_DRIVER(altera_timer) = {
diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile
index 02bb216..0cd7302 100644
--- a/drivers/usb/dwc3/Makefile
+++ b/drivers/usb/dwc3/Makefile
@@ -1,3 +1,7 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
obj-$(CONFIG_USB_DWC3) += dwc3.o
dwc3-y := core.o
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index ab3c94e..0ae3de5 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -281,7 +281,7 @@ static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
return 0;
err1:
- dma_unmap_single((void *)dwc->scratch_addr, dwc->nr_scratch *
+ dma_unmap_single((void *)(uintptr_t)dwc->scratch_addr, dwc->nr_scratch *
DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
err0:
@@ -296,7 +296,7 @@ static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
if (!dwc->nr_scratch)
return;
- dma_unmap_single((void *)dwc->scratch_addr, dwc->nr_scratch *
+ dma_unmap_single((void *)(uintptr_t)dwc->scratch_addr, dwc->nr_scratch *
DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
kfree(dwc->scratchbuf);
}
@@ -629,7 +629,8 @@ int dwc3_uboot_init(struct dwc3_device *dwc3_dev)
dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
dwc->mem = mem;
- dwc->regs = (int *)(dwc3_dev->base + DWC3_GLOBALS_REGS_START);
+ dwc->regs = (void *)(uintptr_t)(dwc3_dev->base +
+ DWC3_GLOBALS_REGS_START);
/* default to highest possible threshold */
lpm_nyet_threshold = 0xff;
diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c
index aba614f..12b133f 100644
--- a/drivers/usb/dwc3/ep0.c
+++ b/drivers/usb/dwc3/ep0.c
@@ -81,8 +81,8 @@ static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
trb->ctrl |= (DWC3_TRB_CTRL_IOC
| DWC3_TRB_CTRL_LST);
- dwc3_flush_cache((int)buf_dma, len);
- dwc3_flush_cache((int)trb, sizeof(*trb));
+ dwc3_flush_cache((long)buf_dma, len);
+ dwc3_flush_cache((long)trb, sizeof(*trb));
if (chain)
return 0;
@@ -790,7 +790,7 @@ static void dwc3_ep0_complete_data(struct dwc3 *dwc,
if (!r)
return;
- dwc3_flush_cache((int)trb, sizeof(*trb));
+ dwc3_flush_cache((long)trb, sizeof(*trb));
status = DWC3_TRB_SIZE_TRBSTS(trb->size);
if (status == DWC3_TRBSTS_SETUP_PENDING) {
@@ -821,7 +821,7 @@ static void dwc3_ep0_complete_data(struct dwc3 *dwc,
ur->actual += transferred;
trb++;
- dwc3_flush_cache((int)trb, sizeof(*trb));
+ dwc3_flush_cache((long)trb, sizeof(*trb));
length = trb->size & DWC3_TRB_SIZE_MASK;
ep0->free_slot = 0;
@@ -831,7 +831,7 @@ static void dwc3_ep0_complete_data(struct dwc3 *dwc,
maxp);
transferred = min_t(u32, ur->length - transferred,
transfer_size - length);
- dwc3_flush_cache((int)dwc->ep0_bounce, DWC3_EP0_BOUNCE_SIZE);
+ dwc3_flush_cache((long)dwc->ep0_bounce, DWC3_EP0_BOUNCE_SIZE);
memcpy(buf, dwc->ep0_bounce, transferred);
} else {
transferred = ur->length - length;
diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
index f3d649a..8ff949d 100644
--- a/drivers/usb/dwc3/gadget.c
+++ b/drivers/usb/dwc3/gadget.c
@@ -244,7 +244,7 @@ void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
list_del(&req->list);
req->trb = NULL;
- dwc3_flush_cache((int)req->request.dma, req->request.length);
+ dwc3_flush_cache((long)req->request.dma, req->request.length);
if (req->request.status == -EINPROGRESS)
req->request.status = status;
@@ -771,8 +771,8 @@ static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
trb->ctrl |= DWC3_TRB_CTRL_HWO;
- dwc3_flush_cache((int)dma, length);
- dwc3_flush_cache((int)trb, sizeof(*trb));
+ dwc3_flush_cache((long)dma, length);
+ dwc3_flush_cache((long)trb, sizeof(*trb));
}
/*
@@ -1769,7 +1769,7 @@ static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
slot %= DWC3_TRB_NUM;
trb = &dep->trb_pool[slot];
- dwc3_flush_cache((int)trb, sizeof(*trb));
+ dwc3_flush_cache((long)trb, sizeof(*trb));
__dwc3_cleanup_done_trbs(dwc, dep, req, trb, event, status);
dwc3_gadget_giveback(dep, req, status);
@@ -2670,7 +2670,7 @@ void dwc3_gadget_uboot_handle_interrupt(struct dwc3 *dwc)
for (i = 0; i < dwc->num_event_buffers; i++) {
evt = dwc->ev_buffs[i];
- dwc3_flush_cache((int)evt->buf, evt->length);
+ dwc3_flush_cache((long)evt->buf, evt->length);
}
dwc3_thread_interrupt(0, dwc);
diff --git a/drivers/usb/dwc3/io.h b/drivers/usb/dwc3/io.h
index 5042a24..0d9fa22 100644
--- a/drivers/usb/dwc3/io.h
+++ b/drivers/usb/dwc3/io.h
@@ -23,7 +23,7 @@
#define CACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE
static inline u32 dwc3_readl(void __iomem *base, u32 offset)
{
- u32 offs = offset - DWC3_GLOBALS_REGS_START;
+ unsigned long offs = offset - DWC3_GLOBALS_REGS_START;
u32 value;
/*
@@ -38,7 +38,7 @@ static inline u32 dwc3_readl(void __iomem *base, u32 offset)
static inline void dwc3_writel(void __iomem *base, u32 offset, u32 value)
{
- u32 offs = offset - DWC3_GLOBALS_REGS_START;
+ unsigned long offs = offset - DWC3_GLOBALS_REGS_START;
/*
* We requested the mem region starting from the Globals address
diff --git a/drivers/usb/gadget/f_thor.c b/drivers/usb/gadget/f_thor.c
index ff1481b..9ed0ce3 100644
--- a/drivers/usb/gadget/f_thor.c
+++ b/drivers/usb/gadget/f_thor.c
@@ -569,7 +569,7 @@ static void thor_tx_data(unsigned char *data, int len)
dev->in_req->length = len;
- debug("%s: dev->in_req->length:%d to_cpy:%d\n", __func__,
+ debug("%s: dev->in_req->length:%d to_cpy:%zd\n", __func__,
dev->in_req->length, sizeof(data));
status = usb_ep_queue(dev->in_ep, dev->in_req, 0);
diff --git a/drivers/usb/gadget/udc/Makefile b/drivers/usb/gadget/udc/Makefile
index 12380f4..1699ccd 100644
--- a/drivers/usb/gadget/udc/Makefile
+++ b/drivers/usb/gadget/udc/Makefile
@@ -1,4 +1,7 @@
#
# USB peripheral controller drivers
#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
obj-$(CONFIG_USB_DWC3_GADGET) += udc-core.o
diff --git a/drivers/usb/gadget/udc/udc-core.c b/drivers/usb/gadget/udc/udc-core.c
index 875e998..326757b 100644
--- a/drivers/usb/gadget/udc/udc-core.c
+++ b/drivers/usb/gadget/udc/udc-core.c
@@ -65,7 +65,7 @@ void usb_gadget_unmap_request(struct usb_gadget *gadget,
if (req->length == 0)
return;
- dma_unmap_single((void *)req->dma, req->length,
+ dma_unmap_single((void *)(uintptr_t)req->dma, req->length,
is_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
}
EXPORT_SYMBOL_GPL(usb_gadget_unmap_request);
diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index 9bde2b2..ccbfc02 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -2205,6 +2205,7 @@ int ohci_register(struct udevice *dev, struct ohci_regs *regs)
if (!ohci->hcca)
return -ENOMEM;
memset(ohci->hcca, 0, sizeof(struct ohci_hcca));
+ flush_dcache_hcca(ohci->hcca);
if (hc_reset(ohci) < 0)
return -EIO;
diff --git a/drivers/usb/musb-new/Makefile b/drivers/usb/musb-new/Makefile
index fd9df72..072d516 100644
--- a/drivers/usb/musb-new/Makefile
+++ b/drivers/usb/musb-new/Makefile
@@ -1,6 +1,8 @@
#
# for USB OTG silicon based on Mentor Graphics INVENTRA designs
#
+# SPDX-License-Identifier: GPL-2.0+
+#
obj-$(CONFIG_USB_MUSB_GADGET) += musb_gadget.o musb_gadget_ep0.o musb_core.o
obj-$(CONFIG_USB_MUSB_GADGET) += musb_uboot.o
diff --git a/drivers/video/atmel_hlcdfb.c b/drivers/video/atmel_hlcdfb.c
index 0ce2370..960b474 100644
--- a/drivers/video/atmel_hlcdfb.c
+++ b/drivers/video/atmel_hlcdfb.c
@@ -162,6 +162,10 @@ void lcd_ctrl_init(void *lcdbase)
lcdc_writel(&regs->lcdc_basecfg1,
LCDC_BASECFG1_RGBMODE_16BPP_RGB_565);
break;
+ case 32:
+ lcdc_writel(&regs->lcdc_basecfg1,
+ LCDC_BASECFG1_RGBMODE_24BPP_RGB_888);
+ break;
default:
BUG();
break;
diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c
index aa7ca86..556a55f 100644
--- a/drivers/video/cfb_console.c
+++ b/drivers/video/cfb_console.c
@@ -2280,8 +2280,7 @@ int drv_video_init(void)
/* Init vga device */
memset(&console_dev, 0, sizeof(console_dev));
strcpy(console_dev.name, "vga");
- console_dev.ext = DEV_EXT_VIDEO; /* Video extensions */
- console_dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_SYSTEM;
+ console_dev.flags = DEV_FLAGS_OUTPUT;
console_dev.putc = video_putc; /* 'putc' function */
console_dev.puts = video_puts; /* 'puts' function */