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authorNikhil Badola <nikhil.badola@freescale.com>2014-11-21 17:25:21 +0530
committerYork Sun <yorksun@freescale.com>2015-05-04 09:23:50 -0700
commit0dc78ff857337a82d39d7e4390e317ffbc93097f (patch)
treed584241cdf4866dadf0659d1fdb073e82b00279e /drivers
parent7fc63cca611b9d2b5f170f9f37e6f99ddf5992a9 (diff)
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drivers: usb: fsl: Workaround for Erratum A004477
Add a delay of 1 microsecond before issuing soft reset to the controller to let ongoing ULPI transaction complete. This prevents corruption of ULPI Function Control Register which eventually prevents phy clock from entering to low power mode Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/usb/host/ehci-fsl.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 2dca524..5fd618d 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -138,6 +138,16 @@ int ehci_hcd_init(int index, enum usb_init_type init,
if (has_erratum_a007798())
set_txfifothresh(ehci, TXFIFOTHRESH);
+ if (has_erratum_a004477()) {
+ /*
+ * When reset is issued while any ULPI transaction is ongoing
+ * then it may result to corruption of ULPI Function Control
+ * Register which eventually causes phy clock to enter low
+ * power mode which stops the clock. Thus delay is required
+ * before reset to let ongoing ULPI transaction complete.
+ */
+ udelay(1);
+ }
return 0;
}