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authorAnatolij Gustschin <agust@denx.de>2011-01-19 22:46:32 +0000
committerAlbert Aribaud <albert.aribaud@free.fr>2011-02-02 00:54:43 +0100
commitafaa9f65c24d815ed4f6133c800884921e051913 (patch)
tree2ded84b8cf87fb1a3497d66e8f651fe7abdd4c57 /drivers
parentdff0109496846fd9787b6cdc0941217ecdf0ae28 (diff)
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SPI: mxc_spi: add SPI clock calculation and setup to the driver
The MXC SPI driver didn't calculate the SPI clock up to now and just used highest possible divider 512 for DATA RATE in the control register. This results in very low transfer rates. The patch adds code to calculate and setup the SPI clock frequency for transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/spi/mxc_spi.c23
1 files changed, 22 insertions, 1 deletions
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index dadf228..2a4ddad 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -199,15 +199,36 @@ void spi_cs_deactivate(struct spi_slave *slave)
!(mxcs->ss_pol));
}
+u32 get_cspi_div(u32 div)
+{
+ int i;
+
+ for (i = 0; i < 8; i++) {
+ if (div <= (4 << i))
+ return i;
+ }
+ return i;
+}
+
#if defined(CONFIG_MX31) || defined(CONFIG_MX35)
static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
unsigned int max_hz, unsigned int mode)
{
unsigned int ctrl_reg;
+ u32 clk_src;
+ u32 div;
+
+ clk_src = mxc_get_clock(MXC_CSPI_CLK);
+
+ div = clk_src / max_hz;
+ div = get_cspi_div(div);
+
+ debug("clk %d Hz, div %d, real clk %d Hz\n",
+ max_hz, div, clk_src / (4 << div));
ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) |
MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) |
- MXC_CSPICTRL_DATARATE(7) | /* FIXME: calculate data rate */
+ MXC_CSPICTRL_DATARATE(div) |
MXC_CSPICTRL_EN |
#ifdef CONFIG_MX35
MXC_CSPICTRL_SSCTL |