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authorYe Li <ye.li@nxp.com>2016-03-03 17:23:26 +0800
committerguoyin.chen <guoyin.chen@freescale.com>2016-03-04 15:53:41 +0800
commit8c8da023f9c530254486cda4bccb3a45d0ae6e28 (patch)
tree609d04081e339771c2175d4e05fd2691241bc6e0 /drivers
parent2f8eaed32b99e436c085802322407f990c43ee05 (diff)
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MLK-12488 mx6sl/ul/sx: Fix incorrect clear mmdc_ch0 handshake mask
Since the MX6UL/SL/SX only has one DDR channel, in CCM_CCDR register the bit[17] for mmdc_ch0 is reserved and its proper state should be 1. When clear this bit, the periph_clk_sel cannot be set and that CDHIPR[periph_clk_sel_busy] handshake never clears. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 4c3e6cd60f1f15061b391965ebc1ccb158129286)
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