summaryrefslogtreecommitdiff
path: root/drivers
diff options
context:
space:
mode:
authorWolfgang Denk <wd@denx.de>2011-04-10 21:24:40 +0200
committerWolfgang Denk <wd@denx.de>2011-04-10 21:24:40 +0200
commit17e967b3dfcc0616a135700a2c39287943ffb958 (patch)
tree5af8e32aefa1073c18e70b3ed048e42b0eac8534 /drivers
parent4fd783d63f85871db03b1f06a2572bf43085af32 (diff)
parentc1c087b753633305a0d656a7b4d65d788f4bfb68 (diff)
downloadu-boot-imx-17e967b3dfcc0616a135700a2c39287943ffb958.zip
u-boot-imx-17e967b3dfcc0616a135700a2c39287943ffb958.tar.gz
u-boot-imx-17e967b3dfcc0616a135700a2c39287943ffb958.tar.bz2
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'drivers')
-rw-r--r--drivers/mmc/fsl_esdhc.c8
-rw-r--r--drivers/qe/uec.c37
2 files changed, 40 insertions, 5 deletions
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 0962ac4..4f1b515 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -178,14 +178,14 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
wml_value = data->blocksize/4;
if (data->flags & MMC_DATA_READ) {
- if (wml_value > 0x10)
- wml_value = 0x10;
+ if (wml_value > WML_RD_WML_MAX)
+ wml_value = WML_RD_WML_MAX_VAL;
esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
esdhc_write32(&regs->dsaddr, (u32)data->dest);
} else {
- if (wml_value > 0x80)
- wml_value = 0x80;
+ if (wml_value > WML_WR_WML_MAX)
+ wml_value = WML_WR_WML_MAX_VAL;
if ((esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL) == 0) {
printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
return TIMEOUT;
diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
index 282ab23..811e3fc 100644
--- a/drivers/qe/uec.c
+++ b/drivers/qe/uec.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2006-2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2006-2011 Freescale Semiconductor, Inc.
*
* Dave Liu <daveliu@freescale.com>
*
@@ -588,9 +588,27 @@ static void phy_change(struct eth_device *dev)
{
uec_private_t *uec = (uec_private_t *)dev->priv;
+#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
+ defined(CONFIG_P1021) || defined(CONFIG_P1025)
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+ /* QE9 and QE12 need to be set for enabling QE MII managment signals */
+ setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9);
+ setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
+#endif
+
/* Update the link, speed, duplex */
uec->mii_info->phyinfo->read_status(uec->mii_info);
+#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
+ defined(CONFIG_P1021) || defined(CONFIG_P1025)
+ /*
+ * QE12 is muxed with LBCTL, it needs to be released for enabling
+ * LBCTL signal for LBC usage.
+ */
+ clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
+#endif
+
/* Adjust the interface according to speed */
adjust_link(dev);
}
@@ -1198,10 +1216,21 @@ static int uec_init(struct eth_device* dev, bd_t *bd)
uec_private_t *uec;
int err, i;
struct phy_info *curphy;
+#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
+ defined(CONFIG_P1021) || defined(CONFIG_P1025)
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#endif
uec = (uec_private_t *)dev->priv;
if (uec->the_first_run == 0) {
+#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
+ defined(CONFIG_P1021) || defined(CONFIG_P1025)
+ /* QE9 and QE12 need to be set for enabling QE MII managment signals */
+ setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9);
+ setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
+#endif
+
err = init_phy(dev);
if (err) {
printf("%s: Cannot initialize PHY, aborting.\n",
@@ -1228,6 +1257,12 @@ static int uec_init(struct eth_device* dev, bd_t *bd)
udelay(100000);
} while (1);
+#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
+ defined(CONFIG_P1021) || defined(CONFIG_P1025)
+ /* QE12 needs to be released for enabling LBCTL signal*/
+ clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
+#endif
+
if (err || i <= 0)
printf("warning: %s: timeout on PHY link\n", dev->name);