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author | Wolfgang Denk <wd@denx.de> | 2008-01-09 11:27:02 +0100 |
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committer | Wolfgang Denk <wd@denx.de> | 2008-01-09 11:27:02 +0100 |
commit | 0b4f57923024ccbdaa4436d6bcc958307dd597bd (patch) | |
tree | 04525dae88a9ec015752725468b46c577ad4939d /drivers | |
parent | c1d16334091653de8eabcc9eb4f3447c98ba5506 (diff) | |
parent | 6775c68683a53c7abc778774641aac6f833a2cbf (diff) | |
download | u-boot-imx-0b4f57923024ccbdaa4436d6bcc958307dd597bd.zip u-boot-imx-0b4f57923024ccbdaa4436d6bcc958307dd597bd.tar.gz u-boot-imx-0b4f57923024ccbdaa4436d6bcc958307dd597bd.tar.bz2 |
Merge branch 'master' of git://www.denx.de/git/u-boot-mpc83xx
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/net/tsec.c | 10 | ||||
-rw-r--r-- | drivers/qe/uec.c | 23 |
2 files changed, 33 insertions, 0 deletions
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index ca6284b..108cebd 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -674,6 +674,15 @@ uint mii_cis8204_setmode(uint mii_reg, struct tsec_private * priv) return MIIM_CIS8204_EPHYCON_INIT; } +uint mii_m88e1111s_setmode(uint mii_reg, struct tsec_private *priv) +{ + uint mii_data = read_phy_reg(priv, mii_reg); + + if (priv->flags & TSEC_REDUCED) + mii_data = (mii_data & 0xfff0) | 0x000b; + return mii_data; +} + /* Initialized required registers to appropriate values, zeroing * those we don't care about (unless zero is bad, in which case, * choose a more appropriate value) @@ -1034,6 +1043,7 @@ struct phy_info phy_info_M88E1111S = { (struct phy_cmd[]){ /* config */ /* Reset and configure the PHY */ {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {0x1b, 0x848f, &mii_m88e1111s_setmode}, {0x14, 0x0cd2, NULL}, /* Delay RGMII TX and RX */ {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c index dc2765b..a27c12a 100644 --- a/drivers/qe/uec.c +++ b/drivers/qe/uec.c @@ -69,6 +69,25 @@ static uec_info_t eth2_uec_info = { }; #endif +#ifdef CONFIG_UEC_ETH3 +static uec_info_t eth3_uec_info = { + .uf_info = { + .ucc_num = CFG_UEC3_UCC_NUM, + .rx_clock = CFG_UEC3_RX_CLK, + .tx_clock = CFG_UEC3_TX_CLK, + .eth_type = CFG_UEC3_ETH_TYPE, + }, + .num_threads_tx = UEC_NUM_OF_THREADS_4, + .num_threads_rx = UEC_NUM_OF_THREADS_4, + .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, + .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, + .tx_bd_ring_len = 16, + .rx_bd_ring_len = 16, + .phy_address = CFG_UEC3_PHY_ADDR, + .enet_interface = CFG_UEC3_INTERFACE_MODE, +}; +#endif + static int uec_mac_enable(uec_private_t *uec, comm_dir_e mode) { uec_t *uec_regs; @@ -1238,6 +1257,10 @@ int uec_initialize(int index) #ifdef CONFIG_UEC_ETH2 uec_info = ð2_uec_info; #endif + } else if (index == 2) { +#ifdef CONFIG_UEC_ETH3 + uec_info = ð3_uec_info; +#endif } else { printf("%s: index is illegal.\n", __FUNCTION__); return -EINVAL; |