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| author | Stefano Babic <sbabic@denx.de> | 2014-02-11 12:55:32 +0100 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2014-02-11 12:55:32 +0100 |
| commit | 17998eff9021b7b579c0387e934d8c52603fe247 (patch) | |
| tree | edc3ef069db4cdaf9c718ae60e095caf42cd1d0d /drivers | |
| parent | 6ba45cc0f8b46533965219cfd90864a60ec1009b (diff) | |
| parent | e97f9d817e600cd6f43d1d0da76f5787e33a5c56 (diff) | |
| download | u-boot-imx-17998eff9021b7b579c0387e934d8c52603fe247.zip u-boot-imx-17998eff9021b7b579c0387e934d8c52603fe247.tar.gz u-boot-imx-17998eff9021b7b579c0387e934d8c52603fe247.tar.bz2 | |
Merge branch 'master' of git://git.denx.de/u-boot-arm
Diffstat (limited to 'drivers')
28 files changed, 1233 insertions, 1513 deletions
diff --git a/drivers/bios_emulator/include/x86emu/prim_asm.h b/drivers/bios_emulator/include/x86emu/prim_asm.h deleted file mode 100644 index 4cb4cab..0000000 --- a/drivers/bios_emulator/include/x86emu/prim_asm.h +++ /dev/null @@ -1,970 +0,0 @@ -/**************************************************************************** -* -* Realmode X86 Emulator Library -* -* Copyright (C) 1991-2004 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich -* -* ======================================================================== -* -* Permission to use, copy, modify, distribute, and sell this software and -* its documentation for any purpose is hereby granted without fee, -* provided that the above copyright notice appear in all copies and that -* both that copyright notice and this permission notice appear in -* supporting documentation, and that the name of the authors not be used -* in advertising or publicity pertaining to distribution of the software -* without specific, written prior permission. The authors makes no -* representations about the suitability of this software for any purpose. -* It is provided "as is" without express or implied warranty. -* -* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, -* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO -* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR -* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF -* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR -* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR -* PERFORMANCE OF THIS SOFTWARE. -* -* ======================================================================== -* -* Language: Watcom C++ 10.6 or later -* Environment: Any -* Developer: Kendall Bennett -* -* Description: Inline assembler versions of the primitive operand -* functions for faster performance. At the moment this is -* x86 inline assembler, but these functions could be replaced -* with native inline assembler for each supported processor -* platform. -* -****************************************************************************/ - -#ifndef __X86EMU_PRIM_ASM_H -#define __X86EMU_PRIM_ASM_H - -#ifdef __WATCOMC__ - -#ifndef VALIDATE -#define __HAVE_INLINE_ASSEMBLER__ -#endif - -u32 get_flags_asm(void); -#pragma aux get_flags_asm = \ - "pushf" \ - "pop eax" \ - value [eax] \ - modify exact [eax]; - -u16 aaa_word_asm(u32 * flags, u16 d); -#pragma aux aaa_word_asm = \ - "push [edi]" \ - "popf" \ - "aaa" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] \ - value [ax] \ - modify exact [ax]; - -u16 aas_word_asm(u32 * flags, u16 d); -#pragma aux aas_word_asm = \ - "push [edi]" \ - "popf" \ - "aas" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] \ - value [ax] \ - modify exact [ax]; - -u16 aad_word_asm(u32 * flags, u16 d); -#pragma aux aad_word_asm = \ - "push [edi]" \ - "popf" \ - "aad" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] \ - value [ax] \ - modify exact [ax]; - -u16 aam_word_asm(u32 * flags, u8 d); -#pragma aux aam_word_asm = \ - "push [edi]" \ - "popf" \ - "aam" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] \ - value [ax] \ - modify exact [ax]; - -u8 adc_byte_asm(u32 * flags, u8 d, u8 s); -#pragma aux adc_byte_asm = \ - "push [edi]" \ - "popf" \ - "adc al,bl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [bl] \ - value [al] \ - modify exact [al bl]; - -u16 adc_word_asm(u32 * flags, u16 d, u16 s); -#pragma aux adc_word_asm = \ - "push [edi]" \ - "popf" \ - "adc ax,bx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [bx] \ - value [ax] \ - modify exact [ax bx]; - -u32 adc_long_asm(u32 * flags, u32 d, u32 s); -#pragma aux adc_long_asm = \ - "push [edi]" \ - "popf" \ - "adc eax,ebx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [ebx] \ - value [eax] \ - modify exact [eax ebx]; - -u8 add_byte_asm(u32 * flags, u8 d, u8 s); -#pragma aux add_byte_asm = \ - "push [edi]" \ - "popf" \ - "add al,bl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [bl] \ - value [al] \ - modify exact [al bl]; - -u16 add_word_asm(u32 * flags, u16 d, u16 s); -#pragma aux add_word_asm = \ - "push [edi]" \ - "popf" \ - "add ax,bx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [bx] \ - value [ax] \ - modify exact [ax bx]; - -u32 add_long_asm(u32 * flags, u32 d, u32 s); -#pragma aux add_long_asm = \ - "push [edi]" \ - "popf" \ - "add eax,ebx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [ebx] \ - value [eax] \ - modify exact [eax ebx]; - -u8 and_byte_asm(u32 * flags, u8 d, u8 s); -#pragma aux and_byte_asm = \ - "push [edi]" \ - "popf" \ - "and al,bl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [bl] \ - value [al] \ - modify exact [al bl]; - -u16 and_word_asm(u32 * flags, u16 d, u16 s); -#pragma aux and_word_asm = \ - "push [edi]" \ - "popf" \ - "and ax,bx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [bx] \ - value [ax] \ - modify exact [ax bx]; - -u32 and_long_asm(u32 * flags, u32 d, u32 s); -#pragma aux and_long_asm = \ - "push [edi]" \ - "popf" \ - "and eax,ebx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [ebx] \ - value [eax] \ - modify exact [eax ebx]; - -u8 cmp_byte_asm(u32 * flags, u8 d, u8 s); -#pragma aux cmp_byte_asm = \ - "push [edi]" \ - "popf" \ - "cmp al,bl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [bl] \ - value [al] \ - modify exact [al bl]; - -u16 cmp_word_asm(u32 * flags, u16 d, u16 s); -#pragma aux cmp_word_asm = \ - "push [edi]" \ - "popf" \ - "cmp ax,bx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [bx] \ - value [ax] \ - modify exact [ax bx]; - -u32 cmp_long_asm(u32 * flags, u32 d, u32 s); -#pragma aux cmp_long_asm = \ - "push [edi]" \ - "popf" \ - "cmp eax,ebx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [ebx] \ - value [eax] \ - modify exact [eax ebx]; - -u8 daa_byte_asm(u32 * flags, u8 d); -#pragma aux daa_byte_asm = \ - "push [edi]" \ - "popf" \ - "daa" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] \ - value [al] \ - modify exact [al]; - -u8 das_byte_asm(u32 * flags, u8 d); -#pragma aux das_byte_asm = \ - "push [edi]" \ - "popf" \ - "das" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] \ - value [al] \ - modify exact [al]; - -u8 dec_byte_asm(u32 * flags, u8 d); -#pragma aux dec_byte_asm = \ - "push [edi]" \ - "popf" \ - "dec al" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] \ - value [al] \ - modify exact [al]; - -u16 dec_word_asm(u32 * flags, u16 d); -#pragma aux dec_word_asm = \ - "push [edi]" \ - "popf" \ - "dec ax" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] \ - value [ax] \ - modify exact [ax]; - -u32 dec_long_asm(u32 * flags, u32 d); -#pragma aux dec_long_asm = \ - "push [edi]" \ - "popf" \ - "dec eax" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] \ - value [eax] \ - modify exact [eax]; - -u8 inc_byte_asm(u32 * flags, u8 d); -#pragma aux inc_byte_asm = \ - "push [edi]" \ - "popf" \ - "inc al" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] \ - value [al] \ - modify exact [al]; - -u16 inc_word_asm(u32 * flags, u16 d); -#pragma aux inc_word_asm = \ - "push [edi]" \ - "popf" \ - "inc ax" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] \ - value [ax] \ - modify exact [ax]; - -u32 inc_long_asm(u32 * flags, u32 d); -#pragma aux inc_long_asm = \ - "push [edi]" \ - "popf" \ - "inc eax" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] \ - value [eax] \ - modify exact [eax]; - -u8 or_byte_asm(u32 * flags, u8 d, u8 s); -#pragma aux or_byte_asm = \ - "push [edi]" \ - "popf" \ - "or al,bl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [bl] \ - value [al] \ - modify exact [al bl]; - -u16 or_word_asm(u32 * flags, u16 d, u16 s); -#pragma aux or_word_asm = \ - "push [edi]" \ - "popf" \ - "or ax,bx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [bx] \ - value [ax] \ - modify exact [ax bx]; - -u32 or_long_asm(u32 * flags, u32 d, u32 s); -#pragma aux or_long_asm = \ - "push [edi]" \ - "popf" \ - "or eax,ebx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [ebx] \ - value [eax] \ - modify exact [eax ebx]; - -u8 neg_byte_asm(u32 * flags, u8 d); -#pragma aux neg_byte_asm = \ - "push [edi]" \ - "popf" \ - "neg al" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] \ - value [al] \ - modify exact [al]; - -u16 neg_word_asm(u32 * flags, u16 d); -#pragma aux neg_word_asm = \ - "push [edi]" \ - "popf" \ - "neg ax" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] \ - value [ax] \ - modify exact [ax]; - -u32 neg_long_asm(u32 * flags, u32 d); -#pragma aux neg_long_asm = \ - "push [edi]" \ - "popf" \ - "neg eax" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] \ - value [eax] \ - modify exact [eax]; - -u8 not_byte_asm(u32 * flags, u8 d); -#pragma aux not_byte_asm = \ - "push [edi]" \ - "popf" \ - "not al" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] \ - value [al] \ - modify exact [al]; - -u16 not_word_asm(u32 * flags, u16 d); -#pragma aux not_word_asm = \ - "push [edi]" \ - "popf" \ - "not ax" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] \ - value [ax] \ - modify exact [ax]; - -u32 not_long_asm(u32 * flags, u32 d); -#pragma aux not_long_asm = \ - "push [edi]" \ - "popf" \ - "not eax" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] \ - value [eax] \ - modify exact [eax]; - -u8 rcl_byte_asm(u32 * flags, u8 d, u8 s); -#pragma aux rcl_byte_asm = \ - "push [edi]" \ - "popf" \ - "rcl al,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [cl] \ - value [al] \ - modify exact [al cl]; - -u16 rcl_word_asm(u32 * flags, u16 d, u8 s); -#pragma aux rcl_word_asm = \ - "push [edi]" \ - "popf" \ - "rcl ax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [cl] \ - value [ax] \ - modify exact [ax cl]; - -u32 rcl_long_asm(u32 * flags, u32 d, u8 s); -#pragma aux rcl_long_asm = \ - "push [edi]" \ - "popf" \ - "rcl eax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [cl] \ - value [eax] \ - modify exact [eax cl]; - -u8 rcr_byte_asm(u32 * flags, u8 d, u8 s); -#pragma aux rcr_byte_asm = \ - "push [edi]" \ - "popf" \ - "rcr al,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [cl] \ - value [al] \ - modify exact [al cl]; - -u16 rcr_word_asm(u32 * flags, u16 d, u8 s); -#pragma aux rcr_word_asm = \ - "push [edi]" \ - "popf" \ - "rcr ax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [cl] \ - value [ax] \ - modify exact [ax cl]; - -u32 rcr_long_asm(u32 * flags, u32 d, u8 s); -#pragma aux rcr_long_asm = \ - "push [edi]" \ - "popf" \ - "rcr eax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [cl] \ - value [eax] \ - modify exact [eax cl]; - -u8 rol_byte_asm(u32 * flags, u8 d, u8 s); -#pragma aux rol_byte_asm = \ - "push [edi]" \ - "popf" \ - "rol al,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [cl] \ - value [al] \ - modify exact [al cl]; - -u16 rol_word_asm(u32 * flags, u16 d, u8 s); -#pragma aux rol_word_asm = \ - "push [edi]" \ - "popf" \ - "rol ax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [cl] \ - value [ax] \ - modify exact [ax cl]; - -u32 rol_long_asm(u32 * flags, u32 d, u8 s); -#pragma aux rol_long_asm = \ - "push [edi]" \ - "popf" \ - "rol eax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [cl] \ - value [eax] \ - modify exact [eax cl]; - -u8 ror_byte_asm(u32 * flags, u8 d, u8 s); -#pragma aux ror_byte_asm = \ - "push [edi]" \ - "popf" \ - "ror al,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [cl] \ - value [al] \ - modify exact [al cl]; - -u16 ror_word_asm(u32 * flags, u16 d, u8 s); -#pragma aux ror_word_asm = \ - "push [edi]" \ - "popf" \ - "ror ax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [cl] \ - value [ax] \ - modify exact [ax cl]; - -u32 ror_long_asm(u32 * flags, u32 d, u8 s); -#pragma aux ror_long_asm = \ - "push [edi]" \ - "popf" \ - "ror eax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [cl] \ - value [eax] \ - modify exact [eax cl]; - -u8 shl_byte_asm(u32 * flags, u8 d, u8 s); -#pragma aux shl_byte_asm = \ - "push [edi]" \ - "popf" \ - "shl al,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [cl] \ - value [al] \ - modify exact [al cl]; - -u16 shl_word_asm(u32 * flags, u16 d, u8 s); -#pragma aux shl_word_asm = \ - "push [edi]" \ - "popf" \ - "shl ax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [cl] \ - value [ax] \ - modify exact [ax cl]; - -u32 shl_long_asm(u32 * flags, u32 d, u8 s); -#pragma aux shl_long_asm = \ - "push [edi]" \ - "popf" \ - "shl eax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [cl] \ - value [eax] \ - modify exact [eax cl]; - -u8 shr_byte_asm(u32 * flags, u8 d, u8 s); -#pragma aux shr_byte_asm = \ - "push [edi]" \ - "popf" \ - "shr al,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [cl] \ - value [al] \ - modify exact [al cl]; - -u16 shr_word_asm(u32 * flags, u16 d, u8 s); -#pragma aux shr_word_asm = \ - "push [edi]" \ - "popf" \ - "shr ax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [cl] \ - value [ax] \ - modify exact [ax cl]; - -u32 shr_long_asm(u32 * flags, u32 d, u8 s); -#pragma aux shr_long_asm = \ - "push [edi]" \ - "popf" \ - "shr eax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [cl] \ - value [eax] \ - modify exact [eax cl]; - -u8 sar_byte_asm(u32 * flags, u8 d, u8 s); -#pragma aux sar_byte_asm = \ - "push [edi]" \ - "popf" \ - "sar al,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [cl] \ - value [al] \ - modify exact [al cl]; - -u16 sar_word_asm(u32 * flags, u16 d, u8 s); -#pragma aux sar_word_asm = \ - "push [edi]" \ - "popf" \ - "sar ax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [cl] \ - value [ax] \ - modify exact [ax cl]; - -u32 sar_long_asm(u32 * flags, u32 d, u8 s); -#pragma aux sar_long_asm = \ - "push [edi]" \ - "popf" \ - "sar eax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [cl] \ - value [eax] \ - modify exact [eax cl]; - -u16 shld_word_asm(u32 * flags, u16 d, u16 fill, u8 s); -#pragma aux shld_word_asm = \ - "push [edi]" \ - "popf" \ - "shld ax,dx,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [dx] [cl] \ - value [ax] \ - modify exact [ax dx cl]; - -u32 shld_long_asm(u32 * flags, u32 d, u32 fill, u8 s); -#pragma aux shld_long_asm = \ - "push [edi]" \ - "popf" \ - "shld eax,edx,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [edx] [cl] \ - value [eax] \ - modify exact [eax edx cl]; - -u16 shrd_word_asm(u32 * flags, u16 d, u16 fill, u8 s); -#pragma aux shrd_word_asm = \ - "push [edi]" \ - "popf" \ - "shrd ax,dx,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [dx] [cl] \ - value [ax] \ - modify exact [ax dx cl]; - -u32 shrd_long_asm(u32 * flags, u32 d, u32 fill, u8 s); -#pragma aux shrd_long_asm = \ - "push [edi]" \ - "popf" \ - "shrd eax,edx,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [edx] [cl] \ - value [eax] \ - modify exact [eax edx cl]; - -u8 sbb_byte_asm(u32 * flags, u8 d, u8 s); -#pragma aux sbb_byte_asm = \ - "push [edi]" \ - "popf" \ - "sbb al,bl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [bl] \ - value [al] \ - modify exact [al bl]; - -u16 sbb_word_asm(u32 * flags, u16 d, u16 s); -#pragma aux sbb_word_asm = \ - "push [edi]" \ - "popf" \ - "sbb ax,bx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [bx] \ - value [ax] \ - modify exact [ax bx]; - -u32 sbb_long_asm(u32 * flags, u32 d, u32 s); -#pragma aux sbb_long_asm = \ - "push [edi]" \ - "popf" \ - "sbb eax,ebx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [ebx] \ - value [eax] \ - modify exact [eax ebx]; - -u8 sub_byte_asm(u32 * flags, u8 d, u8 s); -#pragma aux sub_byte_asm = \ - "push [edi]" \ - "popf" \ - "sub al,bl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [bl] \ - value [al] \ - modify exact [al bl]; - -u16 sub_word_asm(u32 * flags, u16 d, u16 s); -#pragma aux sub_word_asm = \ - "push [edi]" \ - "popf" \ - "sub ax,bx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [bx] \ - value [ax] \ - modify exact [ax bx]; - -u32 sub_long_asm(u32 * flags, u32 d, u32 s); -#pragma aux sub_long_asm = \ - "push [edi]" \ - "popf" \ - "sub eax,ebx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [ebx] \ - value [eax] \ - modify exact [eax ebx]; - -void test_byte_asm(u32 * flags, u8 d, u8 s); -#pragma aux test_byte_asm = \ - "push [edi]" \ - "popf" \ - "test al,bl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [bl] \ - modify exact [al bl]; - -void test_word_asm(u32 * flags, u16 d, u16 s); -#pragma aux test_word_asm = \ - "push [edi]" \ - "popf" \ - "test ax,bx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [bx] \ - modify exact [ax bx]; - -void test_long_asm(u32 * flags, u32 d, u32 s); -#pragma aux test_long_asm = \ - "push [edi]" \ - "popf" \ - "test eax,ebx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [ebx] \ - modify exact [eax ebx]; - -u8 xor_byte_asm(u32 * flags, u8 d, u8 s); -#pragma aux xor_byte_asm = \ - "push [edi]" \ - "popf" \ - "xor al,bl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [bl] \ - value [al] \ - modify exact [al bl]; - -u16 xor_word_asm(u32 * flags, u16 d, u16 s); -#pragma aux xor_word_asm = \ - "push [edi]" \ - "popf" \ - "xor ax,bx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [bx] \ - value [ax] \ - modify exact [ax bx]; - -u32 xor_long_asm(u32 * flags, u32 d, u32 s); -#pragma aux xor_long_asm = \ - "push [edi]" \ - "popf" \ - "xor eax,ebx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [ebx] \ - value [eax] \ - modify exact [eax ebx]; - -void imul_byte_asm(u32 * flags, u16 * ax, u8 d, u8 s); -#pragma aux imul_byte_asm = \ - "push [edi]" \ - "popf" \ - "imul bl" \ - "pushf" \ - "pop [edi]" \ - "mov [esi],ax" \ - parm [edi] [esi] [al] [bl] \ - modify exact [esi ax bl]; - -void imul_word_asm(u32 * flags, u16 * ax, u16 * dx, u16 d, u16 s); -#pragma aux imul_word_asm = \ - "push [edi]" \ - "popf" \ - "imul bx" \ - "pushf" \ - "pop [edi]" \ - "mov [esi],ax" \ - "mov [ecx],dx" \ - parm [edi] [esi] [ecx] [ax] [bx]\ - modify exact [esi edi ax bx dx]; - -void imul_long_asm(u32 * flags, u32 * eax, u32 * edx, u32 d, u32 s); -#pragma aux imul_long_asm = \ - "push [edi]" \ - "popf" \ - "imul ebx" \ - "pushf" \ - "pop [edi]" \ - "mov [esi],eax" \ - "mov [ecx],edx" \ - parm [edi] [esi] [ecx] [eax] [ebx] \ - modify exact [esi edi eax ebx edx]; - -void mul_byte_asm(u32 * flags, u16 * ax, u8 d, u8 s); -#pragma aux mul_byte_asm = \ - "push [edi]" \ - "popf" \ - "mul bl" \ - "pushf" \ - "pop [edi]" \ - "mov [esi],ax" \ - parm [edi] [esi] [al] [bl] \ - modify exact [esi ax bl]; - -void mul_word_asm(u32 * flags, u16 * ax, u16 * dx, u16 d, u16 s); -#pragma aux mul_word_asm = \ - "push [edi]" \ - "popf" \ - "mul bx" \ - "pushf" \ - "pop [edi]" \ - "mov [esi],ax" \ - "mov [ecx],dx" \ - parm [edi] [esi] [ecx] [ax] [bx]\ - modify exact [esi edi ax bx dx]; - -void mul_long_asm(u32 * flags, u32 * eax, u32 * edx, u32 d, u32 s); -#pragma aux mul_long_asm = \ - "push [edi]" \ - "popf" \ - "mul ebx" \ - "pushf" \ - "pop [edi]" \ - "mov [esi],eax" \ - "mov [ecx],edx" \ - parm [edi] [esi] [ecx] [eax] [ebx] \ - modify exact [esi edi eax ebx edx]; - -void idiv_byte_asm(u32 * flags, u8 * al, u8 * ah, u16 d, u8 s); -#pragma aux idiv_byte_asm = \ - "push [edi]" \ - "popf" \ - "idiv bl" \ - "pushf" \ - "pop [edi]" \ - "mov [esi],al" \ - "mov [ecx],ah" \ - parm [edi] [esi] [ecx] [ax] [bl]\ - modify exact [esi edi ax bl]; - -void idiv_word_asm(u32 * flags, u16 * ax, u16 * dx, u16 dlo, u16 dhi, u16 s); -#pragma aux idiv_word_asm = \ - "push [edi]" \ - "popf" \ - "idiv bx" \ - "pushf" \ - "pop [edi]" \ - "mov [esi],ax" \ - "mov [ecx],dx" \ - parm [edi] [esi] [ecx] [ax] [dx] [bx]\ - modify exact [esi edi ax dx bx]; - -void idiv_long_asm(u32 * flags, u32 * eax, u32 * edx, u32 dlo, u32 dhi, u32 s); -#pragma aux idiv_long_asm = \ - "push [edi]" \ - "popf" \ - "idiv ebx" \ - "pushf" \ - "pop [edi]" \ - "mov [esi],eax" \ - "mov [ecx],edx" \ - parm [edi] [esi] [ecx] [eax] [edx] [ebx]\ - modify exact [esi edi eax edx ebx]; - -void div_byte_asm(u32 * flags, u8 * al, u8 * ah, u16 d, u8 s); -#pragma aux div_byte_asm = \ - "push [edi]" \ - "popf" \ - "div bl" \ - "pushf" \ - "pop [edi]" \ - "mov [esi],al" \ - "mov [ecx],ah" \ - parm [edi] [esi] [ecx] [ax] [bl]\ - modify exact [esi edi ax bl]; - -void div_word_asm(u32 * flags, u16 * ax, u16 * dx, u16 dlo, u16 dhi, u16 s); -#pragma aux div_word_asm = \ - "push [edi]" \ - "popf" \ - "div bx" \ - "pushf" \ - "pop [edi]" \ - "mov [esi],ax" \ - "mov [ecx],dx" \ - parm [edi] [esi] [ecx] [ax] [dx] [bx]\ - modify exact [esi edi ax dx bx]; - -void div_long_asm(u32 * flags, u32 * eax, u32 * edx, u32 dlo, u32 dhi, u32 s); -#pragma aux div_long_asm = \ - "push [edi]" \ - "popf" \ - "div ebx" \ - "pushf" \ - "pop [edi]" \ - "mov [esi],eax" \ - "mov [ecx],edx" \ - parm [edi] [esi] [ecx] [eax] [edx] [ebx]\ - modify exact [esi edi eax edx ebx]; - -#endif - -#endif /* __X86EMU_PRIM_ASM_H */ diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c index 9f04133..c805086 100644 --- a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c @@ -39,6 +39,9 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, unsigned int csn_bnds_backup = 0, cs_sa, cs_ea, *csn_bnds_t; int csn = -1; #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003 + u32 save1, save2; +#endif switch (ctrl_num) { case 0: @@ -197,6 +200,8 @@ step2: out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl & 0x7fffffff); out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & 0xffffffeb); out_be32(&ddr->mtcr, 0); + save1 = in_be32(&ddr->debug[12]); + save2 = in_be32(&ddr->debug[21]); out_be32(&ddr->debug[12], 0x00000015); out_be32(&ddr->debug[21], 0x24000000); out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval & 0xffff); @@ -214,6 +219,18 @@ step2: 0x04000000 | MD_CNTL_WRCW | MD_CNTL_MD_VALUE(0x02)); +#if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) + if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN)) + break; + while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN) + ; + out_be32(&ddr->sdram_md_cntl, + MD_CNTL_MD_EN | + MD_CNTL_CS_SEL_CS2_CS3 | + 0x04000000 | + MD_CNTL_WRCW | + MD_CNTL_MD_VALUE(0x02)); +#endif break; case 0x00100000: out_be32(&ddr->sdram_md_cntl, @@ -222,6 +239,18 @@ step2: 0x04000000 | MD_CNTL_WRCW | MD_CNTL_MD_VALUE(0x0a)); +#if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) + if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN)) + break; + while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN) + ; + out_be32(&ddr->sdram_md_cntl, + MD_CNTL_MD_EN | + MD_CNTL_CS_SEL_CS2_CS3 | + 0x04000000 | + MD_CNTL_WRCW | + MD_CNTL_MD_VALUE(0x0a)); +#endif break; case 0x00200000: out_be32(&ddr->sdram_md_cntl, @@ -230,6 +259,18 @@ step2: 0x04000000 | MD_CNTL_WRCW | MD_CNTL_MD_VALUE(0x12)); +#if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) + if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN)) + break; + while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN) + ; + out_be32(&ddr->sdram_md_cntl, + MD_CNTL_MD_EN | + MD_CNTL_CS_SEL_CS2_CS3 | + 0x04000000 | + MD_CNTL_WRCW | + MD_CNTL_MD_VALUE(0x12)); +#endif break; case 0x00300000: out_be32(&ddr->sdram_md_cntl, @@ -238,6 +279,18 @@ step2: 0x04000000 | MD_CNTL_WRCW | MD_CNTL_MD_VALUE(0x1a)); +#if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) + if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN)) + break; + while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN) + ; + out_be32(&ddr->sdram_md_cntl, + MD_CNTL_MD_EN | + MD_CNTL_CS_SEL_CS2_CS3 | + 0x04000000 | + MD_CNTL_WRCW | + MD_CNTL_MD_VALUE(0x1a)); +#endif break; default: out_be32(&ddr->sdram_md_cntl, @@ -246,6 +299,18 @@ step2: 0x04000000 | MD_CNTL_WRCW | MD_CNTL_MD_VALUE(0x02)); +#if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) + if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN)) + break; + while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN) + ; + out_be32(&ddr->sdram_md_cntl, + MD_CNTL_MD_EN | + MD_CNTL_CS_SEL_CS2_CS3 | + 0x04000000 | + MD_CNTL_WRCW | + MD_CNTL_MD_VALUE(0x02)); +#endif printf("Unsupported RC10\n"); break; } @@ -259,8 +324,8 @@ step2: out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); - out_be32(&ddr->debug[12], 0x0); - out_be32(&ddr->debug[21], 0x0); + out_be32(&ddr->debug[12], save1); + out_be32(&ddr->debug[21], save2); out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); } diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c index cb2ac04..9ed9295 100644 --- a/drivers/i2c/designware_i2c.c +++ b/drivers/i2c/designware_i2c.c @@ -266,6 +266,25 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) { unsigned long start_time_rx; +#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW + /* + * EEPROM chips that implement "address overflow" are ones + * like Catalyst 24WC04/08/16 which has 9/10/11 bits of + * address and the extra bits end up in the "chip address" + * bit slots. This makes a 24WC08 (1Kbyte) chip look like + * four 256 byte chips. + * + * Note that we consider the length of the address field to + * still be one byte because the extra address bits are + * hidden in the chip address. + */ + chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); + addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8)); + + debug("%s: fix addr_overflow: chip %02x addr %02x\n", __func__, chip, + addr); +#endif + if (check_params(addr, alen, buffer, len)) return 1; @@ -307,6 +326,25 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) int nb = len; unsigned long start_time_tx; +#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW + /* + * EEPROM chips that implement "address overflow" are ones + * like Catalyst 24WC04/08/16 which has 9/10/11 bits of + * address and the extra bits end up in the "chip address" + * bit slots. This makes a 24WC08 (1Kbyte) chip look like + * four 256 byte chips. + * + * Note that we consider the length of the address field to + * still be one byte because the extra address bits are + * hidden in the chip address. + */ + chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); + addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8)); + + debug("%s: fix addr_overflow: chip %02x addr %02x\n", __func__, chip, + addr); +#endif + if (check_params(addr, alen, buffer, len)) return 1; diff --git a/drivers/i2c/fti2c010.c b/drivers/i2c/fti2c010.c index fb9fa35..68d9a42 100644 --- a/drivers/i2c/fti2c010.c +++ b/drivers/i2c/fti2c010.c @@ -201,7 +201,7 @@ static int fti2c010_read(struct i2c_adapter *adap, struct fti2c010_chip *chip = chip_list + adap->hwadapnr; struct fti2c010_regs *regs = chip->regs; int ret, pos; - uchar paddr[4]; + uchar paddr[4] = { 0 }; to_i2c_addr(paddr, addr, alen); @@ -263,7 +263,7 @@ static int fti2c010_write(struct i2c_adapter *adap, struct fti2c010_chip *chip = chip_list + adap->hwadapnr; struct fti2c010_regs *regs = chip->regs; int ret, pos; - uchar paddr[4]; + uchar paddr[4] = { 0 }; to_i2c_addr(paddr, addr, alen); diff --git a/drivers/i2c/i2c_core.c b/drivers/i2c/i2c_core.c index e1767f4..18d6736 100644 --- a/drivers/i2c/i2c_core.c +++ b/drivers/i2c/i2c_core.c @@ -349,7 +349,7 @@ unsigned int i2c_set_bus_speed(unsigned int speed) return 0; ret = I2C_ADAP->set_bus_speed(I2C_ADAP, speed); if (gd->flags & GD_FLG_RELOC) - I2C_ADAP->speed = ret; + I2C_ADAP->speed = (ret == 0) ? speed : 0; return ret; } diff --git a/drivers/i2c/rcar_i2c.c b/drivers/i2c/rcar_i2c.c index ba2cadb..50cebd6 100644 --- a/drivers/i2c/rcar_i2c.c +++ b/drivers/i2c/rcar_i2c.c @@ -119,11 +119,13 @@ rcar_i2c_raw_read(struct rcar_i2c *dev, u8 chip, uint addr) /* set slave address, receive */ writel((chip << 1) | 1, &dev->icmar); + /* clear status */ + writel(0, &dev->icmsr); /* start master receive */ writel(MCR_MDBS | MCR_MIE | MCR_ESG, &dev->icmcr); - while ((readl(&dev->icmsr) & (MSR_MAT | MSR_MDE)) - != (MSR_MAT | MSR_MDE)) + while ((readl(&dev->icmsr) & (MSR_MAT | MSR_MDR)) + != (MSR_MAT | MSR_MDR)) udelay(10); /* clear ESG */ diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index 4cec5aa..4cec5aa 100755..100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index e3cd0c7..7b146a3 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -500,6 +500,10 @@ static int esdhc_getcd(struct mmc *mmc) struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; int timeout = 1000; +#ifdef CONFIG_ESDHC_DETECT_QUIRK + if (CONFIG_ESDHC_DETECT_QUIRK) + return 1; +#endif while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout) udelay(1000); @@ -592,6 +596,11 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) if (caps & ESDHC_HOSTCAPBLT_HSS) mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; +#ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK + if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK) + mmc->host_caps &= ~MMC_MODE_8BIT; +#endif + mmc->f_min = 400000; mmc->f_max = MIN(gd->arch.sdhc_clk, 52000000); diff --git a/drivers/mmc/pxa_mmc.h b/drivers/mmc/pxa_mmc.h deleted file mode 100644 index 6fa4268..0000000 --- a/drivers/mmc/pxa_mmc.h +++ /dev/null @@ -1,138 +0,0 @@ -/* - * linux/drivers/mmc/mmc_pxa.h - * - * Author: Vladimir Shebordaev, Igor Oblakov - * Copyright: MontaVista Software Inc. - * - * $Id: mmc_pxa.h,v 0.3.1.6 2002/09/25 19:25:48 ted Exp ted $ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef __MMC_PXA_P_H__ -#define __MMC_PXA_P_H__ - -/* PXA-250 MMC controller registers */ - -/* MMC_STRPCL */ -#define MMC_STRPCL_STOP_CLK (0x0001UL) -#define MMC_STRPCL_START_CLK (0x0002UL) - -/* MMC_STAT */ -#define MMC_STAT_END_CMD_RES (0x0001UL << 13) -#define MMC_STAT_PRG_DONE (0x0001UL << 12) -#define MMC_STAT_DATA_TRAN_DONE (0x0001UL << 11) -#define MMC_STAT_CLK_EN (0x0001UL << 8) -#define MMC_STAT_RECV_FIFO_FULL (0x0001UL << 7) -#define MMC_STAT_XMIT_FIFO_EMPTY (0x0001UL << 6) -#define MMC_STAT_RES_CRC_ERROR (0x0001UL << 5) -#define MMC_STAT_SPI_READ_ERROR_TOKEN (0x0001UL << 4) -#define MMC_STAT_CRC_READ_ERROR (0x0001UL << 3) -#define MMC_STAT_CRC_WRITE_ERROR (0x0001UL << 2) -#define MMC_STAT_TIME_OUT_RESPONSE (0x0001UL << 1) -#define MMC_STAT_READ_TIME_OUT (0x0001UL) - -#define MMC_STAT_ERRORS (MMC_STAT_RES_CRC_ERROR|MMC_STAT_SPI_READ_ERROR_TOKEN\ - |MMC_STAT_CRC_READ_ERROR|MMC_STAT_TIME_OUT_RESPONSE\ - |MMC_STAT_READ_TIME_OUT|MMC_STAT_CRC_WRITE_ERROR) - -/* MMC_CLKRT */ -#define MMC_CLKRT_20MHZ (0x0000UL) -#define MMC_CLKRT_10MHZ (0x0001UL) -#define MMC_CLKRT_5MHZ (0x0002UL) -#define MMC_CLKRT_2_5MHZ (0x0003UL) -#define MMC_CLKRT_1_25MHZ (0x0004UL) -#define MMC_CLKRT_0_625MHZ (0x0005UL) -#define MMC_CLKRT_0_3125MHZ (0x0006UL) - -/* MMC_SPI */ -#define MMC_SPI_DISABLE (0x00UL) -#define MMC_SPI_EN (0x01UL) -#define MMC_SPI_CS_EN (0x01UL << 2) -#define MMC_SPI_CS_ADDRESS (0x01UL << 3) -#define MMC_SPI_CRC_ON (0x01UL << 1) - -/* MMC_CMDAT */ -#define MMC_CMDAT_SD_4DAT (0x0001UL << 8) -#define MMC_CMDAT_MMC_DMA_EN (0x0001UL << 7) -#define MMC_CMDAT_INIT (0x0001UL << 6) -#define MMC_CMDAT_BUSY (0x0001UL << 5) -#define MMC_CMDAT_BCR (0x0003UL << 5) -#define MMC_CMDAT_STREAM (0x0001UL << 4) -#define MMC_CMDAT_BLOCK (0x0000UL << 4) -#define MMC_CMDAT_WRITE (0x0001UL << 3) -#define MMC_CMDAT_READ (0x0000UL << 3) -#define MMC_CMDAT_DATA_EN (0x0001UL << 2) -#define MMC_CMDAT_R0 (0) -#define MMC_CMDAT_R1 (0x0001UL) -#define MMC_CMDAT_R2 (0x0002UL) -#define MMC_CMDAT_R3 (0x0003UL) - -/* MMC_RESTO */ -#define MMC_RES_TO_MAX (0x007fUL) /* [6:0] */ - -/* MMC_RDTO */ -#define MMC_READ_TO_MAX (0x0ffffUL) /* [15:0] */ - -/* MMC_BLKLEN */ -#define MMC_BLK_LEN_MAX (0x03ffUL) /* [9:0] */ - -/* MMC_PRTBUF */ -#define MMC_PRTBUF_BUF_PART_FULL (0x01UL) -#define MMC_PRTBUF_BUF_FULL (0x00UL ) - -/* MMC_I_MASK */ -#define MMC_I_MASK_TXFIFO_WR_REQ (0x01UL << 6) -#define MMC_I_MASK_RXFIFO_RD_REQ (0x01UL << 5) -#define MMC_I_MASK_CLK_IS_OFF (0x01UL << 4) -#define MMC_I_MASK_STOP_CMD (0x01UL << 3) -#define MMC_I_MASK_END_CMD_RES (0x01UL << 2) -#define MMC_I_MASK_PRG_DONE (0x01UL << 1) -#define MMC_I_MASK_DATA_TRAN_DONE (0x01UL) -#define MMC_I_MASK_ALL (0x07fUL) - - -/* MMC_I_REG */ -#define MMC_I_REG_TXFIFO_WR_REQ (0x01UL << 6) -#define MMC_I_REG_RXFIFO_RD_REQ (0x01UL << 5) -#define MMC_I_REG_CLK_IS_OFF (0x01UL << 4) -#define MMC_I_REG_STOP_CMD (0x01UL << 3) -#define MMC_I_REG_END_CMD_RES (0x01UL << 2) -#define MMC_I_REG_PRG_DONE (0x01UL << 1) -#define MMC_I_REG_DATA_TRAN_DONE (0x01UL) -#define MMC_I_REG_ALL (0x007fUL) - -/* MMC_CMD */ -#define MMC_CMD_INDEX_MAX (0x006fUL) /* [5:0] */ -#define CMD(x) (x) - -#define MMC_DEFAULT_RCA 1 - -#define MMC_BLOCK_SIZE 512 -#define MMC_MAX_BLOCK_SIZE 512 - -#define MMC_R1_IDLE_STATE 0x01 -#define MMC_R1_ERASE_STATE 0x02 -#define MMC_R1_ILLEGAL_CMD 0x04 -#define MMC_R1_COM_CRC_ERR 0x08 -#define MMC_R1_ERASE_SEQ_ERR 0x01 -#define MMC_R1_ADDR_ERR 0x02 -#define MMC_R1_PARAM_ERR 0x04 - -#define MMC_R1B_WP_ERASE_SKIP 0x0002 -#define MMC_R1B_ERR 0x0004 -#define MMC_R1B_CC_ERR 0x0008 -#define MMC_R1B_CARD_ECC_ERR 0x0010 -#define MMC_R1B_WP_VIOLATION 0x0020 -#define MMC_R1B_ERASE_PARAM 0x0040 -#define MMC_R1B_OOR 0x0080 -#define MMC_R1B_IDLE_STATE 0x0100 -#define MMC_R1B_ERASE_RESET 0x0200 -#define MMC_R1B_ILLEGAL_CMD 0x0400 -#define MMC_R1B_COM_CRC_ERR 0x0800 -#define MMC_R1B_ERASE_SEQ_ERR 0x1000 -#define MMC_R1B_ADDR_ERR 0x2000 -#define MMC_R1B_PARAM_ERR 0x4000 - -#endif /* __MMC_PXA_P_H__ */ diff --git a/drivers/mtd/nand/fsl_ifc_spl.c b/drivers/mtd/nand/fsl_ifc_spl.c index 9de327b..6b43496 100644 --- a/drivers/mtd/nand/fsl_ifc_spl.c +++ b/drivers/mtd/nand/fsl_ifc_spl.c @@ -88,7 +88,11 @@ static inline int bad_block(uchar *marker, int port_size) return __raw_readw((u16 *)marker) != 0xffff; } -static void nand_load(unsigned int offs, int uboot_size, uchar *dst) +#ifdef CONFIG_TPL_BUILD +int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst) +#else +static int nand_load(uint32_t offs, unsigned int uboot_size, void *vdst) +#endif { struct fsl_ifc *ifc = IFC_BASE_ADDR; uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE; @@ -105,6 +109,7 @@ static void nand_load(unsigned int offs, int uboot_size, uchar *dst) int sram_addr; int pg_no; + uchar *dst = vdst; /* Get NAND Flash configuration */ csor = CONFIG_SYS_NAND_CSOR; @@ -208,9 +213,20 @@ static void nand_load(unsigned int offs, int uboot_size, uchar *dst) offs += page_size; } while ((offs & (blk_size - 1)) && (pos < uboot_size)); } + + return 0; } /* + * Defines a static function nand_load_image() here, because non-static makes + * the code too large for certain SPLs(minimal SPL, maximum size <= 4Kbytes) + */ +#ifndef CONFIG_TPL_BUILD +#define nand_spl_load_image(offs, uboot_size, vdst) \ + nand_load(offs, uboot_size, vdst) +#endif + +/* * Main entrypoint for NAND Boot. It's necessary that SDRAM is already * configured and available since this code loads the main U-boot image * from NAND into SDRAM and starts from there. @@ -221,16 +237,17 @@ void nand_boot(void) /* * Load U-Boot image from NAND into RAM */ - nand_load(CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE, - (uchar *)CONFIG_SYS_NAND_U_BOOT_DST); + nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS, + CONFIG_SYS_NAND_U_BOOT_SIZE, + (uchar *)CONFIG_SYS_NAND_U_BOOT_DST); #ifdef CONFIG_NAND_ENV_DST - nand_load(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, - (uchar *)CONFIG_NAND_ENV_DST); + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_NAND_ENV_DST); #ifdef CONFIG_ENV_OFFSET_REDUND - nand_load(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE, - (uchar *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE); + nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE, + (uchar *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE); #endif #endif /* diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index 790d538..389c4de 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -933,6 +933,7 @@ int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength) mtd = &nand_info[nand_curr_device]; nand = mtd->priv; nand->options |= NAND_OWN_BUFFERS; + nand->options &= ~NAND_SUBPAGE_READ; /* Setup the ecc configurations again */ if (hardware) { if (eccstrength == 1) { diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile index 26483a2..9e18fb4 100644 --- a/drivers/mtd/spi/Makefile +++ b/drivers/mtd/spi/Makefile @@ -10,8 +10,8 @@ obj-$(CONFIG_SPL_SPI_LOAD) += spi_spl_load.o obj-$(CONFIG_SPL_SPI_BOOT) += fsl_espi_spl.o endif -obj-$(CONFIG_CMD_SF) += sf.o -obj-$(CONFIG_SPI_FLASH) += sf_probe.o sf_ops.o +obj-$(CONFIG_CMD_SF) += sf.o +obj-$(CONFIG_SPI_FLASH) += sf_params.o sf_probe.o sf_ops.o obj-$(CONFIG_SPI_FRAM_RAMTRON) += ramtron.o obj-$(CONFIG_SPI_FLASH_SANDBOX) += sandbox.o obj-$(CONFIG_SPI_M95XXX) += eeprom_m95xxx.o diff --git a/drivers/mtd/spi/sf.c b/drivers/mtd/spi/sf.c index d5e175c..664e860 100644 --- a/drivers/mtd/spi/sf.c +++ b/drivers/mtd/spi/sf.c @@ -18,6 +18,10 @@ static int spi_flash_read_write(struct spi_slave *spi, unsigned long flags = SPI_XFER_BEGIN; int ret; +#ifdef CONFIG_SF_DUAL_FLASH + if (spi->flags & SPI_XFER_U_PAGE) + flags |= SPI_XFER_U_PAGE; +#endif if (data_len == 0) flags |= SPI_XFER_END; diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index d291746..6bcd522 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -10,12 +10,15 @@ #ifndef _SF_INTERNAL_H_ #define _SF_INTERNAL_H_ +#define SPI_FLASH_3B_ADDR_LEN 3 +#define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN) #define SPI_FLASH_16MB_BOUN 0x1000000 -/* SECT flags */ -#define SECT_4K (1 << 1) -#define SECT_32K (1 << 2) -#define E_FSR (1 << 3) +/* CFI Manufacture ID's */ +#define SPI_FLASH_CFI_MFR_SPANSION 0x01 +#define SPI_FLASH_CFI_MFR_STMICRO 0x20 +#define SPI_FLASH_CFI_MFR_MACRONIX 0xc2 +#define SPI_FLASH_CFI_MFR_WINBOND 0xef /* Erase commands */ #define CMD_ERASE_4K 0x20 @@ -28,6 +31,7 @@ #define CMD_PAGE_PROGRAM 0x02 #define CMD_WRITE_DISABLE 0x04 #define CMD_READ_STATUS 0x05 +#define CMD_QUAD_PAGE_PROGRAM 0x32 #define CMD_READ_STATUS1 0x35 #define CMD_WRITE_ENABLE 0x06 #define CMD_READ_CONFIG 0x35 @@ -36,6 +40,10 @@ /* Read commands */ #define CMD_READ_ARRAY_SLOW 0x03 #define CMD_READ_ARRAY_FAST 0x0b +#define CMD_READ_DUAL_OUTPUT_FAST 0x3b +#define CMD_READ_DUAL_IO_FAST 0xbb +#define CMD_READ_QUAD_OUTPUT_FAST 0x6b +#define CMD_READ_QUAD_IO_FAST 0xeb #define CMD_READ_ID 0x9f /* Bank addr access commands */ @@ -47,8 +55,10 @@ #endif /* Common status */ -#define STATUS_WIP 0x01 -#define STATUS_PEC 0x80 +#define STATUS_WIP (1 << 0) +#define STATUS_QEB_WINSPAN (1 << 1) +#define STATUS_QEB_MXIC (1 << 6) +#define STATUS_PEC (1 << 7) /* Flash timeout values */ #define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ) @@ -86,11 +96,17 @@ int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len, /* Flash erase(sectors) operation, support all possible erase commands */ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len); +/* Read the status register */ +int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs); + /* Program the status register */ -int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr); +int spi_flash_cmd_write_status(struct spi_flash *flash, u8 ws); + +/* Read the config register */ +int spi_flash_cmd_read_config(struct spi_flash *flash, u8 *rc); -/* Set quad enbale bit */ -int spi_flash_set_qeb(struct spi_flash *flash); +/* Program the config register */ +int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc); /* Enable writing on the SPI flash */ static inline int spi_flash_cmd_write_enable(struct spi_flash *flash) diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c index e316a69..1f1bb36 100644 --- a/drivers/mtd/spi/sf_ops.c +++ b/drivers/mtd/spi/sf_ops.c @@ -9,6 +9,7 @@ */ #include <common.h> +#include <malloc.h> #include <spi.h> #include <spi_flash.h> #include <watchdog.h> @@ -23,13 +24,28 @@ static void spi_flash_addr(u32 addr, u8 *cmd) cmd[3] = addr >> 0; } -int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr) +int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs) +{ + int ret; + u8 cmd; + + cmd = CMD_READ_STATUS; + ret = spi_flash_read_common(flash, &cmd, 1, rs, 1); + if (ret < 0) { + debug("SF: fail to read status register\n"); + return ret; + } + + return 0; +} + +int spi_flash_cmd_write_status(struct spi_flash *flash, u8 ws) { u8 cmd; int ret; cmd = CMD_WRITE_STATUS; - ret = spi_flash_write_common(flash, &cmd, 1, &sr, 1); + ret = spi_flash_write_common(flash, &cmd, 1, &ws, 1); if (ret < 0) { debug("SF: fail to write status register\n"); return ret; @@ -38,6 +54,44 @@ int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr) return 0; } +#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) +int spi_flash_cmd_read_config(struct spi_flash *flash, u8 *rc) +{ + int ret; + u8 cmd; + + cmd = CMD_READ_CONFIG; + ret = spi_flash_read_common(flash, &cmd, 1, rc, 1); + if (ret < 0) { + debug("SF: fail to read config register\n"); + return ret; + } + + return 0; +} + +int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc) +{ + u8 data[2]; + u8 cmd; + int ret; + + ret = spi_flash_cmd_read_status(flash, &data[0]); + if (ret < 0) + return ret; + + cmd = CMD_WRITE_STATUS; + data[1] = wc; + ret = spi_flash_write_common(flash, &cmd, 1, &data, 2); + if (ret) { + debug("SF: fail to write config register\n"); + return ret; + } + + return 0; +} +#endif + #ifdef CONFIG_SPI_FLASH_BAR static int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel) { @@ -65,7 +119,7 @@ static int spi_flash_bank(struct spi_flash *flash, u32 offset) u8 bank_sel; int ret; - bank_sel = offset / SPI_FLASH_16MB_BOUN; + bank_sel = offset / (SPI_FLASH_16MB_BOUN << flash->shift); ret = spi_flash_cmd_bankaddr_write(flash, bank_sel); if (ret) { @@ -73,7 +127,29 @@ static int spi_flash_bank(struct spi_flash *flash, u32 offset) return ret; } - return 0; + return bank_sel; +} +#endif + +#ifdef CONFIG_SF_DUAL_FLASH +static void spi_flash_dual_flash(struct spi_flash *flash, u32 *addr) +{ + switch (flash->dual_flash) { + case SF_DUAL_STACKED_FLASH: + if (*addr >= (flash->size >> 1)) { + *addr -= flash->size >> 1; + flash->spi->flags |= SPI_XFER_U_PAGE; + } else { + flash->spi->flags &= ~SPI_XFER_U_PAGE; + } + break; + case SF_DUAL_PARALLEL_FLASH: + *addr >>= flash->shift; + break; + default: + debug("SF: Unsupported dual_flash=%d\n", flash->dual_flash); + break; + } } #endif @@ -81,6 +157,7 @@ int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout) { struct spi_slave *spi = flash->spi; unsigned long timebase; + unsigned long flags = SPI_XFER_BEGIN; int ret; u8 status; u8 check_status = 0x0; @@ -92,7 +169,11 @@ int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout) check_status = poll_bit; } - ret = spi_xfer(spi, 8, &cmd, NULL, SPI_XFER_BEGIN); +#ifdef CONFIG_SF_DUAL_FLASH + if (spi->flags & SPI_XFER_U_PAGE) + flags |= SPI_XFER_U_PAGE; +#endif + ret = spi_xfer(spi, 8, &cmd, NULL, flags); if (ret) { debug("SF: fail to read %s status register\n", cmd == CMD_READ_STATUS ? "read" : "flag"); @@ -165,8 +246,8 @@ int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd, int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len) { - u32 erase_size; - u8 cmd[4]; + u32 erase_size, erase_addr; + u8 cmd[SPI_FLASH_CMD_LEN]; int ret = -1; erase_size = flash->erase_size; @@ -177,15 +258,21 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len) cmd[0] = flash->erase_cmd; while (len) { + erase_addr = offset; + +#ifdef CONFIG_SF_DUAL_FLASH + if (flash->dual_flash > SF_SINGLE_FLASH) + spi_flash_dual_flash(flash, &erase_addr); +#endif #ifdef CONFIG_SPI_FLASH_BAR - ret = spi_flash_bank(flash, offset); + ret = spi_flash_bank(flash, erase_addr); if (ret < 0) return ret; #endif - spi_flash_addr(offset, cmd); + spi_flash_addr(erase_addr, cmd); debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1], - cmd[2], cmd[3], offset); + cmd[2], cmd[3], erase_addr); ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0); if (ret < 0) { @@ -204,16 +291,23 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, size_t len, const void *buf) { unsigned long byte_addr, page_size; + u32 write_addr; size_t chunk_len, actual; - u8 cmd[4]; + u8 cmd[SPI_FLASH_CMD_LEN]; int ret = -1; page_size = flash->page_size; - cmd[0] = CMD_PAGE_PROGRAM; + cmd[0] = flash->write_cmd; for (actual = 0; actual < len; actual += chunk_len) { + write_addr = offset; + +#ifdef CONFIG_SF_DUAL_FLASH + if (flash->dual_flash > SF_SINGLE_FLASH) + spi_flash_dual_flash(flash, &write_addr); +#endif #ifdef CONFIG_SPI_FLASH_BAR - ret = spi_flash_bank(flash, offset); + ret = spi_flash_bank(flash, write_addr); if (ret < 0) return ret; #endif @@ -223,9 +317,9 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, if (flash->spi->max_write_size) chunk_len = min(chunk_len, flash->spi->max_write_size); - spi_flash_addr(offset, cmd); + spi_flash_addr(write_addr, cmd); - debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n", + debug("SF: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); ret = spi_flash_write_common(flash, cmd, sizeof(cmd), @@ -267,8 +361,9 @@ int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, size_t len, void *data) { - u8 cmd[5], bank_sel = 0; - u32 remain_len, read_len; + u8 *cmd, cmdsz; + u32 remain_len, read_len, read_addr; + int bank_sel = 0; int ret = -1; /* Handle memory-mapped SPI */ @@ -285,29 +380,33 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, return 0; } - cmd[0] = CMD_READ_ARRAY_FAST; - cmd[4] = 0x00; + cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte; + cmd = malloc(cmdsz); + memset(cmd, 0, cmdsz); + cmd[0] = flash->read_cmd; while (len) { -#ifdef CONFIG_SPI_FLASH_BAR - bank_sel = offset / SPI_FLASH_16MB_BOUN; + read_addr = offset; - ret = spi_flash_cmd_bankaddr_write(flash, bank_sel); - if (ret) { - debug("SF: fail to set bank%d\n", bank_sel); +#ifdef CONFIG_SF_DUAL_FLASH + if (flash->dual_flash > SF_SINGLE_FLASH) + spi_flash_dual_flash(flash, &read_addr); +#endif +#ifdef CONFIG_SPI_FLASH_BAR + bank_sel = spi_flash_bank(flash, read_addr); + if (bank_sel < 0) return ret; - } #endif - remain_len = (SPI_FLASH_16MB_BOUN * (bank_sel + 1)) - offset; + remain_len = ((SPI_FLASH_16MB_BOUN << flash->shift) * + (bank_sel + 1)) - offset; if (len < remain_len) read_len = len; else read_len = remain_len; - spi_flash_addr(offset, cmd); + spi_flash_addr(read_addr, cmd); - ret = spi_flash_read_common(flash, cmd, sizeof(cmd), - data, read_len); + ret = spi_flash_read_common(flash, cmd, cmdsz, data, read_len); if (ret < 0) { debug("SF: read failed\n"); break; diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c new file mode 100644 index 0000000..daf8fe7 --- /dev/null +++ b/drivers/mtd/spi/sf_params.c @@ -0,0 +1,130 @@ +/* + * SPI flash Params table + * + * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <spi_flash.h> + +#include "sf_internal.h" + +/* SPI/QSPI flash device params structure */ +const struct spi_flash_params spi_flash_params_table[] = { +#ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */ + {"AT45DB011D", 0x1f2200, 0x0, 64 * 1024, 4, 0, SECT_4K}, + {"AT45DB021D", 0x1f2300, 0x0, 64 * 1024, 8, 0, SECT_4K}, + {"AT45DB041D", 0x1f2400, 0x0, 64 * 1024, 8, 0, SECT_4K}, + {"AT45DB081D", 0x1f2500, 0x0, 64 * 1024, 16, 0, SECT_4K}, + {"AT45DB161D", 0x1f2600, 0x0, 64 * 1024, 32, 0, SECT_4K}, + {"AT45DB321D", 0x1f2700, 0x0, 64 * 1024, 64, 0, SECT_4K}, + {"AT45DB641D", 0x1f2800, 0x0, 64 * 1024, 128, 0, SECT_4K}, + {"AT25DF321", 0x1f4701, 0x0, 64 * 1024, 64, 0, SECT_4K}, +#endif +#ifdef CONFIG_SPI_FLASH_EON /* EON */ + {"EN25Q32B", 0x1c3016, 0x0, 64 * 1024, 64, 0, 0}, + {"EN25Q64", 0x1c3017, 0x0, 64 * 1024, 128, 0, SECT_4K}, + {"EN25Q128B", 0x1c3018, 0x0, 64 * 1024, 256, 0, 0}, + {"EN25S64", 0x1c3817, 0x0, 64 * 1024, 128, 0, 0}, +#endif +#ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */ + {"GD25Q64B", 0xc84017, 0x0, 64 * 1024, 128, 0, SECT_4K}, + {"GD25LQ32", 0xc86016, 0x0, 64 * 1024, 64, 0, SECT_4K}, +#endif +#ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */ + {"MX25L2006E", 0xc22012, 0x0, 64 * 1024, 4, 0, 0}, + {"MX25L4005", 0xc22013, 0x0, 64 * 1024, 8, 0, 0}, + {"MX25L8005", 0xc22014, 0x0, 64 * 1024, 16, 0, 0}, + {"MX25L1605D", 0xc22015, 0x0, 64 * 1024, 32, 0, 0}, + {"MX25L3205D", 0xc22016, 0x0, 64 * 1024, 64, 0, 0}, + {"MX25L6405D", 0xc22017, 0x0, 64 * 1024, 128, 0, 0}, + {"MX25L12805", 0xc22018, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP}, + {"MX25L25635F", 0xc22019, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP}, + {"MX25L51235F", 0xc2201a, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP}, + {"MX25L12855E", 0xc22618, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP}, +#endif +#ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */ + {"S25FL008A", 0x010213, 0x0, 64 * 1024, 16, 0, 0}, + {"S25FL016A", 0x010214, 0x0, 64 * 1024, 32, 0, 0}, + {"S25FL032A", 0x010215, 0x0, 64 * 1024, 64, 0, 0}, + {"S25FL064A", 0x010216, 0x0, 64 * 1024, 128, 0, 0}, + {"S25FL128P_256K", 0x012018, 0x0300, 256 * 1024, 64, RD_FULL, WR_QPP}, + {"S25FL128P_64K", 0x012018, 0x0301, 64 * 1024, 256, RD_FULL, WR_QPP}, + {"S25FL032P", 0x010215, 0x4d00, 64 * 1024, 64, RD_FULL, WR_QPP}, + {"S25FL064P", 0x010216, 0x4d00, 64 * 1024, 128, RD_FULL, WR_QPP}, + {"S25FL128S_64K", 0x012018, 0x4d01, 64 * 1024, 256, RD_FULL, WR_QPP}, + {"S25FL256S_256K", 0x010219, 0x4d00, 64 * 1024, 512, RD_FULL, WR_QPP}, + {"S25FL256S_64K", 0x010219, 0x4d01, 64 * 1024, 512, RD_FULL, WR_QPP}, + {"S25FL512S_256K", 0x010220, 0x4d00, 64 * 1024, 1024, RD_FULL, WR_QPP}, + {"S25FL512S_64K", 0x010220, 0x4d01, 64 * 1024, 1024, RD_FULL, WR_QPP}, +#endif +#ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */ + {"M25P10", 0x202011, 0x0, 32 * 1024, 4, 0, 0}, + {"M25P20", 0x202012, 0x0, 64 * 1024, 4, 0, 0}, + {"M25P40", 0x202013, 0x0, 64 * 1024, 8, 0, 0}, + {"M25P80", 0x202014, 0x0, 64 * 1024, 16, 0, 0}, + {"M25P16", 0x202015, 0x0, 64 * 1024, 32, 0, 0}, + {"M25P32", 0x202016, 0x0, 64 * 1024, 64, 0, 0}, + {"M25P64", 0x202017, 0x0, 64 * 1024, 128, 0, 0}, + {"M25P128", 0x202018, 0x0, 256 * 1024, 64, 0, 0}, + {"N25Q32", 0x20ba16, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K}, + {"N25Q32A", 0x20bb16, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K}, + {"N25Q64", 0x20ba17, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K}, + {"N25Q64A", 0x20bb17, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K}, + {"N25Q128", 0x20ba18, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP}, + {"N25Q128A", 0x20bb18, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP}, + {"N25Q256", 0x20ba19, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP | SECT_4K}, + {"N25Q256A", 0x20bb19, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP | SECT_4K}, + {"N25Q512", 0x20ba20, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP | E_FSR | SECT_4K}, + {"N25Q512A", 0x20bb20, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP | E_FSR | SECT_4K}, + {"N25Q1024", 0x20ba21, 0x0, 64 * 1024, 2048, RD_FULL, WR_QPP | E_FSR | SECT_4K}, + {"N25Q1024A", 0x20bb21, 0x0, 64 * 1024, 2048, RD_FULL, WR_QPP | E_FSR | SECT_4K}, +#endif +#ifdef CONFIG_SPI_FLASH_SST /* SST */ + {"SST25VF040B", 0xbf258d, 0x0, 64 * 1024, 8, 0, SECT_4K | SST_WP}, + {"SST25VF080B", 0xbf258e, 0x0, 64 * 1024, 16, 0, SECT_4K | SST_WP}, + {"SST25VF016B", 0xbf2541, 0x0, 64 * 1024, 32, 0, SECT_4K | SST_WP}, + {"SST25VF032B", 0xbf254a, 0x0, 64 * 1024, 64, 0, SECT_4K | SST_WP}, + {"SST25VF064C", 0xbf254b, 0x0, 64 * 1024, 128, 0, SECT_4K}, + {"SST25WF512", 0xbf2501, 0x0, 64 * 1024, 1, 0, SECT_4K | SST_WP}, + {"SST25WF010", 0xbf2502, 0x0, 64 * 1024, 2, 0, SECT_4K | SST_WP}, + {"SST25WF020", 0xbf2503, 0x0, 64 * 1024, 4, 0, SECT_4K | SST_WP}, + {"SST25WF040", 0xbf2504, 0x0, 64 * 1024, 8, 0, SECT_4K | SST_WP}, + {"SST25WF080", 0xbf2505, 0x0, 64 * 1024, 16, 0, SECT_4K | SST_WP}, +#endif +#ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */ + {"W25P80", 0xef2014, 0x0, 64 * 1024, 16, 0, 0}, + {"W25P16", 0xef2015, 0x0, 64 * 1024, 32, 0, 0}, + {"W25P32", 0xef2016, 0x0, 64 * 1024, 64, 0, 0}, + {"W25X40", 0xef3013, 0x0, 64 * 1024, 8, 0, SECT_4K}, + {"W25X16", 0xef3015, 0x0, 64 * 1024, 32, 0, SECT_4K}, + {"W25X32", 0xef3016, 0x0, 64 * 1024, 64, 0, SECT_4K}, + {"W25X64", 0xef3017, 0x0, 64 * 1024, 128, 0, SECT_4K}, + {"W25Q80BL", 0xef4014, 0x0, 64 * 1024, 16, RD_FULL, WR_QPP | SECT_4K}, + {"W25Q16CL", 0xef4015, 0x0, 64 * 1024, 32, RD_FULL, WR_QPP | SECT_4K}, + {"W25Q32BV", 0xef4016, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K}, + {"W25Q64CV", 0xef4017, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K}, + {"W25Q128BV", 0xef4018, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP | SECT_4K}, + {"W25Q256", 0xef4019, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP | SECT_4K}, + {"W25Q80BW", 0xef5014, 0x0, 64 * 1024, 16, RD_FULL, WR_QPP | SECT_4K}, + {"W25Q16DW", 0xef6015, 0x0, 64 * 1024, 32, RD_FULL, WR_QPP | SECT_4K}, + {"W25Q32DW", 0xef6016, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K}, + {"W25Q64DW", 0xef6017, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K}, + {"W25Q128FW", 0xef6018, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP | SECT_4K}, +#endif + /* + * Note: + * Below paired flash devices has similar spi_flash params. + * (S25FL129P_64K, S25FL128S_64K) + * (W25Q80BL, W25Q80BV) + * (W25Q16CL, W25Q16DV) + * (W25Q32BV, W25Q32FV_SPI) + * (W25Q64CV, W25Q64FV_SPI) + * (W25Q128BV, W25Q128FV_SPI) + * (W25Q32DW, W25Q32FV_QPI) + * (W25Q64DW, W25Q64FV_QPI) + * (W25Q128FW, W25Q128FV_QPI) + */ +}; diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c index b863a98..bc3cf6c 100644 --- a/drivers/mtd/spi/sf_probe.c +++ b/drivers/mtd/spi/sf_probe.c @@ -19,154 +19,93 @@ DECLARE_GLOBAL_DATA_PTR; -/** - * struct spi_flash_params - SPI/QSPI flash device params structure - * - * @name: Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO]) - * @jedec: Device jedec ID (0x[1byte_manuf_id][2byte_dev_id]) - * @ext_jedec: Device ext_jedec ID - * @sector_size: Sector size of this device - * @nr_sectors: No.of sectors on this device - * @flags: Importent param, for flash specific behaviour - */ -struct spi_flash_params { - const char *name; - u32 jedec; - u16 ext_jedec; - u32 sector_size; - u32 nr_sectors; - u16 flags; +/* Read commands array */ +static u8 spi_read_cmds_array[] = { + CMD_READ_ARRAY_SLOW, + CMD_READ_DUAL_OUTPUT_FAST, + CMD_READ_DUAL_IO_FAST, + CMD_READ_QUAD_OUTPUT_FAST, + CMD_READ_QUAD_IO_FAST, }; -static const struct spi_flash_params spi_flash_params_table[] = { -#ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */ - {"AT45DB011D", 0x1f2200, 0x0, 64 * 1024, 4, SECT_4K}, - {"AT45DB021D", 0x1f2300, 0x0, 64 * 1024, 8, SECT_4K}, - {"AT45DB041D", 0x1f2400, 0x0, 64 * 1024, 8, SECT_4K}, - {"AT45DB081D", 0x1f2500, 0x0, 64 * 1024, 16, SECT_4K}, - {"AT45DB161D", 0x1f2600, 0x0, 64 * 1024, 32, SECT_4K}, - {"AT45DB321D", 0x1f2700, 0x0, 64 * 1024, 64, SECT_4K}, - {"AT45DB641D", 0x1f2800, 0x0, 64 * 1024, 128, SECT_4K}, - {"AT25DF321", 0x1f4701, 0x0, 64 * 1024, 64, SECT_4K}, -#endif -#ifdef CONFIG_SPI_FLASH_EON /* EON */ - {"EN25Q32B", 0x1c3016, 0x0, 64 * 1024, 64, 0}, - {"EN25Q64", 0x1c3017, 0x0, 64 * 1024, 128, SECT_4K}, - {"EN25Q128B", 0x1c3018, 0x0, 64 * 1024, 256, 0}, - {"EN25S64", 0x1c3817, 0x0, 64 * 1024, 128, 0}, -#endif -#ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */ - {"GD25Q64B", 0xc84017, 0x0, 64 * 1024, 128, SECT_4K}, - {"GD25LQ32", 0xc86016, 0x0, 64 * 1024, 64, SECT_4K}, -#endif -#ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */ - {"MX25L2006E", 0xc22012, 0x0, 64 * 1024, 4, 0}, - {"MX25L4005", 0xc22013, 0x0, 64 * 1024, 8, 0}, - {"MX25L8005", 0xc22014, 0x0, 64 * 1024, 16, 0}, - {"MX25L1605D", 0xc22015, 0x0, 64 * 1024, 32, 0}, - {"MX25L3205D", 0xc22016, 0x0, 64 * 1024, 64, 0}, - {"MX25L6405D", 0xc22017, 0x0, 64 * 1024, 128, 0}, - {"MX25L12805", 0xc22018, 0x0, 64 * 1024, 256, 0}, - {"MX25L25635F", 0xc22019, 0x0, 64 * 1024, 512, 0}, - {"MX25L51235F", 0xc2201a, 0x0, 64 * 1024, 1024, 0}, - {"MX25L12855E", 0xc22618, 0x0, 64 * 1024, 256, 0}, +#ifdef CONFIG_SPI_FLASH_MACRONIX +static int spi_flash_set_qeb_mxic(struct spi_flash *flash) +{ + u8 qeb_status; + int ret; + + ret = spi_flash_cmd_read_status(flash, &qeb_status); + if (ret < 0) + return ret; + + if (qeb_status & STATUS_QEB_MXIC) { + debug("SF: mxic: QEB is already set\n"); + } else { + ret = spi_flash_cmd_write_status(flash, STATUS_QEB_MXIC); + if (ret < 0) + return ret; + } + + return ret; +} #endif -#ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */ - {"S25FL008A", 0x010213, 0x0, 64 * 1024, 16, 0}, - {"S25FL016A", 0x010214, 0x0, 64 * 1024, 32, 0}, - {"S25FL032A", 0x010215, 0x0, 64 * 1024, 64, 0}, - {"S25FL064A", 0x010216, 0x0, 64 * 1024, 128, 0}, - {"S25FL128P_256K", 0x012018, 0x0300, 256 * 1024, 64, 0}, - {"S25FL128P_64K", 0x012018, 0x0301, 64 * 1024, 256, 0}, - {"S25FL032P", 0x010215, 0x4d00, 64 * 1024, 64, 0}, - {"S25FL064P", 0x010216, 0x4d00, 64 * 1024, 128, 0}, - {"S25FL128S_64K", 0x012018, 0x4d01, 64 * 1024, 256, 0}, - {"S25FL256S_256K", 0x010219, 0x4d00, 64 * 1024, 512, 0}, - {"S25FL256S_64K", 0x010219, 0x4d01, 64 * 1024, 512, 0}, - {"S25FL512S_256K", 0x010220, 0x4d00, 64 * 1024, 1024, 0}, - {"S25FL512S_64K", 0x010220, 0x4d01, 64 * 1024, 1024, 0}, + +#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) +static int spi_flash_set_qeb_winspan(struct spi_flash *flash) +{ + u8 qeb_status; + int ret; + + ret = spi_flash_cmd_read_config(flash, &qeb_status); + if (ret < 0) + return ret; + + if (qeb_status & STATUS_QEB_WINSPAN) { + debug("SF: winspan: QEB is already set\n"); + } else { + ret = spi_flash_cmd_write_config(flash, STATUS_QEB_WINSPAN); + if (ret < 0) + return ret; + } + + return ret; +} #endif -#ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */ - {"M25P10", 0x202011, 0x0, 32 * 1024, 4, 0}, - {"M25P20", 0x202012, 0x0, 64 * 1024, 4, 0}, - {"M25P40", 0x202013, 0x0, 64 * 1024, 8, 0}, - {"M25P80", 0x202014, 0x0, 64 * 1024, 16, 0}, - {"M25P16", 0x202015, 0x0, 64 * 1024, 32, 0}, - {"M25P32", 0x202016, 0x0, 64 * 1024, 64, 0}, - {"M25P64", 0x202017, 0x0, 64 * 1024, 128, 0}, - {"M25P128", 0x202018, 0x0, 256 * 1024, 64, 0}, - {"N25Q32", 0x20ba16, 0x0, 64 * 1024, 64, SECT_4K}, - {"N25Q32A", 0x20bb16, 0x0, 64 * 1024, 64, SECT_4K}, - {"N25Q64", 0x20ba17, 0x0, 64 * 1024, 128, SECT_4K}, - {"N25Q64A", 0x20bb17, 0x0, 64 * 1024, 128, SECT_4K}, - {"N25Q128", 0x20ba18, 0x0, 64 * 1024, 256, SECT_4K}, - {"N25Q128A", 0x20bb18, 0x0, 64 * 1024, 256, SECT_4K}, - {"N25Q256", 0x20ba19, 0x0, 64 * 1024, 512, SECT_4K}, - {"N25Q256A", 0x20bb19, 0x0, 64 * 1024, 512, SECT_4K}, - {"N25Q512", 0x20ba20, 0x0, 64 * 1024, 1024, E_FSR | SECT_4K}, - {"N25Q512A", 0x20bb20, 0x0, 64 * 1024, 1024, E_FSR | SECT_4K}, - {"N25Q1024", 0x20ba21, 0x0, 64 * 1024, 2048, E_FSR | SECT_4K}, - {"N25Q1024A", 0x20bb21, 0x0, 64 * 1024, 2048, E_FSR | SECT_4K}, + +static int spi_flash_set_qeb(struct spi_flash *flash, u8 idcode0) +{ + switch (idcode0) { +#ifdef CONFIG_SPI_FLASH_MACRONIX + case SPI_FLASH_CFI_MFR_MACRONIX: + return spi_flash_set_qeb_mxic(flash); #endif -#ifdef CONFIG_SPI_FLASH_SST /* SST */ - {"SST25VF040B", 0xbf258d, 0x0, 64 * 1024, 8, SECT_4K | SST_WP}, - {"SST25VF080B", 0xbf258e, 0x0, 64 * 1024, 16, SECT_4K | SST_WP}, - {"SST25VF016B", 0xbf2541, 0x0, 64 * 1024, 32, SECT_4K | SST_WP}, - {"SST25VF032B", 0xbf254a, 0x0, 64 * 1024, 64, SECT_4K | SST_WP}, - {"SST25VF064C", 0xbf254b, 0x0, 64 * 1024, 128, SECT_4K}, - {"SST25WF512", 0xbf2501, 0x0, 64 * 1024, 1, SECT_4K | SST_WP}, - {"SST25WF010", 0xbf2502, 0x0, 64 * 1024, 2, SECT_4K | SST_WP}, - {"SST25WF020", 0xbf2503, 0x0, 64 * 1024, 4, SECT_4K | SST_WP}, - {"SST25WF040", 0xbf2504, 0x0, 64 * 1024, 8, SECT_4K | SST_WP}, - {"SST25WF080", 0xbf2505, 0x0, 64 * 1024, 16, SECT_4K | SST_WP}, +#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) + case SPI_FLASH_CFI_MFR_SPANSION: + case SPI_FLASH_CFI_MFR_WINBOND: + return spi_flash_set_qeb_winspan(flash); #endif -#ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */ - {"W25P80", 0xef2014, 0x0, 64 * 1024, 16, 0}, - {"W25P16", 0xef2015, 0x0, 64 * 1024, 32, 0}, - {"W25P32", 0xef2016, 0x0, 64 * 1024, 64, 0}, - {"W25X40", 0xef3013, 0x0, 64 * 1024, 8, SECT_4K}, - {"W25X16", 0xef3015, 0x0, 64 * 1024, 32, SECT_4K}, - {"W25X32", 0xef3016, 0x0, 64 * 1024, 64, SECT_4K}, - {"W25X64", 0xef3017, 0x0, 64 * 1024, 128, SECT_4K}, - {"W25Q80BL", 0xef4014, 0x0, 64 * 1024, 16, SECT_4K}, - {"W25Q16CL", 0xef4015, 0x0, 64 * 1024, 32, SECT_4K}, - {"W25Q32BV", 0xef4016, 0x0, 64 * 1024, 64, SECT_4K}, - {"W25Q64CV", 0xef4017, 0x0, 64 * 1024, 128, SECT_4K}, - {"W25Q128BV", 0xef4018, 0x0, 64 * 1024, 256, SECT_4K}, - {"W25Q256", 0xef4019, 0x0, 64 * 1024, 512, SECT_4K}, - {"W25Q80BW", 0xef5014, 0x0, 64 * 1024, 16, SECT_4K}, - {"W25Q16DW", 0xef6015, 0x0, 64 * 1024, 32, SECT_4K}, - {"W25Q32DW", 0xef6016, 0x0, 64 * 1024, 64, SECT_4K}, - {"W25Q64DW", 0xef6017, 0x0, 64 * 1024, 128, SECT_4K}, - {"W25Q128FW", 0xef6018, 0x0, 64 * 1024, 256, SECT_4K}, +#ifdef CONFIG_SPI_FLASH_STMICRO + case SPI_FLASH_CFI_MFR_STMICRO: + debug("SF: QEB is volatile for %02x flash\n", idcode0); + return 0; #endif - /* - * Note: - * Below paired flash devices has similar spi_flash params. - * (S25FL129P_64K, S25FL128S_64K) - * (W25Q80BL, W25Q80BV) - * (W25Q16CL, W25Q16DV) - * (W25Q32BV, W25Q32FV_SPI) - * (W25Q64CV, W25Q64FV_SPI) - * (W25Q128BV, W25Q128FV_SPI) - * (W25Q32DW, W25Q32FV_QPI) - * (W25Q64DW, W25Q64FV_QPI) - * (W25Q128FW, W25Q128FV_QPI) - */ -}; + default: + printf("SF: Need set QEB func for %02x flash\n", idcode0); + return -1; + } +} static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi, u8 *idcode) { const struct spi_flash_params *params; struct spi_flash *flash; - int i; + u8 cmd; u16 jedec = idcode[1] << 8 | idcode[2]; u16 ext_jedec = idcode[3] << 8 | idcode[4]; - /* Get the flash id (jedec = manuf_id + dev_id, ext_jedec) */ - for (i = 0; i < ARRAY_SIZE(spi_flash_params_table); i++) { - params = &spi_flash_params_table[i]; + params = spi_flash_params_table; + for (; params->name != NULL; params++) { if ((params->jedec >> 16) == idcode[0]) { if ((params->jedec & 0xFFFF) == jedec) { if (params->ext_jedec == 0) @@ -177,7 +116,7 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi, } } - if (i == ARRAY_SIZE(spi_flash_params_table)) { + if (!params->name) { printf("SF: Unsupported flash IDs: "); printf("manuf %02x, jedec %04x, ext_jedec %04x\n", idcode[0], jedec, ext_jedec); @@ -195,6 +134,7 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi, flash->spi = spi; flash->name = params->name; flash->memory_map = spi->memory_map; + flash->dual_flash = flash->spi->option; /* Assign spi_flash ops */ flash->write = spi_flash_cmd_write_ops; @@ -206,23 +146,74 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi, flash->read = spi_flash_cmd_read_ops; /* Compute the flash size */ - flash->page_size = (ext_jedec == 0x4d00) ? 512 : 256; - flash->sector_size = params->sector_size; - flash->size = flash->sector_size * params->nr_sectors; + flash->shift = (flash->dual_flash & SF_DUAL_PARALLEL_FLASH) ? 1 : 0; + flash->page_size = ((ext_jedec == 0x4d00) ? 512 : 256) << flash->shift; + flash->sector_size = params->sector_size << flash->shift; + flash->size = flash->sector_size * params->nr_sectors << flash->shift; +#ifdef CONFIG_SF_DUAL_FLASH + if (flash->dual_flash & SF_DUAL_STACKED_FLASH) + flash->size <<= 1; +#endif /* Compute erase sector and command */ if (params->flags & SECT_4K) { flash->erase_cmd = CMD_ERASE_4K; - flash->erase_size = 4096; + flash->erase_size = 4096 << flash->shift; } else if (params->flags & SECT_32K) { flash->erase_cmd = CMD_ERASE_32K; - flash->erase_size = 32768; + flash->erase_size = 32768 << flash->shift; } else { flash->erase_cmd = CMD_ERASE_64K; flash->erase_size = flash->sector_size; } - /* Poll cmd seclection */ + /* Look for the fastest read cmd */ + cmd = fls(params->e_rd_cmd & flash->spi->op_mode_rx); + if (cmd) { + cmd = spi_read_cmds_array[cmd - 1]; + flash->read_cmd = cmd; + } else { + /* Go for default supported read cmd */ + flash->read_cmd = CMD_READ_ARRAY_FAST; + } + + /* Not require to look for fastest only two write cmds yet */ + if (params->flags & WR_QPP && flash->spi->op_mode_tx & SPI_OPM_TX_QPP) + flash->write_cmd = CMD_QUAD_PAGE_PROGRAM; + else + /* Go for default supported write cmd */ + flash->write_cmd = CMD_PAGE_PROGRAM; + + /* Set the quad enable bit - only for quad commands */ + if ((flash->read_cmd == CMD_READ_QUAD_OUTPUT_FAST) || + (flash->read_cmd == CMD_READ_QUAD_IO_FAST) || + (flash->write_cmd == CMD_QUAD_PAGE_PROGRAM)) { + if (spi_flash_set_qeb(flash, idcode[0])) { + debug("SF: Fail to set QEB for %02x\n", idcode[0]); + return NULL; + } + } + + /* Read dummy_byte: dummy byte is determined based on the + * dummy cycles of a particular command. + * Fast commands - dummy_byte = dummy_cycles/8 + * I/O commands- dummy_byte = (dummy_cycles * no.of lines)/8 + * For I/O commands except cmd[0] everything goes on no.of lines + * based on particular command but incase of fast commands except + * data all go on single line irrespective of command. + */ + switch (flash->read_cmd) { + case CMD_READ_QUAD_IO_FAST: + flash->dummy_byte = 2; + break; + case CMD_READ_ARRAY_SLOW: + flash->dummy_byte = 0; + break; + default: + flash->dummy_byte = 1; + } + + /* Poll cmd selection */ flash->poll_cmd = CMD_READ_STATUS; #ifdef CONFIG_SPI_FLASH_STMICRO if (params->flags & E_FSR) @@ -339,7 +330,10 @@ static struct spi_flash *spi_flash_probe_slave(struct spi_slave *spi) puts("\n"); #endif #ifndef CONFIG_SPI_FLASH_BAR - if (flash->size > SPI_FLASH_16MB_BOUN) { + if (((flash->dual_flash == SF_SINGLE_FLASH) && + (flash->size > SPI_FLASH_16MB_BOUN)) || + ((flash->dual_flash > SF_SINGLE_FLASH) && + (flash->size > SPI_FLASH_16MB_BOUN << 1))) { puts("SF: Warning - Only lower 16MiB accessible,"); puts(" Full access #define CONFIG_SPI_FLASH_BAR\n"); } diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c index 74c72d3f..cd787f4 100644 --- a/drivers/net/fm/init.c +++ b/drivers/net/fm/init.c @@ -276,64 +276,13 @@ static void ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop) "status", "disabled", strlen("disabled") + 1, 1); } -#ifdef CONFIG_SYS_FMAN_V3 -static int ft_fixup_xgec(void *blob, struct fm_eth_info *info) -{ - int off, i, ci; -#define FM1_10GEC3_RX_PORT_ADDR (CONFIG_SYS_CCSRBAR_PHYS + 0x488000) -#define FM1_10GEC3_TX_PORT_ADDR (CONFIG_SYS_CCSRBAR_PHYS + 0x4a8000) -#define FM1_10GEC3_MAC_ADDR (CONFIG_SYS_CCSRBAR_PHYS + 0x4e0000) - - if ((info->port == FM1_10GEC3) || (info->port == FM1_10GEC4)) { - ci = (info->port == FM1_10GEC3) ? 2 : 3; - i = (info->port == FM1_10GEC3) ? 0 : 1; - - off = fdt_node_offset_by_compat_reg(blob, "fsl,fman-port-1g-rx", - FM1_10GEC3_RX_PORT_ADDR + - i * 0x1000); - if (off > 0) { - fdt_setprop(blob, off, "cell-index", &ci, sizeof(int)); - fdt_setprop(blob, off, "compatible", - "fsl,fman-port-10g-rx", 20); - } else { - goto err; - } - - off = fdt_node_offset_by_compat_reg(blob, "fsl,fman-port-1g-tx", - FM1_10GEC3_TX_PORT_ADDR + - i * 0x1000); - if (off > 0) { - fdt_setprop(blob, off, "cell-index", &ci, sizeof(int)); - fdt_setprop(blob, off, "compatible", - "fsl,fman-port-10g-tx", 20); - } else { - goto err; - } - - off = fdt_node_offset_by_compat_reg(blob, "fsl,fman-memac", - FM1_10GEC3_MAC_ADDR + - i * 0x2000); - if (off > 0) - fdt_setprop(blob, off, "cell-index", &ci, sizeof(int)); - else - goto err; - } - return 0; -err: - printf("WARNING: Fail to find the node\n"); - return -1; -} -#endif - void fdt_fixup_fman_ethernet(void *blob) { int i; #ifdef CONFIG_SYS_FMAN_V3 - for (i = 0; i < ARRAY_SIZE(fm_info); i++) { + for (i = 0; i < ARRAY_SIZE(fm_info); i++) ft_fixup_port(blob, &fm_info[i], "fsl,fman-memac"); - ft_fixup_xgec(blob, &fm_info[i]); - } #else for (i = 0; i < ARRAY_SIZE(fm_info); i++) { if (fm_info[i].type == FM_ETH_1G_E) diff --git a/drivers/net/fm/t2080.c b/drivers/net/fm/t2080.c index b5c1e9f..3b6212f 100644 --- a/drivers/net/fm/t2080.c +++ b/drivers/net/fm/t2080.c @@ -50,15 +50,17 @@ phy_interface_t fman_port_enet_if(enum fm_port port) if (is_device_disabled(port)) return PHY_INTERFACE_MODE_NONE; - if ((port == FM1_10GEC1 || port == FM1_10GEC2 || - port == FM1_10GEC3 || port == FM1_10GEC4) && + if ((port == FM1_10GEC1 || port == FM1_10GEC2) && ((is_serdes_configured(XAUI_FM1_MAC9)) || - (is_serdes_configured(XFI_FM1_MAC1)) || - (is_serdes_configured(XFI_FM1_MAC2)) || (is_serdes_configured(XFI_FM1_MAC9)) || (is_serdes_configured(XFI_FM1_MAC10)))) return PHY_INTERFACE_MODE_XGMII; + if ((port == FM1_10GEC3 || port == FM1_10GEC4) && + ((is_serdes_configured(XFI_FM1_MAC1)) || + (is_serdes_configured(XFI_FM1_MAC2)))) + return PHY_INTERFACE_MODE_XGMII; + if ((port == FM1_DTSEC3) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII)) return PHY_INTERFACE_MODE_RGMII; diff --git a/drivers/net/nicext.h b/drivers/net/nicext.h deleted file mode 100644 index ff422e7..0000000 --- a/drivers/net/nicext.h +++ /dev/null @@ -1,109 +0,0 @@ -/**************************************************************************** - * Copyright(c) 2000-2001 Broadcom Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation. - * - * Name: nicext.h - * - * Description: Broadcom Network Interface Card Extension (NICE) is an - * extension to Linux NET device kernel mode drivers. - * NICE is designed to provide additional functionalities, - * such as receive packet intercept. To support Broadcom NICE, - * the network device driver can be modified by adding an - * device ioctl handler and by indicating receiving packets - * to the NICE receive handler. Broadcom NICE will only be - * enabled by a NICE-aware intermediate driver, such as - * Broadcom Advanced Server Program Driver (BASP). When NICE - * is not enabled, the modified network device drivers - * functions exactly as other non-NICE aware drivers. - * - * Author: Frankie Fan - * - * Created: September 17, 2000 - * - ****************************************************************************/ -#ifndef _nicext_h_ -#define _nicext_h_ - -/* - * ioctl for NICE - */ -#define SIOCNICE SIOCDEVPRIVATE+7 - -/* - * SIOCNICE: - * - * The following structure needs to be less than IFNAMSIZ (16 bytes) because - * we're overloading ifreq.ifr_ifru. - * - * If 16 bytes is not enough, we should consider relaxing this because - * this is no field after ifr_ifru in the ifreq structure. But we may - * run into future compatiability problem in case of changing struct ifreq. - */ -struct nice_req -{ - __u32 cmd; - - union - { -#ifdef __KERNEL__ - /* cmd = NICE_CMD_SET_RX or NICE_CMD_GET_RX */ - struct - { - void (*nrqus1_rx)( struct sk_buff*, void* ); - void* nrqus1_ctx; - } nrqu_nrqus1; - - /* cmd = NICE_CMD_QUERY_SUPPORT */ - struct - { - __u32 nrqus2_magic; - __u32 nrqus2_support_rx:1; - __u32 nrqus2_support_vlan:1; - __u32 nrqus2_support_get_speed:1; - } nrqu_nrqus2; -#endif - - /* cmd = NICE_CMD_GET_SPEED */ - struct - { - unsigned int nrqus3_speed; /* 0 if link is down, */ - /* otherwise speed in Mbps */ - } nrqu_nrqus3; - - /* cmd = NICE_CMD_BLINK_LED */ - struct - { - unsigned int nrqus4_blink_time; /* blink duration in seconds */ - } nrqu_nrqus4; - - } nrq_nrqu; -}; - -#define nrq_rx nrq_nrqu.nrqu_nrqus1.nrqus1_rx -#define nrq_ctx nrq_nrqu.nrqu_nrqus1.nrqus1_ctx -#define nrq_support_rx nrq_nrqu.nrqu_nrqus2.nrqus2_support_rx -#define nrq_magic nrq_nrqu.nrqu_nrqus2.nrqus2_magic -#define nrq_support_vlan nrq_nrqu.nrqu_nrqus2.nrqus2_support_vlan -#define nrq_support_get_speed nrq_nrqu.nrqu_nrqus2.nrqus2_support_get_speed -#define nrq_speed nrq_nrqu.nrqu_nrqus3.nrqus3_speed -#define nrq_blink_time nrq_nrqu.nrqu_nrqus4.nrqus4_blink_time - -/* - * magic constants - */ -#define NICE_REQUESTOR_MAGIC 0x4543494E /* NICE in ascii */ -#define NICE_DEVICE_MAGIC 0x4E494345 /* ECIN in ascii */ - -/* - * command field - */ -#define NICE_CMD_QUERY_SUPPORT 0x00000001 -#define NICE_CMD_SET_RX 0x00000002 -#define NICE_CMD_GET_RX 0x00000003 -#define NICE_CMD_GET_SPEED 0x00000004 -#define NICE_CMD_BLINK_LED 0x00000005 - -#endif /* _nicext_h_ */ diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index b20b4df..32c2ab9 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -50,7 +50,7 @@ static struct phy_driver AR8021_driver = { static struct phy_driver AR8031_driver = { .name = "AR8031/AR8033", .uid = 0x4dd074, - .mask = 0x4fffff, + .mask = 0xffffffef, .features = PHY_GBIT_FEATURES, .config = ar8021_config, .startup = genphy_startup, @@ -60,7 +60,7 @@ static struct phy_driver AR8031_driver = { static struct phy_driver AR8035_driver = { .name = "AR8035", .uid = 0x4dd072, - .mask = 0x4fffff, + .mask = 0xffffffef, .features = PHY_GBIT_FEATURES, .config = ar8035_config, .startup = genphy_startup, diff --git a/drivers/power/fuel_gauge/fg_max17042.c b/drivers/power/fuel_gauge/fg_max17042.c index c285747..154ca6a 100644 --- a/drivers/power/fuel_gauge/fg_max17042.c +++ b/drivers/power/fuel_gauge/fg_max17042.c @@ -20,21 +20,30 @@ static int fg_write_regs(struct pmic *p, u8 addr, u16 *data, int num) int ret = 0; int i; - for (i = 0; i < num; i++, addr++) - ret |= pmic_reg_write(p, addr, *(data + i)); + for (i = 0; i < num; i++, addr++) { + ret = pmic_reg_write(p, addr, *(data + i)); + if (ret) + return ret; + } - return ret; + return 0; } static int fg_read_regs(struct pmic *p, u8 addr, u16 *data, int num) { + unsigned int dat; int ret = 0; int i; - for (i = 0; i < num; i++, addr++) - ret |= pmic_reg_read(p, addr, (u32 *) (data + i)); + for (i = 0; i < num; i++, addr++) { + ret = pmic_reg_read(p, addr, &dat); + if (ret) + return ret; - return ret; + *(data + i) = (u16)dat; + } + + return 0; } static int fg_write_and_verify(struct pmic *p, u8 addr, u16 data) @@ -57,9 +66,13 @@ static int fg_write_and_verify(struct pmic *p, u8 addr, u16 data) static void por_fuelgauge_init(struct pmic *p) { u16 r_data0[16], r_data1[16], r_data2[16]; - u32 rewrite_count = 5, i = 0; - unsigned int val; - int ret = 0; + u32 rewrite_count = 5; + u32 check_count; + u32 lock_count; + u32 i = 0; + u32 val; + s32 ret = 0; + char *status_msg; /* Delay 500 ms */ mdelay(500); @@ -67,29 +80,55 @@ static void por_fuelgauge_init(struct pmic *p) pmic_reg_write(p, MAX17042_CONFIG, 0x2310); rewrite_model: + check_count = 5; + lock_count = 5; + + if (!rewrite_count--) { + status_msg = "init failed!"; + goto error; + } + /* Unlock Model Access */ pmic_reg_write(p, MAX17042_MLOCKReg1, MODEL_UNLOCK1); pmic_reg_write(p, MAX17042_MLOCKReg2, MODEL_UNLOCK2); /* Write/Read/Verify the Custom Model */ - ret |= fg_write_regs(p, MAX17042_MODEL1, cell_character0, + ret = fg_write_regs(p, MAX17042_MODEL1, cell_character0, ARRAY_SIZE(cell_character0)); - ret |= fg_write_regs(p, MAX17042_MODEL2, cell_character1, + if (ret) + goto rewrite_model; + + ret = fg_write_regs(p, MAX17042_MODEL2, cell_character1, ARRAY_SIZE(cell_character1)); - ret |= fg_write_regs(p, MAX17042_MODEL3, cell_character2, + if (ret) + goto rewrite_model; + + ret = fg_write_regs(p, MAX17042_MODEL3, cell_character2, ARRAY_SIZE(cell_character2)); + if (ret) + goto rewrite_model; - if (ret) { - printf("%s: Cell parameters write failed!\n", __func__); - return; +check_model: + if (!check_count--) { + if (rewrite_count) + goto rewrite_model; + else + status_msg = "check failed!"; + + goto error; } - ret |= fg_read_regs(p, MAX17042_MODEL1, r_data0, ARRAY_SIZE(r_data0)); - ret |= fg_read_regs(p, MAX17042_MODEL2, r_data1, ARRAY_SIZE(r_data1)); - ret |= fg_read_regs(p, MAX17042_MODEL3, r_data2, ARRAY_SIZE(r_data2)); + ret = fg_read_regs(p, MAX17042_MODEL1, r_data0, ARRAY_SIZE(r_data0)); + if (ret) + goto check_model; + + ret = fg_read_regs(p, MAX17042_MODEL2, r_data1, ARRAY_SIZE(r_data1)); + if (ret) + goto check_model; + ret = fg_read_regs(p, MAX17042_MODEL3, r_data2, ARRAY_SIZE(r_data2)); if (ret) - printf("%s: Cell parameters read failed!\n", __func__); + goto check_model; for (i = 0; i < 16; i++) { if ((cell_character0[i] != r_data0[i]) @@ -98,29 +137,37 @@ rewrite_model: goto rewrite_model; } +lock_model: + if (!lock_count--) { + if (rewrite_count) + goto rewrite_model; + else + status_msg = "lock failed!"; + + goto error; + } + /* Lock model access */ pmic_reg_write(p, MAX17042_MLOCKReg1, MODEL_LOCK1); pmic_reg_write(p, MAX17042_MLOCKReg2, MODEL_LOCK2); /* Verify the model access is locked */ - ret |= fg_read_regs(p, MAX17042_MODEL1, r_data0, ARRAY_SIZE(r_data0)); - ret |= fg_read_regs(p, MAX17042_MODEL2, r_data1, ARRAY_SIZE(r_data1)); - ret |= fg_read_regs(p, MAX17042_MODEL3, r_data2, ARRAY_SIZE(r_data2)); + ret = fg_read_regs(p, MAX17042_MODEL1, r_data0, ARRAY_SIZE(r_data0)); + if (ret) + goto lock_model; - if (ret) { - printf("%s: Cell parameters read failed!\n", __func__); - return; - } + ret = fg_read_regs(p, MAX17042_MODEL2, r_data1, ARRAY_SIZE(r_data1)); + if (ret) + goto lock_model; + + ret = fg_read_regs(p, MAX17042_MODEL3, r_data2, ARRAY_SIZE(r_data2)); + if (ret) + goto lock_model; for (i = 0; i < ARRAY_SIZE(r_data0); i++) { /* Check if model locked */ - if (r_data0[i] || r_data1[i] || r_data2[i]) { - /* Rewrite model data - prevent from endless loop */ - if (rewrite_count--) { - puts("FG - Lock model access failed!\n"); - goto rewrite_model; - } - } + if (r_data0[i] || r_data1[i] || r_data2[i]) + goto lock_model; } /* Write Custom Parameters */ @@ -137,6 +184,11 @@ rewrite_model: /* Delay at least 350 ms */ mdelay(350); + + status_msg = "OK!"; +error: + debug("%s: model init status: %s\n", p->name, status_msg); + return; } static int power_update_battery(struct pmic *p, struct pmic *bat) @@ -178,7 +230,7 @@ static int power_check_battery(struct pmic *p, struct pmic *bat) ret |= pmic_reg_read(p, MAX17042_STATUS, &val); debug("fg status: 0x%x\n", val); - if (val == MAX17042_POR) + if (val & MAX17042_POR) por_fuelgauge_init(p); ret |= pmic_reg_read(p, MAX17042_VERSION, &val); diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index d5a7143..81b6af6 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_CF_SPI) += cf_spi.o obj-$(CONFIG_CF_QSPI) += cf_qspi.o obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o +obj-$(CONFIG_FTSSP010_SPI) += ftssp010_spi.o obj-$(CONFIG_ICH_SPI) += ich.o obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o obj-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o diff --git a/drivers/spi/ftssp010_spi.c b/drivers/spi/ftssp010_spi.c new file mode 100644 index 0000000..aa3b5a0 --- /dev/null +++ b/drivers/spi/ftssp010_spi.c @@ -0,0 +1,508 @@ +/* + * (C) Copyright 2013 + * Faraday Technology Corporation. <http://www.faraday-tech.com/tw/> + * Kuo-Jung Su <dantesu@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <linux/compat.h> +#include <asm/io.h> +#include <malloc.h> +#include <spi.h> + +#ifndef CONFIG_FTSSP010_BASE_LIST +#define CONFIG_FTSSP010_BASE_LIST { CONFIG_FTSSP010_BASE } +#endif + +#ifndef CONFIG_FTSSP010_GPIO_BASE +#define CONFIG_FTSSP010_GPIO_BASE 0 +#endif + +#ifndef CONFIG_FTSSP010_GPIO_LIST +#define CONFIG_FTSSP010_GPIO_LIST { CONFIG_FTSSP010_GPIO_BASE } +#endif + +#ifndef CONFIG_FTSSP010_CLOCK +#define CONFIG_FTSSP010_CLOCK clk_get_rate("SSP"); +#endif + +#ifndef CONFIG_FTSSP010_TIMEOUT +#define CONFIG_FTSSP010_TIMEOUT 100 +#endif + +/* FTSSP010 chip registers */ +struct ftssp010_regs { + uint32_t cr[3];/* control register */ + uint32_t sr; /* status register */ + uint32_t icr; /* interrupt control register */ + uint32_t isr; /* interrupt status register */ + uint32_t dr; /* data register */ + uint32_t rsvd[17]; + uint32_t revr; /* revision register */ + uint32_t fear; /* feature register */ +}; + +/* Control Register 0 */ +#define CR0_FFMT_MASK (7 << 12) +#define CR0_FFMT_SSP (0 << 12) +#define CR0_FFMT_SPI (1 << 12) +#define CR0_FFMT_MICROWIRE (2 << 12) +#define CR0_FFMT_I2S (3 << 12) +#define CR0_FFMT_AC97 (4 << 12) +#define CR0_FLASH (1 << 11) +#define CR0_FSDIST(x) (((x) & 0x03) << 8) +#define CR0_LOOP (1 << 7) /* loopback mode */ +#define CR0_LSB (1 << 6) /* LSB */ +#define CR0_FSPO (1 << 5) /* fs atcive low (I2S only) */ +#define CR0_FSJUSTIFY (1 << 4) +#define CR0_OPM_SLAVE (0 << 2) +#define CR0_OPM_MASTER (3 << 2) +#define CR0_OPM_I2S_MSST (3 << 2) /* master stereo mode */ +#define CR0_OPM_I2S_MSMO (2 << 2) /* master mono mode */ +#define CR0_OPM_I2S_SLST (1 << 2) /* slave stereo mode */ +#define CR0_OPM_I2S_SLMO (0 << 2) /* slave mono mode */ +#define CR0_SCLKPO (1 << 1) /* clock polarity */ +#define CR0_SCLKPH (1 << 0) /* clock phase */ + +/* Control Register 1 */ +#define CR1_PDL(x) (((x) & 0xff) << 24) /* padding length */ +#define CR1_SDL(x) ((((x) - 1) & 0x1f) << 16) /* data length */ +#define CR1_DIV(x) (((x) - 1) & 0xffff) /* clock divider */ + +/* Control Register 2 */ +#define CR2_CS(x) (((x) & 3) << 10) /* CS/FS select */ +#define CR2_FS (1 << 9) /* CS/FS signal level */ +#define CR2_TXEN (1 << 8) /* tx enable */ +#define CR2_RXEN (1 << 7) /* rx enable */ +#define CR2_RESET (1 << 6) /* chip reset */ +#define CR2_TXFC (1 << 3) /* tx fifo Clear */ +#define CR2_RXFC (1 << 2) /* rx fifo Clear */ +#define CR2_TXDOE (1 << 1) /* tx data output enable */ +#define CR2_EN (1 << 0) /* chip enable */ + +/* Status Register */ +#define SR_RFF (1 << 0) /* rx fifo full */ +#define SR_TFNF (1 << 1) /* tx fifo not full */ +#define SR_BUSY (1 << 2) /* chip busy */ +#define SR_RFVE(reg) (((reg) >> 4) & 0x1f) /* rx fifo valid entries */ +#define SR_TFVE(reg) (((reg) >> 12) & 0x1f) /* tx fifo valid entries */ + +/* Feature Register */ +#define FEAR_BITS(reg) ((((reg) >> 0) & 0xff) + 1) /* data width */ +#define FEAR_RFSZ(reg) ((((reg) >> 8) & 0xff) + 1) /* rx fifo size */ +#define FEAR_TFSZ(reg) ((((reg) >> 16) & 0xff) + 1) /* tx fifo size */ +#define FEAR_AC97 (1 << 24) +#define FEAR_I2S (1 << 25) +#define FEAR_SPI_MWR (1 << 26) +#define FEAR_SSP (1 << 27) +#define FEAR_SPDIF (1 << 28) + +/* FTGPIO010 chip registers */ +struct ftgpio010_regs { + uint32_t out; /* 0x00: Data Output */ + uint32_t in; /* 0x04: Data Input */ + uint32_t dir; /* 0x08: Direction */ + uint32_t bypass; /* 0x0c: Bypass */ + uint32_t set; /* 0x10: Data Set */ + uint32_t clr; /* 0x14: Data Clear */ + uint32_t pull_up; /* 0x18: Pull-Up Enabled */ + uint32_t pull_st; /* 0x1c: Pull State (0=pull-down, 1=pull-up) */ +}; + +struct ftssp010_gpio { + struct ftgpio010_regs *regs; + uint32_t pin; +}; + +struct ftssp010_spi { + struct spi_slave slave; + struct ftssp010_gpio gpio; + struct ftssp010_regs *regs; + uint32_t fifo; + uint32_t mode; + uint32_t div; + uint32_t clk; + uint32_t speed; + uint32_t revision; +}; + +static inline struct ftssp010_spi *to_ftssp010_spi(struct spi_slave *slave) +{ + return container_of(slave, struct ftssp010_spi, slave); +} + +static int get_spi_chip(int bus, struct ftssp010_spi *chip) +{ + uint32_t fear, base[] = CONFIG_FTSSP010_BASE_LIST; + + if (bus >= ARRAY_SIZE(base) || !base[bus]) + return -1; + + chip->regs = (struct ftssp010_regs *)base[bus]; + + chip->revision = readl(&chip->regs->revr); + + fear = readl(&chip->regs->fear); + chip->fifo = min_t(uint32_t, FEAR_TFSZ(fear), FEAR_RFSZ(fear)); + + return 0; +} + +static int get_spi_gpio(int bus, struct ftssp010_gpio *chip) +{ + uint32_t base[] = CONFIG_FTSSP010_GPIO_LIST; + + if (bus >= ARRAY_SIZE(base) || !base[bus]) + return -1; + + chip->regs = (struct ftgpio010_regs *)(base[bus] & 0xfff00000); + chip->pin = base[bus] & 0x1f; + + /* make it an output pin */ + setbits_le32(&chip->regs->dir, 1 << chip->pin); + + return 0; +} + +static int ftssp010_wait(struct ftssp010_spi *chip) +{ + struct ftssp010_regs *regs = chip->regs; + int ret = -1; + ulong t; + + /* wait until device idle */ + for (t = get_timer(0); get_timer(t) < CONFIG_FTSSP010_TIMEOUT; ) { + if (readl(®s->sr) & SR_BUSY) + continue; + ret = 0; + break; + } + + if (ret) + puts("ftspi010: busy timeout\n"); + + return ret; +} + +static int ftssp010_wait_tx(struct ftssp010_spi *chip) +{ + struct ftssp010_regs *regs = chip->regs; + int ret = -1; + ulong t; + + /* wait until tx fifo not full */ + for (t = get_timer(0); get_timer(t) < CONFIG_FTSSP010_TIMEOUT; ) { + if (!(readl(®s->sr) & SR_TFNF)) + continue; + ret = 0; + break; + } + + if (ret) + puts("ftssp010: tx timeout\n"); + + return ret; +} + +static int ftssp010_wait_rx(struct ftssp010_spi *chip) +{ + struct ftssp010_regs *regs = chip->regs; + int ret = -1; + ulong t; + + /* wait until rx fifo not empty */ + for (t = get_timer(0); get_timer(t) < CONFIG_FTSSP010_TIMEOUT; ) { + if (!SR_RFVE(readl(®s->sr))) + continue; + ret = 0; + break; + } + + if (ret) + puts("ftssp010: rx timeout\n"); + + return ret; +} + +static int ftssp010_spi_work_transfer_v2(struct ftssp010_spi *chip, + const void *tx_buf, void *rx_buf, int len, uint flags) +{ + struct ftssp010_regs *regs = chip->regs; + const uint8_t *txb = tx_buf; + uint8_t *rxb = rx_buf; + + while (len > 0) { + int i, depth = min(chip->fifo >> 2, len); + uint32_t xmsk = 0; + + if (tx_buf) { + for (i = 0; i < depth; ++i) { + ftssp010_wait_tx(chip); + writel(*txb++, ®s->dr); + } + xmsk |= CR2_TXEN | CR2_TXDOE; + if ((readl(®s->cr[2]) & xmsk) != xmsk) + setbits_le32(®s->cr[2], xmsk); + } + if (rx_buf) { + xmsk |= CR2_RXEN; + if ((readl(®s->cr[2]) & xmsk) != xmsk) + setbits_le32(®s->cr[2], xmsk); + for (i = 0; i < depth; ++i) { + ftssp010_wait_rx(chip); + *rxb++ = (uint8_t)readl(®s->dr); + } + } + + len -= depth; + } + + return 0; +} + +static int ftssp010_spi_work_transfer_v1(struct ftssp010_spi *chip, + const void *tx_buf, void *rx_buf, int len, uint flags) +{ + struct ftssp010_regs *regs = chip->regs; + const uint8_t *txb = tx_buf; + uint8_t *rxb = rx_buf; + + while (len > 0) { + int i, depth = min(chip->fifo >> 2, len); + uint32_t tmp; + + for (i = 0; i < depth; ++i) { + ftssp010_wait_tx(chip); + writel(txb ? (*txb++) : 0, ®s->dr); + } + for (i = 0; i < depth; ++i) { + ftssp010_wait_rx(chip); + tmp = readl(®s->dr); + if (rxb) + *rxb++ = (uint8_t)tmp; + } + + len -= depth; + } + + return 0; +} + +static void ftssp010_cs_set(struct ftssp010_spi *chip, int high) +{ + struct ftssp010_regs *regs = chip->regs; + struct ftssp010_gpio *gpio = &chip->gpio; + uint32_t mask; + + /* cs pull high/low */ + if (chip->revision >= 0x11900) { + mask = CR2_CS(chip->slave.cs) | (high ? CR2_FS : 0); + writel(mask, ®s->cr[2]); + } else if (gpio->regs) { + mask = 1 << gpio->pin; + if (high) + writel(mask, &gpio->regs->set); + else + writel(mask, &gpio->regs->clr); + } + + /* extra delay for signal propagation */ + udelay_masked(1); +} + +/* + * Determine if a SPI chipselect is valid. + * This function is provided by the board if the low-level SPI driver + * needs it to determine if a given chipselect is actually valid. + * + * Returns: 1 if bus:cs identifies a valid chip on this board, 0 + * otherwise. + */ +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + struct ftssp010_spi chip; + + if (get_spi_chip(bus, &chip)) + return 0; + + if (!cs) + return 1; + else if ((cs < 4) && (chip.revision >= 0x11900)) + return 1; + + return 0; +} + +/* + * Activate a SPI chipselect. + * This function is provided by the board code when using a driver + * that can't control its chipselects automatically (e.g. + * common/soft_spi.c). When called, it should activate the chip select + * to the device identified by "slave". + */ +void spi_cs_activate(struct spi_slave *slave) +{ + struct ftssp010_spi *chip = to_ftssp010_spi(slave); + struct ftssp010_regs *regs = chip->regs; + + /* cs pull */ + if (chip->mode & SPI_CS_HIGH) + ftssp010_cs_set(chip, 1); + else + ftssp010_cs_set(chip, 0); + + /* chip enable + fifo clear */ + setbits_le32(®s->cr[2], CR2_EN | CR2_TXFC | CR2_RXFC); +} + +/* + * Deactivate a SPI chipselect. + * This function is provided by the board code when using a driver + * that can't control its chipselects automatically (e.g. + * common/soft_spi.c). When called, it should deactivate the chip + * select to the device identified by "slave". + */ +void spi_cs_deactivate(struct spi_slave *slave) +{ + struct ftssp010_spi *chip = to_ftssp010_spi(slave); + + /* wait until chip idle */ + ftssp010_wait(chip); + + /* cs pull */ + if (chip->mode & SPI_CS_HIGH) + ftssp010_cs_set(chip, 0); + else + ftssp010_cs_set(chip, 1); +} + +void spi_init(void) +{ + /* nothing to do */ +} + +struct spi_slave *spi_setup_slave(uint bus, uint cs, uint max_hz, uint mode) +{ + struct ftssp010_spi *chip; + + if (mode & SPI_3WIRE) { + puts("ftssp010: can't do 3-wire\n"); + return NULL; + } + + if (mode & SPI_SLAVE) { + puts("ftssp010: can't do slave mode\n"); + return NULL; + } + + if (mode & SPI_PREAMBLE) { + puts("ftssp010: can't skip preamble bytes\n"); + return NULL; + } + + if (!spi_cs_is_valid(bus, cs)) { + puts("ftssp010: invalid (bus, cs)\n"); + return NULL; + } + + chip = spi_alloc_slave(struct ftssp010_spi, bus, cs); + if (!chip) + return NULL; + + if (get_spi_chip(bus, chip)) + goto free_out; + + if (chip->revision < 0x11900 && get_spi_gpio(bus, &chip->gpio)) { + puts("ftssp010: Before revision 1.19.0, its clock & cs are\n" + "controlled by tx engine which is not synced with rx engine,\n" + "so the clock & cs might be shutdown before rx engine\n" + "finishs its jobs.\n" + "If possible, please add a dedicated gpio for it.\n"); + } + + chip->mode = mode; + chip->clk = CONFIG_FTSSP010_CLOCK; + chip->div = 2; + if (max_hz) { + while (chip->div < 0xffff) { + if ((chip->clk / (2 * chip->div)) <= max_hz) + break; + chip->div += 1; + } + } + chip->speed = chip->clk / (2 * chip->div); + + return &chip->slave; + +free_out: + free(chip); + return NULL; +} + +void spi_free_slave(struct spi_slave *slave) +{ + free(slave); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + struct ftssp010_spi *chip = to_ftssp010_spi(slave); + struct ftssp010_regs *regs = chip->regs; + + writel(CR1_SDL(8) | CR1_DIV(chip->div), ®s->cr[1]); + + if (chip->revision >= 0x11900) { + writel(CR0_OPM_MASTER | CR0_FFMT_SPI | CR0_FSPO | CR0_FLASH, + ®s->cr[0]); + writel(CR2_TXFC | CR2_RXFC, + ®s->cr[2]); + } else { + writel(CR0_OPM_MASTER | CR0_FFMT_SPI | CR0_FSPO, + ®s->cr[0]); + writel(CR2_TXFC | CR2_RXFC | CR2_EN | CR2_TXDOE, + ®s->cr[2]); + } + + if (chip->mode & SPI_LOOP) + setbits_le32(®s->cr[0], CR0_LOOP); + + if (chip->mode & SPI_CPOL) + setbits_le32(®s->cr[0], CR0_SCLKPO); + + if (chip->mode & SPI_CPHA) + setbits_le32(®s->cr[0], CR0_SCLKPH); + + spi_cs_deactivate(slave); + + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + struct ftssp010_spi *chip = to_ftssp010_spi(slave); + struct ftssp010_regs *regs = chip->regs; + + writel(0, ®s->cr[2]); +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct ftssp010_spi *chip = to_ftssp010_spi(slave); + uint32_t len = bitlen >> 3; + + if (flags & SPI_XFER_BEGIN) + spi_cs_activate(slave); + + if (chip->revision >= 0x11900) + ftssp010_spi_work_transfer_v2(chip, dout, din, len, flags); + else + ftssp010_spi_work_transfer_v1(chip, dout, din, len, flags); + + if (flags & SPI_XFER_END) + spi_cs_deactivate(slave); + + return 0; +} diff --git a/drivers/spi/sh_spi.c b/drivers/spi/sh_spi.c index 744afe3..7ca5e36 100644 --- a/drivers/spi/sh_spi.c +++ b/drivers/spi/sh_spi.c @@ -151,7 +151,6 @@ static int sh_spi_send(struct sh_spi *ss, const unsigned char *tx_data, { int i, cur_len, ret = 0; int remain = (int)len; - unsigned long tmp; if (len >= SH_SPI_FIFO_SIZE) sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1); @@ -183,9 +182,7 @@ static int sh_spi_send(struct sh_spi *ss, const unsigned char *tx_data, } if (flags & SPI_XFER_END) { - tmp = sh_spi_read(&ss->regs->cr1); - tmp = tmp & ~(SH_SPI_SSD | SH_SPI_SSDB); - sh_spi_write(tmp, &ss->regs->cr1); + sh_spi_clear_bit(SH_SPI_SSD | SH_SPI_SSDB, &ss->regs->cr1); sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1); udelay(100); write_fifo_empty_wait(ss); @@ -198,16 +195,13 @@ static int sh_spi_receive(struct sh_spi *ss, unsigned char *rx_data, unsigned int len, unsigned long flags) { int i; - unsigned long tmp; if (len > SH_SPI_MAX_BYTE) sh_spi_write(SH_SPI_MAX_BYTE, &ss->regs->cr3); else sh_spi_write(len, &ss->regs->cr3); - tmp = sh_spi_read(&ss->regs->cr1); - tmp = tmp & ~(SH_SPI_SSD | SH_SPI_SSDB); - sh_spi_write(tmp, &ss->regs->cr1); + sh_spi_clear_bit(SH_SPI_SSD | SH_SPI_SSDB, &ss->regs->cr1); sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1); for (i = 0; i < len; i++) { diff --git a/drivers/usb/gadget/fotg210.c b/drivers/usb/gadget/fotg210.c index 6e19db1..3acf6a1 100644 --- a/drivers/usb/gadget/fotg210.c +++ b/drivers/usb/gadget/fotg210.c @@ -245,6 +245,7 @@ static int fotg210_dma(struct fotg210_ep *ep, struct fotg210_request *req) if (ep->id == 0) { /* Wait until cx/ep0 fifo empty */ fotg210_cxwait(chip, CXFIFO_CXFIFOE); + udelay(1); writel(DMAFIFO_CX, ®s->dma_fifo); } else { /* Wait until epx fifo empty */ @@ -847,6 +848,13 @@ int usb_gadget_handle_interrupts(void) /* CX interrupts */ if (gisr & GISR_GRP0) { st = readl(®s->gisr0); + /* + * Write 1 and then 0 works for both W1C & RW. + * + * HW v1.11.0+: It's a W1C register (write 1 clear) + * HW v1.10.0-: It's a R/W register (write 0 clear) + */ + writel(st & GISR0_CXABORT, ®s->gisr0); writel(0, ®s->gisr0); if (st & GISR0_CXERR) @@ -873,6 +881,13 @@ int usb_gadget_handle_interrupts(void) /* Device Status Interrupts */ if (gisr & GISR_GRP2) { st = readl(®s->gisr2); + /* + * Write 1 and then 0 works for both W1C & RW. + * + * HW v1.11.0+: It's a W1C register (write 1 clear) + * HW v1.10.0-: It's a R/W register (write 0 clear) + */ + writel(st, ®s->gisr2); writel(0, ®s->gisr2); if (st & GISR2_RESET) diff --git a/drivers/usb/host/ehci-exynos.c b/drivers/usb/host/ehci-exynos.c index 66b4de0..9356878 100644 --- a/drivers/usb/host/ehci-exynos.c +++ b/drivers/usb/host/ehci-exynos.c @@ -88,6 +88,8 @@ static int exynos_usb_parse_dt(const void *blob, struct exynos_ehci *exynos) /* Setup the EHCI host controller. */ static void setup_usb_phy(struct exynos_usb_phy *usb) { + u32 hsic_ctrl; + set_usbhost_mode(USB20_PHY_CFG_HOST_LINK_EN); set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_EN); @@ -112,6 +114,32 @@ static void setup_usb_phy(struct exynos_usb_phy *usb) clrbits_le32(&usb->usbphyctrl0, HOST_CTRL0_LINKSWRST | HOST_CTRL0_UTMISWRST); + + /* HSIC Phy Setting */ + hsic_ctrl = (HSIC_CTRL_FORCESUSPEND | + HSIC_CTRL_FORCESLEEP | + HSIC_CTRL_SIDDQ); + + clrbits_le32(&usb->hsicphyctrl1, hsic_ctrl); + clrbits_le32(&usb->hsicphyctrl2, hsic_ctrl); + + hsic_ctrl = (((HSIC_CTRL_REFCLKDIV_12 & HSIC_CTRL_REFCLKDIV_MASK) + << HSIC_CTRL_REFCLKDIV_SHIFT) + | ((HSIC_CTRL_REFCLKSEL & HSIC_CTRL_REFCLKSEL_MASK) + << HSIC_CTRL_REFCLKSEL_SHIFT) + | HSIC_CTRL_UTMISWRST); + + setbits_le32(&usb->hsicphyctrl1, hsic_ctrl); + setbits_le32(&usb->hsicphyctrl2, hsic_ctrl); + + udelay(10); + + clrbits_le32(&usb->hsicphyctrl1, HSIC_CTRL_PHYSWRST | + HSIC_CTRL_UTMISWRST); + + clrbits_le32(&usb->hsicphyctrl2, HSIC_CTRL_PHYSWRST | + HSIC_CTRL_UTMISWRST); + udelay(20); /* EHCI Ctrl setting */ @@ -125,6 +153,8 @@ static void setup_usb_phy(struct exynos_usb_phy *usb) /* Reset the EHCI host controller. */ static void reset_usb_phy(struct exynos_usb_phy *usb) { + u32 hsic_ctrl; + /* HOST_PHY reset */ setbits_le32(&usb->usbphyctrl0, HOST_CTRL0_PHYSWRST | @@ -133,6 +163,15 @@ static void reset_usb_phy(struct exynos_usb_phy *usb) HOST_CTRL0_FORCESUSPEND | HOST_CTRL0_FORCESLEEP); + /* HSIC Phy reset */ + hsic_ctrl = (HSIC_CTRL_FORCESUSPEND | + HSIC_CTRL_FORCESLEEP | + HSIC_CTRL_SIDDQ | + HSIC_CTRL_PHYSWRST); + + setbits_le32(&usb->hsicphyctrl1, hsic_ctrl); + setbits_le32(&usb->hsicphyctrl2, hsic_ctrl); + set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_DISABLE); } @@ -164,6 +203,8 @@ int ehci_hcd_init(int index, enum usb_init_type init, setup_usb_phy(ctx->usb); + board_usb_init(index, init); + *hccr = ctx->hcd; *hcor = (struct ehci_hcor *)((uint32_t) *hccr + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); diff --git a/drivers/video/ipu_regs.h b/drivers/video/ipu_regs.h index 73e57ea..21e9c99 100644 --- a/drivers/video/ipu_regs.h +++ b/drivers/video/ipu_regs.h @@ -171,7 +171,7 @@ struct ipu_cm { u32 gpr; u32 reserved0[26]; u32 ch_db_mode_sel[2]; - u32 reserved1[16]; + u32 reserved1[4]; u32 alt_ch_db_mode_sel[2]; u32 reserved2[2]; u32 ch_trb_mode_sel[2]; @@ -188,7 +188,7 @@ struct ipu_idmac { u32 sub_addr[5]; u32 bndm_en[2]; u32 sc_cord[2]; - u32 reserved[45]; + u32 reserved[44]; u32 ch_busy[2]; }; |