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authorStefan Roese <sr@denx.de>2009-05-20 10:58:03 +0200
committerStefan Roese <sr@denx.de>2009-05-23 12:51:39 +0200
commitf40f6db278f602b55820693634a7256b0b4e4b80 (patch)
tree084f2b6e6b58c8c2320d5d3fc565e434ac0b0ab4 /drivers
parent399aab7748bef053d59612211e1bd7a3fabfce18 (diff)
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nand: Fix problem with ECC ordering for PPC4xx NDFC platforms
This patch enables Smart Media (SMC) ECC byte ordering which is used on the PPC4xx NAND FLASH controller (NDFC). Without this patch we have incompatible ECC byte ordering to the Linux kernel NDFC driver. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Scott Wood <scottwood@freescale.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/mtd/nand/nand_ecc.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/mtd/nand/nand_ecc.c b/drivers/mtd/nand/nand_ecc.c
index 94923b9..463f9cb 100644
--- a/drivers/mtd/nand/nand_ecc.c
+++ b/drivers/mtd/nand/nand_ecc.c
@@ -48,6 +48,11 @@
#include <asm/errno.h>
#include <linux/mtd/mtd.h>
+/* The PPC4xx NDFC uses Smart Media (SMC) bytes order */
+#ifdef CONFIG_NAND_NDFC
+#define CONFIG_MTD_NAND_ECC_SMC
+#endif
+
/*
* NAND-SPL has no sofware ECC for now, so don't include nand_calculate_ecc(),
* only nand_correct_data() is needed