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authorEran Liberty <liberty@freescale.com>2005-07-28 10:08:46 -0500
committerJon Loeliger <jdl@freescale.com>2005-07-28 10:08:46 -0500
commitf046ccd15c8bc9613bfd72916b761a127d36e5c6 (patch)
tree40b48bdc1fff75c661cab5c4806a322a67e9dc44 /drivers
parent63be111e72371b6edc6d02134dd785abb6be188c (diff)
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* Patch by Eran Liberty
Add support for the Freescale MPC8349ADS board.
Diffstat (limited to 'drivers')
-rw-r--r--drivers/tsec.c23
-rw-r--r--drivers/tsec.h15
2 files changed, 24 insertions, 14 deletions
diff --git a/drivers/tsec.c b/drivers/tsec.c
index 5ac6334..f5067b3 100644
--- a/drivers/tsec.c
+++ b/drivers/tsec.c
@@ -8,7 +8,6 @@
*
* Copyright 2004 Freescale Semiconductor.
* (C) Copyright 2003, Motorola, Inc.
- * maintained by Jon Loeliger (loeliger@freescale.com)
* author Andy Fleming
*
*/
@@ -70,12 +69,12 @@ struct tsec_info_struct {
* FEC_PHYIDX
*/
static struct tsec_info_struct tsec_info[] = {
-#ifdef CONFIG_MPC85XX_TSEC1
+#if defined(CONFIG_MPC85XX_TSEC1) || defined(CONFIG_MPC83XX_TSEC1)
{TSEC1_PHY_ADDR, TSEC_GIGABIT, TSEC1_PHYIDX},
#else
{ 0, 0, 0},
#endif
-#ifdef CONFIG_MPC85XX_TSEC2
+#if defined(CONFIG_MPC85XX_TSEC2) || defined(CONFIG_MPC83XX_TSEC2)
{TSEC2_PHY_ADDR, TSEC_GIGABIT, TSEC2_PHYIDX},
#else
{ 0, 0, 0},
@@ -83,12 +82,12 @@ static struct tsec_info_struct tsec_info[] = {
#ifdef CONFIG_MPC85XX_FEC
{FEC_PHY_ADDR, 0, FEC_PHYIDX},
#else
-# ifdef CONFIG_MPC85XX_TSEC3
+# if defined(CONFIG_MPC85XX_TSEC3) || defined(CONFIG_MPC83XX_TSEC3)
{TSEC3_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC3_PHYIDX},
# else
{ 0, 0, 0},
# endif
-# ifdef CONFIG_MPC85XX_TSEC4
+# if defined(CONFIG_MPC85XX_TSEC4) || defined(CONFIG_MPC83XX_TSEC4)
{TSEC4_PHY_ADDR, TSEC_REDUCED, TSEC4_PHYIDX},
# else
{ 0, 0, 0},
@@ -236,7 +235,7 @@ void write_phy_reg(struct tsec_private *priv, uint regnum, uint value)
regbase->miimadd = (phyid << 8) | regnum;
regbase->miimcon = value;
- asm("msync");
+ asm("sync");
timeout=1000000;
while((regbase->miimind & MIIMIND_BUSY) && timeout--);
@@ -261,11 +260,11 @@ uint read_phy_reg(struct tsec_private *priv, uint regnum)
/* Clear the command register, and wait */
regbase->miimcom = 0;
- asm("msync");
+ asm("sync");
/* Initiate a read command, and wait */
regbase->miimcom = MIIM_READ_COMMAND;
- asm("msync");
+ asm("sync");
/* Wait for the the indication that the read is done */
while((regbase->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY)));
@@ -293,14 +292,14 @@ static int init_phy(struct eth_device *dev)
regs->tbipa = TBIPA_VALUE;
regs = (volatile tsec_t *)(TSEC_BASE_ADDR + TSEC_SIZE);
regs->tbipa = TBIPA_VALUE;
- asm("msync");
+ asm("sync");
}
/* Reset MII (due to new addresses) */
priv->phyregs->miimcfg = MIIMCFG_RESET;
- asm("msync");
+ asm("sync");
priv->phyregs->miimcfg = MIIMCFG_INIT_VALUE;
- asm("msync");
+ asm("sync");
while(priv->phyregs->miimind & MIIMIND_BUSY);
if(0 == relocated)
@@ -439,7 +438,7 @@ uint mii_cis8204_fixled(uint mii_reg, struct tsec_private *priv)
for(phyid=0;phyid<4;phyid++) {
regbase->miimadd = (phyid << 8) | mii_reg;
regbase->miimcon = MIIM_CIS8204_SLEDCON_INIT;
- asm("msync");
+ asm("sync");
timeout=1000000;
while((regbase->miimind & MIIMIND_BUSY) && timeout--);
diff --git a/drivers/tsec.h b/drivers/tsec.h
index d1c70aa..15961d7 100644
--- a/drivers/tsec.h
+++ b/drivers/tsec.h
@@ -18,11 +18,22 @@
#define __TSEC_H
#include <net.h>
-#include <mpc85xx.h>
+#include <config.h>
+
+#ifndef CFG_TSEC1_OFFSET
+ #define CFG_TSEC1_OFFSET (0x24000)
+#endif
-#define TSEC_BASE_ADDR (CFG_IMMR + 0x24000)
#define TSEC_SIZE 0x01000
+/* FIXME: Should these be pushed back to 83xx and 85xx config files? */
+#if defined(CONFIG_MPC85xx)
+ #define TSEC_BASE_ADDR (CFG_IMMR + CFG_TSEC1_OFFSET)
+#elif defined(CONFIG_MPC83XX)
+ #define TSEC_BASE_ADDR (CFG_IMMRBAR + CFG_TSEC1_OFFSET)
+#endif
+
+
#define MAC_ADDR_LEN 6
/* #define TSEC_TIMEOUT 1000000 */