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authorNobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>2008-08-22 17:48:51 +0900
committerNobuhiro Iwamatsu <iwamatsu@nigauri.org>2008-08-31 23:02:21 +0900
commitab09f433b50bb83b5e440c335bc3839ee069e534 (patch)
tree2c2d4a4860b3d94958858f3c2ab157d020242e88 /drivers
parentc655fad06ba3fb042dbc667724a40e1a9a091248 (diff)
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sh: add support Renesas SH7723
Renesas SH7723 has 5 SCIF, SD, Camera, LCDC and other. This patch supports CPU register's header file and SCIF serial driver. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/serial/serial_sh.c46
1 files changed, 34 insertions, 12 deletions
diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c
index 46600e6..61c2b82 100644
--- a/drivers/serial/serial_sh.c
+++ b/drivers/serial/serial_sh.c
@@ -20,14 +20,20 @@
#include <common.h>
#include <asm/processor.h>
-#if defined (CONFIG_CONS_SCIF0)
-#define SCIF_BASE SCIF0_BASE
-#elif defined (CONFIG_CONS_SCIF1)
-#define SCIF_BASE SCIF1_BASE
-#elif defined (CONFIG_CONS_SCIF2)
-#define SCIF_BASE SCIF2_BASE
+#if defined(CONFIG_CONS_SCIF0)
+# define SCIF_BASE SCIF0_BASE
+#elif defined(CONFIG_CONS_SCIF1)
+# define SCIF_BASE SCIF1_BASE
+#elif defined(CONFIG_CONS_SCIF2)
+# define SCIF_BASE SCIF2_BASE
+#elif defined(CONFIG_CONS_SCIF3)
+# define SCIF_BASE SCIF3_BASE
+#elif defined(CONFIG_CONS_SCIF4)
+# define SCIF_BASE SCIF4_BASE
+#elif defined(CONFIG_CONS_SCIF5)
+# define SCIF_BASE SCIF5_BASE
#else
-#error "Default SCIF doesn't set....."
+# error "Default SCIF doesn't set....."
#endif
/* Base register */
@@ -36,7 +42,8 @@
#define SCSCR (vu_short *)(SCIF_BASE + 0x8)
#define SCFCR (vu_short *)(SCIF_BASE + 0x18)
#define SCFDR (vu_short *)(SCIF_BASE + 0x1C)
-#ifdef CONFIG_CPU_SH7720 /* SH7720 specific */
+#if defined(CONFIG_CPU_SH7720) || \
+ (defined(CONFIG_CPU_SH7723) && defined(CONFIG_SCIF_A))
# define SCFSR (vu_short *)(SCIF_BASE + 0x14) /* SCSSR */
# define SCFTDR (vu_char *)(SCIF_BASE + 0x20)
# define SCFRDR (vu_char *)(SCIF_BASE + 0x24)
@@ -55,7 +62,7 @@
# define LSR_ORER 1
# define FIFOLEVEL_MASK 0xFF
#elif defined(CONFIG_CPU_SH7763)
-# if defined (CONFIG_CONS_SCIF2)
+# if defined(CONFIG_CONS_SCIF2)
# define SCSPTR (vu_short *)(SCIF_BASE + 0x20)
# define SCLSR (vu_short *)(SCIF_BASE + 0x24)
# define LSR_ORER 1
@@ -68,6 +75,16 @@
# define LSR_ORER 1
# define FIFOLEVEL_MASK 0xFF
# endif
+#elif defined(CONFIG_CPU_SH7723)
+# if defined(CONIFG_SCIF_A)
+# define SCLSR SCFSR
+# define LSR_ORER 0x0200
+# define FIFOLEVEL_MASK 0x3F
+#else
+# define SCLSR (vu_short *)(SCIF_BASE + 0x24)
+# define LSR_ORER 1
+# define FIFOLEVEL_MASK 0x1F
+#endif
#elif defined(CONFIG_CPU_SH7750) || \
defined(CONFIG_CPU_SH7751) || \
defined(CONFIG_CPU_SH7722) || \
@@ -90,6 +107,9 @@
/* SCBRR register value setting */
#if defined(CONFIG_CPU_SH7720)
# define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
+#elif defined(CONFIG_CPU_SH7723) && defined(CONFIG_SCIF_A)
+/* SH7723 SCIFA use bus clock. So clock *2 */
+# define SCBRR_VALUE(bps, clk) (((clk*2*2)+16*bps)/(32*bps)-1)
#else /* Generic SuperH */
# define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
#endif
@@ -168,7 +188,7 @@ void serial_puts(const char *s)
int serial_tstc(void)
{
- return serial_rx_fifo_level()? 1 : 0;
+ return serial_rx_fifo_level() ? 1 : 0;
}
#define FSR_ERR_CLEAR 0x0063
@@ -192,14 +212,16 @@ int serial_getc_check(void)
handle_error();
if (*SCLSR & LSR_ORER)
handle_error();
- return (status & (FSR_DR | FSR_RDF));
+ return status & (FSR_DR | FSR_RDF);
}
int serial_getc(void)
{
unsigned short status;
char ch;
- while (!serial_getc_check()) ;
+
+ while (!serial_getc_check())
+ ;
ch = *SCFRDR;
status = *SCFSR;