diff options
| author | Hans de Goede <hdegoede@redhat.com> | 2015-01-13 13:21:46 +0100 |
|---|---|---|
| committer | Hans de Goede <hdegoede@redhat.com> | 2015-01-22 12:34:55 +0100 |
| commit | 6515032e3b88f0774f93fb05deaf20e48a515fe4 (patch) | |
| tree | 7f4d251b1b4b07d64e5bff19d2e44c975498ef88 /drivers | |
| parent | b56f6e2b4e0291efbe1b50f082dec73272ad7ab3 (diff) | |
| download | u-boot-imx-6515032e3b88f0774f93fb05deaf20e48a515fe4.zip u-boot-imx-6515032e3b88f0774f93fb05deaf20e48a515fe4.tar.gz u-boot-imx-6515032e3b88f0774f93fb05deaf20e48a515fe4.tar.bz2 | |
sunxi: display: Make lcd display clk phase configurable
While running some tests with an Olinuxino-A13-Micro + a 7" Olimex LCD module
I noticed that the screen flickered. This is caused by the lcd display clk
phase reg value being set to 0, where it should be 1 in this setup.
This commit adds a Kconfig option for the lcd display clk phase, so that we
can set it per board. This defaults to 1, because looking at all the fex
files in sunxi-boards, that is by far the most used value.
This commit updated the Ippo and MSI Primo73 tablet defconfigs to override the
default of 1 with 0, as that is the correct value for those tablets, this
keeps the register settings the same as before this commit.
The Olinuxino-A13 defconfigs are not updated, changing the register setting
for these boards from 0 to 1, this is intentional.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/video/sunxi_display.c | 7 |
1 files changed, 1 insertions, 6 deletions
diff --git a/drivers/video/sunxi_display.c b/drivers/video/sunxi_display.c index d92dfa8..b2ac608 100644 --- a/drivers/video/sunxi_display.c +++ b/drivers/video/sunxi_display.c @@ -587,12 +587,7 @@ static void sunxi_lcdc_tcon0_mode_set(const struct ctfb_res_modes *mode) &lcdc->tcon0_frm_ctrl); } -#ifdef CONFIG_VIDEO_LCD_IF_PARALLEL - val = SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE0; -#endif -#ifdef CONFIG_VIDEO_LCD_IF_LVDS - val = SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE60; -#endif + val = SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(CONFIG_VIDEO_LCD_DCLK_PHASE); if (!(mode->sync & FB_SYNC_HOR_HIGH_ACT)) val |= SUNXI_LCDC_TCON_HSYNC_MASK; if (!(mode->sync & FB_SYNC_VERT_HIGH_ACT)) |