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authorHans de Goede <hdegoede@redhat.com>2014-12-07 21:09:31 +0100
committerHans de Goede <hdegoede@redhat.com>2015-01-14 14:56:37 +0100
commit1aac47bd1bf8f1f4a5f12bf7c8e06a18e5b649b4 (patch)
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parent5af741f1e98457de626f01302138de20c948fd46 (diff)
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sun6i: clock_set_pll5: Calculate k and m rather then hardcoding them
Our old hardcoded k and m values are based on PLL5 being configured in steps of 48 MHz, which is correct for sun6i where the DRAM PLL runs at twice the DRAM CLK, which is usually configured in 24 MHz step. But on the A23 (sun8i) the PLL5 runs at half the DRAM CLK, so we require 12 MHz steps. This commit adjusts clock_set_pll5 to automatically select the best k and m depending on the requested clk rate. Suggested-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
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