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authorPaul Burton <paul.burton@imgtec.com>2013-11-08 11:18:42 +0000
committerDaniel Schwierzeck <daniel.schwierzeck@gmail.com>2013-11-09 17:21:01 +0100
commitfa476f75bfff55772f0ebde3d5e02dc745e70f40 (patch)
tree083e3e4b6f2bf615ee073cdf6d0c25445113bd00 /drivers
parent15c5cdf5aa6b292145e5e3e220ec1f42b11eff6f (diff)
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mips32: detect L1 cache sizes if they're not defined
For boards such as the MIPS Malta with an FPGA core card it is desirable to be able to detect the L1 cache sizes at runtime, since they are not dependant upon the board but on the FPGA bitstream in use. This patch performs that detection when the CONFIG_SYS_[DI]CACHE_SIZE macros are not defined by the board configuration. In cases where the sizes are detected this patch also removes the restriction that the I-cache & D-cache line sizes must be the same, as this is not necessarily true. If the cache sizes are defined by a configuration then they will be hardcoded as before, so this patch will not add overhead to such boards. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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