summaryrefslogtreecommitdiff
path: root/drivers
diff options
context:
space:
mode:
authorMarek Vasut <marex@denx.de>2013-08-26 17:45:23 +0200
committerJagannadha Sutradharudu Teki <jaganna@xilinx.com>2013-08-27 19:39:39 +0530
commita928a36ff91ba585310491f2d8c08ec2d30bc2b0 (patch)
treec8e46d7db9d68165341974287f50cab039394fca /drivers
parent2b26201a2aef0b310b7c04702b0dba5dea493f77 (diff)
downloadu-boot-imx-a928a36ff91ba585310491f2d8c08ec2d30bc2b0.zip
u-boot-imx-a928a36ff91ba585310491f2d8c08ec2d30bc2b0.tar.gz
u-boot-imx-a928a36ff91ba585310491f2d8c08ec2d30bc2b0.tar.bz2
spi: mxs_spi: Configure chipselect after block reset
The chipselect must be written into the CTRL0 register after the SSP block is reset, otherwise the block will always use ChipSelect #0. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/spi/mxs_spi.c12
1 files changed, 3 insertions, 9 deletions
diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c
index 3cf7142..2b9f395 100644
--- a/drivers/spi/mxs_spi.c
+++ b/drivers/spi/mxs_spi.c
@@ -56,8 +56,6 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int mode)
{
struct mxs_spi_slave *mxs_slave;
- struct mxs_ssp_regs *ssp_regs;
- int reg;
if (!spi_cs_is_valid(bus, cs)) {
printf("mxs_spi: invalid bus %d / chip select %d\n", bus, cs);
@@ -74,13 +72,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
mxs_slave->max_khz = max_hz / 1000;
mxs_slave->mode = mode;
mxs_slave->regs = mxs_ssp_regs_by_bus(bus);
- ssp_regs = mxs_slave->regs;
- reg = readl(&ssp_regs->hw_ssp_ctrl0);
- reg &= ~(MXS_SSP_CHIPSELECT_MASK);
- reg |= cs << MXS_SSP_CHIPSELECT_SHIFT;
-
- writel(reg, &ssp_regs->hw_ssp_ctrl0);
return &mxs_slave->slave;
err_init:
@@ -102,7 +94,9 @@ int spi_claim_bus(struct spi_slave *slave)
mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
- writel(SSP_CTRL0_BUS_WIDTH_ONE_BIT, &ssp_regs->hw_ssp_ctrl0);
+ writel((slave->cs << MXS_SSP_CHIPSELECT_SHIFT) |
+ SSP_CTRL0_BUS_WIDTH_ONE_BIT,
+ &ssp_regs->hw_ssp_ctrl0);
reg = SSP_CTRL1_SSP_MODE_SPI | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS;
reg |= (mxs_slave->mode & SPI_CPOL) ? SSP_CTRL1_POLARITY : 0;