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authorMarek Vasut <marex@denx.de>2012-08-31 16:18:10 +0000
committerStefano Babic <sbabic@denx.de>2012-09-06 14:17:55 +0200
commit97ed12cedf9cd47ddc4553c3fa9f3e8f92cba8c3 (patch)
tree4dce75b62cf8142b0dc78ca45c3c5e51787a661d /drivers
parente9f7eafd3cc932d5d6e7e8acd96d5f15679e4a86 (diff)
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MX28: MMC: Avoid DMA DCache race condition
This patch prevents dcache-related problem. The problem manifested itself on the SPI driver, this is just a port to the MMC driver. The scenario is the same. In case an "mmc read" is issued to a buffer which was written right before it and data cache is enabled, the cache eviction might happen during the DMA transfer into the buffer, therefore corrupting the buffer. Clear any cache lines that might contain the buffer to prevent such issue. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/mmc/mxsmmc.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/mmc/mxsmmc.c b/drivers/mmc/mxsmmc.c
index 9a98c6b..c80b41b 100644
--- a/drivers/mmc/mxsmmc.c
+++ b/drivers/mmc/mxsmmc.c
@@ -119,6 +119,10 @@ static int mxsmmc_send_cmd_dma(struct mxsmmc_priv *priv, struct mmc_data *data)
(uint32_t)(priv->desc->cmd.address + cache_data_count));
}
+ /* Invalidate the area, so no writeback into the RAM races with DMA */
+ invalidate_dcache_range((uint32_t)priv->desc->cmd.address,
+ (uint32_t)(priv->desc->cmd.address + cache_data_count));
+
priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM |
(data_count << MXS_DMA_DESC_BYTES_OFFSET);