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authorMichal Simek <monstr@monstr.eu>2007-08-15 21:06:52 +0200
committerMichal Simek <monstr@monstr.eu>2007-08-15 21:06:52 +0200
commit19909edb97140a5ea3139705589bb90e023ab5e1 (patch)
tree6629766d2355d3c01b96b0c5ee6b9fd73502c943 /drivers
parentd1ed28cf36ab6b1d4c479809de7252bf53d2f2d4 (diff)
parent210f463c71917b7a4495c2103c228b9c179ae64d (diff)
downloadu-boot-imx-19909edb97140a5ea3139705589bb90e023ab5e1.zip
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Merge git://www.denx.de/git/u-boot into merge
Diffstat (limited to 'drivers')
-rwxr-xr-x[-rw-r--r--]drivers/Makefile8
-rw-r--r--drivers/ahci.c4
-rwxr-xr-xdrivers/at45.c566
-rw-r--r--drivers/bcm570x.c2322
-rw-r--r--drivers/bcm570x_lm.h207
-rw-r--r--drivers/bcm570x_mm.h58
-rw-r--r--drivers/bios_emulator/Makefile2
-rw-r--r--drivers/bios_emulator/besys.c2
-rw-r--r--drivers/bios_emulator/bios.c2
-rw-r--r--drivers/bios_emulator/biosemu.c3
-rw-r--r--drivers/bios_emulator/x86emu/debug.c4
-rw-r--r--drivers/bios_emulator/x86emu/decode.c4
-rw-r--r--drivers/bios_emulator/x86emu/ops.c5
-rw-r--r--drivers/bios_emulator/x86emu/ops2.c4
-rw-r--r--drivers/bios_emulator/x86emu/prim_ops.c4
-rw-r--r--drivers/bios_emulator/x86emu/sys.c4
-rw-r--r--drivers/dataflash.c279
-rw-r--r--drivers/dm9000x.c15
-rw-r--r--drivers/fsl_i2c.c3
-rw-r--r--drivers/fsl_pci_init.c46
-rw-r--r--drivers/isp116x-hcd.c1413
-rw-r--r--drivers/isp116x.h489
-rw-r--r--drivers/macb.c59
-rw-r--r--drivers/nand/nand_util.c21
-rw-r--r--drivers/pci_auto.c2
-rw-r--r--drivers/qe/qe.c2
-rw-r--r--drivers/qe/qe.h2
-rw-r--r--drivers/qe/uec.c27
-rw-r--r--drivers/qe/uec.h1
-rw-r--r--drivers/qe/uec_phy.c14
-rw-r--r--drivers/qe/uec_phy.h6
-rw-r--r--drivers/rtl8139.c9
-rw-r--r--drivers/tigon3.c9697
-rw-r--r--drivers/tigon3.h3749
-rw-r--r--drivers/tsec.c54
-rw-r--r--drivers/tsec.h4
-rw-r--r--drivers/usb_ohci.c1918
-rw-r--r--drivers/usb_ohci.h445
-rw-r--r--drivers/usbdcore_ep0.c163
-rw-r--r--drivers/usbdcore_mpc8xx.c1400
-rw-r--r--drivers/usbdcore_omap1510.c27
-rw-r--r--drivers/usbtty.c699
-rw-r--r--drivers/usbtty.h60
43 files changed, 14947 insertions, 8856 deletions
diff --git a/drivers/Makefile b/drivers/Makefile
index 881153a..3ee6312 100644..100755
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -27,11 +27,11 @@ include $(TOPDIR)/config.mk
LIB = $(obj)libdrivers.a
-COBJS = 3c589.o 5701rls.o ali512x.o ata_piix.o atmel_usart.o \
+COBJS = 3c589.o 5701rls.o ali512x.o at45.o ata_piix.o atmel_usart.o \
bcm570x.o bcm570x_autoneg.o cfb_console.o cfi_flash.o \
cs8900.o ct69000.o dataflash.o dc2114x.o dm9000x.o \
e1000.o eepro100.o enc28j60.o \
- i8042.o inca-ip_sw.o keyboard.o \
+ i8042.o inca-ip_sw.o isp116x-hcd.o keyboard.o \
lan91c96.o macb.o \
natsemi.o ne2000.o netarm_eth.o netconsole.o \
ns16550.o ns8382x.o ns87308.o ns7520_eth.o omap1510_i2c.o \
@@ -47,7 +47,9 @@ COBJS = 3c589.o 5701rls.o ali512x.o ata_piix.o atmel_usart.o \
status_led.o sym53c8xx.o systemace.o ahci.o \
ti_pci1410a.o tigon3.o tsec.o \
tsi108_eth.o tsi108_i2c.o tsi108_pci.o \
- usbdcore.o usbdcore_ep0.o usbdcore_omap1510.o usbtty.o \
+ usb_ohci.o \
+ usbdcore.o usbdcore_ep0.o usbdcore_mpc8xx.o usbdcore_omap1510.o \
+ usbtty.o \
videomodes.o w83c553f.o \
ks8695eth.o \
pxa_pcmcia.o mpc8xx_pcmcia.o tqm8xx_pcmcia.o \
diff --git a/drivers/ahci.c b/drivers/ahci.c
index ccd4d71..3d82c62 100644
--- a/drivers/ahci.c
+++ b/drivers/ahci.c
@@ -259,8 +259,8 @@ static int ahci_init_one(pci_dev_t pdev)
memset((void *)ataid, 0, sizeof(hd_driveid_t *) * AHCI_MAX_PORTS);
- probe_ent = malloc(sizeof(probe_ent));
- memset(probe_ent, 0, sizeof(probe_ent));
+ probe_ent = malloc(sizeof(struct ahci_probe_ent));
+ memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
probe_ent->dev = pdev;
pci_read_config_dword(pdev, AHCI_PCI_BAR, &iobase);
diff --git a/drivers/at45.c b/drivers/at45.c
new file mode 100755
index 0000000..507ff36
--- /dev/null
+++ b/drivers/at45.c
@@ -0,0 +1,566 @@
+/* Driver for ATMEL DataFlash support
+ * Author : Hamid Ikdoumi (Atmel)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <config.h>
+#include <common.h>
+
+#ifdef CONFIG_HAS_DATAFLASH
+#include <dataflash.h>
+
+/*
+ * spi.c API
+ */
+extern unsigned int AT91F_SpiWrite (AT91PS_DataflashDesc pDesc);
+extern void AT91F_SpiEnable(int cs);
+
+#define AT91C_TIMEOUT_WRDY 200000
+
+
+/*----------------------------------------------------------------------*/
+/* \fn AT91F_DataFlashSendCommand */
+/* \brief Generic function to send a command to the dataflash */
+/*----------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_DataFlashSendCommand(
+ AT91PS_DataFlash pDataFlash,
+ unsigned char OpCode,
+ unsigned int CmdSize,
+ unsigned int DataflashAddress)
+{
+ unsigned int adr;
+
+ if ( (pDataFlash->pDataFlashDesc->state) != IDLE)
+ return DATAFLASH_BUSY;
+
+ /* process the address to obtain page address and byte address */
+ adr = ((DataflashAddress / (pDataFlash->pDevice->pages_size)) <<
+ pDataFlash->pDevice->page_offset) + (DataflashAddress %
+ (pDataFlash->pDevice->pages_size));
+
+ /* fill the command buffer */
+ pDataFlash->pDataFlashDesc->command[0] = OpCode;
+ if (pDataFlash->pDevice->pages_number >= 16384) {
+ pDataFlash->pDataFlashDesc->command[1] =
+ (unsigned char)((adr & 0x0F000000) >> 24);
+ pDataFlash->pDataFlashDesc->command[2] =
+ (unsigned char)((adr & 0x00FF0000) >> 16);
+ pDataFlash->pDataFlashDesc->command[3] =
+ (unsigned char)((adr & 0x0000FF00) >> 8);
+ pDataFlash->pDataFlashDesc->command[4] =
+ (unsigned char)(adr & 0x000000FF);
+ } else {
+ pDataFlash->pDataFlashDesc->command[1] =
+ (unsigned char)((adr & 0x00FF0000) >> 16);
+ pDataFlash->pDataFlashDesc->command[2] =
+ (unsigned char)((adr & 0x0000FF00) >> 8);
+ pDataFlash->pDataFlashDesc->command[3] =
+ (unsigned char)(adr & 0x000000FF);
+ pDataFlash->pDataFlashDesc->command[4] = 0;
+ }
+ pDataFlash->pDataFlashDesc->command[5] = 0;
+ pDataFlash->pDataFlashDesc->command[6] = 0;
+ pDataFlash->pDataFlashDesc->command[7] = 0;
+
+ /* Initialize the SpiData structure for the spi write fuction */
+ pDataFlash->pDataFlashDesc->tx_cmd_pt =
+ pDataFlash->pDataFlashDesc->command;
+ pDataFlash->pDataFlashDesc->tx_cmd_size = CmdSize;
+ pDataFlash->pDataFlashDesc->rx_cmd_pt =
+ pDataFlash->pDataFlashDesc->command;
+ pDataFlash->pDataFlashDesc->rx_cmd_size = CmdSize;
+
+ /* send the command and read the data */
+ return AT91F_SpiWrite (pDataFlash->pDataFlashDesc); }
+
+
+/*----------------------------------------------------------------------*/
+/* \fn AT91F_DataFlashGetStatus */
+/* \brief Read the status register of the dataflash */
+/*----------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_DataFlashGetStatus(AT91PS_DataflashDesc pDesc)
+{
+ AT91S_DataFlashStatus status;
+
+ /* if a transfert is in progress ==> return 0 */
+ if( (pDesc->state) != IDLE)
+ return DATAFLASH_BUSY;
+
+ /* first send the read status command (D7H) */
+ pDesc->command[0] = DB_STATUS;
+ pDesc->command[1] = 0;
+
+ pDesc->DataFlash_state = GET_STATUS;
+ pDesc->tx_data_size = 0; /* Transmit the command */
+ /* and receive response */
+ pDesc->tx_cmd_pt = pDesc->command;
+ pDesc->rx_cmd_pt = pDesc->command;
+ pDesc->rx_cmd_size = 2;
+ pDesc->tx_cmd_size = 2;
+ status = AT91F_SpiWrite (pDesc);
+
+ pDesc->DataFlash_state = *( (unsigned char *) (pDesc->rx_cmd_pt) +1);
+
+ return status;
+}
+
+
+/*----------------------------------------------------------------------*/
+/* \fn AT91F_DataFlashWaitReady */
+/* \brief wait for dataflash ready (bit7 of the status register == 1) */
+/*----------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_DataFlashWaitReady(AT91PS_DataflashDesc
+pDataFlashDesc, unsigned int timeout)
+{
+ pDataFlashDesc->DataFlash_state = IDLE;
+
+ do {
+ AT91F_DataFlashGetStatus(pDataFlashDesc);
+ timeout--;
+ } while( ((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) &&
+ (timeout > 0) );
+
+ if((pDataFlashDesc->DataFlash_state & 0x80) != 0x80)
+ return DATAFLASH_ERROR;
+
+ return DATAFLASH_OK;
+}
+
+
+/*--------------------------------------------------------------------------*/
+/* Function Name : AT91F_DataFlashContinuousRead */
+/* Object : Continuous stream Read */
+/* Input Parameters : DataFlash Service */
+/* : <src> = dataflash address */
+/* : <*dataBuffer> = data buffer pointer */
+/* : <sizeToRead> = data buffer size */
+/* Return value : State of the dataflash */
+/*--------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_DataFlashContinuousRead (
+ AT91PS_DataFlash pDataFlash,
+ int src,
+ unsigned char *dataBuffer,
+ int sizeToRead )
+{
+ AT91S_DataFlashStatus status;
+ /* Test the size to read in the device */
+ if ( (src + sizeToRead) >
+ (pDataFlash->pDevice->pages_size *
+ (pDataFlash->pDevice->pages_number)))
+ return DATAFLASH_MEMORY_OVERFLOW;
+
+ pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer;
+ pDataFlash->pDataFlashDesc->rx_data_size = sizeToRead;
+ pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer;
+ pDataFlash->pDataFlashDesc->tx_data_size = sizeToRead;
+
+ status = AT91F_DataFlashSendCommand
+ (pDataFlash, DB_CONTINUOUS_ARRAY_READ, 8, src);
+ /* Send the command to the dataflash */
+ return(status);
+}
+
+
+/*---------------------------------------------------------------------------*/
+/* Function Name : AT91F_DataFlashPagePgmBuf */
+/* Object : Main memory page program thru buffer 1 or buffer 2 */
+/* Input Parameters : DataFlash Service */
+/* : <*src> = Source buffer */
+/* : <dest> = dataflash destination address */
+/* : <SizeToWrite> = data buffer size */
+/* Return value : State of the dataflash */
+/*---------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf(
+ AT91PS_DataFlash pDataFlash,
+ unsigned char *src,
+ unsigned int dest,
+ unsigned int SizeToWrite)
+{
+ int cmdsize;
+ pDataFlash->pDataFlashDesc->tx_data_pt = src;
+ pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite;
+ pDataFlash->pDataFlashDesc->rx_data_pt = src;
+ pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite;
+
+ cmdsize = 4;
+ /* Send the command to the dataflash */
+ if (pDataFlash->pDevice->pages_number >= 16384)
+ cmdsize = 5;
+ return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_PGM_BUF1,
+cmdsize, dest)); }
+
+
+/*---------------------------------------------------------------------------*/
+/* Function Name : AT91F_MainMemoryToBufferTransfert */
+/* Object : Read a page in the SRAM Buffer 1 or 2 */
+/* Input Parameters : DataFlash Service */
+/* : Page concerned */
+/* : */
+/* Return value : State of the dataflash */
+/*---------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert(
+ AT91PS_DataFlash pDataFlash,
+ unsigned char BufferCommand,
+ unsigned int page)
+{
+ int cmdsize;
+ /* Test if the buffer command is legal */
+ if ((BufferCommand != DB_PAGE_2_BUF1_TRF)
+ && (BufferCommand != DB_PAGE_2_BUF2_TRF))
+ return DATAFLASH_BAD_COMMAND;
+
+ /* no data to transmit or receive */
+ pDataFlash->pDataFlashDesc->tx_data_size = 0;
+ cmdsize = 4;
+ if (pDataFlash->pDevice->pages_number >= 16384)
+ cmdsize = 5;
+ return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize,
+page*pDataFlash->pDevice->pages_size));
+}
+
+
+/*-------------------------------------------------------------------------- */
+/* Function Name : AT91F_DataFlashWriteBuffer */
+/* Object : Write data to the internal sram buffer 1 or 2 */
+/* Input Parameters : DataFlash Service */
+/* : <BufferCommand> = command to write buffer1 or 2 */
+/* : <*dataBuffer> = data buffer to write */
+/* : <bufferAddress> = address in the internal buffer */
+/* : <SizeToWrite> = data buffer size */
+/* Return value : State of the dataflash */
+/*---------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer (
+ AT91PS_DataFlash pDataFlash,
+ unsigned char BufferCommand,
+ unsigned char *dataBuffer,
+ unsigned int bufferAddress,
+ int SizeToWrite )
+{
+ int cmdsize;
+ /* Test if the buffer command is legal */
+ if ((BufferCommand != DB_BUF1_WRITE)
+ && (BufferCommand != DB_BUF2_WRITE))
+ return DATAFLASH_BAD_COMMAND;
+
+ /* buffer address must be lower than page size */
+ if (bufferAddress > pDataFlash->pDevice->pages_size)
+ return DATAFLASH_BAD_ADDRESS;
+
+ if ( (pDataFlash->pDataFlashDesc->state) != IDLE)
+ return DATAFLASH_BUSY;
+
+ /* Send first Write Command */
+ pDataFlash->pDataFlashDesc->command[0] = BufferCommand;
+ pDataFlash->pDataFlashDesc->command[1] = 0;
+ if (pDataFlash->pDevice->pages_number >= 16384) {
+ pDataFlash->pDataFlashDesc->command[2] = 0;
+ pDataFlash->pDataFlashDesc->command[3] =
+ (unsigned char)(((unsigned int)(bufferAddress &
+ pDataFlash->pDevice->byte_mask)) >> 8);
+ pDataFlash->pDataFlashDesc->command[4] =
+ (unsigned char)((unsigned int)bufferAddress & 0x00FF);
+ cmdsize = 5;
+ } else {
+ pDataFlash->pDataFlashDesc->command[2] =
+ (unsigned char)(((unsigned int)(bufferAddress &
+ pDataFlash->pDevice->byte_mask)) >> 8);
+ pDataFlash->pDataFlashDesc->command[3] =
+ (unsigned char)((unsigned int)bufferAddress & 0x00FF);
+ pDataFlash->pDataFlashDesc->command[4] = 0;
+ cmdsize = 4;
+ }
+
+ pDataFlash->pDataFlashDesc->tx_cmd_pt =
+ pDataFlash->pDataFlashDesc->command;
+ pDataFlash->pDataFlashDesc->tx_cmd_size = cmdsize;
+ pDataFlash->pDataFlashDesc->rx_cmd_pt =
+ pDataFlash->pDataFlashDesc->command;
+ pDataFlash->pDataFlashDesc->rx_cmd_size = cmdsize;
+
+ pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer;
+ pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer;
+ pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite;
+ pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite;
+
+ return AT91F_SpiWrite(pDataFlash->pDataFlashDesc);
+}
+
+/*---------------------------------------------------------------------------*/
+/* Function Name : AT91F_PageErase */
+/* Object : Erase a page */
+/* Input Parameters : DataFlash Service */
+/* : Page concerned */
+/* : */
+/* Return value : State of the dataflash */
+/*---------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_PageErase(
+ AT91PS_DataFlash pDataFlash,
+ unsigned int page)
+{
+ int cmdsize;
+ /* Test if the buffer command is legal */
+ /* no data to transmit or receive */
+ pDataFlash->pDataFlashDesc->tx_data_size = 0;
+
+ cmdsize = 4;
+ if (pDataFlash->pDevice->pages_number >= 16384)
+ cmdsize = 5;
+ return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_ERASE, cmdsize,
+page*pDataFlash->pDevice->pages_size));
+}
+
+
+/*---------------------------------------------------------------------------*/
+/* Function Name : AT91F_BlockErase */
+/* Object : Erase a Block */
+/* Input Parameters : DataFlash Service */
+/* : Page concerned */
+/* : */
+/* Return value : State of the dataflash */
+/*---------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_BlockErase(
+ AT91PS_DataFlash pDataFlash,
+ unsigned int block)
+{
+ int cmdsize;
+ /* Test if the buffer command is legal */
+ /* no data to transmit or receive */
+ pDataFlash->pDataFlashDesc->tx_data_size = 0;
+ cmdsize = 4;
+ if (pDataFlash->pDevice->pages_number >= 16384)
+ cmdsize = 5;
+ return(AT91F_DataFlashSendCommand (pDataFlash, DB_BLOCK_ERASE,cmdsize,
+block*8*pDataFlash->pDevice->pages_size));
+}
+
+/*---------------------------------------------------------------------------*/
+/* Function Name : AT91F_WriteBufferToMain */
+/* Object : Write buffer to the main memory */
+/* Input Parameters : DataFlash Service */
+/* : <BufferCommand> = command to send to buffer1 or buffer2 */
+/* : <dest> = main memory address */
+/* Return value : State of the dataflash */
+/*---------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_WriteBufferToMain (
+ AT91PS_DataFlash pDataFlash,
+ unsigned char BufferCommand,
+ unsigned int dest )
+{
+ int cmdsize;
+ /* Test if the buffer command is correct */
+ if ((BufferCommand != DB_BUF1_PAGE_PGM) &&
+ (BufferCommand != DB_BUF1_PAGE_ERASE_PGM) &&
+ (BufferCommand != DB_BUF2_PAGE_PGM) &&
+ (BufferCommand != DB_BUF2_PAGE_ERASE_PGM) )
+ return DATAFLASH_BAD_COMMAND;
+
+ /* no data to transmit or receive */
+ pDataFlash->pDataFlashDesc->tx_data_size = 0;
+
+ cmdsize = 4;
+ if (pDataFlash->pDevice->pages_number >= 16384)
+ cmdsize = 5;
+ /* Send the command to the dataflash */
+ return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize,
+ dest)); }
+
+
+/*---------------------------------------------------------------------------*/
+/* Function Name : AT91F_PartialPageWrite */
+/* Object : Erase partielly a page */
+/* Input Parameters : <page> = page number */
+/* : <AdrInpage> = adr to begin the fading */
+/* : <length> = Number of bytes to erase */
+/*---------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_PartialPageWrite (
+ AT91PS_DataFlash pDataFlash,
+ unsigned char *src,
+ unsigned int dest,
+ unsigned int size)
+{
+ unsigned int page;
+ unsigned int AdrInPage;
+
+ page = dest / (pDataFlash->pDevice->pages_size);
+ AdrInPage = dest % (pDataFlash->pDevice->pages_size);
+
+ /* Read the contents of the page in the Sram Buffer */
+ AT91F_MainMemoryToBufferTransfert(pDataFlash,
+ DB_PAGE_2_BUF1_TRF, page);
+ AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
+ AT91C_TIMEOUT_WRDY);
+ /*Update the SRAM buffer */
+ AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src,
+ AdrInPage, size);
+
+ AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
+ AT91C_TIMEOUT_WRDY);
+
+ /* Erase page if a 128 Mbits device */
+ if (pDataFlash->pDevice->pages_number >= 16384) {
+ AT91F_PageErase(pDataFlash, page);
+ /* Rewrite the modified Sram Buffer in the main memory */
+ AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
+ AT91C_TIMEOUT_WRDY);
+ }
+
+ /* Rewrite the modified Sram Buffer in the main memory */
+ return(AT91F_WriteBufferToMain(pDataFlash, DB_BUF1_PAGE_ERASE_PGM,
+ (page*pDataFlash->pDevice->pages_size)));
+}
+
+/*---------------------------------------------------------------------------*/
+/* Function Name : AT91F_DataFlashWrite */
+/* Object : */
+/* Input Parameters : <*src> = Source buffer */
+/* : <dest> = dataflash adress */
+/* : <size> = data buffer size */
+/*---------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_DataFlashWrite(
+ AT91PS_DataFlash pDataFlash,
+ unsigned char *src,
+ int dest,
+ int size )
+{
+ unsigned int length;
+ unsigned int page;
+ unsigned int status;
+
+ AT91F_SpiEnable(pDataFlash->pDevice->cs);
+
+ if ( (dest + size) > (pDataFlash->pDevice->pages_size *
+ (pDataFlash->pDevice->pages_number)))
+ return DATAFLASH_MEMORY_OVERFLOW;
+
+ /* If destination does not fit a page start address */
+ if ((dest % ((unsigned int)(pDataFlash->pDevice->pages_size))) != 0 )
+ {
+ length = pDataFlash->pDevice->pages_size -
+ (dest %
+ ((unsigned int)
+ (pDataFlash->pDevice->pages_size)));
+
+ if (size < length)
+ length = size;
+
+ if(!AT91F_PartialPageWrite(pDataFlash,src, dest, length))
+ return DATAFLASH_ERROR;
+
+ AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
+ AT91C_TIMEOUT_WRDY);
+
+ /* Update size, source and destination pointers */
+ size -= length;
+ dest += length;
+ src += length;
+ }
+
+ while (( size - pDataFlash->pDevice->pages_size ) >= 0 ) {
+ /* program dataflash page */
+ page = (unsigned int)dest / (pDataFlash->pDevice->pages_size);
+
+ status = AT91F_DataFlashWriteBuffer(pDataFlash,
+ DB_BUF1_WRITE, src, 0,
+ pDataFlash->pDevice->pages_size);
+ AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
+ AT91C_TIMEOUT_WRDY);
+
+ status = AT91F_PageErase(pDataFlash, page);
+ AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
+ AT91C_TIMEOUT_WRDY);
+ if (!status)
+ return DATAFLASH_ERROR;
+
+ status = AT91F_WriteBufferToMain (pDataFlash,
+ DB_BUF1_PAGE_PGM, dest);
+ if(!status)
+ return DATAFLASH_ERROR;
+
+ AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
+ AT91C_TIMEOUT_WRDY);
+
+ /* Update size, source and destination pointers */
+ size -= pDataFlash->pDevice->pages_size;
+ dest += pDataFlash->pDevice->pages_size;
+ src += pDataFlash->pDevice->pages_size;
+ }
+
+ /* If still some bytes to read */
+ if ( size > 0 ) {
+ /* program dataflash page */
+ if(!AT91F_PartialPageWrite(pDataFlash, src, dest, size) )
+ return DATAFLASH_ERROR;
+
+ AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
+ AT91C_TIMEOUT_WRDY);
+ }
+ return DATAFLASH_OK;
+}
+
+
+/*---------------------------------------------------------------------------*/
+/* Function Name : AT91F_DataFlashRead */
+/* Object : Read a block in dataflash */
+/* Input Parameters : */
+/* Return value : */
+/*---------------------------------------------------------------------------*/
+int AT91F_DataFlashRead(
+ AT91PS_DataFlash pDataFlash,
+ unsigned long addr,
+ unsigned long size,
+ char *buffer)
+{
+ unsigned long SizeToRead;
+
+ AT91F_SpiEnable(pDataFlash->pDevice->cs);
+
+ if(AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
+ AT91C_TIMEOUT_WRDY) != DATAFLASH_OK)
+ return -1;
+
+ while (size) {
+ SizeToRead = (size < 0x8000)? size:0x8000;
+
+ if (AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc,
+ AT91C_TIMEOUT_WRDY) != DATAFLASH_OK)
+ return -1;
+
+ if (AT91F_DataFlashContinuousRead (pDataFlash, addr,
+ (uchar *) buffer, SizeToRead) != DATAFLASH_OK)
+ return -1;
+
+ size -= SizeToRead;
+ addr += SizeToRead;
+ buffer += SizeToRead;
+ }
+
+ return DATAFLASH_OK;
+}
+
+/*---------------------------------------------------------------------------*/
+/* Function Name : AT91F_DataflashProbe */
+/* Object : */
+/* Input Parameters : */
+/* Return value : Dataflash status register */
+/*---------------------------------------------------------------------------*/
+int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc) {
+ AT91F_SpiEnable(cs);
+ AT91F_DataFlashGetStatus(pDesc);
+ return((pDesc->command[1] == 0xFF)? 0: pDesc->command[1] & 0x3C);
+}
+#endif
diff --git a/drivers/bcm570x.c b/drivers/bcm570x.c
index 703cda4..c8f4064 100644
--- a/drivers/bcm570x.c
+++ b/drivers/bcm570x.c
@@ -18,7 +18,6 @@
#include <pci.h>
#include <malloc.h>
-
/*
* PCI Registers and definitions.
*/
@@ -31,7 +30,6 @@
#define BCM570X_MBAR 0x80100000
#define BCM570X_ILINE 1
-
#define SECOND_USEC 1000000
#define MAX_PACKET_SIZE 1600
#define MAX_UNITS 4
@@ -39,62 +37,61 @@
/* Globals to this module */
int initialized = 0;
unsigned int ioBase = 0;
-volatile PLM_DEVICE_BLOCK pDevice = NULL; /* 570x softc */
-volatile PUM_DEVICE_BLOCK pUmDevice = NULL;
+volatile PLM_DEVICE_BLOCK pDevice = NULL; /* 570x softc */
+volatile PUM_DEVICE_BLOCK pUmDevice = NULL;
/* Used to pass the full-duplex flag, etc. */
-int line_speed[MAX_UNITS] = {0,0,0,0};
-static int full_duplex[MAX_UNITS] = {1,1,1,1};
-static int rx_flow_control[MAX_UNITS] = {0,0,0,0};
-static int tx_flow_control[MAX_UNITS] = {0,0,0,0};
-static int auto_flow_control[MAX_UNITS] = {0,0,0,0};
-static int tx_checksum[MAX_UNITS] = {1,1,1,1};
-static int rx_checksum[MAX_UNITS] = {1,1,1,1};
-static int auto_speed[MAX_UNITS] = {1,1,1,1};
+int line_speed[MAX_UNITS] = { 0, 0, 0, 0 };
+static int full_duplex[MAX_UNITS] = { 1, 1, 1, 1 };
+static int rx_flow_control[MAX_UNITS] = { 0, 0, 0, 0 };
+static int tx_flow_control[MAX_UNITS] = { 0, 0, 0, 0 };
+static int auto_flow_control[MAX_UNITS] = { 0, 0, 0, 0 };
+static int tx_checksum[MAX_UNITS] = { 1, 1, 1, 1 };
+static int rx_checksum[MAX_UNITS] = { 1, 1, 1, 1 };
+static int auto_speed[MAX_UNITS] = { 1, 1, 1, 1 };
#if JUMBO_FRAMES
/* Jumbo MTU for interfaces. */
-static int mtu[MAX_UNITS] = {0,0,0,0};
+static int mtu[MAX_UNITS] = { 0, 0, 0, 0 };
#endif
/* Turn on Wake-on lan for a device unit */
-static int enable_wol[MAX_UNITS] = {0,0,0,0};
+static int enable_wol[MAX_UNITS] = { 0, 0, 0, 0 };
#define TX_DESC_CNT DEFAULT_TX_PACKET_DESC_COUNT
static unsigned int tx_pkt_desc_cnt[MAX_UNITS] =
- {TX_DESC_CNT,TX_DESC_CNT,TX_DESC_CNT, TX_DESC_CNT};
+ { TX_DESC_CNT, TX_DESC_CNT, TX_DESC_CNT, TX_DESC_CNT };
#define RX_DESC_CNT DEFAULT_STD_RCV_DESC_COUNT
static unsigned int rx_std_desc_cnt[MAX_UNITS] =
- {RX_DESC_CNT,RX_DESC_CNT,RX_DESC_CNT,RX_DESC_CNT};
+ { RX_DESC_CNT, RX_DESC_CNT, RX_DESC_CNT, RX_DESC_CNT };
-static unsigned int rx_adaptive_coalesce[MAX_UNITS] = {1,1,1,1};
+static unsigned int rx_adaptive_coalesce[MAX_UNITS] = { 1, 1, 1, 1 };
#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
#define JBO_DESC_CNT DEFAULT_JUMBO_RCV_DESC_COUNT
static unsigned int rx_jumbo_desc_cnt[MAX_UNITS] =
- {JBO_DESC_CNT, JBO_DESC_CNT, JBO_DESC_CNT, JBO_DESC_CNT};
+ { JBO_DESC_CNT, JBO_DESC_CNT, JBO_DESC_CNT, JBO_DESC_CNT };
#endif
#define RX_COAL_TK DEFAULT_RX_COALESCING_TICKS
static unsigned int rx_coalesce_ticks[MAX_UNITS] =
- {RX_COAL_TK, RX_COAL_TK, RX_COAL_TK, RX_COAL_TK};
+ { RX_COAL_TK, RX_COAL_TK, RX_COAL_TK, RX_COAL_TK };
#define RX_COAL_FM DEFAULT_RX_MAX_COALESCED_FRAMES
static unsigned int rx_max_coalesce_frames[MAX_UNITS] =
- {RX_COAL_FM, RX_COAL_FM, RX_COAL_FM, RX_COAL_FM};
+ { RX_COAL_FM, RX_COAL_FM, RX_COAL_FM, RX_COAL_FM };
#define TX_COAL_TK DEFAULT_TX_COALESCING_TICKS
static unsigned int tx_coalesce_ticks[MAX_UNITS] =
- {TX_COAL_TK, TX_COAL_TK, TX_COAL_TK, TX_COAL_TK};
+ { TX_COAL_TK, TX_COAL_TK, TX_COAL_TK, TX_COAL_TK };
#define TX_COAL_FM DEFAULT_TX_MAX_COALESCED_FRAMES
static unsigned int tx_max_coalesce_frames[MAX_UNITS] =
- {TX_COAL_FM, TX_COAL_FM, TX_COAL_FM, TX_COAL_FM};
+ { TX_COAL_FM, TX_COAL_FM, TX_COAL_FM, TX_COAL_FM };
#define ST_COAL_TK DEFAULT_STATS_COALESCING_TICKS
static unsigned int stats_coalesce_ticks[MAX_UNITS] =
- {ST_COAL_TK, ST_COAL_TK, ST_COAL_TK, ST_COAL_TK};
-
+ { ST_COAL_TK, ST_COAL_TK, ST_COAL_TK, ST_COAL_TK };
/*
* Legitimate values for BCM570x device types
@@ -134,707 +131,701 @@ typedef enum {
/* Chip-Rev names for each device-type */
static struct {
- char* name;
+ char *name;
} chip_rev[] = {
- {"BCM5700VIGIL"},
- {"BCM5700A6"},
- {"BCM5700T6"},
- {"BCM5700A9"},
- {"BCM5700T9"},
- {"BCM5700"},
- {"BCM5701A5"},
- {"BCM5701T1"},
- {"BCM5701T8"},
- {"BCM5701A7"},
- {"BCM5701A10"},
- {"BCM5701A12"},
- {"BCM5701"},
- {"BCM5702"},
- {"BCM5703"},
- {"BCM5703A31"},
- {"TC996T"},
- {"TC996ST"},
- {"TC996SSX"},
- {"TC996SX"},
- {"TC996BT"},
- {"TC997T"},
- {"TC997SX"},
- {"TC1000T"},
- {"TC940BR01"},
- {"TC942BR01"},
- {"NC6770"},
- {"NC7760"},
- {"NC7770"},
- {"NC7780"},
- {0}
+ {
+ "BCM5700VIGIL"}, {
+ "BCM5700A6"}, {
+ "BCM5700T6"}, {
+ "BCM5700A9"}, {
+ "BCM5700T9"}, {
+ "BCM5700"}, {
+ "BCM5701A5"}, {
+ "BCM5701T1"}, {
+ "BCM5701T8"}, {
+ "BCM5701A7"}, {
+ "BCM5701A10"}, {
+ "BCM5701A12"}, {
+ "BCM5701"}, {
+ "BCM5702"}, {
+ "BCM5703"}, {
+ "BCM5703A31"}, {
+ "TC996T"}, {
+ "TC996ST"}, {
+ "TC996SSX"}, {
+ "TC996SX"}, {
+ "TC996BT"}, {
+ "TC997T"}, {
+ "TC997SX"}, {
+ "TC1000T"}, {
+ "TC940BR01"}, {
+ "TC942BR01"}, {
+ "NC6770"}, {
+ "NC7760"}, {
+ "NC7770"}, {
+ "NC7780"}, {
+ 0}
};
-
/* indexed by board_t, above */
static struct {
- char *name;
+ char *name;
} board_info[] = {
- { "Broadcom Vigil B5700 1000Base-T" },
- { "Broadcom BCM5700 1000Base-T" },
- { "Broadcom BCM5700 1000Base-SX" },
- { "Broadcom BCM5700 1000Base-SX" },
- { "Broadcom BCM5700 1000Base-T" },
- { "Broadcom BCM5700" },
- { "Broadcom BCM5701 1000Base-T" },
- { "Broadcom BCM5701 1000Base-T" },
- { "Broadcom BCM5701 1000Base-T" },
- { "Broadcom BCM5701 1000Base-SX" },
- { "Broadcom BCM5701 1000Base-T" },
- { "Broadcom BCM5701 1000Base-T" },
- { "Broadcom BCM5701" },
- { "Broadcom BCM5702 1000Base-T" },
- { "Broadcom BCM5703 1000Base-T" },
- { "Broadcom BCM5703 1000Base-SX" },
- { "3Com 3C996 10/100/1000 Server NIC" },
- { "3Com 3C996 10/100/1000 Server NIC" },
- { "3Com 3C996 Gigabit Fiber-SX Server NIC" },
- { "3Com 3C996 Gigabit Fiber-SX Server NIC" },
- { "3Com 3C996B Gigabit Server NIC" },
- { "3Com 3C997 Gigabit Server NIC" },
- { "3Com 3C997 Gigabit Fiber-SX Server NIC" },
- { "3Com 3C1000 Gigabit NIC" },
- { "3Com 3C940 Gigabit LOM (21X21)" },
- { "3Com 3C942 Gigabit LOM (31X31)" },
- { "Compaq NC6770 Gigabit Server Adapter" },
- { "Compaq NC7760 Gigabit Server Adapter" },
- { "Compaq NC7770 Gigabit Server Adapter" },
- { "Compaq NC7780 Gigabit Server Adapter" },
- { 0 },
-};
+ {
+ "Broadcom Vigil B5700 1000Base-T"}, {
+ "Broadcom BCM5700 1000Base-T"}, {
+ "Broadcom BCM5700 1000Base-SX"}, {
+ "Broadcom BCM5700 1000Base-SX"}, {
+ "Broadcom BCM5700 1000Base-T"}, {
+ "Broadcom BCM5700"}, {
+ "Broadcom BCM5701 1000Base-T"}, {
+ "Broadcom BCM5701 1000Base-T"}, {
+ "Broadcom BCM5701 1000Base-T"}, {
+ "Broadcom BCM5701 1000Base-SX"}, {
+ "Broadcom BCM5701 1000Base-T"}, {
+ "Broadcom BCM5701 1000Base-T"}, {
+ "Broadcom BCM5701"}, {
+ "Broadcom BCM5702 1000Base-T"}, {
+ "Broadcom BCM5703 1000Base-T"}, {
+ "Broadcom BCM5703 1000Base-SX"}, {
+ "3Com 3C996 10/100/1000 Server NIC"}, {
+ "3Com 3C996 10/100/1000 Server NIC"}, {
+ "3Com 3C996 Gigabit Fiber-SX Server NIC"}, {
+ "3Com 3C996 Gigabit Fiber-SX Server NIC"}, {
+ "3Com 3C996B Gigabit Server NIC"}, {
+ "3Com 3C997 Gigabit Server NIC"}, {
+ "3Com 3C997 Gigabit Fiber-SX Server NIC"}, {
+ "3Com 3C1000 Gigabit NIC"}, {
+ "3Com 3C940 Gigabit LOM (21X21)"}, {
+ "3Com 3C942 Gigabit LOM (31X31)"}, {
+ "Compaq NC6770 Gigabit Server Adapter"}, {
+ "Compaq NC7760 Gigabit Server Adapter"}, {
+ "Compaq NC7770 Gigabit Server Adapter"}, {
+ "Compaq NC7780 Gigabit Server Adapter"}, {
+0},};
/* PCI Devices which use the 570x chipset */
struct pci_device_table {
- unsigned short vendor_id, device_id; /* Vendor/DeviceID */
- unsigned short subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
- unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */
- unsigned long board_id; /* Data private to the driver */
- int io_size, min_latency;
+ unsigned short vendor_id, device_id; /* Vendor/DeviceID */
+ unsigned short subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
+ unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */
+ unsigned long board_id; /* Data private to the driver */
+ int io_size, min_latency;
} bcm570xDevices[] = {
- {0x14e4, 0x1644, 0x1014, 0x0277, 0, 0, BCM5700VIGIL ,128,32},
- {0x14e4, 0x1644, 0x14e4, 0x1644, 0, 0, BCM5700A6 ,128,32},
- {0x14e4, 0x1644, 0x14e4, 0x2, 0, 0, BCM5700T6 ,128,32},
- {0x14e4, 0x1644, 0x14e4, 0x3, 0, 0, BCM5700A9 ,128,32},
- {0x14e4, 0x1644, 0x14e4, 0x4, 0, 0, BCM5700T9 ,128,32},
- {0x14e4, 0x1644, 0x1028, 0xd1, 0, 0, BCM5700 ,128,32},
- {0x14e4, 0x1644, 0x1028, 0x0106, 0, 0, BCM5700 ,128,32},
- {0x14e4, 0x1644, 0x1028, 0x0109, 0, 0, BCM5700 ,128,32},
- {0x14e4, 0x1644, 0x1028, 0x010a, 0, 0, BCM5700 ,128,32},
- {0x14e4, 0x1644, 0x10b7, 0x1000, 0, 0, TC996T ,128,32},
- {0x14e4, 0x1644, 0x10b7, 0x1001, 0, 0, TC996ST ,128,32},
- {0x14e4, 0x1644, 0x10b7, 0x1002, 0, 0, TC996SSX ,128,32},
- {0x14e4, 0x1644, 0x10b7, 0x1003, 0, 0, TC997T ,128,32},
- {0x14e4, 0x1644, 0x10b7, 0x1005, 0, 0, TC997SX ,128,32},
- {0x14e4, 0x1644, 0x10b7, 0x1008, 0, 0, TC942BR01 ,128,32},
- {0x14e4, 0x1644, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5700 ,128,32},
- {0x14e4, 0x1645, 0x14e4, 1, 0, 0, BCM5701A5 ,128,32},
- {0x14e4, 0x1645, 0x14e4, 5, 0, 0, BCM5701T1 ,128,32},
- {0x14e4, 0x1645, 0x14e4, 6, 0, 0, BCM5701T8 ,128,32},
- {0x14e4, 0x1645, 0x14e4, 7, 0, 0, BCM5701A7 ,128,32},
- {0x14e4, 0x1645, 0x14e4, 8, 0, 0, BCM5701A10 ,128,32},
- {0x14e4, 0x1645, 0x14e4, 0x8008, 0, 0, BCM5701A12 ,128,32},
- {0x14e4, 0x1645, 0x0e11, 0xc1, 0, 0, NC6770 ,128,32},
- {0x14e4, 0x1645, 0x0e11, 0x7c, 0, 0, NC7770 ,128,32},
- {0x14e4, 0x1645, 0x0e11, 0x85, 0, 0, NC7780 ,128,32},
- {0x14e4, 0x1645, 0x1028, 0x0121, 0, 0, BCM5701 ,128,32},
- {0x14e4, 0x1645, 0x10b7, 0x1004, 0, 0, TC996SX ,128,32},
- {0x14e4, 0x1645, 0x10b7, 0x1006, 0, 0, TC996BT ,128,32},
- {0x14e4, 0x1645, 0x10b7, 0x1007, 0, 0, TC1000T ,128,32},
- {0x14e4, 0x1645, 0x10b7, 0x1008, 0, 0, TC940BR01 ,128,32},
- {0x14e4, 0x1645, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5701 ,128,32},
- {0x14e4, 0x1646, 0x14e4, 0x8009, 0, 0, BCM5702 ,128,32},
- {0x14e4, 0x1646, 0x0e11, 0xbb, 0, 0, NC7760 ,128,32},
- {0x14e4, 0x1646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5702 ,128,32},
- {0x14e4, 0x16a6, 0x14e4, 0x8009, 0, 0, BCM5702 ,128,32},
- {0x14e4, 0x16a6, 0x0e11, 0xbb, 0, 0, NC7760 ,128,32},
- {0x14e4, 0x16a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5702 ,128,32},
- {0x14e4, 0x1647, 0x14e4, 0x0009, 0, 0, BCM5703 ,128,32},
- {0x14e4, 0x1647, 0x14e4, 0x000a, 0, 0, BCM5703A31 ,128,32},
- {0x14e4, 0x1647, 0x14e4, 0x000b, 0, 0, BCM5703 ,128,32},
- {0x14e4, 0x1647, 0x14e4, 0x800a, 0, 0, BCM5703 ,128,32},
- {0x14e4, 0x1647, 0x0e11, 0x9a, 0, 0, NC7770 ,128,32},
- {0x14e4, 0x1647, 0x0e11, 0x99, 0, 0, NC7780 ,128,32},
- {0x14e4, 0x1647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5703 ,128,32},
- {0x14e4, 0x16a7, 0x14e4, 0x0009, 0, 0, BCM5703 ,128,32},
- {0x14e4, 0x16a7, 0x14e4, 0x000a, 0, 0, BCM5703A31 ,128,32},
- {0x14e4, 0x16a7, 0x14e4, 0x000b, 0, 0, BCM5703 ,128,32},
- {0x14e4, 0x16a7, 0x14e4, 0x800a, 0, 0, BCM5703 ,128,32},
- {0x14e4, 0x16a7, 0x0e11, 0x9a, 0, 0, NC7770 ,128,32},
- {0x14e4, 0x16a7, 0x0e11, 0x99, 0, 0, NC7780 ,128,32},
- {0x14e4, 0x16a7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5703 ,128,32}
+ {
+ 0x14e4, 0x1644, 0x1014, 0x0277, 0, 0, BCM5700VIGIL, 128, 32}, {
+ 0x14e4, 0x1644, 0x14e4, 0x1644, 0, 0, BCM5700A6, 128, 32}, {
+ 0x14e4, 0x1644, 0x14e4, 0x2, 0, 0, BCM5700T6, 128, 32}, {
+ 0x14e4, 0x1644, 0x14e4, 0x3, 0, 0, BCM5700A9, 128, 32}, {
+ 0x14e4, 0x1644, 0x14e4, 0x4, 0, 0, BCM5700T9, 128, 32}, {
+ 0x14e4, 0x1644, 0x1028, 0xd1, 0, 0, BCM5700, 128, 32}, {
+ 0x14e4, 0x1644, 0x1028, 0x0106, 0, 0, BCM5700, 128, 32}, {
+ 0x14e4, 0x1644, 0x1028, 0x0109, 0, 0, BCM5700, 128, 32}, {
+ 0x14e4, 0x1644, 0x1028, 0x010a, 0, 0, BCM5700, 128, 32}, {
+ 0x14e4, 0x1644, 0x10b7, 0x1000, 0, 0, TC996T, 128, 32}, {
+ 0x14e4, 0x1644, 0x10b7, 0x1001, 0, 0, TC996ST, 128, 32}, {
+ 0x14e4, 0x1644, 0x10b7, 0x1002, 0, 0, TC996SSX, 128, 32}, {
+ 0x14e4, 0x1644, 0x10b7, 0x1003, 0, 0, TC997T, 128, 32}, {
+ 0x14e4, 0x1644, 0x10b7, 0x1005, 0, 0, TC997SX, 128, 32}, {
+ 0x14e4, 0x1644, 0x10b7, 0x1008, 0, 0, TC942BR01, 128, 32}, {
+ 0x14e4, 0x1644, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5700, 128, 32}, {
+ 0x14e4, 0x1645, 0x14e4, 1, 0, 0, BCM5701A5, 128, 32}, {
+ 0x14e4, 0x1645, 0x14e4, 5, 0, 0, BCM5701T1, 128, 32}, {
+ 0x14e4, 0x1645, 0x14e4, 6, 0, 0, BCM5701T8, 128, 32}, {
+ 0x14e4, 0x1645, 0x14e4, 7, 0, 0, BCM5701A7, 128, 32}, {
+ 0x14e4, 0x1645, 0x14e4, 8, 0, 0, BCM5701A10, 128, 32}, {
+ 0x14e4, 0x1645, 0x14e4, 0x8008, 0, 0, BCM5701A12, 128, 32}, {
+ 0x14e4, 0x1645, 0x0e11, 0xc1, 0, 0, NC6770, 128, 32}, {
+ 0x14e4, 0x1645, 0x0e11, 0x7c, 0, 0, NC7770, 128, 32}, {
+ 0x14e4, 0x1645, 0x0e11, 0x85, 0, 0, NC7780, 128, 32}, {
+ 0x14e4, 0x1645, 0x1028, 0x0121, 0, 0, BCM5701, 128, 32}, {
+ 0x14e4, 0x1645, 0x10b7, 0x1004, 0, 0, TC996SX, 128, 32}, {
+ 0x14e4, 0x1645, 0x10b7, 0x1006, 0, 0, TC996BT, 128, 32}, {
+ 0x14e4, 0x1645, 0x10b7, 0x1007, 0, 0, TC1000T, 128, 32}, {
+ 0x14e4, 0x1645, 0x10b7, 0x1008, 0, 0, TC940BR01, 128, 32}, {
+ 0x14e4, 0x1645, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5701, 128, 32}, {
+ 0x14e4, 0x1646, 0x14e4, 0x8009, 0, 0, BCM5702, 128, 32}, {
+ 0x14e4, 0x1646, 0x0e11, 0xbb, 0, 0, NC7760, 128, 32}, {
+ 0x14e4, 0x1646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5702, 128, 32}, {
+ 0x14e4, 0x16a6, 0x14e4, 0x8009, 0, 0, BCM5702, 128, 32}, {
+ 0x14e4, 0x16a6, 0x0e11, 0xbb, 0, 0, NC7760, 128, 32}, {
+ 0x14e4, 0x16a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5702, 128, 32}, {
+ 0x14e4, 0x1647, 0x14e4, 0x0009, 0, 0, BCM5703, 128, 32}, {
+ 0x14e4, 0x1647, 0x14e4, 0x000a, 0, 0, BCM5703A31, 128, 32}, {
+ 0x14e4, 0x1647, 0x14e4, 0x000b, 0, 0, BCM5703, 128, 32}, {
+ 0x14e4, 0x1647, 0x14e4, 0x800a, 0, 0, BCM5703, 128, 32}, {
+ 0x14e4, 0x1647, 0x0e11, 0x9a, 0, 0, NC7770, 128, 32}, {
+ 0x14e4, 0x1647, 0x0e11, 0x99, 0, 0, NC7780, 128, 32}, {
+ 0x14e4, 0x1647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5703, 128, 32}, {
+ 0x14e4, 0x16a7, 0x14e4, 0x0009, 0, 0, BCM5703, 128, 32}, {
+ 0x14e4, 0x16a7, 0x14e4, 0x000a, 0, 0, BCM5703A31, 128, 32}, {
+ 0x14e4, 0x16a7, 0x14e4, 0x000b, 0, 0, BCM5703, 128, 32}, {
+ 0x14e4, 0x16a7, 0x14e4, 0x800a, 0, 0, BCM5703, 128, 32}, {
+ 0x14e4, 0x16a7, 0x0e11, 0x9a, 0, 0, NC7770, 128, 32}, {
+ 0x14e4, 0x16a7, 0x0e11, 0x99, 0, 0, NC7780, 128, 32}, {
+ 0x14e4, 0x16a7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5703, 128, 32}
};
#define n570xDevices (sizeof(bcm570xDevices)/sizeof(bcm570xDevices[0]))
-
/*
* Allocate a packet buffer from the bcm570x packet pool.
*/
-void *
-bcm570xPktAlloc(int u, int pksize)
+void *bcm570xPktAlloc (int u, int pksize)
{
- return malloc(pksize);
+ return malloc (pksize);
}
/*
* Free a packet previously allocated from the bcm570x packet
* buffer pool.
*/
-void
-bcm570xPktFree(int u, void *p)
+void bcm570xPktFree (int u, void *p)
{
- free(p);
+ free (p);
}
-int
-bcm570xReplenishRxBuffers(PUM_DEVICE_BLOCK pUmDevice)
+int bcm570xReplenishRxBuffers (PUM_DEVICE_BLOCK pUmDevice)
{
- PLM_PACKET pPacket;
- PUM_PACKET pUmPacket;
- void *skb;
- int queue_rx = 0;
- int ret = 0;
-
- while ((pUmPacket = (PUM_PACKET)
- QQ_PopHead(&pUmDevice->rx_out_of_buf_q.Container)) != 0) {
-
- pPacket = (PLM_PACKET) pUmPacket;
-
- /* reuse an old skb */
- if (pUmPacket->skbuff) {
- QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
- queue_rx = 1;
- continue;
- }
- if ( ( skb = bcm570xPktAlloc(pUmDevice->index,
- pPacket->u.Rx.RxBufferSize + 2)) == 0) {
- QQ_PushHead(&pUmDevice->rx_out_of_buf_q.Container,pPacket);
- printf("NOTICE: Out of RX memory.\n");
- ret = 1;
- break;
- }
+ PLM_PACKET pPacket;
+ PUM_PACKET pUmPacket;
+ void *skb;
+ int queue_rx = 0;
+ int ret = 0;
+
+ while ((pUmPacket = (PUM_PACKET)
+ QQ_PopHead (&pUmDevice->rx_out_of_buf_q.Container)) != 0) {
+
+ pPacket = (PLM_PACKET) pUmPacket;
+
+ /* reuse an old skb */
+ if (pUmPacket->skbuff) {
+ QQ_PushTail (&pDevice->RxPacketFreeQ.Container,
+ pPacket);
+ queue_rx = 1;
+ continue;
+ }
+ if ((skb = bcm570xPktAlloc (pUmDevice->index,
+ pPacket->u.Rx.RxBufferSize + 2)) ==
+ 0) {
+ QQ_PushHead (&pUmDevice->rx_out_of_buf_q.Container,
+ pPacket);
+ printf ("NOTICE: Out of RX memory.\n");
+ ret = 1;
+ break;
+ }
- pUmPacket->skbuff = skb;
- QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
- queue_rx = 1;
- }
+ pUmPacket->skbuff = skb;
+ QQ_PushTail (&pDevice->RxPacketFreeQ.Container, pPacket);
+ queue_rx = 1;
+ }
- if (queue_rx) {
- LM_QueueRxPackets(pDevice);
- }
+ if (queue_rx) {
+ LM_QueueRxPackets (pDevice);
+ }
- return ret;
+ return ret;
}
/*
* Probe, Map, and Init 570x device.
*/
-int eth_init(bd_t *bis)
+int eth_init (bd_t * bis)
{
- int i, rv, devFound = FALSE;
- pci_dev_t devbusfn;
- unsigned short status;
-
- /* Find PCI device, if it exists, configure ... */
- for( i = 0; i < n570xDevices; i++){
- devbusfn = pci_find_device(bcm570xDevices[i].vendor_id,
- bcm570xDevices[i].device_id, 0);
- if(devbusfn == -1) {
- continue; /* No device of that vendor/device ID */
+ int i, rv, devFound = FALSE;
+ pci_dev_t devbusfn;
+ unsigned short status;
+
+ /* Find PCI device, if it exists, configure ... */
+ for (i = 0; i < n570xDevices; i++) {
+ devbusfn = pci_find_device (bcm570xDevices[i].vendor_id,
+ bcm570xDevices[i].device_id, 0);
+ if (devbusfn == -1) {
+ continue; /* No device of that vendor/device ID */
+ } else {
+
+ /* Set ILINE */
+ pci_write_config_byte (devbusfn,
+ PCI_INTERRUPT_LINE,
+ BCM570X_ILINE);
+
+ /*
+ * 0x10 - 0x14 define one 64-bit MBAR.
+ * 0x14 is the higher-order address bits of the BAR.
+ */
+ pci_write_config_dword (devbusfn,
+ PCI_BASE_ADDRESS_1, 0);
+
+ ioBase = BCM570X_MBAR;
+
+ pci_write_config_dword (devbusfn,
+ PCI_BASE_ADDRESS_0, ioBase);
+
+ /*
+ * Enable PCI memory, IO, and Master -- don't
+ * reset any status bits in doing so.
+ */
+ pci_read_config_word (devbusfn, PCI_COMMAND, &status);
+
+ status |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
+
+ pci_write_config_word (devbusfn, PCI_COMMAND, status);
+
+ printf
+ ("\n%s: bus %d, device %d, function %d: MBAR=0x%x\n",
+ board_info[bcm570xDevices[i].board_id].name,
+ PCI_BUS (devbusfn), PCI_DEV (devbusfn),
+ PCI_FUNC (devbusfn), ioBase);
+
+ /* Allocate once, but always clear on init */
+ if (!pDevice) {
+ pDevice = malloc (sizeof (UM_DEVICE_BLOCK));
+ pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
+ memset (pDevice, 0x0, sizeof (UM_DEVICE_BLOCK));
+ }
+
+ /* Configure pci dev structure */
+ pUmDevice->pdev = devbusfn;
+ pUmDevice->index = 0;
+ pUmDevice->tx_pkt = 0;
+ pUmDevice->rx_pkt = 0;
+ devFound = TRUE;
+ break;
+ }
+ }
+
+ if (!devFound) {
+ printf
+ ("eth_init: FAILURE: no BCM570x Ethernet devices found.\n");
+ return -1;
+ }
+
+ /* Setup defaults for chip */
+ pDevice->TaskToOffload = LM_TASK_OFFLOAD_NONE;
+
+ if (pDevice->ChipRevId == T3_CHIP_ID_5700_B0) {
+ pDevice->TaskToOffload = LM_TASK_OFFLOAD_NONE;
} else {
- /* Set ILINE */
- pci_write_config_byte(devbusfn,
- PCI_INTERRUPT_LINE, BCM570X_ILINE);
-
- /*
- * 0x10 - 0x14 define one 64-bit MBAR.
- * 0x14 is the higher-order address bits of the BAR.
- */
- pci_write_config_dword(devbusfn,
- PCI_BASE_ADDRESS_1, 0);
-
- ioBase = BCM570X_MBAR;
-
- pci_write_config_dword(devbusfn,
- PCI_BASE_ADDRESS_0, ioBase);
-
- /*
- * Enable PCI memory, IO, and Master -- don't
- * reset any status bits in doing so.
- */
- pci_read_config_word(devbusfn,
- PCI_COMMAND, &status);
-
- status |= PCI_COMMAND_MEMORY|PCI_COMMAND_MASTER;
-
- pci_write_config_word(devbusfn,
- PCI_COMMAND, status);
-
- printf("\n%s: bus %d, device %d, function %d: MBAR=0x%x\n",
- board_info[bcm570xDevices[i].board_id].name,
- PCI_BUS(devbusfn),
- PCI_DEV(devbusfn),
- PCI_FUNC(devbusfn),
- ioBase);
-
- /* Allocate once, but always clear on init */
- if (!pDevice) {
- pDevice = malloc(sizeof(UM_DEVICE_BLOCK));
- pUmDevice = (PUM_DEVICE_BLOCK)pDevice;
- memset(pDevice, 0x0, sizeof(UM_DEVICE_BLOCK));
- }
-
- /* Configure pci dev structure */
- pUmDevice->pdev = devbusfn;
- pUmDevice->index = 0;
- pUmDevice->tx_pkt = 0;
- pUmDevice->rx_pkt = 0;
- devFound = TRUE;
- break;
+ if (rx_checksum[i]) {
+ pDevice->TaskToOffload |=
+ LM_TASK_OFFLOAD_RX_TCP_CHECKSUM |
+ LM_TASK_OFFLOAD_RX_UDP_CHECKSUM;
+ }
+
+ if (tx_checksum[i]) {
+ pDevice->TaskToOffload |=
+ LM_TASK_OFFLOAD_TX_TCP_CHECKSUM |
+ LM_TASK_OFFLOAD_TX_UDP_CHECKSUM;
+ pDevice->NoTxPseudoHdrChksum = TRUE;
+ }
+ }
+
+ /* Set Device PCI Memory base address */
+ pDevice->pMappedMemBase = (PLM_UINT8) ioBase;
+
+ /* Pull down adapter info */
+ if ((rv = LM_GetAdapterInfo (pDevice)) != LM_STATUS_SUCCESS) {
+ printf ("bcm570xEnd: LM_GetAdapterInfo failed: rv=%d!\n", rv);
+ return -2;
}
- }
- if(!devFound){
- printf("eth_init: FAILURE: no BCM570x Ethernet devices found.\n");
- return -1;
- }
+ /* Lock not needed */
+ pUmDevice->do_global_lock = 0;
- /* Setup defaults for chip */
- pDevice->TaskToOffload = LM_TASK_OFFLOAD_NONE;
+ if (T3_ASIC_REV (pUmDevice->lm_dev.ChipRevId) == T3_ASIC_REV_5700) {
+ /* The 5700 chip works best without interleaved register */
+ /* accesses on certain machines. */
+ pUmDevice->do_global_lock = 1;
+ }
- if (pDevice->ChipRevId == T3_CHIP_ID_5700_B0) {
- pDevice->TaskToOffload = LM_TASK_OFFLOAD_NONE;
- } else {
+ /* Setup timer delays */
+ if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
+ pDevice->UseTaggedStatus = TRUE;
+ pUmDevice->timer_interval = CFG_HZ;
+ } else {
+ pUmDevice->timer_interval = CFG_HZ / 50;
+ }
- if (rx_checksum[i]) {
- pDevice->TaskToOffload |=
- LM_TASK_OFFLOAD_RX_TCP_CHECKSUM |
- LM_TASK_OFFLOAD_RX_UDP_CHECKSUM;
+ /* Grab name .... */
+ pUmDevice->name =
+ (char *)malloc (strlen (board_info[bcm570xDevices[i].board_id].name)
+ + 1);
+ strcpy (pUmDevice->name, board_info[bcm570xDevices[i].board_id].name);
+
+ memcpy (pDevice->NodeAddress, bis->bi_enetaddr, 6);
+ LM_SetMacAddress (pDevice, bis->bi_enetaddr);
+ /* Init queues .. */
+ QQ_InitQueue (&pUmDevice->rx_out_of_buf_q.Container,
+ MAX_RX_PACKET_DESC_COUNT);
+ pUmDevice->rx_last_cnt = pUmDevice->tx_last_cnt = 0;
+
+ /* delay for 4 seconds */
+ pUmDevice->delayed_link_ind = (4 * CFG_HZ) / pUmDevice->timer_interval;
+
+ pUmDevice->adaptive_expiry = CFG_HZ / pUmDevice->timer_interval;
+
+ /* Sometimes we get spurious ints. after reset when link is down. */
+ /* This field tells the isr to service the int. even if there is */
+ /* no status block update. */
+ pUmDevice->adapter_just_inited =
+ (3 * CFG_HZ) / pUmDevice->timer_interval;
+
+ /* Initialize 570x */
+ if (LM_InitializeAdapter (pDevice) != LM_STATUS_SUCCESS) {
+ printf ("ERROR: Adapter initialization failed.\n");
+ return ERROR;
}
- if (tx_checksum[i]) {
- pDevice->TaskToOffload |=
- LM_TASK_OFFLOAD_TX_TCP_CHECKSUM |
- LM_TASK_OFFLOAD_TX_UDP_CHECKSUM;
- pDevice->NoTxPseudoHdrChksum = TRUE;
+ /* Enable chip ISR */
+ LM_EnableInterrupt (pDevice);
+
+ /* Clear MC table */
+ LM_MulticastClear (pDevice);
+
+ /* Enable Multicast */
+ LM_SetReceiveMask (pDevice,
+ pDevice->ReceiveMask | LM_ACCEPT_ALL_MULTICAST);
+
+ pUmDevice->opened = 1;
+ pUmDevice->tx_full = 0;
+ pUmDevice->tx_pkt = 0;
+ pUmDevice->rx_pkt = 0;
+ printf ("eth%d: %s @0x%lx,",
+ pDevice->index, pUmDevice->name, (unsigned long)ioBase);
+ printf ("node addr ");
+ for (i = 0; i < 6; i++) {
+ printf ("%2.2x", pDevice->NodeAddress[i]);
}
- }
-
- /* Set Device PCI Memory base address */
- pDevice->pMappedMemBase = (PLM_UINT8) ioBase;
-
- /* Pull down adapter info */
- if ((rv = LM_GetAdapterInfo(pDevice)) != LM_STATUS_SUCCESS) {
- printf("bcm570xEnd: LM_GetAdapterInfo failed: rv=%d!\n", rv );
- return -2;
- }
-
- /* Lock not needed */
- pUmDevice->do_global_lock = 0;
-
- if (T3_ASIC_REV(pUmDevice->lm_dev.ChipRevId) == T3_ASIC_REV_5700) {
- /* The 5700 chip works best without interleaved register */
- /* accesses on certain machines. */
- pUmDevice->do_global_lock = 1;
- }
-
- /* Setup timer delays */
- if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) {
- pDevice->UseTaggedStatus = TRUE;
- pUmDevice->timer_interval = CFG_HZ;
- }
- else {
- pUmDevice->timer_interval = CFG_HZ / 50;
- }
-
- /* Grab name .... */
- pUmDevice->name =
- (char*)malloc(strlen(board_info[bcm570xDevices[i].board_id].name)+1);
- strcpy(pUmDevice->name,board_info[bcm570xDevices[i].board_id].name);
-
- memcpy(pDevice->NodeAddress, bis->bi_enetaddr, 6);
- LM_SetMacAddress(pDevice, bis->bi_enetaddr);
- /* Init queues .. */
- QQ_InitQueue(&pUmDevice->rx_out_of_buf_q.Container,
- MAX_RX_PACKET_DESC_COUNT);
- pUmDevice->rx_last_cnt = pUmDevice->tx_last_cnt = 0;
-
- /* delay for 4 seconds */
- pUmDevice->delayed_link_ind =
- (4 * CFG_HZ) / pUmDevice->timer_interval;
-
- pUmDevice->adaptive_expiry =
- CFG_HZ / pUmDevice->timer_interval;
-
- /* Sometimes we get spurious ints. after reset when link is down. */
- /* This field tells the isr to service the int. even if there is */
- /* no status block update. */
- pUmDevice->adapter_just_inited =
- (3 * CFG_HZ) / pUmDevice->timer_interval;
-
- /* Initialize 570x */
- if (LM_InitializeAdapter(pDevice) != LM_STATUS_SUCCESS) {
- printf("ERROR: Adapter initialization failed.\n");
- return ERROR;
- }
-
- /* Enable chip ISR */
- LM_EnableInterrupt(pDevice);
-
- /* Clear MC table */
- LM_MulticastClear(pDevice);
-
- /* Enable Multicast */
- LM_SetReceiveMask(pDevice,
- pDevice->ReceiveMask | LM_ACCEPT_ALL_MULTICAST);
-
- pUmDevice->opened = 1;
- pUmDevice->tx_full = 0;
- pUmDevice->tx_pkt = 0;
- pUmDevice->rx_pkt = 0;
- printf("eth%d: %s @0x%lx,",
- pDevice->index, pUmDevice->name, (unsigned long)ioBase);
- printf( "node addr ");
- for (i = 0; i < 6; i++) {
- printf("%2.2x", pDevice->NodeAddress[i]);
- }
- printf("\n");
-
- printf("eth%d: ", pDevice->index);
- printf("%s with ",
- chip_rev[bcm570xDevices[i].board_id].name);
-
- if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5400_PHY_ID)
- printf("Broadcom BCM5400 Copper ");
- else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID)
- printf("Broadcom BCM5401 Copper ");
- else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5411_PHY_ID)
- printf("Broadcom BCM5411 Copper ");
- else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5701_PHY_ID)
- printf("Broadcom BCM5701 Integrated Copper ");
- else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5703_PHY_ID)
- printf("Broadcom BCM5703 Integrated Copper ");
- else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM8002_PHY_ID)
- printf("Broadcom BCM8002 SerDes ");
- else if (pDevice->EnableTbi)
- printf("Agilent HDMP-1636 SerDes ");
- else
- printf("Unknown ");
- printf("transceiver found\n");
-
- printf("eth%d: %s, MTU: %d,",
- pDevice->index, pDevice->BusSpeedStr, 1500);
-
- if ((pDevice->ChipRevId != T3_CHIP_ID_5700_B0) &&
- rx_checksum[i])
- printf("Rx Checksum ON\n");
- else
- printf("Rx Checksum OFF\n");
- initialized++;
-
- return 0;
+ printf ("\n");
+
+ printf ("eth%d: ", pDevice->index);
+ printf ("%s with ", chip_rev[bcm570xDevices[i].board_id].name);
+
+ if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5400_PHY_ID)
+ printf ("Broadcom BCM5400 Copper ");
+ else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID)
+ printf ("Broadcom BCM5401 Copper ");
+ else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5411_PHY_ID)
+ printf ("Broadcom BCM5411 Copper ");
+ else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5701_PHY_ID)
+ printf ("Broadcom BCM5701 Integrated Copper ");
+ else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5703_PHY_ID)
+ printf ("Broadcom BCM5703 Integrated Copper ");
+ else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM8002_PHY_ID)
+ printf ("Broadcom BCM8002 SerDes ");
+ else if (pDevice->EnableTbi)
+ printf ("Agilent HDMP-1636 SerDes ");
+ else
+ printf ("Unknown ");
+ printf ("transceiver found\n");
+
+ printf ("eth%d: %s, MTU: %d,",
+ pDevice->index, pDevice->BusSpeedStr, 1500);
+
+ if ((pDevice->ChipRevId != T3_CHIP_ID_5700_B0) && rx_checksum[i])
+ printf ("Rx Checksum ON\n");
+ else
+ printf ("Rx Checksum OFF\n");
+ initialized++;
+
+ return 0;
}
/* Ethernet Interrupt service routine */
-void
-eth_isr(void)
+void eth_isr (void)
{
- LM_UINT32 oldtag, newtag;
- int i;
-
- pUmDevice->interrupt = 1;
-
- if (pDevice->UseTaggedStatus) {
- if ((pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_UPDATED) ||
- pUmDevice->adapter_just_inited) {
- MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, 1);
- oldtag = pDevice->pStatusBlkVirt->StatusTag;
-
- for (i = 0; ; i++) {
- pDevice->pStatusBlkVirt->Status &= ~STATUS_BLOCK_UPDATED;
- LM_ServiceInterrupts(pDevice);
- newtag = pDevice->pStatusBlkVirt->StatusTag;
- if ((newtag == oldtag) || (i > 50)) {
- MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, newtag << 24);
- if (pDevice->UndiFix) {
- REG_WR(pDevice, Grc.LocalCtrl,
- pDevice->GrcLocalCtrl | 0x2);
- }
- break;
- }
- oldtag = newtag;
- }
+ LM_UINT32 oldtag, newtag;
+ int i;
+
+ pUmDevice->interrupt = 1;
+
+ if (pDevice->UseTaggedStatus) {
+ if ((pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_UPDATED) ||
+ pUmDevice->adapter_just_inited) {
+ MB_REG_WR (pDevice, Mailbox.Interrupt[0].Low, 1);
+ oldtag = pDevice->pStatusBlkVirt->StatusTag;
+
+ for (i = 0;; i++) {
+ pDevice->pStatusBlkVirt->Status &=
+ ~STATUS_BLOCK_UPDATED;
+ LM_ServiceInterrupts (pDevice);
+ newtag = pDevice->pStatusBlkVirt->StatusTag;
+ if ((newtag == oldtag) || (i > 50)) {
+ MB_REG_WR (pDevice,
+ Mailbox.Interrupt[0].Low,
+ newtag << 24);
+ if (pDevice->UndiFix) {
+ REG_WR (pDevice, Grc.LocalCtrl,
+ pDevice->
+ GrcLocalCtrl | 0x2);
+ }
+ break;
+ }
+ oldtag = newtag;
+ }
+ }
+ } else {
+ while (pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_UPDATED) {
+ unsigned int dummy;
+
+ pDevice->pMemView->Mailbox.Interrupt[0].Low = 1;
+ pDevice->pStatusBlkVirt->Status &=
+ ~STATUS_BLOCK_UPDATED;
+ LM_ServiceInterrupts (pDevice);
+ pDevice->pMemView->Mailbox.Interrupt[0].Low = 0;
+ dummy = pDevice->pMemView->Mailbox.Interrupt[0].Low;
+ }
+ }
+
+ /* Allocate new RX buffers */
+ if (QQ_GetEntryCnt (&pUmDevice->rx_out_of_buf_q.Container)) {
+ bcm570xReplenishRxBuffers (pUmDevice);
}
- }
- else {
- while (pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_UPDATED) {
- unsigned int dummy;
-
- pDevice->pMemView->Mailbox.Interrupt[0].Low = 1;
- pDevice->pStatusBlkVirt->Status &= ~STATUS_BLOCK_UPDATED;
- LM_ServiceInterrupts(pDevice);
- pDevice->pMemView->Mailbox.Interrupt[0].Low = 0;
- dummy = pDevice->pMemView->Mailbox.Interrupt[0].Low;
+
+ /* Queue packets */
+ if (QQ_GetEntryCnt (&pDevice->RxPacketFreeQ.Container)) {
+ LM_QueueRxPackets (pDevice);
+ }
+
+ if (pUmDevice->tx_queued) {
+ pUmDevice->tx_queued = 0;
}
- }
-
- /* Allocate new RX buffers */
- if (QQ_GetEntryCnt(&pUmDevice->rx_out_of_buf_q.Container)) {
- bcm570xReplenishRxBuffers(pUmDevice);
- }
-
- /* Queue packets */
- if (QQ_GetEntryCnt(&pDevice->RxPacketFreeQ.Container)) {
- LM_QueueRxPackets(pDevice);
- }
-
- if (pUmDevice->tx_queued) {
- pUmDevice->tx_queued = 0;
- }
-
- if(pUmDevice->tx_full){
- if(pDevice->LinkStatus != LM_STATUS_LINK_DOWN){
- printf("NOTICE: tx was previously blocked, restarting MUX\n");
- pUmDevice->tx_full = 0;
+
+ if (pUmDevice->tx_full) {
+ if (pDevice->LinkStatus != LM_STATUS_LINK_DOWN) {
+ printf
+ ("NOTICE: tx was previously blocked, restarting MUX\n");
+ pUmDevice->tx_full = 0;
+ }
}
- }
- pUmDevice->interrupt = 0;
+ pUmDevice->interrupt = 0;
}
-int
-eth_send(volatile void *packet, int length)
+int eth_send (volatile void *packet, int length)
{
- int status = 0;
+ int status = 0;
#if ET_DEBUG
- unsigned char* ptr = (unsigned char*)packet;
+ unsigned char *ptr = (unsigned char *)packet;
#endif
- PLM_PACKET pPacket;
- PUM_PACKET pUmPacket;
+ PLM_PACKET pPacket;
+ PUM_PACKET pUmPacket;
- /* Link down, return */
- while(pDevice->LinkStatus == LM_STATUS_LINK_DOWN) {
+ /* Link down, return */
+ while (pDevice->LinkStatus == LM_STATUS_LINK_DOWN) {
#if 0
- printf("eth%d: link down - check cable or link partner.\n",
- pUmDevice->index);
+ printf ("eth%d: link down - check cable or link partner.\n",
+ pUmDevice->index);
#endif
- eth_isr();
+ eth_isr ();
+
+ /* Wait to see link for one-half a second before sending ... */
+ udelay (1500000);
- /* Wait to see link for one-half a second before sending ... */
- udelay(1500000);
+ }
- }
+ /* Clear sent flag */
+ pUmDevice->tx_pkt = 0;
- /* Clear sent flag */
- pUmDevice->tx_pkt = 0;
+ /* Previously blocked */
+ if (pUmDevice->tx_full) {
+ printf ("eth%d: tx blocked.\n", pUmDevice->index);
+ return 0;
+ }
- /* Previously blocked */
- if(pUmDevice->tx_full){
- printf("eth%d: tx blocked.\n", pUmDevice->index);
- return 0;
- }
+ pPacket = (PLM_PACKET)
+ QQ_PopHead (&pDevice->TxPacketFreeQ.Container);
- pPacket = (PLM_PACKET)
- QQ_PopHead(&pDevice->TxPacketFreeQ.Container);
+ if (pPacket == 0) {
+ pUmDevice->tx_full = 1;
+ printf ("bcm570xEndSend: TX full!\n");
+ return 0;
+ }
- if (pPacket == 0) {
- pUmDevice->tx_full = 1;
- printf("bcm570xEndSend: TX full!\n");
- return 0;
- }
+ if (pDevice->SendBdLeft.counter == 0) {
+ pUmDevice->tx_full = 1;
+ printf ("bcm570xEndSend: no more TX descriptors!\n");
+ QQ_PushHead (&pDevice->TxPacketFreeQ.Container, pPacket);
+ return 0;
+ }
- if (pDevice->SendBdLeft.counter == 0) {
- pUmDevice->tx_full = 1;
- printf("bcm570xEndSend: no more TX descriptors!\n");
- QQ_PushHead(&pDevice->TxPacketFreeQ.Container, pPacket);
- return 0;
- }
-
- if (length <= 0){
- printf("eth: bad packet size: %d\n", length);
- goto out;
- }
-
- /* Get packet buffers and fragment list */
- pUmPacket = (PUM_PACKET) pPacket;
- /* Single DMA Descriptor transmit.
- * Fragments may be provided, but one DMA descriptor max is
- * used to send the packet.
- */
- if (MM_CoalesceTxBuffer (pDevice, pPacket) != LM_STATUS_SUCCESS) {
- if (pUmPacket->skbuff == NULL){
- /* Packet was discarded */
- printf("TX: failed (1)\n");
- status = 1;
- } else{
- printf("TX: failed (2)\n");
- status = 2;
+ if (length <= 0) {
+ printf ("eth: bad packet size: %d\n", length);
+ goto out;
}
- QQ_PushHead (&pDevice->TxPacketFreeQ.Container, pPacket);
- return status;
- }
-
- /* Copy packet to DMA buffer */
- memset(pUmPacket->skbuff, 0x0, MAX_PACKET_SIZE);
- memcpy((void*)pUmPacket->skbuff, (void*)packet, length);
- pPacket->PacketSize = length;
- pPacket->Flags |= SND_BD_FLAG_END|SND_BD_FLAG_COAL_NOW;
- pPacket->u.Tx.FragCount = 1;
- /* We've already provided a frame ready for transmission */
- pPacket->Flags &= ~SND_BD_FLAG_TCP_UDP_CKSUM;
-
- if ( LM_SendPacket(pDevice, pPacket) == LM_STATUS_FAILURE){
- /*
- * A lower level send failure will push the packet descriptor back
- * in the free queue, so just deal with the VxWorks clusters.
+
+ /* Get packet buffers and fragment list */
+ pUmPacket = (PUM_PACKET) pPacket;
+ /* Single DMA Descriptor transmit.
+ * Fragments may be provided, but one DMA descriptor max is
+ * used to send the packet.
*/
- if (pUmPacket->skbuff == NULL){
- printf("TX failed (1)!\n");
- /* Packet was discarded */
- status = 3;
- } else {
- /* A resource problem ... */
- printf("TX failed (2)!\n");
- status = 4;
+ if (MM_CoalesceTxBuffer (pDevice, pPacket) != LM_STATUS_SUCCESS) {
+ if (pUmPacket->skbuff == NULL) {
+ /* Packet was discarded */
+ printf ("TX: failed (1)\n");
+ status = 1;
+ } else {
+ printf ("TX: failed (2)\n");
+ status = 2;
+ }
+ QQ_PushHead (&pDevice->TxPacketFreeQ.Container, pPacket);
+ return status;
}
- if (QQ_GetEntryCnt(&pDevice->TxPacketFreeQ.Container) == 0) {
- printf("TX: emptyQ!\n");
- pUmDevice->tx_full = 1;
+ /* Copy packet to DMA buffer */
+ memset (pUmPacket->skbuff, 0x0, MAX_PACKET_SIZE);
+ memcpy ((void *)pUmPacket->skbuff, (void *)packet, length);
+ pPacket->PacketSize = length;
+ pPacket->Flags |= SND_BD_FLAG_END | SND_BD_FLAG_COAL_NOW;
+ pPacket->u.Tx.FragCount = 1;
+ /* We've already provided a frame ready for transmission */
+ pPacket->Flags &= ~SND_BD_FLAG_TCP_UDP_CKSUM;
+
+ if (LM_SendPacket (pDevice, pPacket) == LM_STATUS_FAILURE) {
+ /*
+ * A lower level send failure will push the packet descriptor back
+ * in the free queue, so just deal with the VxWorks clusters.
+ */
+ if (pUmPacket->skbuff == NULL) {
+ printf ("TX failed (1)!\n");
+ /* Packet was discarded */
+ status = 3;
+ } else {
+ /* A resource problem ... */
+ printf ("TX failed (2)!\n");
+ status = 4;
+ }
+
+ if (QQ_GetEntryCnt (&pDevice->TxPacketFreeQ.Container) == 0) {
+ printf ("TX: emptyQ!\n");
+ pUmDevice->tx_full = 1;
+ }
}
- }
- while(pUmDevice->tx_pkt == 0){
- /* Service TX */
- eth_isr();
- }
+ while (pUmDevice->tx_pkt == 0) {
+ /* Service TX */
+ eth_isr ();
+ }
#if ET_DEBUG
- printf("eth_send: 0x%x, %d bytes\n"
- "[%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x] ...\n",
- (int)pPacket, length,
- ptr[0],ptr[1],ptr[2],ptr[3],ptr[4],ptr[5],
- ptr[6],ptr[7],ptr[8],ptr[9],ptr[10],ptr[11],ptr[12],
- ptr[13],ptr[14],ptr[15]);
+ printf ("eth_send: 0x%x, %d bytes\n"
+ "[%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x] ...\n",
+ (int)pPacket, length,
+ ptr[0], ptr[1], ptr[2], ptr[3], ptr[4], ptr[5],
+ ptr[6], ptr[7], ptr[8], ptr[9], ptr[10], ptr[11], ptr[12],
+ ptr[13], ptr[14], ptr[15]);
#endif
- pUmDevice->tx_pkt = 0;
- QQ_PushHead(&pDevice->TxPacketFreeQ.Container, pPacket);
+ pUmDevice->tx_pkt = 0;
+ QQ_PushHead (&pDevice->TxPacketFreeQ.Container, pPacket);
- /* Done with send */
- out:
- return status;
+ /* Done with send */
+ out:
+ return status;
}
-
/* Ethernet receive */
-int
-eth_rx(void)
+int eth_rx (void)
{
- PLM_PACKET pPacket = NULL;
- PUM_PACKET pUmPacket = NULL;
- void *skb;
- int size=0;
+ PLM_PACKET pPacket = NULL;
+ PUM_PACKET pUmPacket = NULL;
+ void *skb;
+ int size = 0;
- while(TRUE) {
+ while (TRUE) {
- bcm570x_service_isr:
- /* Pull down packet if it is there */
- eth_isr();
+ bcm570x_service_isr:
+ /* Pull down packet if it is there */
+ eth_isr ();
- /* Indicate RX packets called */
- if(pUmDevice->rx_pkt){
- /* printf("eth_rx: got a packet...\n"); */
- pUmDevice->rx_pkt = 0;
- } else {
- /* printf("eth_rx: waiting for packet...\n"); */
- goto bcm570x_service_isr;
- }
+ /* Indicate RX packets called */
+ if (pUmDevice->rx_pkt) {
+ /* printf("eth_rx: got a packet...\n"); */
+ pUmDevice->rx_pkt = 0;
+ } else {
+ /* printf("eth_rx: waiting for packet...\n"); */
+ goto bcm570x_service_isr;
+ }
- pPacket = (PLM_PACKET)
- QQ_PopHead(&pDevice->RxPacketReceivedQ.Container);
+ pPacket = (PLM_PACKET)
+ QQ_PopHead (&pDevice->RxPacketReceivedQ.Container);
- if (pPacket == 0){
- printf("eth_rx: empty packet!\n");
- goto bcm570x_service_isr;
- }
+ if (pPacket == 0) {
+ printf ("eth_rx: empty packet!\n");
+ goto bcm570x_service_isr;
+ }
- pUmPacket = (PUM_PACKET) pPacket;
+ pUmPacket = (PUM_PACKET) pPacket;
#if ET_DEBUG
- printf("eth_rx: packet @0x%x\n",
- (int)pPacket);
+ printf ("eth_rx: packet @0x%x\n", (int)pPacket);
#endif
- /* If the packet generated an error, reuse buffer */
- if ((pPacket->PacketStatus != LM_STATUS_SUCCESS) ||
- ((size = pPacket->PacketSize) > pDevice->RxMtu)) {
-
- /* reuse skb */
- QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
- printf("eth_rx: error in packet dma!\n");
- goto bcm570x_service_isr;
- }
+ /* If the packet generated an error, reuse buffer */
+ if ((pPacket->PacketStatus != LM_STATUS_SUCCESS) ||
+ ((size = pPacket->PacketSize) > pDevice->RxMtu)) {
+
+ /* reuse skb */
+ QQ_PushTail (&pDevice->RxPacketFreeQ.Container,
+ pPacket);
+ printf ("eth_rx: error in packet dma!\n");
+ goto bcm570x_service_isr;
+ }
- /* Set size and address */
- skb = pUmPacket->skbuff;
- size = pPacket->PacketSize;
+ /* Set size and address */
+ skb = pUmPacket->skbuff;
+ size = pPacket->PacketSize;
- /* Pass the packet up to the protocol
- * layers.
- */
- NetReceive(skb, size);
+ /* Pass the packet up to the protocol
+ * layers.
+ */
+ NetReceive (skb, size);
- /* Free packet buffer */
- bcm570xPktFree (pUmDevice->index, skb);
- pUmPacket->skbuff = NULL;
+ /* Free packet buffer */
+ bcm570xPktFree (pUmDevice->index, skb);
+ pUmPacket->skbuff = NULL;
- /* Reuse SKB */
- QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
+ /* Reuse SKB */
+ QQ_PushTail (&pDevice->RxPacketFreeQ.Container, pPacket);
- return 0; /* Got a packet, bail ... */
- }
- return size;
+ return 0; /* Got a packet, bail ... */
+ }
+ return size;
}
-
/* Shut down device */
-void
-eth_halt(void)
+void eth_halt (void)
{
- int i;
- if ( initialized)
- if (pDevice && pUmDevice && pUmDevice->opened){
- printf("\neth%d:%s,", pUmDevice->index, pUmDevice->name);
- printf("HALT,");
- /* stop device */
- LM_Halt(pDevice);
- printf("POWER DOWN,");
- LM_SetPowerState(pDevice, LM_POWER_STATE_D3);
-
- /* Free the memory allocated by the device in tigon3 */
- for (i = 0; i < pUmDevice->mem_list_num; i++) {
- if (pUmDevice->mem_list[i]) {
- /* sanity check */
- if (pUmDevice->dma_list[i]) { /* cache-safe memory */
- free(pUmDevice->mem_list[i]);
- } else {
- free(pUmDevice->mem_list[i]); /* normal memory */
+ int i;
+ if (initialized)
+ if (pDevice && pUmDevice && pUmDevice->opened) {
+ printf ("\neth%d:%s,", pUmDevice->index,
+ pUmDevice->name);
+ printf ("HALT,");
+ /* stop device */
+ LM_Halt (pDevice);
+ printf ("POWER DOWN,");
+ LM_SetPowerState (pDevice, LM_POWER_STATE_D3);
+
+ /* Free the memory allocated by the device in tigon3 */
+ for (i = 0; i < pUmDevice->mem_list_num; i++) {
+ if (pUmDevice->mem_list[i]) {
+ /* sanity check */
+ if (pUmDevice->dma_list[i]) { /* cache-safe memory */
+ free (pUmDevice->mem_list[i]);
+ } else {
+ free (pUmDevice->mem_list[i]); /* normal memory */
+ }
+ }
+ }
+ pUmDevice->opened = 0;
+ free (pDevice);
+ pDevice = NULL;
+ pUmDevice = NULL;
+ initialized = 0;
+ printf ("done - offline.\n");
}
- }
- }
- pUmDevice->opened = 0;
- free(pDevice);
- pDevice = NULL;
- pUmDevice = NULL;
- initialized = 0;
- printf("done - offline.\n");
- }
}
-
/*
*
* Middle Module: Interface between the HW driver (tigon3 modules) and
@@ -843,409 +834,380 @@ eth_halt(void)
*/
/* Middle module dependency - size of a packet descriptor */
-int MM_Packet_Desc_Size = sizeof(UM_PACKET);
-
+int MM_Packet_Desc_Size = sizeof (UM_PACKET);
LM_STATUS
-MM_ReadConfig32(PLM_DEVICE_BLOCK pDevice,
- LM_UINT32 Offset,
- LM_UINT32 *pValue32)
+MM_ReadConfig32 (PLM_DEVICE_BLOCK pDevice,
+ LM_UINT32 Offset, LM_UINT32 * pValue32)
{
- UM_DEVICE_BLOCK *pUmDevice;
- pUmDevice = (UM_DEVICE_BLOCK *) pDevice;
- pci_read_config_dword(pUmDevice->pdev,
- Offset, (u32 *) pValue32);
- return LM_STATUS_SUCCESS;
+ UM_DEVICE_BLOCK *pUmDevice;
+ pUmDevice = (UM_DEVICE_BLOCK *) pDevice;
+ pci_read_config_dword (pUmDevice->pdev, Offset, (u32 *) pValue32);
+ return LM_STATUS_SUCCESS;
}
-
LM_STATUS
-MM_WriteConfig32(PLM_DEVICE_BLOCK pDevice,
- LM_UINT32 Offset,
- LM_UINT32 Value32)
+MM_WriteConfig32 (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, LM_UINT32 Value32)
{
- UM_DEVICE_BLOCK *pUmDevice;
- pUmDevice = (UM_DEVICE_BLOCK *) pDevice;
- pci_write_config_dword(pUmDevice->pdev,
- Offset, Value32);
- return LM_STATUS_SUCCESS;
+ UM_DEVICE_BLOCK *pUmDevice;
+ pUmDevice = (UM_DEVICE_BLOCK *) pDevice;
+ pci_write_config_dword (pUmDevice->pdev, Offset, Value32);
+ return LM_STATUS_SUCCESS;
}
-
LM_STATUS
-MM_ReadConfig16(PLM_DEVICE_BLOCK pDevice,
- LM_UINT32 Offset,
- LM_UINT16 *pValue16)
+MM_ReadConfig16 (PLM_DEVICE_BLOCK pDevice,
+ LM_UINT32 Offset, LM_UINT16 * pValue16)
{
- UM_DEVICE_BLOCK *pUmDevice;
- pUmDevice = (UM_DEVICE_BLOCK *) pDevice;
- pci_read_config_word(pUmDevice->pdev,
- Offset, (u16*) pValue16);
- return LM_STATUS_SUCCESS;
+ UM_DEVICE_BLOCK *pUmDevice;
+ pUmDevice = (UM_DEVICE_BLOCK *) pDevice;
+ pci_read_config_word (pUmDevice->pdev, Offset, (u16 *) pValue16);
+ return LM_STATUS_SUCCESS;
}
LM_STATUS
-MM_WriteConfig16(PLM_DEVICE_BLOCK pDevice,
- LM_UINT32 Offset,
- LM_UINT16 Value16)
+MM_WriteConfig16 (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, LM_UINT16 Value16)
{
- UM_DEVICE_BLOCK *pUmDevice;
- pUmDevice = (UM_DEVICE_BLOCK *) pDevice;
- pci_write_config_word(pUmDevice->pdev,
- Offset, Value16);
- return LM_STATUS_SUCCESS;
+ UM_DEVICE_BLOCK *pUmDevice;
+ pUmDevice = (UM_DEVICE_BLOCK *) pDevice;
+ pci_write_config_word (pUmDevice->pdev, Offset, Value16);
+ return LM_STATUS_SUCCESS;
}
-
LM_STATUS
-MM_AllocateSharedMemory(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize,
- PLM_VOID *pMemoryBlockVirt,
- PLM_PHYSICAL_ADDRESS pMemoryBlockPhy,
- LM_BOOL Cached)
+MM_AllocateSharedMemory (PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize,
+ PLM_VOID * pMemoryBlockVirt,
+ PLM_PHYSICAL_ADDRESS pMemoryBlockPhy, LM_BOOL Cached)
{
- PLM_VOID pvirt;
- PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
- dma_addr_t mapping;
+ PLM_VOID pvirt;
+ PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
+ dma_addr_t mapping;
- pvirt = malloc(BlockSize);
- mapping = (dma_addr_t)(pvirt);
- if (!pvirt)
- return LM_STATUS_FAILURE;
+ pvirt = malloc (BlockSize);
+ mapping = (dma_addr_t) (pvirt);
+ if (!pvirt)
+ return LM_STATUS_FAILURE;
- pUmDevice->mem_list[pUmDevice->mem_list_num] = pvirt;
- pUmDevice->dma_list[pUmDevice->mem_list_num] = mapping;
- pUmDevice->mem_size_list[pUmDevice->mem_list_num++] = BlockSize;
- memset(pvirt, 0, BlockSize);
+ pUmDevice->mem_list[pUmDevice->mem_list_num] = pvirt;
+ pUmDevice->dma_list[pUmDevice->mem_list_num] = mapping;
+ pUmDevice->mem_size_list[pUmDevice->mem_list_num++] = BlockSize;
+ memset (pvirt, 0, BlockSize);
- *pMemoryBlockVirt = (PLM_VOID) pvirt;
- MM_SetAddr (pMemoryBlockPhy, (dma_addr_t) mapping);
+ *pMemoryBlockVirt = (PLM_VOID) pvirt;
+ MM_SetAddr (pMemoryBlockPhy, (dma_addr_t) mapping);
- return LM_STATUS_SUCCESS;
+ return LM_STATUS_SUCCESS;
}
-
LM_STATUS
-MM_AllocateMemory(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize,
- PLM_VOID *pMemoryBlockVirt)
+MM_AllocateMemory (PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize,
+ PLM_VOID * pMemoryBlockVirt)
{
- PLM_VOID pvirt;
- PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
+ PLM_VOID pvirt;
+ PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
- pvirt = malloc(BlockSize);
+ pvirt = malloc (BlockSize);
- if (!pvirt)
- return LM_STATUS_FAILURE;
+ if (!pvirt)
+ return LM_STATUS_FAILURE;
- pUmDevice->mem_list[pUmDevice->mem_list_num] = pvirt;
- pUmDevice->dma_list[pUmDevice->mem_list_num] = 0;
- pUmDevice->mem_size_list[pUmDevice->mem_list_num++] = BlockSize;
- memset(pvirt, 0, BlockSize);
- *pMemoryBlockVirt = pvirt;
+ pUmDevice->mem_list[pUmDevice->mem_list_num] = pvirt;
+ pUmDevice->dma_list[pUmDevice->mem_list_num] = 0;
+ pUmDevice->mem_size_list[pUmDevice->mem_list_num++] = BlockSize;
+ memset (pvirt, 0, BlockSize);
+ *pMemoryBlockVirt = pvirt;
- return LM_STATUS_SUCCESS;
+ return LM_STATUS_SUCCESS;
}
-LM_STATUS
-MM_MapMemBase(PLM_DEVICE_BLOCK pDevice)
+LM_STATUS MM_MapMemBase (PLM_DEVICE_BLOCK pDevice)
{
- printf("BCM570x PCI Memory base address @0x%x\n",
- (unsigned int)pDevice->pMappedMemBase);
- return LM_STATUS_SUCCESS;
+ printf ("BCM570x PCI Memory base address @0x%x\n",
+ (unsigned int)pDevice->pMappedMemBase);
+ return LM_STATUS_SUCCESS;
}
-LM_STATUS
-MM_InitializeUmPackets(PLM_DEVICE_BLOCK pDevice)
+LM_STATUS MM_InitializeUmPackets (PLM_DEVICE_BLOCK pDevice)
{
- int i;
- void* skb;
- PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
- PUM_PACKET pUmPacket = NULL;
- PLM_PACKET pPacket = NULL;
-
- for (i = 0; i < pDevice->RxPacketDescCnt; i++) {
- pPacket = QQ_PopHead(&pDevice->RxPacketFreeQ.Container);
- pUmPacket = (PUM_PACKET) pPacket;
+ int i;
+ void *skb;
+ PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
+ PUM_PACKET pUmPacket = NULL;
+ PLM_PACKET pPacket = NULL;
+
+ for (i = 0; i < pDevice->RxPacketDescCnt; i++) {
+ pPacket = QQ_PopHead (&pDevice->RxPacketFreeQ.Container);
+ pUmPacket = (PUM_PACKET) pPacket;
+
+ if (pPacket == 0) {
+ printf ("MM_InitializeUmPackets: Bad RxPacketFreeQ\n");
+ }
- if (pPacket == 0) {
- printf("MM_InitializeUmPackets: Bad RxPacketFreeQ\n");
- }
+ skb = bcm570xPktAlloc (pUmDevice->index,
+ pPacket->u.Rx.RxBufferSize + 2);
- skb = bcm570xPktAlloc(pUmDevice->index,
- pPacket->u.Rx.RxBufferSize + 2);
+ if (skb == 0) {
+ pUmPacket->skbuff = 0;
+ QQ_PushTail (&pUmDevice->rx_out_of_buf_q.Container,
+ pPacket);
+ printf ("MM_InitializeUmPackets: out of buffer.\n");
+ continue;
+ }
- if (skb == 0) {
- pUmPacket->skbuff = 0;
- QQ_PushTail(&pUmDevice->rx_out_of_buf_q.Container, pPacket);
- printf("MM_InitializeUmPackets: out of buffer.\n");
- continue;
+ pUmPacket->skbuff = skb;
+ QQ_PushTail (&pDevice->RxPacketFreeQ.Container, pPacket);
}
- pUmPacket->skbuff = skb;
- QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
- }
-
- pUmDevice->rx_low_buf_thresh = pDevice->RxPacketDescCnt / 8;
+ pUmDevice->rx_low_buf_thresh = pDevice->RxPacketDescCnt / 8;
- return LM_STATUS_SUCCESS;
+ return LM_STATUS_SUCCESS;
}
-LM_STATUS
-MM_GetConfig(PLM_DEVICE_BLOCK pDevice)
+LM_STATUS MM_GetConfig (PLM_DEVICE_BLOCK pDevice)
{
- PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
- int index = pDevice->index;
-
- if (auto_speed[index] == 0)
- pDevice->DisableAutoNeg = TRUE;
- else
- pDevice->DisableAutoNeg = FALSE;
-
- if (line_speed[index] == 0) {
- pDevice->RequestedMediaType =
- LM_REQUESTED_MEDIA_TYPE_AUTO;
- pDevice->DisableAutoNeg = FALSE;
- }
- else {
- if (line_speed[index] == 1000) {
- if (pDevice->EnableTbi) {
- pDevice->RequestedMediaType =
- LM_REQUESTED_MEDIA_TYPE_FIBER_1000MBPS_FULL_DUPLEX;
- }
- else if (full_duplex[index]) {
- pDevice->RequestedMediaType =
- LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS_FULL_DUPLEX;
- }
- else {
- pDevice->RequestedMediaType =
- LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS;
- }
- if (!pDevice->EnableTbi)
+ PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
+ int index = pDevice->index;
+
+ if (auto_speed[index] == 0)
+ pDevice->DisableAutoNeg = TRUE;
+ else
pDevice->DisableAutoNeg = FALSE;
+
+ if (line_speed[index] == 0) {
+ pDevice->RequestedMediaType = LM_REQUESTED_MEDIA_TYPE_AUTO;
+ pDevice->DisableAutoNeg = FALSE;
+ } else {
+ if (line_speed[index] == 1000) {
+ if (pDevice->EnableTbi) {
+ pDevice->RequestedMediaType =
+ LM_REQUESTED_MEDIA_TYPE_FIBER_1000MBPS_FULL_DUPLEX;
+ } else if (full_duplex[index]) {
+ pDevice->RequestedMediaType =
+ LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS_FULL_DUPLEX;
+ } else {
+ pDevice->RequestedMediaType =
+ LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS;
+ }
+ if (!pDevice->EnableTbi)
+ pDevice->DisableAutoNeg = FALSE;
+ } else if (line_speed[index] == 100) {
+ if (full_duplex[index]) {
+ pDevice->RequestedMediaType =
+ LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS_FULL_DUPLEX;
+ } else {
+ pDevice->RequestedMediaType =
+ LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS;
+ }
+ } else if (line_speed[index] == 10) {
+ if (full_duplex[index]) {
+ pDevice->RequestedMediaType =
+ LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS_FULL_DUPLEX;
+ } else {
+ pDevice->RequestedMediaType =
+ LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS;
+ }
+ } else {
+ pDevice->RequestedMediaType =
+ LM_REQUESTED_MEDIA_TYPE_AUTO;
+ pDevice->DisableAutoNeg = FALSE;
+ }
+
}
- else if (line_speed[index] == 100) {
- if (full_duplex[index]) {
- pDevice->RequestedMediaType =
- LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS_FULL_DUPLEX;
- }
- else {
- pDevice->RequestedMediaType =
- LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS;
- }
- }
- else if (line_speed[index] == 10) {
- if (full_duplex[index]) {
- pDevice->RequestedMediaType =
- LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS_FULL_DUPLEX;
- }
- else {
- pDevice->RequestedMediaType =
- LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS;
- }
+ pDevice->FlowControlCap = 0;
+ if (rx_flow_control[index] != 0) {
+ pDevice->FlowControlCap |= LM_FLOW_CONTROL_RECEIVE_PAUSE;
}
- else {
- pDevice->RequestedMediaType =
- LM_REQUESTED_MEDIA_TYPE_AUTO;
- pDevice->DisableAutoNeg = FALSE;
+ if (tx_flow_control[index] != 0) {
+ pDevice->FlowControlCap |= LM_FLOW_CONTROL_TRANSMIT_PAUSE;
}
-
- }
- pDevice->FlowControlCap = 0;
- if (rx_flow_control[index] != 0) {
- pDevice->FlowControlCap |= LM_FLOW_CONTROL_RECEIVE_PAUSE;
- }
- if (tx_flow_control[index] != 0) {
- pDevice->FlowControlCap |= LM_FLOW_CONTROL_TRANSMIT_PAUSE;
- }
- if ((auto_flow_control[index] != 0) &&
- (pDevice->DisableAutoNeg == FALSE)) {
-
- pDevice->FlowControlCap |= LM_FLOW_CONTROL_AUTO_PAUSE;
- if ((tx_flow_control[index] == 0) &&
- (rx_flow_control[index] == 0)) {
- pDevice->FlowControlCap |=
- LM_FLOW_CONTROL_TRANSMIT_PAUSE |
- LM_FLOW_CONTROL_RECEIVE_PAUSE;
+ if ((auto_flow_control[index] != 0) &&
+ (pDevice->DisableAutoNeg == FALSE)) {
+
+ pDevice->FlowControlCap |= LM_FLOW_CONTROL_AUTO_PAUSE;
+ if ((tx_flow_control[index] == 0) &&
+ (rx_flow_control[index] == 0)) {
+ pDevice->FlowControlCap |=
+ LM_FLOW_CONTROL_TRANSMIT_PAUSE |
+ LM_FLOW_CONTROL_RECEIVE_PAUSE;
+ }
}
- }
- /* Default MTU for now */
- pUmDevice->mtu = 1500;
+ /* Default MTU for now */
+ pUmDevice->mtu = 1500;
#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
- if (pUmDevice->mtu > 1500) {
- pDevice->RxMtu = pUmDevice->mtu;
- pDevice->RxJumboDescCnt = DEFAULT_JUMBO_RCV_DESC_COUNT;
- }
- else {
- pDevice->RxJumboDescCnt = 0;
- }
- pDevice->RxJumboDescCnt = rx_jumbo_desc_cnt[index];
+ if (pUmDevice->mtu > 1500) {
+ pDevice->RxMtu = pUmDevice->mtu;
+ pDevice->RxJumboDescCnt = DEFAULT_JUMBO_RCV_DESC_COUNT;
+ } else {
+ pDevice->RxJumboDescCnt = 0;
+ }
+ pDevice->RxJumboDescCnt = rx_jumbo_desc_cnt[index];
#else
- pDevice->RxMtu = pUmDevice->mtu;
+ pDevice->RxMtu = pUmDevice->mtu;
#endif
- if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) {
- pDevice->UseTaggedStatus = TRUE;
- pUmDevice->timer_interval = CFG_HZ;
- }
- else {
- pUmDevice->timer_interval = CFG_HZ/50;
- }
-
- pDevice->TxPacketDescCnt = tx_pkt_desc_cnt[index];
- pDevice->RxStdDescCnt = rx_std_desc_cnt[index];
- /* Note: adaptive coalescence really isn't adaptive in this driver */
- pUmDevice->rx_adaptive_coalesce = rx_adaptive_coalesce[index];
- if (!pUmDevice->rx_adaptive_coalesce) {
- pDevice->RxCoalescingTicks = rx_coalesce_ticks[index];
- if (pDevice->RxCoalescingTicks > MAX_RX_COALESCING_TICKS)
- pDevice->RxCoalescingTicks = MAX_RX_COALESCING_TICKS;
- pUmDevice->rx_curr_coalesce_ticks =pDevice->RxCoalescingTicks;
-
- pDevice->RxMaxCoalescedFrames = rx_max_coalesce_frames[index];
- if (pDevice->RxMaxCoalescedFrames>MAX_RX_MAX_COALESCED_FRAMES)
- pDevice->RxMaxCoalescedFrames =
- MAX_RX_MAX_COALESCED_FRAMES;
- pUmDevice->rx_curr_coalesce_frames =
- pDevice->RxMaxCoalescedFrames;
- pDevice->StatsCoalescingTicks = stats_coalesce_ticks[index];
- if (pDevice->StatsCoalescingTicks>MAX_STATS_COALESCING_TICKS)
- pDevice->StatsCoalescingTicks=
- MAX_STATS_COALESCING_TICKS;
- }
- else {
- pUmDevice->rx_curr_coalesce_frames =
- DEFAULT_RX_MAX_COALESCED_FRAMES;
- pUmDevice->rx_curr_coalesce_ticks =
- DEFAULT_RX_COALESCING_TICKS;
+ if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
+ pDevice->UseTaggedStatus = TRUE;
+ pUmDevice->timer_interval = CFG_HZ;
+ } else {
+ pUmDevice->timer_interval = CFG_HZ / 50;
}
- pDevice->TxCoalescingTicks = tx_coalesce_ticks[index];
- if (pDevice->TxCoalescingTicks > MAX_TX_COALESCING_TICKS)
- pDevice->TxCoalescingTicks = MAX_TX_COALESCING_TICKS;
- pDevice->TxMaxCoalescedFrames = tx_max_coalesce_frames[index];
- if (pDevice->TxMaxCoalescedFrames > MAX_TX_MAX_COALESCED_FRAMES)
- pDevice->TxMaxCoalescedFrames = MAX_TX_MAX_COALESCED_FRAMES;
- if (enable_wol[index]) {
- pDevice->WakeUpModeCap = LM_WAKE_UP_MODE_MAGIC_PACKET;
- pDevice->WakeUpMode = LM_WAKE_UP_MODE_MAGIC_PACKET;
- }
- pDevice->NicSendBd = TRUE;
+ pDevice->TxPacketDescCnt = tx_pkt_desc_cnt[index];
+ pDevice->RxStdDescCnt = rx_std_desc_cnt[index];
+ /* Note: adaptive coalescence really isn't adaptive in this driver */
+ pUmDevice->rx_adaptive_coalesce = rx_adaptive_coalesce[index];
+ if (!pUmDevice->rx_adaptive_coalesce) {
+ pDevice->RxCoalescingTicks = rx_coalesce_ticks[index];
+ if (pDevice->RxCoalescingTicks > MAX_RX_COALESCING_TICKS)
+ pDevice->RxCoalescingTicks = MAX_RX_COALESCING_TICKS;
+ pUmDevice->rx_curr_coalesce_ticks = pDevice->RxCoalescingTicks;
+
+ pDevice->RxMaxCoalescedFrames = rx_max_coalesce_frames[index];
+ if (pDevice->RxMaxCoalescedFrames > MAX_RX_MAX_COALESCED_FRAMES)
+ pDevice->RxMaxCoalescedFrames =
+ MAX_RX_MAX_COALESCED_FRAMES;
+ pUmDevice->rx_curr_coalesce_frames =
+ pDevice->RxMaxCoalescedFrames;
+ pDevice->StatsCoalescingTicks = stats_coalesce_ticks[index];
+ if (pDevice->StatsCoalescingTicks > MAX_STATS_COALESCING_TICKS)
+ pDevice->StatsCoalescingTicks =
+ MAX_STATS_COALESCING_TICKS;
+ } else {
+ pUmDevice->rx_curr_coalesce_frames =
+ DEFAULT_RX_MAX_COALESCED_FRAMES;
+ pUmDevice->rx_curr_coalesce_ticks = DEFAULT_RX_COALESCING_TICKS;
+ }
+ pDevice->TxCoalescingTicks = tx_coalesce_ticks[index];
+ if (pDevice->TxCoalescingTicks > MAX_TX_COALESCING_TICKS)
+ pDevice->TxCoalescingTicks = MAX_TX_COALESCING_TICKS;
+ pDevice->TxMaxCoalescedFrames = tx_max_coalesce_frames[index];
+ if (pDevice->TxMaxCoalescedFrames > MAX_TX_MAX_COALESCED_FRAMES)
+ pDevice->TxMaxCoalescedFrames = MAX_TX_MAX_COALESCED_FRAMES;
+
+ if (enable_wol[index]) {
+ pDevice->WakeUpModeCap = LM_WAKE_UP_MODE_MAGIC_PACKET;
+ pDevice->WakeUpMode = LM_WAKE_UP_MODE_MAGIC_PACKET;
+ }
+ pDevice->NicSendBd = TRUE;
- /* Don't update status blocks during interrupt */
- pDevice->RxCoalescingTicksDuringInt = 0;
- pDevice->TxCoalescingTicksDuringInt = 0;
+ /* Don't update status blocks during interrupt */
+ pDevice->RxCoalescingTicksDuringInt = 0;
+ pDevice->TxCoalescingTicksDuringInt = 0;
- return LM_STATUS_SUCCESS;
+ return LM_STATUS_SUCCESS;
}
-
-LM_STATUS
-MM_StartTxDma(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket)
+LM_STATUS MM_StartTxDma (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket)
{
- PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
- printf("Start TX DMA: dev=%d packet @0x%x\n",
- (int)pUmDevice->index, (unsigned int)pPacket);
+ PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
+ printf ("Start TX DMA: dev=%d packet @0x%x\n",
+ (int)pUmDevice->index, (unsigned int)pPacket);
- return LM_STATUS_SUCCESS;
+ return LM_STATUS_SUCCESS;
}
-LM_STATUS
-MM_CompleteTxDma(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket)
+LM_STATUS MM_CompleteTxDma (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket)
{
- PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
- printf("Complete TX DMA: dev=%d packet @0x%x\n",
- (int)pUmDevice->index, (unsigned int)pPacket);
- return LM_STATUS_SUCCESS;
+ PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
+ printf ("Complete TX DMA: dev=%d packet @0x%x\n",
+ (int)pUmDevice->index, (unsigned int)pPacket);
+ return LM_STATUS_SUCCESS;
}
-
-LM_STATUS
-MM_IndicateStatus(PLM_DEVICE_BLOCK pDevice, LM_STATUS Status)
+LM_STATUS MM_IndicateStatus (PLM_DEVICE_BLOCK pDevice, LM_STATUS Status)
{
- char buf[128];
- char lcd[4];
- PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
- LM_FLOW_CONTROL flow_control;
-
- pUmDevice->delayed_link_ind = 0;
- memset(lcd, 0x0, 4);
-
- if (Status == LM_STATUS_LINK_DOWN) {
- sprintf(buf,"eth%d: %s: NIC Link is down\n",
- pUmDevice->index,pUmDevice->name);
- lcd[0] = 'L';lcd[1]='N';lcd[2]='K';lcd[3] = '?';
- } else if (Status == LM_STATUS_LINK_ACTIVE) {
- sprintf(buf,"eth%d:%s: ", pUmDevice->index, pUmDevice->name);
-
- if (pDevice->LineSpeed == LM_LINE_SPEED_1000MBPS){
- strcat(buf,"1000 Mbps ");
- lcd[0] = '1';lcd[1]='G';lcd[2]='B';
- } else if (pDevice->LineSpeed == LM_LINE_SPEED_100MBPS){
- strcat(buf,"100 Mbps ");
- lcd[0] = '1';lcd[1]='0';lcd[2]='0';
- } else if (pDevice->LineSpeed == LM_LINE_SPEED_10MBPS){
- strcat(buf,"10 Mbps ");
- lcd[0] = '1';lcd[1]='0';lcd[2]=' ';
- }
- if (pDevice->DuplexMode == LM_DUPLEX_MODE_FULL){
- strcat(buf, "full duplex");
- lcd[3] = 'F';
- } else {
- strcat(buf, "half duplex");
- lcd[3] = 'H';
- }
- strcat(buf, " link up");
-
- flow_control = pDevice->FlowControl &
- (LM_FLOW_CONTROL_RECEIVE_PAUSE |
- LM_FLOW_CONTROL_TRANSMIT_PAUSE);
-
- if (flow_control) {
- if (flow_control & LM_FLOW_CONTROL_RECEIVE_PAUSE) {
- strcat(buf,", receive ");
- if (flow_control & LM_FLOW_CONTROL_TRANSMIT_PAUSE)
- strcat(buf," & transmit ");
- }
- else {
- strcat(buf,", transmit ");
- }
- strcat(buf,"flow control ON");
- } else {
- strcat(buf, ", flow control OFF");
+ char buf[128];
+ char lcd[4];
+ PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
+ LM_FLOW_CONTROL flow_control;
+
+ pUmDevice->delayed_link_ind = 0;
+ memset (lcd, 0x0, 4);
+
+ if (Status == LM_STATUS_LINK_DOWN) {
+ sprintf (buf, "eth%d: %s: NIC Link is down\n",
+ pUmDevice->index, pUmDevice->name);
+ lcd[0] = 'L';
+ lcd[1] = 'N';
+ lcd[2] = 'K';
+ lcd[3] = '?';
+ } else if (Status == LM_STATUS_LINK_ACTIVE) {
+ sprintf (buf, "eth%d:%s: ", pUmDevice->index, pUmDevice->name);
+
+ if (pDevice->LineSpeed == LM_LINE_SPEED_1000MBPS) {
+ strcat (buf, "1000 Mbps ");
+ lcd[0] = '1';
+ lcd[1] = 'G';
+ lcd[2] = 'B';
+ } else if (pDevice->LineSpeed == LM_LINE_SPEED_100MBPS) {
+ strcat (buf, "100 Mbps ");
+ lcd[0] = '1';
+ lcd[1] = '0';
+ lcd[2] = '0';
+ } else if (pDevice->LineSpeed == LM_LINE_SPEED_10MBPS) {
+ strcat (buf, "10 Mbps ");
+ lcd[0] = '1';
+ lcd[1] = '0';
+ lcd[2] = ' ';
+ }
+ if (pDevice->DuplexMode == LM_DUPLEX_MODE_FULL) {
+ strcat (buf, "full duplex");
+ lcd[3] = 'F';
+ } else {
+ strcat (buf, "half duplex");
+ lcd[3] = 'H';
+ }
+ strcat (buf, " link up");
+
+ flow_control = pDevice->FlowControl &
+ (LM_FLOW_CONTROL_RECEIVE_PAUSE |
+ LM_FLOW_CONTROL_TRANSMIT_PAUSE);
+
+ if (flow_control) {
+ if (flow_control & LM_FLOW_CONTROL_RECEIVE_PAUSE) {
+ strcat (buf, ", receive ");
+ if (flow_control &
+ LM_FLOW_CONTROL_TRANSMIT_PAUSE)
+ strcat (buf, " & transmit ");
+ } else {
+ strcat (buf, ", transmit ");
+ }
+ strcat (buf, "flow control ON");
+ } else {
+ strcat (buf, ", flow control OFF");
+ }
+ strcat (buf, "\n");
+ printf ("%s", buf);
}
- strcat(buf,"\n");
- printf("%s",buf);
- }
#if 0
- sysLedDsply(lcd[0],lcd[1],lcd[2],lcd[3]);
+ sysLedDsply (lcd[0], lcd[1], lcd[2], lcd[3]);
#endif
- return LM_STATUS_SUCCESS;
+ return LM_STATUS_SUCCESS;
}
-LM_STATUS
-MM_FreeRxBuffer(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket)
+LM_STATUS MM_FreeRxBuffer (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket)
{
- PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
- PUM_PACKET pUmPacket;
- void *skb;
+ PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
+ PUM_PACKET pUmPacket;
+ void *skb;
- pUmPacket = (PUM_PACKET) pPacket;
+ pUmPacket = (PUM_PACKET) pPacket;
- if ((skb = pUmPacket->skbuff))
- bcm570xPktFree(pUmDevice->index, skb);
+ if ((skb = pUmPacket->skbuff))
+ bcm570xPktFree (pUmDevice->index, skb);
- pUmPacket->skbuff = 0;
+ pUmPacket->skbuff = 0;
- return LM_STATUS_SUCCESS;
+ return LM_STATUS_SUCCESS;
}
-unsigned long
-MM_AnGetCurrentTime_us(PAN_STATE_INFO pAnInfo)
+unsigned long MM_AnGetCurrentTime_us (PAN_STATE_INFO pAnInfo)
{
- return get_timer(0);
+ return get_timer (0);
}
/*
@@ -1258,86 +1220,82 @@ MM_AnGetCurrentTime_us(PAN_STATE_INFO pAnInfo)
* non-fatal. The incoming cluster chain is not freed, giving
* the caller the choice of whether to try a retransmit later.
*/
-LM_STATUS
-MM_CoalesceTxBuffer(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket)
+LM_STATUS MM_CoalesceTxBuffer (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket)
{
- PUM_PACKET pUmPacket = (PUM_PACKET) pPacket;
- PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
- void *skbnew;
- int len = 0;
-
- if (len == 0)
- return (LM_STATUS_SUCCESS);
-
- if (len > MAX_PACKET_SIZE){
- printf ("eth%d: xmit frame discarded, too big!, size = %d\n",
- pUmDevice->index, len);
- return (LM_STATUS_FAILURE);
- }
+ PUM_PACKET pUmPacket = (PUM_PACKET) pPacket;
+ PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
+ void *skbnew;
+ int len = 0;
+
+ if (len == 0)
+ return (LM_STATUS_SUCCESS);
+
+ if (len > MAX_PACKET_SIZE) {
+ printf ("eth%d: xmit frame discarded, too big!, size = %d\n",
+ pUmDevice->index, len);
+ return (LM_STATUS_FAILURE);
+ }
- skbnew = bcm570xPktAlloc(pUmDevice->index, MAX_PACKET_SIZE);
+ skbnew = bcm570xPktAlloc (pUmDevice->index, MAX_PACKET_SIZE);
- if (skbnew == NULL) {
- pUmDevice->tx_full = 1;
- printf ("eth%d: out of transmit buffers", pUmDevice->index);
- return (LM_STATUS_FAILURE);
- }
+ if (skbnew == NULL) {
+ pUmDevice->tx_full = 1;
+ printf ("eth%d: out of transmit buffers", pUmDevice->index);
+ return (LM_STATUS_FAILURE);
+ }
- /* New packet values */
- pUmPacket->skbuff = skbnew;
- pUmPacket->lm_packet.u.Tx.FragCount = 1;
+ /* New packet values */
+ pUmPacket->skbuff = skbnew;
+ pUmPacket->lm_packet.u.Tx.FragCount = 1;
- return (LM_STATUS_SUCCESS);
+ return (LM_STATUS_SUCCESS);
}
-
-LM_STATUS
-MM_IndicateRxPackets(PLM_DEVICE_BLOCK pDevice)
+LM_STATUS MM_IndicateRxPackets (PLM_DEVICE_BLOCK pDevice)
{
- PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
- pUmDevice->rx_pkt = 1;
- return LM_STATUS_SUCCESS;
+ PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
+ pUmDevice->rx_pkt = 1;
+ return LM_STATUS_SUCCESS;
}
-LM_STATUS
-MM_IndicateTxPackets(PLM_DEVICE_BLOCK pDevice)
+LM_STATUS MM_IndicateTxPackets (PLM_DEVICE_BLOCK pDevice)
{
- PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
- PLM_PACKET pPacket;
- PUM_PACKET pUmPacket;
- void *skb;
- while ( TRUE ) {
-
- pPacket = (PLM_PACKET)
- QQ_PopHead(&pDevice->TxPacketXmittedQ.Container);
-
- if (pPacket == 0)
- break;
-
- pUmPacket = (PUM_PACKET) pPacket;
- skb = (void*)pUmPacket->skbuff;
-
- /*
- * Free MBLK if we transmitted a fragmented packet or a
- * non-fragmented packet straight from the VxWorks
- * buffer pool. If packet was copied to a local transmit
- * buffer, then there's no MBUF to free, just free
- * the transmit buffer back to the cluster pool.
- */
-
- if (skb)
- bcm570xPktFree (pUmDevice->index, skb);
-
- pUmPacket->skbuff = 0;
- QQ_PushTail(&pDevice->TxPacketFreeQ.Container, pPacket);
- pUmDevice->tx_pkt = 1;
- }
- if (pUmDevice->tx_full) {
- if (QQ_GetEntryCnt(&pDevice->TxPacketFreeQ.Container) >=
- (QQ_GetSize(&pDevice->TxPacketFreeQ.Container) >> 1))
- pUmDevice->tx_full = 0;
- }
- return LM_STATUS_SUCCESS;
+ PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
+ PLM_PACKET pPacket;
+ PUM_PACKET pUmPacket;
+ void *skb;
+ while (TRUE) {
+
+ pPacket = (PLM_PACKET)
+ QQ_PopHead (&pDevice->TxPacketXmittedQ.Container);
+
+ if (pPacket == 0)
+ break;
+
+ pUmPacket = (PUM_PACKET) pPacket;
+ skb = (void *)pUmPacket->skbuff;
+
+ /*
+ * Free MBLK if we transmitted a fragmented packet or a
+ * non-fragmented packet straight from the VxWorks
+ * buffer pool. If packet was copied to a local transmit
+ * buffer, then there's no MBUF to free, just free
+ * the transmit buffer back to the cluster pool.
+ */
+
+ if (skb)
+ bcm570xPktFree (pUmDevice->index, skb);
+
+ pUmPacket->skbuff = 0;
+ QQ_PushTail (&pDevice->TxPacketFreeQ.Container, pPacket);
+ pUmDevice->tx_pkt = 1;
+ }
+ if (pUmDevice->tx_full) {
+ if (QQ_GetEntryCnt (&pDevice->TxPacketFreeQ.Container) >=
+ (QQ_GetSize (&pDevice->TxPacketFreeQ.Container) >> 1))
+ pUmDevice->tx_full = 0;
+ }
+ return LM_STATUS_SUCCESS;
}
/*
@@ -1345,16 +1303,12 @@ MM_IndicateTxPackets(PLM_DEVICE_BLOCK pDevice)
* Return its length and physical address.
*/
void MM_MapTxDma
- (
- PLM_DEVICE_BLOCK pDevice,
- struct _LM_PACKET *pPacket,
- T3_64BIT_HOST_ADDR *paddr,
- LM_UINT32 *len,
- int frag)
-{
- PUM_PACKET pUmPacket = (PUM_PACKET) pPacket;
- *len = pPacket->PacketSize;
- MM_SetT3Addr(paddr, (dma_addr_t) pUmPacket->skbuff);
+ (PLM_DEVICE_BLOCK pDevice,
+ struct _LM_PACKET *pPacket,
+ T3_64BIT_HOST_ADDR * paddr, LM_UINT32 * len, int frag) {
+ PUM_PACKET pUmPacket = (PUM_PACKET) pPacket;
+ *len = pPacket->PacketSize;
+ MM_SetT3Addr (paddr, (dma_addr_t) pUmPacket->skbuff);
}
/*
@@ -1362,35 +1316,31 @@ void MM_MapTxDma
* to a physical address as seen from a PCI device. Store the
* result at paddr.
*/
-void MM_MapRxDma(
- PLM_DEVICE_BLOCK pDevice,
- struct _LM_PACKET *pPacket,
- T3_64BIT_HOST_ADDR *paddr)
+void MM_MapRxDma (PLM_DEVICE_BLOCK pDevice,
+ struct _LM_PACKET *pPacket, T3_64BIT_HOST_ADDR * paddr)
{
- PUM_PACKET pUmPacket = (PUM_PACKET) pPacket;
- MM_SetT3Addr(paddr, (dma_addr_t) pUmPacket->skbuff);
+ PUM_PACKET pUmPacket = (PUM_PACKET) pPacket;
+ MM_SetT3Addr (paddr, (dma_addr_t) pUmPacket->skbuff);
}
-void
-MM_SetAddr (LM_PHYSICAL_ADDRESS *paddr, dma_addr_t addr)
+void MM_SetAddr (LM_PHYSICAL_ADDRESS * paddr, dma_addr_t addr)
{
#if (BITS_PER_LONG == 64)
- paddr->High = ((unsigned long) addr) >> 32;
- paddr->Low = ((unsigned long) addr) & 0xffffffff;
+ paddr->High = ((unsigned long)addr) >> 32;
+ paddr->Low = ((unsigned long)addr) & 0xffffffff;
#else
paddr->High = 0;
- paddr->Low = (unsigned long) addr;
+ paddr->Low = (unsigned long)addr;
#endif
}
-void
-MM_SetT3Addr(T3_64BIT_HOST_ADDR *paddr, dma_addr_t addr)
+void MM_SetT3Addr (T3_64BIT_HOST_ADDR * paddr, dma_addr_t addr)
{
- unsigned long baddr = (unsigned long) addr;
+ unsigned long baddr = (unsigned long)addr;
#if (BITS_PER_LONG == 64)
- set_64bit_addr(paddr, baddr & 0xffffffff, baddr >> 32);
+ set_64bit_addr (paddr, baddr & 0xffffffff, baddr >> 32);
#else
- set_64bit_addr(paddr, baddr, 0);
+ set_64bit_addr (paddr, baddr, 0);
#endif
}
@@ -1403,42 +1353,38 @@ MM_SetT3Addr(T3_64BIT_HOST_ADDR *paddr, dma_addr_t addr)
* If any uses of the function remain, they will refer to the single copy
* in the library.
*/
-void
-atomic_set(atomic_t* entry, int val)
+void atomic_set (atomic_t * entry, int val)
{
- entry->counter = val;
+ entry->counter = val;
}
-int
-atomic_read(atomic_t* entry)
+
+int atomic_read (atomic_t * entry)
{
- return entry->counter;
+ return entry->counter;
}
-void
-atomic_inc(atomic_t* entry)
+
+void atomic_inc (atomic_t * entry)
{
- if(entry)
- entry->counter++;
+ if (entry)
+ entry->counter++;
}
-void
-atomic_dec(atomic_t* entry)
+void atomic_dec (atomic_t * entry)
{
- if(entry)
- entry->counter--;
+ if (entry)
+ entry->counter--;
}
-void
-atomic_sub(int a, atomic_t* entry)
+void atomic_sub (int a, atomic_t * entry)
{
- if(entry)
- entry->counter -= a;
+ if (entry)
+ entry->counter -= a;
}
-void
-atomic_add(int a, atomic_t* entry)
+void atomic_add (int a, atomic_t * entry)
{
- if(entry)
- entry->counter += a;
+ if (entry)
+ entry->counter += a;
}
/******************************************************************************/
@@ -1446,68 +1392,57 @@ atomic_add(int a, atomic_t* entry)
/* */
/* Return: */
/******************************************************************************/
-void
-QQ_InitQueue(
-PQQ_CONTAINER pQueue,
-unsigned int QueueSize) {
- pQueue->Head = 0;
- pQueue->Tail = 0;
- pQueue->Size = QueueSize+1;
- atomic_set(&pQueue->EntryCnt, 0);
-} /* QQ_InitQueue */
-
+void QQ_InitQueue (PQQ_CONTAINER pQueue, unsigned int QueueSize)
+{
+ pQueue->Head = 0;
+ pQueue->Tail = 0;
+ pQueue->Size = QueueSize + 1;
+ atomic_set (&pQueue->EntryCnt, 0);
+} /* QQ_InitQueue */
/******************************************************************************/
/* Description: */
/* */
/* Return: */
/******************************************************************************/
-char
-QQ_Full(
-PQQ_CONTAINER pQueue) {
- unsigned int NewHead;
-
- NewHead = (pQueue->Head + 1) % pQueue->Size;
+char QQ_Full (PQQ_CONTAINER pQueue)
+{
+ unsigned int NewHead;
- return(NewHead == pQueue->Tail);
-} /* QQ_Full */
+ NewHead = (pQueue->Head + 1) % pQueue->Size;
+ return (NewHead == pQueue->Tail);
+} /* QQ_Full */
/******************************************************************************/
/* Description: */
/* */
/* Return: */
/******************************************************************************/
-char
-QQ_Empty(
-PQQ_CONTAINER pQueue) {
- return(pQueue->Head == pQueue->Tail);
-} /* QQ_Empty */
-
+char QQ_Empty (PQQ_CONTAINER pQueue)
+{
+ return (pQueue->Head == pQueue->Tail);
+} /* QQ_Empty */
/******************************************************************************/
/* Description: */
/* */
/* Return: */
/******************************************************************************/
-unsigned int
-QQ_GetSize(
-PQQ_CONTAINER pQueue) {
- return pQueue->Size;
-} /* QQ_GetSize */
-
+unsigned int QQ_GetSize (PQQ_CONTAINER pQueue)
+{
+ return pQueue->Size;
+} /* QQ_GetSize */
/******************************************************************************/
/* Description: */
/* */
/* Return: */
/******************************************************************************/
-unsigned int
-QQ_GetEntryCnt(
-PQQ_CONTAINER pQueue) {
- return atomic_read(&pQueue->EntryCnt);
-} /* QQ_GetEntryCnt */
-
+unsigned int QQ_GetEntryCnt (PQQ_CONTAINER pQueue)
+{
+ return atomic_read (&pQueue->EntryCnt);
+} /* QQ_GetEntryCnt */
/******************************************************************************/
/* Description: */
@@ -1516,28 +1451,25 @@ PQQ_CONTAINER pQueue) {
/* TRUE entry was added successfully. */
/* FALSE queue is full. */
/******************************************************************************/
-char
-QQ_PushHead(
-PQQ_CONTAINER pQueue,
-PQQ_ENTRY pEntry) {
- unsigned int Head;
+char QQ_PushHead (PQQ_CONTAINER pQueue, PQQ_ENTRY pEntry)
+{
+ unsigned int Head;
- Head = (pQueue->Head + 1) % pQueue->Size;
+ Head = (pQueue->Head + 1) % pQueue->Size;
#if !defined(QQ_NO_OVERFLOW_CHECK)
- if(Head == pQueue->Tail) {
- return 0;
- } /* if */
-#endif /* QQ_NO_OVERFLOW_CHECK */
+ if (Head == pQueue->Tail) {
+ return 0;
+ } /* if */
+#endif /* QQ_NO_OVERFLOW_CHECK */
- pQueue->Array[pQueue->Head] = pEntry;
- wmb();
- pQueue->Head = Head;
- atomic_inc(&pQueue->EntryCnt);
-
- return -1;
-} /* QQ_PushHead */
+ pQueue->Array[pQueue->Head] = pEntry;
+ wmb ();
+ pQueue->Head = Head;
+ atomic_inc (&pQueue->EntryCnt);
+ return -1;
+} /* QQ_PushHead */
/******************************************************************************/
/* Description: */
@@ -1546,146 +1478,126 @@ PQQ_ENTRY pEntry) {
/* TRUE entry was added successfully. */
/* FALSE queue is full. */
/******************************************************************************/
-char
-QQ_PushTail(
-PQQ_CONTAINER pQueue,
-PQQ_ENTRY pEntry) {
- unsigned int Tail;
-
- Tail = pQueue->Tail;
- if(Tail == 0) {
- Tail = pQueue->Size;
- } /* if */
- Tail--;
+char QQ_PushTail (PQQ_CONTAINER pQueue, PQQ_ENTRY pEntry)
+{
+ unsigned int Tail;
-#if !defined(QQ_NO_OVERFLOW_CHECK)
- if(Tail == pQueue->Head) {
- return 0;
- } /* if */
-#endif /* QQ_NO_OVERFLOW_CHECK */
+ Tail = pQueue->Tail;
+ if (Tail == 0) {
+ Tail = pQueue->Size;
+ } /* if */
+ Tail--;
- pQueue->Array[Tail] = pEntry;
- wmb();
- pQueue->Tail = Tail;
- atomic_inc(&pQueue->EntryCnt);
+#if !defined(QQ_NO_OVERFLOW_CHECK)
+ if (Tail == pQueue->Head) {
+ return 0;
+ } /* if */
+#endif /* QQ_NO_OVERFLOW_CHECK */
- return -1;
-} /* QQ_PushTail */
+ pQueue->Array[Tail] = pEntry;
+ wmb ();
+ pQueue->Tail = Tail;
+ atomic_inc (&pQueue->EntryCnt);
+ return -1;
+} /* QQ_PushTail */
/******************************************************************************/
/* Description: */
/* */
/* Return: */
/******************************************************************************/
-PQQ_ENTRY
-QQ_PopHead(
-PQQ_CONTAINER pQueue) {
- unsigned int Head;
- PQQ_ENTRY Entry;
+PQQ_ENTRY QQ_PopHead (PQQ_CONTAINER pQueue)
+{
+ unsigned int Head;
+ PQQ_ENTRY Entry;
- Head = pQueue->Head;
+ Head = pQueue->Head;
#if !defined(QQ_NO_UNDERFLOW_CHECK)
- if(Head == pQueue->Tail) {
- return (PQQ_ENTRY) 0;
- } /* if */
-#endif /* QQ_NO_UNDERFLOW_CHECK */
-
- if(Head == 0) {
- Head = pQueue->Size;
- } /* if */
- Head--;
+ if (Head == pQueue->Tail) {
+ return (PQQ_ENTRY) 0;
+ } /* if */
+#endif /* QQ_NO_UNDERFLOW_CHECK */
- Entry = pQueue->Array[Head];
- membar();
+ if (Head == 0) {
+ Head = pQueue->Size;
+ } /* if */
+ Head--;
- pQueue->Head = Head;
- atomic_dec(&pQueue->EntryCnt);
+ Entry = pQueue->Array[Head];
+ membar ();
- return Entry;
-} /* QQ_PopHead */
+ pQueue->Head = Head;
+ atomic_dec (&pQueue->EntryCnt);
+ return Entry;
+} /* QQ_PopHead */
/******************************************************************************/
/* Description: */
/* */
/* Return: */
/******************************************************************************/
-PQQ_ENTRY
-QQ_PopTail(
-PQQ_CONTAINER pQueue) {
- unsigned int Tail;
- PQQ_ENTRY Entry;
+PQQ_ENTRY QQ_PopTail (PQQ_CONTAINER pQueue)
+{
+ unsigned int Tail;
+ PQQ_ENTRY Entry;
- Tail = pQueue->Tail;
+ Tail = pQueue->Tail;
#if !defined(QQ_NO_UNDERFLOW_CHECK)
- if(Tail == pQueue->Head) {
- return (PQQ_ENTRY) 0;
- } /* if */
-#endif /* QQ_NO_UNDERFLOW_CHECK */
-
- Entry = pQueue->Array[Tail];
- membar();
- pQueue->Tail = (Tail + 1) % pQueue->Size;
- atomic_dec(&pQueue->EntryCnt);
+ if (Tail == pQueue->Head) {
+ return (PQQ_ENTRY) 0;
+ } /* if */
+#endif /* QQ_NO_UNDERFLOW_CHECK */
- return Entry;
-} /* QQ_PopTail */
+ Entry = pQueue->Array[Tail];
+ membar ();
+ pQueue->Tail = (Tail + 1) % pQueue->Size;
+ atomic_dec (&pQueue->EntryCnt);
+ return Entry;
+} /* QQ_PopTail */
/******************************************************************************/
/* Description: */
/* */
/* Return: */
/******************************************************************************/
-PQQ_ENTRY
-QQ_GetHead(
- PQQ_CONTAINER pQueue,
- unsigned int Idx)
+PQQ_ENTRY QQ_GetHead (PQQ_CONTAINER pQueue, unsigned int Idx)
{
- if(Idx >= atomic_read(&pQueue->EntryCnt))
- {
- return (PQQ_ENTRY) 0;
- }
-
- if(pQueue->Head > Idx)
- {
- Idx = pQueue->Head - Idx;
- }
- else
- {
- Idx = pQueue->Size - (Idx - pQueue->Head);
- }
- Idx--;
-
- return pQueue->Array[Idx];
-}
+ if (Idx >= atomic_read (&pQueue->EntryCnt)) {
+ return (PQQ_ENTRY) 0;
+ }
+
+ if (pQueue->Head > Idx) {
+ Idx = pQueue->Head - Idx;
+ } else {
+ Idx = pQueue->Size - (Idx - pQueue->Head);
+ }
+ Idx--;
+ return pQueue->Array[Idx];
+}
/******************************************************************************/
/* Description: */
/* */
/* Return: */
/******************************************************************************/
-PQQ_ENTRY
-QQ_GetTail(
- PQQ_CONTAINER pQueue,
- unsigned int Idx)
+PQQ_ENTRY QQ_GetTail (PQQ_CONTAINER pQueue, unsigned int Idx)
{
- if(Idx >= atomic_read(&pQueue->EntryCnt))
- {
- return (PQQ_ENTRY) 0;
- }
-
- Idx += pQueue->Tail;
- if(Idx >= pQueue->Size)
- {
- Idx = Idx - pQueue->Size;
- }
-
- return pQueue->Array[Idx];
+ if (Idx >= atomic_read (&pQueue->EntryCnt)) {
+ return (PQQ_ENTRY) 0;
+ }
+
+ Idx += pQueue->Tail;
+ if (Idx >= pQueue->Size) {
+ Idx = Idx - pQueue->Size;
+ }
+
+ return pQueue->Array[Idx];
}
#endif
diff --git a/drivers/bcm570x_lm.h b/drivers/bcm570x_lm.h
index 607f3fd..2ea6ca8 100644
--- a/drivers/bcm570x_lm.h
+++ b/drivers/bcm570x_lm.h
@@ -19,29 +19,28 @@
#include "bcm570x_queue.h"
#include "bcm570x_bits.h"
-
/******************************************************************************/
/* Basic types. */
/******************************************************************************/
-typedef char LM_CHAR, *PLM_CHAR;
-typedef unsigned int LM_UINT, *PLM_UINT;
-typedef unsigned char LM_UINT8, *PLM_UINT8;
-typedef unsigned short LM_UINT16, *PLM_UINT16;
-typedef unsigned int LM_UINT32, *PLM_UINT32;
-typedef unsigned int LM_COUNTER, *PLM_COUNTER;
-typedef void LM_VOID, *PLM_VOID;
-typedef char LM_BOOL, *PLM_BOOL;
+typedef char LM_CHAR, *PLM_CHAR;
+typedef unsigned int LM_UINT, *PLM_UINT;
+typedef unsigned char LM_UINT8, *PLM_UINT8;
+typedef unsigned short LM_UINT16, *PLM_UINT16;
+typedef unsigned int LM_UINT32, *PLM_UINT32;
+typedef unsigned int LM_COUNTER, *PLM_COUNTER;
+typedef void LM_VOID, *PLM_VOID;
+typedef char LM_BOOL, *PLM_BOOL;
/* 64bit value. */
typedef struct {
#ifdef BIG_ENDIAN_HOST
- LM_UINT32 High;
- LM_UINT32 Low;
-#else /* BIG_ENDIAN_HOST */
- LM_UINT32 Low;
- LM_UINT32 High;
-#endif /* !BIG_ENDIAN_HOST */
+ LM_UINT32 High;
+ LM_UINT32 Low;
+#else /* BIG_ENDIAN_HOST */
+ LM_UINT32 Low;
+ LM_UINT32 High;
+#endif /* !BIG_ENDIAN_HOST */
} LM_UINT64, *PLM_UINT64;
typedef LM_UINT64 LM_PHYSICAL_ADDRESS, *PLM_PHYSICAL_ADDRESS;
@@ -58,15 +57,13 @@ typedef LM_UINT64 LM_PHYSICAL_ADDRESS, *PLM_PHYSICAL_ADDRESS;
} \
}
-
#ifndef NULL
#define NULL ((void *) 0)
-#endif /* NULL */
+#endif /* NULL */
#ifndef OFFSETOF
#define OFFSETOF(_s, _m) (MM_UINT_PTR(&(((_s *) 0)->_m)))
-#endif /* OFFSETOF */
-
+#endif /* OFFSETOF */
/******************************************************************************/
/* Simple macros. */
@@ -100,26 +97,24 @@ typedef LM_UINT64 LM_PHYSICAL_ADDRESS, *PLM_PHYSICAL_ADDRESS;
((unsigned char *) (_Dst))[4] = ((unsigned char *) (_Src))[4]; \
((unsigned char *) (_Dst))[5] = ((unsigned char *) (_Src))[5];
-
/******************************************************************************/
/* Constants. */
/******************************************************************************/
#define ETHERNET_ADDRESS_SIZE 6
#define ETHERNET_PACKET_HEADER_SIZE 14
-#define MIN_ETHERNET_PACKET_SIZE 64 /* with 4 byte crc. */
-#define MAX_ETHERNET_PACKET_SIZE 1518 /* with 4 byte crc. */
+#define MIN_ETHERNET_PACKET_SIZE 64 /* with 4 byte crc. */
+#define MAX_ETHERNET_PACKET_SIZE 1518 /* with 4 byte crc. */
#define MIN_ETHERNET_PACKET_SIZE_NO_CRC 60
#define MAX_ETHERNET_PACKET_SIZE_NO_CRC 1514
-#define MAX_ETHERNET_PACKET_BUFFER_SIZE 1536 /* A nice even number. */
+#define MAX_ETHERNET_PACKET_BUFFER_SIZE 1536 /* A nice even number. */
#ifndef LM_MAX_MC_TABLE_SIZE
#define LM_MAX_MC_TABLE_SIZE 32
-#endif /* LM_MAX_MC_TABLE_SIZE */
+#endif /* LM_MAX_MC_TABLE_SIZE */
#define LM_MC_ENTRY_SIZE (ETHERNET_ADDRESS_SIZE+1)
#define LM_MC_INSTANCE_COUNT_INDEX (LM_MC_ENTRY_SIZE-1)
-
/* Receive filter masks. */
#define LM_ACCEPT_UNICAST 0x0001
#define LM_ACCEPT_MULTICAST 0x0002
@@ -129,7 +124,6 @@ typedef LM_UINT64 LM_PHYSICAL_ADDRESS, *PLM_PHYSICAL_ADDRESS;
#define LM_PROMISCUOUS_MODE 0x10000
-
/******************************************************************************/
/* PCI registers. */
/******************************************************************************/
@@ -169,20 +163,20 @@ typedef LM_UINT64 LM_PHYSICAL_ADDRESS, *PLM_PHYSICAL_ADDRESS;
/******************************************************************************/
typedef struct {
- LM_UINT32 FragSize;
- LM_PHYSICAL_ADDRESS FragBuf;
+ LM_UINT32 FragSize;
+ LM_PHYSICAL_ADDRESS FragBuf;
} LM_FRAG, *PLM_FRAG;
typedef struct {
- /* FragCount is initialized for the caller to the maximum array size, on */
- /* return FragCount is the number of the actual fragments in the array. */
- LM_UINT32 FragCount;
+ /* FragCount is initialized for the caller to the maximum array size, on */
+ /* return FragCount is the number of the actual fragments in the array. */
+ LM_UINT32 FragCount;
- /* Total buffer size. */
- LM_UINT32 TotalSize;
+ /* Total buffer size. */
+ LM_UINT32 TotalSize;
- /* Fragment array buffer. */
- LM_FRAG Fragments[1];
+ /* Fragment array buffer. */
+ LM_FRAG Fragments[1];
} LM_FRAG_LIST, *PLM_FRAG_LIST;
#define DECLARE_FRAG_LIST_BUFFER_TYPE(_FRAG_LIST_TYPE_NAME, _MAX_FRAG_COUNT) \
@@ -191,7 +185,6 @@ typedef struct {
LM_FRAG FragListBuffer[_MAX_FRAG_COUNT-1]; \
} _FRAG_LIST_TYPE_NAME, *P##_FRAG_LIST_TYPE_NAME
-
/******************************************************************************/
/* Status codes. */
/******************************************************************************/
@@ -217,7 +210,6 @@ typedef struct {
typedef LM_UINT LM_STATUS, *PLM_STATUS;
-
/******************************************************************************/
/* Requested media type. */
/******************************************************************************/
@@ -240,7 +232,6 @@ typedef LM_UINT LM_STATUS, *PLM_STATUS;
typedef LM_UINT32 LM_REQUESTED_MEDIA_TYPE, *PLM_REQUESTED_MEDIA_TYPE;
-
/******************************************************************************/
/* Media type. */
/******************************************************************************/
@@ -254,7 +245,6 @@ typedef LM_UINT32 LM_REQUESTED_MEDIA_TYPE, *PLM_REQUESTED_MEDIA_TYPE;
typedef LM_UINT32 LM_MEDIA_TYPE, *PLM_MEDIA_TYPE;
-
/******************************************************************************/
/* Line speed. */
/******************************************************************************/
@@ -266,7 +256,6 @@ typedef LM_UINT32 LM_MEDIA_TYPE, *PLM_MEDIA_TYPE;
typedef LM_UINT32 LM_LINE_SPEED, *PLM_LINE_SPEED;
-
/******************************************************************************/
/* Duplex mode. */
/******************************************************************************/
@@ -277,7 +266,6 @@ typedef LM_UINT32 LM_LINE_SPEED, *PLM_LINE_SPEED;
typedef LM_UINT32 LM_DUPLEX_MODE, *PLM_DUPLEX_MODE;
-
/******************************************************************************/
/* Power state. */
/******************************************************************************/
@@ -289,7 +277,6 @@ typedef LM_UINT32 LM_DUPLEX_MODE, *PLM_DUPLEX_MODE;
typedef LM_UINT32 LM_POWER_STATE, *PLM_POWER_STATE;
-
/******************************************************************************/
/* Task offloading. */
/******************************************************************************/
@@ -305,7 +292,6 @@ typedef LM_UINT32 LM_POWER_STATE, *PLM_POWER_STATE;
typedef LM_UINT32 LM_TASK_OFFLOAD, *PLM_TASK_OFFLOAD;
-
/******************************************************************************/
/* Flow control. */
/******************************************************************************/
@@ -324,7 +310,6 @@ typedef LM_UINT32 LM_TASK_OFFLOAD, *PLM_TASK_OFFLOAD;
typedef LM_UINT32 LM_FLOW_CONTROL, *PLM_FLOW_CONTROL;
-
/******************************************************************************/
/* Wake up mode. */
/******************************************************************************/
@@ -336,7 +321,6 @@ typedef LM_UINT32 LM_FLOW_CONTROL, *PLM_FLOW_CONTROL;
typedef LM_UINT32 LM_WAKE_UP_MODE, *PLM_WAKE_UP_MODE;
-
/******************************************************************************/
/* Counters. */
/******************************************************************************/
@@ -362,7 +346,6 @@ typedef LM_UINT32 LM_WAKE_UP_MODE, *PLM_WAKE_UP_MODE;
typedef LM_UINT32 LM_COUNTER_TYPE, *PLM_COUNTER_TYPE;
-
/******************************************************************************/
/* Forward definition. */
/******************************************************************************/
@@ -370,82 +353,82 @@ typedef LM_UINT32 LM_COUNTER_TYPE, *PLM_COUNTER_TYPE;
typedef struct _LM_DEVICE_BLOCK *PLM_DEVICE_BLOCK;
typedef struct _LM_PACKET *PLM_PACKET;
-
/******************************************************************************/
/* Function prototypes. */
/******************************************************************************/
-LM_STATUS LM_GetAdapterInfo(PLM_DEVICE_BLOCK pDevice);
-LM_STATUS LM_InitializeAdapter(PLM_DEVICE_BLOCK pDevice);
-LM_STATUS LM_ResetAdapter(PLM_DEVICE_BLOCK pDevice);
-LM_STATUS LM_DisableInterrupt(PLM_DEVICE_BLOCK pDevice);
-LM_STATUS LM_EnableInterrupt(PLM_DEVICE_BLOCK pDevice);
-LM_STATUS LM_SendPacket(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket);
-LM_STATUS LM_ServiceInterrupts(PLM_DEVICE_BLOCK pDevice);
-LM_STATUS LM_QueueRxPackets(PLM_DEVICE_BLOCK pDevice);
-LM_STATUS LM_SetReceiveMask(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Mask);
-LM_STATUS LM_Halt(PLM_DEVICE_BLOCK pDevice);
-LM_STATUS LM_Abort(PLM_DEVICE_BLOCK pDevice);
-LM_STATUS LM_MulticastAdd(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMcAddress);
-LM_STATUS LM_MulticastDel(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMcAddress);
-LM_STATUS LM_MulticastClear(PLM_DEVICE_BLOCK pDevice);
-LM_STATUS LM_SetMacAddress(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMacAddress);
-LM_STATUS LM_LoopbackAddress(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pAddress);
-
-LM_UINT32 LM_GetCrcCounter(PLM_DEVICE_BLOCK pDevice);
-
-LM_WAKE_UP_MODE LM_PMCapabilities(PLM_DEVICE_BLOCK pDevice);
-LM_STATUS LM_NwufAdd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 ByteMaskSize,
- LM_UINT8 *pByteMask, LM_UINT8 *pPattern);
-LM_STATUS LM_NwufRemove(PLM_DEVICE_BLOCK pDevice, LM_UINT32 ByteMaskSize,
- LM_UINT8 *pByteMask, LM_UINT8 *pPattern);
-LM_STATUS LM_SetPowerState(PLM_DEVICE_BLOCK pDevice, LM_POWER_STATE PowerLevel);
-
-LM_VOID LM_ReadPhy(PLM_DEVICE_BLOCK pDevice, LM_UINT32 PhyReg,
- PLM_UINT32 pData32);
-LM_VOID LM_WritePhy(PLM_DEVICE_BLOCK pDevice, LM_UINT32 PhyReg,
- LM_UINT32 Data32);
-
-LM_STATUS LM_ControlLoopBack(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Control);
-LM_STATUS LM_SetupPhy(PLM_DEVICE_BLOCK pDevice);
-int LM_BlinkLED(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlinkDuration);
-
+LM_STATUS LM_GetAdapterInfo (PLM_DEVICE_BLOCK pDevice);
+LM_STATUS LM_InitializeAdapter (PLM_DEVICE_BLOCK pDevice);
+LM_STATUS LM_ResetAdapter (PLM_DEVICE_BLOCK pDevice);
+LM_STATUS LM_DisableInterrupt (PLM_DEVICE_BLOCK pDevice);
+LM_STATUS LM_EnableInterrupt (PLM_DEVICE_BLOCK pDevice);
+LM_STATUS LM_SendPacket (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket);
+LM_STATUS LM_ServiceInterrupts (PLM_DEVICE_BLOCK pDevice);
+LM_STATUS LM_QueueRxPackets (PLM_DEVICE_BLOCK pDevice);
+LM_STATUS LM_SetReceiveMask (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Mask);
+LM_STATUS LM_Halt (PLM_DEVICE_BLOCK pDevice);
+LM_STATUS LM_Abort (PLM_DEVICE_BLOCK pDevice);
+LM_STATUS LM_MulticastAdd (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMcAddress);
+LM_STATUS LM_MulticastDel (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMcAddress);
+LM_STATUS LM_MulticastClear (PLM_DEVICE_BLOCK pDevice);
+LM_STATUS LM_SetMacAddress (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMacAddress);
+LM_STATUS LM_LoopbackAddress (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pAddress);
+
+LM_UINT32 LM_GetCrcCounter (PLM_DEVICE_BLOCK pDevice);
+
+LM_WAKE_UP_MODE LM_PMCapabilities (PLM_DEVICE_BLOCK pDevice);
+LM_STATUS LM_NwufAdd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 ByteMaskSize,
+ LM_UINT8 * pByteMask, LM_UINT8 * pPattern);
+LM_STATUS LM_NwufRemove (PLM_DEVICE_BLOCK pDevice, LM_UINT32 ByteMaskSize,
+ LM_UINT8 * pByteMask, LM_UINT8 * pPattern);
+LM_STATUS LM_SetPowerState (PLM_DEVICE_BLOCK pDevice,
+ LM_POWER_STATE PowerLevel);
+
+LM_VOID LM_ReadPhy (PLM_DEVICE_BLOCK pDevice, LM_UINT32 PhyReg,
+ PLM_UINT32 pData32);
+LM_VOID LM_WritePhy (PLM_DEVICE_BLOCK pDevice, LM_UINT32 PhyReg,
+ LM_UINT32 Data32);
+
+LM_STATUS LM_ControlLoopBack (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Control);
+LM_STATUS LM_SetupPhy (PLM_DEVICE_BLOCK pDevice);
+int LM_BlinkLED (PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlinkDuration);
/******************************************************************************/
/* These are the OS specific functions called by LMAC. */
/******************************************************************************/
-LM_STATUS MM_ReadConfig16(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset,
- LM_UINT16 *pValue16);
-LM_STATUS MM_WriteConfig16(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset,
- LM_UINT16 Value16);
-LM_STATUS MM_ReadConfig32(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset,
- LM_UINT32 *pValue32);
-LM_STATUS MM_WriteConfig32(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset,
- LM_UINT32 Value32);
-LM_STATUS MM_MapMemBase(PLM_DEVICE_BLOCK pDevice);
-LM_STATUS MM_MapIoBase(PLM_DEVICE_BLOCK pDevice);
-LM_STATUS MM_IndicateRxPackets(PLM_DEVICE_BLOCK pDevice);
-LM_STATUS MM_IndicateTxPackets(PLM_DEVICE_BLOCK pDevice);
-LM_STATUS MM_StartTxDma(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket);
-LM_STATUS MM_CompleteTxDma(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket);
-LM_STATUS MM_AllocateMemory(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize,
- PLM_VOID *pMemoryBlockVirt);
-LM_STATUS MM_AllocateSharedMemory(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize,
- PLM_VOID *pMemoryBlockVirt, PLM_PHYSICAL_ADDRESS pMemoryBlockPhy,
- LM_BOOL Cached);
-LM_STATUS MM_GetConfig(PLM_DEVICE_BLOCK pDevice);
-LM_STATUS MM_IndicateStatus(PLM_DEVICE_BLOCK pDevice, LM_STATUS Status);
-LM_STATUS MM_InitializeUmPackets(PLM_DEVICE_BLOCK pDevice);
-LM_STATUS MM_FreeRxBuffer(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket);
-LM_STATUS MM_CoalesceTxBuffer(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket);
-LM_STATUS LM_MbufWorkAround(PLM_DEVICE_BLOCK pDevice);
-LM_STATUS LM_SetLinkSpeed(PLM_DEVICE_BLOCK pDevice,
- LM_REQUESTED_MEDIA_TYPE RequestedMediaType);
+LM_STATUS MM_ReadConfig16 (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset,
+ LM_UINT16 * pValue16);
+LM_STATUS MM_WriteConfig16 (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset,
+ LM_UINT16 Value16);
+LM_STATUS MM_ReadConfig32 (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset,
+ LM_UINT32 * pValue32);
+LM_STATUS MM_WriteConfig32 (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset,
+ LM_UINT32 Value32);
+LM_STATUS MM_MapMemBase (PLM_DEVICE_BLOCK pDevice);
+LM_STATUS MM_MapIoBase (PLM_DEVICE_BLOCK pDevice);
+LM_STATUS MM_IndicateRxPackets (PLM_DEVICE_BLOCK pDevice);
+LM_STATUS MM_IndicateTxPackets (PLM_DEVICE_BLOCK pDevice);
+LM_STATUS MM_StartTxDma (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket);
+LM_STATUS MM_CompleteTxDma (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket);
+LM_STATUS MM_AllocateMemory (PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize,
+ PLM_VOID * pMemoryBlockVirt);
+LM_STATUS MM_AllocateSharedMemory (PLM_DEVICE_BLOCK pDevice,
+ LM_UINT32 BlockSize,
+ PLM_VOID * pMemoryBlockVirt,
+ PLM_PHYSICAL_ADDRESS pMemoryBlockPhy,
+ LM_BOOL Cached);
+LM_STATUS MM_GetConfig (PLM_DEVICE_BLOCK pDevice);
+LM_STATUS MM_IndicateStatus (PLM_DEVICE_BLOCK pDevice, LM_STATUS Status);
+LM_STATUS MM_InitializeUmPackets (PLM_DEVICE_BLOCK pDevice);
+LM_STATUS MM_FreeRxBuffer (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket);
+LM_STATUS MM_CoalesceTxBuffer (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket);
+LM_STATUS LM_MbufWorkAround (PLM_DEVICE_BLOCK pDevice);
+LM_STATUS LM_SetLinkSpeed (PLM_DEVICE_BLOCK pDevice,
+ LM_REQUESTED_MEDIA_TYPE RequestedMediaType);
#if INCLUDE_5703_A0_FIX
-LM_STATUS LM_Load5703DmaWFirmware(PLM_DEVICE_BLOCK pDevice);
+LM_STATUS LM_Load5703DmaWFirmware (PLM_DEVICE_BLOCK pDevice);
#endif
-
-#endif /* LM_H */
+#endif /* LM_H */
diff --git a/drivers/bcm570x_mm.h b/drivers/bcm570x_mm.h
index b7cbf8a..ff5302f 100644
--- a/drivers/bcm570x_mm.h
+++ b/drivers/bcm570x_mm.h
@@ -45,7 +45,7 @@ extern int MM_Packet_Desc_Size;
#define MM_PACKET_DESC_SIZE MM_Packet_Desc_Size
-DECLARE_QUEUE_TYPE(UM_RX_PACKET_Q, MAX_RX_PACKET_DESC_COUNT+1);
+DECLARE_QUEUE_TYPE (UM_RX_PACKET_Q, MAX_RX_PACKET_DESC_COUNT + 1);
#define MAX_MEM 16
@@ -65,51 +65,50 @@ typedef struct _UM_DEVICE_BLOCK {
int mtu;
int index;
int opened;
- int delayed_link_ind; /* Delay link status during initial load */
- int adapter_just_inited; /* the first few seconds after init. */
- int spurious_int; /* new -- unsupported */
+ int delayed_link_ind; /* Delay link status during initial load */
+ int adapter_just_inited; /* the first few seconds after init. */
+ int spurious_int; /* new -- unsupported */
int timer_interval;
int adaptive_expiry;
- int crc_counter_expiry; /* new -- unsupported */
- int poll_tib_expiry; /* new -- unsupported */
+ int crc_counter_expiry; /* new -- unsupported */
+ int poll_tib_expiry; /* new -- unsupported */
int tx_full;
int tx_queued;
int line_speed; /* in Mbps, 0 if link is down */
UM_RX_PACKET_Q rx_out_of_buf_q;
int rx_out_of_buf;
- int rx_low_buf_thresh; /* changed to rx_buf_repl_thresh */
+ int rx_low_buf_thresh; /* changed to rx_buf_repl_thresh */
int rx_buf_repl_panic_thresh;
- int rx_buf_align; /* new -- unsupported */
+ int rx_buf_align; /* new -- unsupported */
int do_global_lock;
mutex_t global_lock;
mutex_t undi_lock;
long undi_flags;
volatile int interrupt;
int tasklet_pending;
- int tasklet_busy; /* new -- unsupported */
+ int tasklet_busy; /* new -- unsupported */
int rx_pkt;
int tx_pkt;
-#ifdef NICE_SUPPORT /* unsupported, this is a linux ioctl */
- void (*nice_rx)(void*, void* );
- void* nice_ctx;
-#endif /* NICE_SUPPORT */
+#ifdef NICE_SUPPORT /* unsupported, this is a linux ioctl */
+ void (*nice_rx) (void *, void *);
+ void *nice_ctx;
+#endif /* NICE_SUPPORT */
int rx_adaptive_coalesce;
unsigned int rx_last_cnt;
unsigned int tx_last_cnt;
unsigned int rx_curr_coalesce_frames;
unsigned int rx_curr_coalesce_ticks;
- unsigned int tx_curr_coalesce_frames; /* new -- unsupported */
-#if TIGON3_DEBUG /* new -- unsupported */
+ unsigned int tx_curr_coalesce_frames; /* new -- unsupported */
+#if TIGON3_DEBUG /* new -- unsupported */
uint tx_zc_count;
uint tx_chksum_count;
uint tx_himem_count;
uint rx_good_chksum_count;
#endif
- unsigned int rx_bad_chksum_count; /* new -- unsupported */
- unsigned int rx_misc_errors; /* new -- unsupported */
+ unsigned int rx_bad_chksum_count; /* new -- unsupported */
+ unsigned int rx_misc_errors; /* new -- unsupported */
} UM_DEVICE_BLOCK, *PUM_DEVICE_BLOCK;
-
/* Physical/PCI DMA address */
typedef union {
dma_addr_t dma_map;
@@ -117,9 +116,9 @@ typedef union {
/* Packet */
typedef struct
-_UM_PACKET {
- LM_PACKET lm_packet;
- void* skbuff; /* Address of packet buffer */
+ _UM_PACKET {
+ LM_PACKET lm_packet;
+ void *skbuff; /* Address of packet buffer */
} UM_PACKET, *PUM_PACKET;
#define MM_ACQUIRE_UNDI_LOCK(_pDevice)
@@ -137,15 +136,14 @@ _UM_PACKET {
#define MEM_TO_PCI_PHYS(addr) (addr)
-extern void MM_SetAddr (LM_PHYSICAL_ADDRESS *paddr, dma_addr_t addr);
-extern void MM_SetT3Addr(T3_64BIT_HOST_ADDR *paddr, dma_addr_t addr);
+extern void MM_SetAddr (LM_PHYSICAL_ADDRESS * paddr, dma_addr_t addr);
+extern void MM_SetT3Addr (T3_64BIT_HOST_ADDR * paddr, dma_addr_t addr);
extern void MM_MapTxDma (PLM_DEVICE_BLOCK pDevice,
- struct _LM_PACKET *pPacket, T3_64BIT_HOST_ADDR *paddr,
- LM_UINT32 *len, int frag);
-extern void MM_MapRxDma ( PLM_DEVICE_BLOCK pDevice,
- struct _LM_PACKET *pPacket,
- T3_64BIT_HOST_ADDR *paddr);
-
+ struct _LM_PACKET *pPacket, T3_64BIT_HOST_ADDR * paddr,
+ LM_UINT32 * len, int frag);
+extern void MM_MapRxDma (PLM_DEVICE_BLOCK pDevice,
+ struct _LM_PACKET *pPacket,
+ T3_64BIT_HOST_ADDR * paddr);
/* BSP needs to provide sysUsecDelay and sysSerialPrintString */
extern void sysSerialPrintString (char *s);
@@ -157,4 +155,4 @@ extern void sysSerialPrintString (char *s);
#if 0
#define cpu_to_le32(val) LONGSWAP(val)
#endif
-#endif /* MM_H */
+#endif /* MM_H */
diff --git a/drivers/bios_emulator/Makefile b/drivers/bios_emulator/Makefile
index ba7d436..586e83b 100644
--- a/drivers/bios_emulator/Makefile
+++ b/drivers/bios_emulator/Makefile
@@ -1,6 +1,6 @@
include $(TOPDIR)/config.mk
-LIB := libatibiosemu.a
+LIB := $(obj)libatibiosemu.a
X86DIR = ./x86emu
diff --git a/drivers/bios_emulator/besys.c b/drivers/bios_emulator/besys.c
index 2a8e1a0..4c4bc8d 100644
--- a/drivers/bios_emulator/besys.c
+++ b/drivers/bios_emulator/besys.c
@@ -49,6 +49,7 @@
#include "biosemui.h"
+#if defined(CONFIG_BIOSEMU)
/*------------------------- Global Variables ------------------------------*/
#ifndef __i386__
@@ -717,3 +718,4 @@ void X86API BE_outl(X86EMU_pioAddr port, u32 val)
#endif
LOG_outpd(port, val);
}
+#endif
diff --git a/drivers/bios_emulator/bios.c b/drivers/bios_emulator/bios.c
index ed5437e..7aa1bfb2e 100644
--- a/drivers/bios_emulator/bios.c
+++ b/drivers/bios_emulator/bios.c
@@ -43,6 +43,7 @@
#include "biosemui.h"
+#if defined(CONFIG_BIOSEMU)
/*----------------------------- Implementation ----------------------------*/
/****************************************************************************
@@ -319,3 +320,4 @@ void _BE_bios_init(u32 * intrTab)
bios_intr_tab[0x6D] = int10;
X86EMU_setupIntrFuncs(bios_intr_tab);
}
+#endif
diff --git a/drivers/bios_emulator/biosemu.c b/drivers/bios_emulator/biosemu.c
index 06d4ad3..4c3aedf 100644
--- a/drivers/bios_emulator/biosemu.c
+++ b/drivers/bios_emulator/biosemu.c
@@ -48,6 +48,8 @@
#include "biosemui.h"
#include <malloc.h>
+#if defined(CONFIG_BIOSEMU)
+
BE_sysEnv _BE_env = {{0}};
static X86EMU_memFuncs _BE_mem __attribute__((section(".got2"))) = {
BE_rdb,
@@ -368,3 +370,4 @@ int X86API BE_int86x(int intno, RMREGS * in, RMREGS * out, RMSREGS * sregs)
sregs->gs = M.x86.R_GS;
return out->x.ax;
}
+#endif
diff --git a/drivers/bios_emulator/x86emu/debug.c b/drivers/bios_emulator/x86emu/debug.c
index 0f58a69..915739c 100644
--- a/drivers/bios_emulator/x86emu/debug.c
+++ b/drivers/bios_emulator/x86emu/debug.c
@@ -40,6 +40,8 @@
#include "x86emu/x86emui.h"
#include <stdarg.h>
+#if defined(CONFIG_BIOSEMU)
+
/*----------------------------- Implementation ----------------------------*/
#ifdef DEBUG
@@ -459,3 +461,5 @@ void x86emu_dump_xregs(void)
printk("NC ");
printk("\n");
}
+
+#endif
diff --git a/drivers/bios_emulator/x86emu/decode.c b/drivers/bios_emulator/x86emu/decode.c
index 1e2dcfe..879f0a0 100644
--- a/drivers/bios_emulator/x86emu/decode.c
+++ b/drivers/bios_emulator/x86emu/decode.c
@@ -39,6 +39,8 @@
#include "x86emu/x86emui.h"
+#if defined(CONFIG_BIOSEMU)
+
/*----------------------------- Implementation ----------------------------*/
/****************************************************************************
@@ -1142,3 +1144,5 @@ unsigned decode_rmXX_address(int mod, int rm)
return decode_rm01_address(rm);
return decode_rm10_address(rm);
}
+
+#endif
diff --git a/drivers/bios_emulator/x86emu/ops.c b/drivers/bios_emulator/x86emu/ops.c
index d1380ce..d334fb5 100644
--- a/drivers/bios_emulator/x86emu/ops.c
+++ b/drivers/bios_emulator/x86emu/ops.c
@@ -76,6 +76,9 @@
****************************************************************************/
#include "x86emu/x86emui.h"
+
+#if defined(CONFIG_BIOSEMU)
+
/*----------------------------- Implementation ----------------------------*/
/* constant arrays to do several instructions in just one function */
@@ -5429,3 +5432,5 @@ void (*x86emu_optab[256])(u8) __attribute__ ((section(".got2"))) =
/* 0xfe */ x86emuOp_opcFE_byte_RM,
/* 0xff */ x86emuOp_opcFF_word_RM,
};
+
+#endif
diff --git a/drivers/bios_emulator/x86emu/ops2.c b/drivers/bios_emulator/x86emu/ops2.c
index 631a340..81c0d49 100644
--- a/drivers/bios_emulator/x86emu/ops2.c
+++ b/drivers/bios_emulator/x86emu/ops2.c
@@ -46,6 +46,8 @@
#include "x86emu/x86emui.h"
+#if defined(CONFIG_BIOSEMU)
+
/*----------------------------- Implementation ----------------------------*/
/****************************************************************************
@@ -1768,3 +1770,5 @@ void (*x86emu_optab2[256])(u8) __attribute__((section(".got2"))) =
/* 0xfe */ x86emuOp2_illegal_op,
/* 0xff */ x86emuOp2_illegal_op,
};
+
+#endif
diff --git a/drivers/bios_emulator/x86emu/prim_ops.c b/drivers/bios_emulator/x86emu/prim_ops.c
index e0827d7..c1152ea 100644
--- a/drivers/bios_emulator/x86emu/prim_ops.c
+++ b/drivers/bios_emulator/x86emu/prim_ops.c
@@ -100,6 +100,8 @@
#define PRIM_OPS_NO_REDEFINE_ASM
#include "x86emu/x86emui.h"
+#if defined(CONFIG_BIOSEMU)
+
/*------------------------- Global Variables ------------------------------*/
static u32 x86emu_parity_tab[8] =
@@ -2443,3 +2445,5 @@ DB( if (CHECK_SP_ACCESS())
M.x86.R_SP += 4;
return res;
}
+
+#endif
diff --git a/drivers/bios_emulator/x86emu/sys.c b/drivers/bios_emulator/x86emu/sys.c
index bb7fcd9..566389f 100644
--- a/drivers/bios_emulator/x86emu/sys.c
+++ b/drivers/bios_emulator/x86emu/sys.c
@@ -41,6 +41,8 @@
#include "x86emu/x86emui.h"
+#if defined(CONFIG_BIOSEMU)
+
/*------------------------- Global Variables ------------------------------*/
X86EMU_sysEnv _X86EMU_env; /* Global emulator machine state */
@@ -320,3 +322,5 @@ void X86EMU_prepareForInt(int num)
M.x86.R_IP = mem_access_word(num * 4);
M.x86.intr = 0;
}
+
+#endif
diff --git a/drivers/dataflash.c b/drivers/dataflash.c
index 17eb859..91903c8 100644
--- a/drivers/dataflash.c
+++ b/drivers/dataflash.c
@@ -26,18 +26,67 @@
AT91S_DATAFLASH_INFO dataflash_info[CFG_MAX_DATAFLASH_BANKS];
static AT91S_DataFlash DataFlashInst;
+#ifdef CONFIG_AT91SAM9260EK
+int cs[][CFG_MAX_DATAFLASH_BANKS] = {
+ {CFG_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */
+ {CFG_DATAFLASH_LOGIC_ADDR_CS1, 1}
+};
+#elif defined(CONFIG_AT91SAM9263EK)
+int cs[][CFG_MAX_DATAFLASH_BANKS] = {
+ {CFG_DATAFLASH_LOGIC_ADDR_CS0, 0} /* Logical adress, CS */
+};
+#else
int cs[][CFG_MAX_DATAFLASH_BANKS] = {
{CFG_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */
{CFG_DATAFLASH_LOGIC_ADDR_CS3, 3}
};
+#endif
/*define the area offsets*/
+#if defined(CONFIG_AT91SAM9261EK) || defined(CONFIG_AT91SAM9260EK) || defined(CONFIG_AT91SAM9263EK)
+#if defined(CONFIG_NEW_PARTITION)
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+ {0x00000000, 0x00003FFF, FLAG_PROTECT_SET, 0, "Bootstrap"}, /* ROM code */
+ {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"}, /* u-boot environment */
+ {0x00008400, 0x0003DDFF, FLAG_PROTECT_SET, 0, "U-Boot"}, /* u-boot code */
+ {0x0003DE00, 0x00041FFF, FLAG_PROTECT_CLEAR, FLAG_SETENV, "MON"}, /* Room for alternative boot monitor */
+ {0x00042000, 0x0018BFFF, FLAG_PROTECT_CLEAR, FLAG_SETENV, "OS"}, /* data area size to tune */
+ {0x0018C000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, FLAG_SETENV, "FS"}, /* data area size to tune */
+};
+#else
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+ {0, 0x3fff, FLAG_PROTECT_SET}, /* ROM code */
+ {0x4000, 0x7fff, FLAG_PROTECT_CLEAR}, /* u-boot environment */
+ {0x8000, 0x37fff, FLAG_PROTECT_SET}, /* u-boot code */
+ {0x38000, 0x1fffff, FLAG_PROTECT_CLEAR}, /* data area size to tune */
+};
+#endif
+#elif defined(CONFIG_NEW_PARTITION)
+/*define the area offsets*/
+/* Invalid partitions should be defined with start > end */
+dataflash_protect_t area_list[NB_DATAFLASH_AREA*CFG_MAX_DATAFLASH_BANKS] = {
+ {0x00000000, 0x000083ff, FLAG_PROTECT_SET, 0, "Bootstrap"}, /* ROM code */
+ {0x00008400, 0x00020fff, FLAG_PROTECT_SET, 0, "U-Boot"}, /* u-boot code */
+ {0x00021000, 0x000293ff, FLAG_PROTECT_CLEAR, 0, "Environment"}, /* u-boot environment 8Kb */
+ {0x00029400, 0x00041fff, FLAG_PROTECT_INVALID, 0, "<Unused>"}, /* Rest of Sector 1 */
+ {0x00042000, 0x0018Bfff, FLAG_PROTECT_CLEAR, FLAG_SETENV, "OS"}, /* data area size to tune */
+ {0x0018C000, 0xffffffff, FLAG_PROTECT_CLEAR, FLAG_SETENV, "FS"}, /* data area size to tune */
+
+ {0x00000000, 0xffffffff, FLAG_PROTECT_CLEAR, FLAG_SETENV, "Data"}, /* data area */
+ {0xffffffff, 0x00000000, FLAG_PROTECT_INVALID, 0, "<Invalid>"}, /* Invalid */
+ {0xffffffff, 0x00000000, FLAG_PROTECT_INVALID, 0, "<Invalid>"}, /* Invalid */
+ {0xffffffff, 0x00000000, FLAG_PROTECT_INVALID, 0, "<Invalid>"}, /* Invalid */
+ {0xffffffff, 0x00000000, FLAG_PROTECT_INVALID, 0, "<Invalid>"}, /* Invalid */
+ {0xffffffff, 0x00000000, FLAG_PROTECT_INVALID, 0, "<Invalid>"}, /* Invalid */
+};
+#else
dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
{0, 0x7fff, FLAG_PROTECT_SET}, /* ROM code */
{0x8000, 0x1ffff, FLAG_PROTECT_SET}, /* u-boot code */
{0x20000, 0x27fff, FLAG_PROTECT_CLEAR}, /* u-boot environment */
{0x28000, 0x1fffff, FLAG_PROTECT_CLEAR}, /* data area size to tune */
};
+#endif
extern void AT91F_SpiInit (void);
extern int AT91F_DataflashProbe (int i, AT91PS_DataflashDesc pDesc);
@@ -45,22 +94,28 @@ extern int AT91F_DataFlashRead (AT91PS_DataFlash pDataFlash,
unsigned long addr,
unsigned long size, char *buffer);
extern int AT91F_DataFlashWrite( AT91PS_DataFlash pDataFlash,
- unsigned char *src,
- int dest,
- int size );
+ unsigned char *src,
+ int dest,
+ int size );
int AT91F_DataflashInit (void)
{
int i, j;
int dfcode;
+ int part = 0;
+ int last_part;
+ int found[CFG_MAX_DATAFLASH_BANKS];
+ unsigned char protected;
AT91F_SpiInit ();
for (i = 0; i < CFG_MAX_DATAFLASH_BANKS; i++) {
+ found[i] = 0;
dataflash_info[i].Desc.state = IDLE;
dataflash_info[i].id = 0;
dataflash_info[i].Device.pages_number = 0;
- dfcode = AT91F_DataflashProbe (cs[i][1], &dataflash_info[i].Desc);
+ dfcode = AT91F_DataflashProbe (cs[i][1],
+ &dataflash_info[i].Desc);
switch (dfcode) {
case AT45DB161:
@@ -72,6 +127,7 @@ int AT91F_DataflashInit (void)
dataflash_info[i].Desc.DataFlash_state = IDLE;
dataflash_info[i].logical_address = cs[i][0];
dataflash_info[i].id = dfcode;
+ found[i] += dfcode;;
break;
case AT45DB321:
@@ -83,6 +139,7 @@ int AT91F_DataflashInit (void)
dataflash_info[i].Desc.DataFlash_state = IDLE;
dataflash_info[i].logical_address = cs[i][0];
dataflash_info[i].id = dfcode;
+ found[i] += dfcode;;
break;
case AT45DB642:
@@ -94,7 +151,9 @@ int AT91F_DataflashInit (void)
dataflash_info[i].Desc.DataFlash_state = IDLE;
dataflash_info[i].logical_address = cs[i][0];
dataflash_info[i].id = dfcode;
+ found[i] += dfcode;;
break;
+
case AT45DB128:
dataflash_info[i].Device.pages_number = 16384;
dataflash_info[i].Device.pages_size = 1056;
@@ -104,9 +163,11 @@ int AT91F_DataflashInit (void)
dataflash_info[i].Desc.DataFlash_state = IDLE;
dataflash_info[i].logical_address = cs[i][0];
dataflash_info[i].id = dfcode;
+ found[i] += dfcode;;
break;
default:
+ dfcode = 0;
break;
}
/* set the last area end to the dataflash size*/
@@ -114,16 +175,64 @@ int AT91F_DataflashInit (void)
(dataflash_info[i].Device.pages_number *
dataflash_info[i].Device.pages_size)-1;
+ last_part=0;
/* set the area addresses */
for(j = 0; j<NB_DATAFLASH_AREA; j++) {
- dataflash_info[i].Device.area_list[j].start = area_list[j].start + dataflash_info[i].logical_address;
- dataflash_info[i].Device.area_list[j].end = area_list[j].end + dataflash_info[i].logical_address;
- dataflash_info[i].Device.area_list[j].protected = area_list[j].protected;
+ if(found[i]!=0) {
+ dataflash_info[i].Device.area_list[j].start =
+ area_list[part].start +
+ dataflash_info[i].logical_address;
+ if(area_list[part].end == 0xffffffff) {
+ dataflash_info[i].Device.area_list[j].end =
+ dataflash_info[i].end_address +
+ dataflash_info [i].logical_address;
+ last_part = 1;
+ } else {
+ dataflash_info[i].Device.area_list[j].end =
+ area_list[part].end +
+ dataflash_info[i].logical_address;
+ }
+ protected = area_list[part].protected;
+ /* Set the environment according to the label...*/
+ if(protected == FLAG_PROTECT_INVALID) {
+ dataflash_info[i].Device.area_list[j].protected =
+ FLAG_PROTECT_INVALID;
+ } else {
+ dataflash_info[i].Device.area_list[j].protected =
+ protected;
+ }
+ strcpy((char*)(dataflash_info[i].Device.area_list[j].label),
+ (const char *)area_list[part].label);
+ }
+ part++;
}
}
- return (1);
+ return found[0];
}
+#ifdef CONFIG_NEW_DF_PARTITION
+int AT91F_DataflashSetEnv (void)
+{
+ int i, j;
+ int part;
+ unsigned char env;
+ unsigned char s[32]; /* Will fit a long int in hex */
+ unsigned long start;
+ for (i = 0, part= 0; i < CFG_MAX_DATAFLASH_BANKS; i++) {
+ for(j = 0; j<NB_DATAFLASH_AREA; j++) {
+ env = area_list[part].setenv;
+ /* Set the environment according to the label...*/
+ if((env & FLAG_SETENV) == FLAG_SETENV) {
+ start =
+ dataflash_info[i].Device.area_list[j].start;
+ sprintf(s,"%X",start);
+ setenv(area_list[part].label,s);
+ }
+ part++;
+ }
+ }
+}
+#endif
void dataflash_print_info (void)
{
@@ -131,25 +240,25 @@ void dataflash_print_info (void)
for (i = 0; i < CFG_MAX_DATAFLASH_BANKS; i++) {
if (dataflash_info[i].id != 0) {
- printf ("DataFlash:");
+ printf("DataFlash:");
switch (dataflash_info[i].id) {
case AT45DB161:
- printf ("AT45DB161\n");
+ printf("AT45DB161\n");
break;
case AT45DB321:
- printf ("AT45DB321\n");
+ printf("AT45DB321\n");
break;
case AT45DB642:
- printf ("AT45DB642\n");
+ printf("AT45DB642\n");
break;
case AT45DB128:
- printf ("AT45DB128\n");
+ printf("AT45DB128\n");
break;
}
- printf ("Nb pages: %6d\n"
+ printf("Nb pages: %6d\n"
"Page Size: %6d\n"
"Size=%8d bytes\n"
"Logical address: 0x%08X\n",
@@ -159,28 +268,44 @@ void dataflash_print_info (void)
dataflash_info[i].Device.pages_size,
(unsigned int) dataflash_info[i].logical_address);
for (j=0; j< NB_DATAFLASH_AREA; j++) {
- printf ("Area %i:\t%08lX to %08lX %s\n", j,
- dataflash_info[i].Device.area_list[j].start,
- dataflash_info[i].Device.area_list[j].end,
- (dataflash_info[i].Device.area_list[j].protected ==
- FLAG_PROTECT_SET) ? "(RO)" : "");
+ switch(dataflash_info[i].Device.area_list[j].protected) {
+ case FLAG_PROTECT_SET:
+ case FLAG_PROTECT_CLEAR:
+ printf("Area %i:\t%08lX to %08lX %s", j,
+ dataflash_info[i].Device.area_list[j].start,
+ dataflash_info[i].Device.area_list[j].end,
+ (dataflash_info[i].Device.area_list[j].protected==FLAG_PROTECT_SET) ? "(RO)" : " ");
+#ifdef CONFIG_NEW_DF_PARTITION
+ printf(" %s\n", dataflash_info[i].Device.area_list[j].label);
+#else
+ printf("\n");
+#endif
+ break;
+#ifdef CONFIG_NEW_DF_PARTITION
+ case FLAG_PROTECT_INVALID:
+ break;
+#endif
+ }
}
}
}
}
-/*------------------------------------------------------------------------------*/
-/* Function Name : AT91F_DataflashSelect */
-/* Object : Select the correct device */
-/*------------------------------------------------------------------------------*/
-AT91PS_DataFlash AT91F_DataflashSelect (AT91PS_DataFlash pFlash, unsigned long *addr)
+/*---------------------------------------------------------------------------*/
+/* Function Name : AT91F_DataflashSelect */
+/* Object : Select the correct device */
+/*---------------------------------------------------------------------------*/
+AT91PS_DataFlash AT91F_DataflashSelect (AT91PS_DataFlash pFlash,
+ unsigned long *addr)
{
char addr_valid = 0;
int i;
for (i = 0; i < CFG_MAX_DATAFLASH_BANKS; i++)
- if ((*addr & 0xFF000000) == dataflash_info[i].logical_address) {
+ if ( dataflash_info[i].id
+ && ((((int) addr) & 0xFF000000) ==
+ dataflash_info[i].logical_address)) {
addr_valid = 1;
break;
}
@@ -194,10 +319,10 @@ AT91PS_DataFlash AT91F_DataflashSelect (AT91PS_DataFlash pFlash, unsigned long *
return (pFlash);
}
-/*------------------------------------------------------------------------------*/
-/* Function Name : addr_dataflash */
-/* Object : Test if address is valid */
-/*------------------------------------------------------------------------------*/
+/*---------------------------------------------------------------------------*/
+/* Function Name : addr_dataflash */
+/* Object : Test if address is valid */
+/*---------------------------------------------------------------------------*/
int addr_dataflash (unsigned long addr)
{
int addr_valid = 0;
@@ -213,25 +338,27 @@ int addr_dataflash (unsigned long addr)
return addr_valid;
}
-/*-----------------------------------------------------------------------------*/
-/* Function Name : size_dataflash */
-/* Object : Test if address is valid regarding the size */
-/*-----------------------------------------------------------------------------*/
-int size_dataflash (AT91PS_DataFlash pdataFlash, unsigned long addr, unsigned long size)
+/*---------------------------------------------------------------------------*/
+/* Function Name : size_dataflash */
+/* Object : Test if address is valid regarding the size */
+/*---------------------------------------------------------------------------*/
+int size_dataflash (AT91PS_DataFlash pdataFlash, unsigned long addr,
+ unsigned long size)
{
/* is outside the dataflash */
if (((int)addr & 0x0FFFFFFF) > (pdataFlash->pDevice->pages_size *
pdataFlash->pDevice->pages_number)) return 0;
/* is too large for the dataflash */
if (size > ((pdataFlash->pDevice->pages_size *
- pdataFlash->pDevice->pages_number) - ((int)addr & 0x0FFFFFFF))) return 0;
+ pdataFlash->pDevice->pages_number) -
+ ((int)addr & 0x0FFFFFFF))) return 0;
return 1;
}
-/*-----------------------------------------------------------------------------*/
-/* Function Name : prot_dataflash */
-/* Object : Test if destination area is protected */
-/*-----------------------------------------------------------------------------*/
+/*---------------------------------------------------------------------------*/
+/* Function Name : prot_dataflash */
+/* Object : Test if destination area is protected */
+/*---------------------------------------------------------------------------*/
int prot_dataflash (AT91PS_DataFlash pdataFlash, unsigned long addr)
{
int area;
@@ -241,17 +368,23 @@ int area;
(addr < pdataFlash->pDevice->area_list[area].end))
break;
}
- if (area == NB_DATAFLASH_AREA) return -1;
+ if (area == NB_DATAFLASH_AREA)
+ return -1;
+
/*test protection value*/
- if (pdataFlash->pDevice->area_list[area].protected == FLAG_PROTECT_SET) return 0;
+ if (pdataFlash->pDevice->area_list[area].protected == FLAG_PROTECT_SET)
+ return 0;
+ if (pdataFlash->pDevice->area_list[area].protected == FLAG_PROTECT_INVALID)
+ return 0;
return 1;
}
-/*-----------------------------------------------------------------------------*/
-/* Function Name : dataflash_real_protect */
-/* Object : protect/unprotect area */
-/*-----------------------------------------------------------------------------*/
-int dataflash_real_protect (int flag, unsigned long start_addr, unsigned long end_addr)
+/*--------------------------------------------------------------------------*/
+/* Function Name : dataflash_real_protect */
+/* Object : protect/unprotect area */
+/*--------------------------------------------------------------------------*/
+int dataflash_real_protect (int flag, unsigned long start_addr,
+ unsigned long end_addr)
{
int i,j, area1, area2, addr_valid = 0;
/* find dataflash */
@@ -267,27 +400,38 @@ int i,j, area1, area2, addr_valid = 0;
}
/* find start area */
for (area1=0; area1 < NB_DATAFLASH_AREA; area1++) {
- if (start_addr == dataflash_info[i].Device.area_list[area1].start) break;
+ if (start_addr == dataflash_info[i].Device.area_list[area1].start)
+ break;
}
if (area1 == NB_DATAFLASH_AREA) return -1;
/* find end area */
for (area2=0; area2 < NB_DATAFLASH_AREA; area2++) {
- if (end_addr == dataflash_info[i].Device.area_list[area2].end) break;
+ if (end_addr == dataflash_info[i].Device.area_list[area2].end)
+ break;
}
- if (area2 == NB_DATAFLASH_AREA) return -1;
+ if (area2 == NB_DATAFLASH_AREA)
+ return -1;
/*set protection value*/
for(j = area1; j < area2+1 ; j++)
- if (flag == 0) dataflash_info[i].Device.area_list[j].protected = FLAG_PROTECT_CLEAR;
- else dataflash_info[i].Device.area_list[j].protected = FLAG_PROTECT_SET;
+ if(dataflash_info[i].Device.area_list[j].protected
+ != FLAG_PROTECT_INVALID) {
+ if (flag == 0) {
+ dataflash_info[i].Device.area_list[j].protected
+ = FLAG_PROTECT_CLEAR;
+ } else {
+ dataflash_info[i].Device.area_list[j].protected
+ = FLAG_PROTECT_SET;
+ }
+ }
return (area2-area1+1);
}
-/*------------------------------------------------------------------------------*/
-/* Function Name : read_dataflash */
-/* Object : dataflash memory read */
-/*------------------------------------------------------------------------------*/
+/*---------------------------------------------------------------------------*/
+/* Function Name : read_dataflash */
+/* Object : dataflash memory read */
+/*---------------------------------------------------------------------------*/
int read_dataflash (unsigned long addr, unsigned long size, char *result)
{
unsigned long AddrToRead = addr;
@@ -305,12 +449,12 @@ int read_dataflash (unsigned long addr, unsigned long size, char *result)
}
-/*-----------------------------------------------------------------------------*/
-/* Function Name : write_dataflash */
-/* Object : write a block in dataflash */
-/*-----------------------------------------------------------------------------*/
+/*---------------------------------------------------------------------------*/
+/* Function Name : write_dataflash */
+/* Object : write a block in dataflash */
+/*---------------------------------------------------------------------------*/
int write_dataflash (unsigned long addr_dest, unsigned long addr_src,
- unsigned long size)
+ unsigned long size)
{
unsigned long AddrToWrite = addr_dest;
AT91PS_DataFlash pFlash = &DataFlashInst;
@@ -329,7 +473,8 @@ int write_dataflash (unsigned long addr_dest, unsigned long addr_src,
if (AddrToWrite == -1)
return -1;
- return AT91F_DataFlashWrite (pFlash, (uchar *)addr_src, AddrToWrite, size);
+ return AT91F_DataFlashWrite (pFlash, (uchar *)addr_src,
+ AddrToWrite, size);
}
@@ -339,22 +484,22 @@ void dataflash_perror (int err)
case ERR_OK:
break;
case ERR_TIMOUT:
- printf ("Timeout writing to DataFlash\n");
+ printf("Timeout writing to DataFlash\n");
break;
case ERR_PROTECTED:
- printf ("Can't write to protected DataFlash sectors\n");
+ printf("Can't write to protected/invalid DataFlash sectors\n");
break;
case ERR_INVAL:
- printf ("Outside available DataFlash\n");
+ printf("Outside available DataFlash\n");
break;
case ERR_UNKNOWN_FLASH_TYPE:
- printf ("Unknown Type of DataFlash\n");
+ printf("Unknown Type of DataFlash\n");
break;
case ERR_PROG_ERROR:
- printf ("General DataFlash Programming Error\n");
+ printf("General DataFlash Programming Error\n");
break;
default:
- printf ("%s[%d] FIXME: rc=%d\n", __FILE__, __LINE__, err);
+ printf("%s[%d] FIXME: rc=%d\n", __FILE__, __LINE__, err);
break;
}
}
diff --git a/drivers/dm9000x.c b/drivers/dm9000x.c
index 6877076..78acb09 100644
--- a/drivers/dm9000x.c
+++ b/drivers/dm9000x.c
@@ -302,6 +302,21 @@ eth_init(bd_t * bd)
/* Set Node address */
for (i = 0; i < 6; i++)
((u16 *) bd->bi_enetaddr)[i] = read_srom_word(i);
+
+ if (!is_zero_ether_addr(bd->bi_enetaddr) &&
+ !is_mutlicast_ether_addr(bd->bi_enetaddr)) {
+ /* try reading from environment */
+ u8 i;
+ char *s, *e;
+ s = getenv ("ethaddr");
+ for (i = 0; i < 6; ++i) {
+ bd->bi_enetaddr[i] = s ?
+ simple_strtoul (s, &e, 16) : 0;
+ if (s)
+ s = (*e) ? e + 1 : e;
+ }
+ }
+
printf("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n", bd->bi_enetaddr[0],
bd->bi_enetaddr[1], bd->bi_enetaddr[2], bd->bi_enetaddr[3],
bd->bi_enetaddr[4], bd->bi_enetaddr[5]);
diff --git a/drivers/fsl_i2c.c b/drivers/fsl_i2c.c
index ebae5af..22485ea 100644
--- a/drivers/fsl_i2c.c
+++ b/drivers/fsl_i2c.c
@@ -69,9 +69,10 @@ i2c_init(int speed, int slaveadd)
dev = (struct fsl_i2c *) (CFG_IMMR + CFG_I2C2_OFFSET);
writeb(0, &dev->cr); /* stop I2C controller */
+ udelay(5); /* let it shutdown in peace */
writeb(0x3F, &dev->fdr); /* set bus speed */
writeb(0x3F, &dev->dfsrr); /* set default filter */
- writeb(slaveadd, &dev->adr); /* write slave address */
+ writeb(slaveadd << 1, &dev->adr); /* write slave address */
writeb(0x0, &dev->sr); /* clear status register */
writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */
#endif /* CFG_I2C2_OFFSET */
diff --git a/drivers/fsl_pci_init.c b/drivers/fsl_pci_init.c
index 1d1f6df..1084dc6 100644
--- a/drivers/fsl_pci_init.c
+++ b/drivers/fsl_pci_init.c
@@ -15,7 +15,7 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
-#define DEBUG
+
#include <common.h>
#ifdef CONFIG_FSL_PCI_INIT
@@ -93,7 +93,11 @@ fsl_pci_init(struct pci_controller *hose)
hose->current_busno = hose->first_busno;
pci->pedr = 0xffffffff; /* Clear any errors */
- pci->peer = 0xffffffff; /* Enable Error Interupts */
+ pci->peer = ~0x20140; /* Enable All Error Interupts except
+ * - Master abort (pci)
+ * - Master PERR (pci)
+ * - ICCA (PCIe)
+ */
pci_hose_read_config_dword (hose, dev, PCI_DCR, &temp32);
temp32 |= 0xf000e; /* set URR, FER, NFER (but not CER) */
pci_hose_write_config_dword(hose, dev, PCI_DCR, temp32);
@@ -108,7 +112,7 @@ fsl_pci_init(struct pci_controller *hose)
if (!enabled) {
debug("....PCIE link error. Skipping scan."
- "LTSSM=0x%02x\n", temp16);
+ "LTSSM=0x%02x\n", ltssm);
hose->last_busno = hose->first_busno;
return;
}
@@ -118,61 +122,41 @@ fsl_pci_init(struct pci_controller *hose)
#ifdef DEBUG
pci_hose_read_config_word(hose, dev, PCI_LSR, &temp16);
neg_link_w = (temp16 & 0x3f0 ) >> 4;
- debug("...PCIE LTSSM=0x%x, Negotiated link width=%d\n",
+ printf("...PCIE LTSSM=0x%x, Negotiated link width=%d\n",
ltssm, neg_link_w);
#endif
hose->current_busno++; /* Start scan with secondary */
pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
- } else {
-#if 0
-/* done in pci_hose_config_device() */
- pci_hose_read_config_word(hose, dev, PCI_COMMAND, &temp16);
- temp16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER |
- PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
- pci_hose_write_config_word(hose, dev, PCI_COMMAND, temp16);
- pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
- pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
-#endif
}
/* Call setup to allocate PCSRBAR window */
pciauto_setup_device(hose, dev, 1, hose->pci_mem,
hose->pci_prefetch, hose->pci_io);
-
+#ifndef CONFIG_PCI_NOSCAN
printf (" Scanning PCI bus %02x\n", hose->current_busno);
hose->last_busno = pci_hose_scan_bus(hose,hose->current_busno);
if ( bridge ) { /* update limit regs and subordinate busno */
pciauto_postscan_setup_bridge(hose, dev, hose->last_busno);
}
+#else
+ hose->last_busno = hose->current_busno;
+#endif
/* Clear all error indications */
- if (pci->pme_msg_det && pci->pme_msg_det != 0xffffffff) {
- debug("pci_fsl_init: pme_msg_det@%x=%x. Clearing\n",
- &pci->pme_msg_det, pci->pme_msg_det);
- pci->pme_msg_det = 0xffffffff;
- }
-
- if (pci->pedr) {
- debug("pci_fsl_init: pedr@%x=%x. Clearing\n",
- &pci->pedr, pci->pedr);
- pci->pedr = 0xffffffff;
- }
+ pci->pme_msg_det = 0xffffffff;
+ pci->pedr = 0xffffffff;
pci_hose_read_config_word (hose, dev, PCI_DSR, &temp16);
if (temp16) {
- debug("pci_fsl_init: PCI_DSR@%x=%x. Clearing\n",
- PCI_DSR, temp16);
pci_hose_write_config_word(hose, dev,
- PCI_DSR, 0xffff);
+ PCI_DSR, 0xffff);
}
pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16);
if (temp16) {
- debug("pci_fsl_init: PCI_SEC_STATUS@%x=%x. Clearing\n",
- PCI_SEC_STATUS, temp16);
pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff);
}
}
diff --git a/drivers/isp116x-hcd.c b/drivers/isp116x-hcd.c
new file mode 100644
index 0000000..8e2bc7a
--- /dev/null
+++ b/drivers/isp116x-hcd.c
@@ -0,0 +1,1413 @@
+/*
+ * ISP116x HCD (Host Controller Driver) for u-boot.
+ *
+ * Copyright (C) 2006-2007 Rodolfo Giometti <giometti@linux.it>
+ * Copyright (C) 2006-2007 Eurotech S.p.A. <info@eurotech.it>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ *
+ * Derived in part from the SL811 HCD driver "u-boot/drivers/sl811_usb.c"
+ * (original copyright message follows):
+ *
+ * (C) Copyright 2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * This code is based on linux driver for sl811hs chip, source at
+ * drivers/usb/host/sl811.c:
+ *
+ * SL811 Host Controller Interface driver for USB.
+ *
+ * Copyright (c) 2003/06, Courage Co., Ltd.
+ *
+ * Based on:
+ * 1.uhci.c by Linus Torvalds, Johannes Erdfelt, Randy Dunlap,
+ * Georg Acher, Deti Fliegl, Thomas Sailer, Roman Weissgaerber,
+ * Adam Richter, Gregory P. Smith;
+ * 2.Original SL811 driver (hc_sl811.o) by Pei Liu <pbl@cypress.com>
+ * 3.Rewrited as sl811.o by Yin Aihua <yinah:couragetech.com.cn>
+ *
+ * [[GNU/GPL disclaimer]]
+ *
+ * and in part from AU1x00 OHCI HCD driver "u-boot/cpu/mips/au1x00_usb_ohci.c"
+ * (original copyright message follows):
+ *
+ * URB OHCI HCD (Host Controller Driver) for USB on the AU1x00.
+ *
+ * (C) Copyright 2003
+ * Gary Jennejohn, DENX Software Engineering <gj@denx.de>
+ *
+ * [[GNU/GPL disclaimer]]
+ *
+ * Note: Part of this code has been derived from linux
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_USB_ISP116X_HCD
+#include <asm/io.h>
+#include <usb.h>
+#include <malloc.h>
+#include <linux/list.h>
+
+/*
+ * ISP116x chips require certain delays between accesses to its
+ * registers. The following timing options exist.
+ *
+ * 1. Configure your memory controller (the best)
+ * 2. Use ndelay (easiest, poorest). For that, enable the following macro.
+ *
+ * Value is in microseconds.
+ */
+#ifdef ISP116X_HCD_USE_UDELAY
+#define UDELAY 1
+#endif
+
+/*
+ * On some (slowly?) machines an extra delay after data packing into
+ * controller's FIFOs is required, * otherwise you may get the following
+ * error:
+ *
+ * uboot> usb start
+ * (Re)start USB...
+ * USB: scanning bus for devices... isp116x: isp116x_submit_job: CTL:TIMEOUT
+ * isp116x: isp116x_submit_job: ****** FIFO not ready! ******
+ *
+ * USB device not responding, giving up (status=4)
+ * isp116x: isp116x_submit_job: ****** FIFO not empty! ******
+ * isp116x: isp116x_submit_job: ****** FIFO not empty! ******
+ * isp116x: isp116x_submit_job: ****** FIFO not empty! ******
+ * 3 USB Device(s) found
+ * scanning bus for storage devices... 0 Storage Device(s) found
+ *
+ * Value is in milliseconds.
+ */
+#ifdef ISP116X_HCD_USE_EXTRA_DELAY
+#define EXTRA_DELAY 2
+#endif
+
+/*
+ * Enable the following defines if you wish enable debugging messages.
+ */
+#undef DEBUG /* enable debugging messages */
+#undef TRACE /* enable tracing code */
+#undef VERBOSE /* verbose debugging messages */
+
+#include "isp116x.h"
+
+#define DRIVER_VERSION "08 Jan 2007"
+static const char hcd_name[] = "isp116x-hcd";
+
+struct isp116x isp116x_dev;
+struct isp116x_platform_data isp116x_board;
+int got_rhsc = 0; /* root hub status change */
+struct usb_device *devgone; /* device which was disconnected */
+int rh_devnum = 0; /* address of Root Hub endpoint */
+
+/* ------------------------------------------------------------------------- */
+
+#define ALIGN(x,a) (((x)+(a)-1UL)&~((a)-1UL))
+#define min_t(type,x,y) \
+ ({ type __x = (x); type __y = (y); __x < __y ? __x : __y; })
+
+/* ------------------------------------------------------------------------- */
+
+static int isp116x_reset(struct isp116x *isp116x);
+
+/* --- Debugging functions ------------------------------------------------- */
+
+#define isp116x_show_reg(d, r) { \
+ if ((r) < 0x20) { \
+ DBG("%-12s[%02x]: %08x", #r, \
+ r, isp116x_read_reg32(d, r)); \
+ } else { \
+ DBG("%-12s[%02x]: %04x", #r, \
+ r, isp116x_read_reg16(d, r)); \
+ } \
+}
+
+#define isp116x_show_regs(d) { \
+ isp116x_show_reg(d, HCREVISION); \
+ isp116x_show_reg(d, HCCONTROL); \
+ isp116x_show_reg(d, HCCMDSTAT); \
+ isp116x_show_reg(d, HCINTSTAT); \
+ isp116x_show_reg(d, HCINTENB); \
+ isp116x_show_reg(d, HCFMINTVL); \
+ isp116x_show_reg(d, HCFMREM); \
+ isp116x_show_reg(d, HCFMNUM); \
+ isp116x_show_reg(d, HCLSTHRESH); \
+ isp116x_show_reg(d, HCRHDESCA); \
+ isp116x_show_reg(d, HCRHDESCB); \
+ isp116x_show_reg(d, HCRHSTATUS); \
+ isp116x_show_reg(d, HCRHPORT1); \
+ isp116x_show_reg(d, HCRHPORT2); \
+ isp116x_show_reg(d, HCHWCFG); \
+ isp116x_show_reg(d, HCDMACFG); \
+ isp116x_show_reg(d, HCXFERCTR); \
+ isp116x_show_reg(d, HCuPINT); \
+ isp116x_show_reg(d, HCuPINTENB); \
+ isp116x_show_reg(d, HCCHIPID); \
+ isp116x_show_reg(d, HCSCRATCH); \
+ isp116x_show_reg(d, HCITLBUFLEN); \
+ isp116x_show_reg(d, HCATLBUFLEN); \
+ isp116x_show_reg(d, HCBUFSTAT); \
+ isp116x_show_reg(d, HCRDITL0LEN); \
+ isp116x_show_reg(d, HCRDITL1LEN); \
+}
+
+#if defined(TRACE)
+
+static int isp116x_get_current_frame_number(struct usb_device *usb_dev)
+{
+ struct isp116x *isp116x = &isp116x_dev;
+
+ return isp116x_read_reg32(isp116x, HCFMNUM);
+}
+
+static void dump_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+ int len, char *str)
+{
+#if defined(VERBOSE)
+ int i;
+#endif
+
+ DBG("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d stat:%#lx",
+ str,
+ isp116x_get_current_frame_number(dev),
+ usb_pipedevice(pipe),
+ usb_pipeendpoint(pipe),
+ usb_pipeout(pipe) ? 'O' : 'I',
+ usb_pipetype(pipe) < 2 ?
+ (usb_pipeint(pipe) ?
+ "INTR" : "ISOC") :
+ (usb_pipecontrol(pipe) ? "CTRL" : "BULK"), len, dev->status);
+#if defined(VERBOSE)
+ if (len > 0 && buffer) {
+ printf(__FILE__ ": data(%d):", len);
+ for (i = 0; i < 16 && i < len; i++)
+ printf(" %02x", ((__u8 *) buffer)[i]);
+ printf("%s\n", i < len ? "..." : "");
+ }
+#endif
+}
+
+#define PTD_DIR_STR(ptd) ({char __c; \
+ switch(PTD_GET_DIR(ptd)){ \
+ case 0: __c = 's'; break; \
+ case 1: __c = 'o'; break; \
+ default: __c = 'i'; break; \
+ }; __c;})
+
+/*
+ Dump PTD info. The code documents the format
+ perfectly, right :)
+*/
+static inline void dump_ptd(struct ptd *ptd)
+{
+#if defined(VERBOSE)
+ int k;
+#endif
+
+ DBG("PTD(ext) : cc:%x %d%c%d %d,%d,%d t:%x %x%x%x",
+ PTD_GET_CC(ptd),
+ PTD_GET_FA(ptd), PTD_DIR_STR(ptd), PTD_GET_EP(ptd),
+ PTD_GET_COUNT(ptd), PTD_GET_LEN(ptd), PTD_GET_MPS(ptd),
+ PTD_GET_TOGGLE(ptd),
+ PTD_GET_ACTIVE(ptd), PTD_GET_SPD(ptd), PTD_GET_LAST(ptd));
+#if defined(VERBOSE)
+ printf("isp116x: %s: PTD(byte): ", __FUNCTION__);
+ for (k = 0; k < sizeof(struct ptd); ++k)
+ printf("%02x ", ((u8 *) ptd)[k]);
+ printf("\n");
+#endif
+}
+
+static inline void dump_ptd_data(struct ptd *ptd, u8 * buf, int type)
+{
+#if defined(VERBOSE)
+ int k;
+
+ if (type == 0 /* 0ut data */ ) {
+ printf("isp116x: %s: out data: ", __FUNCTION__);
+ for (k = 0; k < PTD_GET_LEN(ptd); ++k)
+ printf("%02x ", ((u8 *) buf)[k]);
+ printf("\n");
+ }
+ if (type == 1 /* 1n data */ ) {
+ printf("isp116x: %s: in data: ", __FUNCTION__);
+ for (k = 0; k < PTD_GET_COUNT(ptd); ++k)
+ printf("%02x ", ((u8 *) buf)[k]);
+ printf("\n");
+ }
+
+ if (PTD_GET_LAST(ptd))
+ DBG("--- last PTD ---");
+#endif
+}
+
+#else
+
+#define dump_msg(dev, pipe, buffer, len, str) do { } while (0)
+#define dump_pkt(dev, pipe, buffer, len, setup, str, small) do {} while (0)
+
+#define dump_ptd(ptd) do {} while (0)
+#define dump_ptd_data(ptd, buf, type) do {} while (0)
+
+#endif
+
+/* --- Virtual Root Hub ---------------------------------------------------- */
+
+/* Device descriptor */
+static __u8 root_hub_dev_des[] = {
+ 0x12, /* __u8 bLength; */
+ 0x01, /* __u8 bDescriptorType; Device */
+ 0x10, /* __u16 bcdUSB; v1.1 */
+ 0x01,
+ 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
+ 0x00, /* __u8 bDeviceSubClass; */
+ 0x00, /* __u8 bDeviceProtocol; */
+ 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
+ 0x00, /* __u16 idVendor; */
+ 0x00,
+ 0x00, /* __u16 idProduct; */
+ 0x00,
+ 0x00, /* __u16 bcdDevice; */
+ 0x00,
+ 0x00, /* __u8 iManufacturer; */
+ 0x01, /* __u8 iProduct; */
+ 0x00, /* __u8 iSerialNumber; */
+ 0x01 /* __u8 bNumConfigurations; */
+};
+
+/* Configuration descriptor */
+static __u8 root_hub_config_des[] = {
+ 0x09, /* __u8 bLength; */
+ 0x02, /* __u8 bDescriptorType; Configuration */
+ 0x19, /* __u16 wTotalLength; */
+ 0x00,
+ 0x01, /* __u8 bNumInterfaces; */
+ 0x01, /* __u8 bConfigurationValue; */
+ 0x00, /* __u8 iConfiguration; */
+ 0x40, /* __u8 bmAttributes;
+ Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
+ 0x00, /* __u8 MaxPower; */
+
+ /* interface */
+ 0x09, /* __u8 if_bLength; */
+ 0x04, /* __u8 if_bDescriptorType; Interface */
+ 0x00, /* __u8 if_bInterfaceNumber; */
+ 0x00, /* __u8 if_bAlternateSetting; */
+ 0x01, /* __u8 if_bNumEndpoints; */
+ 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
+ 0x00, /* __u8 if_bInterfaceSubClass; */
+ 0x00, /* __u8 if_bInterfaceProtocol; */
+ 0x00, /* __u8 if_iInterface; */
+
+ /* endpoint */
+ 0x07, /* __u8 ep_bLength; */
+ 0x05, /* __u8 ep_bDescriptorType; Endpoint */
+ 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
+ 0x03, /* __u8 ep_bmAttributes; Interrupt */
+ 0x00, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
+ 0x02,
+ 0xff /* __u8 ep_bInterval; 255 ms */
+};
+
+static unsigned char root_hub_str_index0[] = {
+ 0x04, /* __u8 bLength; */
+ 0x03, /* __u8 bDescriptorType; String-descriptor */
+ 0x09, /* __u8 lang ID */
+ 0x04, /* __u8 lang ID */
+};
+
+static unsigned char root_hub_str_index1[] = {
+ 0x22, /* __u8 bLength; */
+ 0x03, /* __u8 bDescriptorType; String-descriptor */
+ 'I', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'S', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'P', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ '1', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ '1', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ '6', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'x', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ ' ', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'R', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'o', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'o', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 't', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ ' ', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'H', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'u', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'b', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+};
+
+/*
+ * Hub class-specific descriptor is constructed dynamically
+ */
+
+/* --- Virtual root hub management functions ------------------------------- */
+
+static int rh_check_port_status(struct isp116x *isp116x)
+{
+ u32 temp, ndp, i;
+ int res;
+
+ res = -1;
+ temp = isp116x_read_reg32(isp116x, HCRHSTATUS);
+ ndp = (temp & RH_A_NDP);
+ for (i = 0; i < ndp; i++) {
+ temp = isp116x_read_reg32(isp116x, HCRHPORT1 + i);
+ /* check for a device disconnect */
+ if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
+ (RH_PS_PESC | RH_PS_CSC)) && ((temp & RH_PS_CCS) == 0)) {
+ res = i;
+ break;
+ }
+ }
+ return res;
+}
+
+/* --- HC management functions --------------------------------------------- */
+
+/* Write len bytes to fifo, pad till 32-bit boundary
+ */
+static void write_ptddata_to_fifo(struct isp116x *isp116x, void *buf, int len)
+{
+ u8 *dp = (u8 *) buf;
+ u16 *dp2 = (u16 *) buf;
+ u16 w;
+ int quot = len % 4;
+
+ if ((unsigned long)dp2 & 1) {
+ /* not aligned */
+ for (; len > 1; len -= 2) {
+ w = *dp++;
+ w |= *dp++ << 8;
+ isp116x_raw_write_data16(isp116x, w);
+ }
+ if (len)
+ isp116x_write_data16(isp116x, (u16) * dp);
+ } else {
+ /* aligned */
+ for (; len > 1; len -= 2)
+ isp116x_raw_write_data16(isp116x, *dp2++);
+ if (len)
+ isp116x_write_data16(isp116x, 0xff & *((u8 *) dp2));
+ }
+ if (quot == 1 || quot == 2)
+ isp116x_raw_write_data16(isp116x, 0);
+}
+
+/* Read len bytes from fifo and then read till 32-bit boundary
+ */
+static void read_ptddata_from_fifo(struct isp116x *isp116x, void *buf, int len)
+{
+ u8 *dp = (u8 *) buf;
+ u16 *dp2 = (u16 *) buf;
+ u16 w;
+ int quot = len % 4;
+
+ if ((unsigned long)dp2 & 1) {
+ /* not aligned */
+ for (; len > 1; len -= 2) {
+ w = isp116x_raw_read_data16(isp116x);
+ *dp++ = w & 0xff;
+ *dp++ = (w >> 8) & 0xff;
+ }
+ if (len)
+ *dp = 0xff & isp116x_read_data16(isp116x);
+ } else {
+ /* aligned */
+ for (; len > 1; len -= 2)
+ *dp2++ = isp116x_raw_read_data16(isp116x);
+ if (len)
+ *(u8 *) dp2 = 0xff & isp116x_read_data16(isp116x);
+ }
+ if (quot == 1 || quot == 2)
+ isp116x_raw_read_data16(isp116x);
+}
+
+/* Write PTD's and data for scheduled transfers into the fifo ram.
+ * Fifo must be empty and ready */
+static void pack_fifo(struct isp116x *isp116x, struct usb_device *dev,
+ unsigned long pipe, struct ptd *ptd, int n, void *data,
+ int len)
+{
+ int buflen = n * sizeof(struct ptd) + len;
+ int i, done;
+
+ DBG("--- pack buffer %p - %d bytes (fifo %d) ---", data, len, buflen);
+
+ isp116x_write_reg16(isp116x, HCuPINT, HCuPINT_AIIEOT);
+ isp116x_write_reg16(isp116x, HCXFERCTR, buflen);
+ isp116x_write_addr(isp116x, HCATLPORT | ISP116x_WRITE_OFFSET);
+
+ done = 0;
+ for (i = 0; i < n; i++) {
+ DBG("i=%d - done=%d - len=%d", i, done, PTD_GET_LEN(&ptd[i]));
+
+ dump_ptd(&ptd[i]);
+ isp116x_write_data16(isp116x, ptd[i].count);
+ isp116x_write_data16(isp116x, ptd[i].mps);
+ isp116x_write_data16(isp116x, ptd[i].len);
+ isp116x_write_data16(isp116x, ptd[i].faddr);
+
+ dump_ptd_data(&ptd[i], (__u8 *) data + done, 0);
+ write_ptddata_to_fifo(isp116x,
+ (__u8 *) data + done,
+ PTD_GET_LEN(&ptd[i]));
+
+ done += PTD_GET_LEN(&ptd[i]);
+ }
+}
+
+/* Read the processed PTD's and data from fifo ram back to URBs' buffers.
+ * Fifo must be full and done */
+static int unpack_fifo(struct isp116x *isp116x, struct usb_device *dev,
+ unsigned long pipe, struct ptd *ptd, int n, void *data,
+ int len)
+{
+ int buflen = n * sizeof(struct ptd) + len;
+ int i, done, cc, ret;
+
+ isp116x_write_reg16(isp116x, HCuPINT, HCuPINT_AIIEOT);
+ isp116x_write_reg16(isp116x, HCXFERCTR, buflen);
+ isp116x_write_addr(isp116x, HCATLPORT);
+
+ ret = TD_CC_NOERROR;
+ done = 0;
+ for (i = 0; i < n; i++) {
+ DBG("i=%d - done=%d - len=%d", i, done, PTD_GET_LEN(&ptd[i]));
+
+ ptd[i].count = isp116x_read_data16(isp116x);
+ ptd[i].mps = isp116x_read_data16(isp116x);
+ ptd[i].len = isp116x_read_data16(isp116x);
+ ptd[i].faddr = isp116x_read_data16(isp116x);
+ dump_ptd(&ptd[i]);
+
+ read_ptddata_from_fifo(isp116x,
+ (__u8 *) data + done,
+ PTD_GET_LEN(&ptd[i]));
+ dump_ptd_data(&ptd[i], (__u8 *) data + done, 1);
+
+ done += PTD_GET_LEN(&ptd[i]);
+
+ cc = PTD_GET_CC(&ptd[i]);
+ if (cc == TD_DATAUNDERRUN) { /* underrun is no error... */
+ DBG("allowed data underrun");
+ cc = TD_CC_NOERROR;
+ }
+ if (cc != TD_CC_NOERROR && ret == TD_CC_NOERROR)
+ ret = cc;
+ }
+
+ DBG("--- unpack buffer %p - %d bytes (fifo %d) ---", data, len, buflen);
+
+ return ret;
+}
+
+/* Interrupt handling
+ */
+static int isp116x_interrupt(struct isp116x *isp116x)
+{
+ u16 irqstat;
+ u32 intstat;
+ int ret = 0;
+
+ isp116x_write_reg16(isp116x, HCuPINTENB, 0);
+ irqstat = isp116x_read_reg16(isp116x, HCuPINT);
+ isp116x_write_reg16(isp116x, HCuPINT, irqstat);
+ DBG(">>>>>> irqstat %x <<<<<<", irqstat);
+
+ if (irqstat & HCuPINT_ATL) {
+ DBG(">>>>>> HCuPINT_ATL <<<<<<");
+ udelay(500);
+ ret = 1;
+ }
+
+ if (irqstat & HCuPINT_OPR) {
+ intstat = isp116x_read_reg32(isp116x, HCINTSTAT);
+ isp116x_write_reg32(isp116x, HCINTSTAT, intstat);
+ DBG(">>>>>> HCuPINT_OPR %x <<<<<<", intstat);
+
+ if (intstat & HCINT_UE) {
+ ERR("unrecoverable error, controller disabled");
+
+ /* FIXME: be optimistic, hope that bug won't repeat
+ * often. Make some non-interrupt context restart the
+ * controller. Count and limit the retries though;
+ * either hardware or software errors can go forever...
+ */
+ isp116x_reset(isp116x);
+ ret = -1;
+ return -1;
+ }
+
+ if (intstat & HCINT_RHSC) {
+ got_rhsc = 1;
+ ret = 1;
+ /* When root hub or any of its ports is going
+ to come out of suspend, it may take more
+ than 10ms for status bits to stabilize. */
+ wait_ms(20);
+ }
+
+ if (intstat & HCINT_SO) {
+ ERR("schedule overrun");
+ ret = -1;
+ }
+
+ irqstat &= ~HCuPINT_OPR;
+ }
+
+ return ret;
+}
+
+#define PTD_NUM 64 /* it should be enougth... */
+struct ptd ptd[PTD_NUM];
+static inline int max_transfer_len(struct usb_device *dev, unsigned long pipe)
+{
+ return min(PTD_NUM * usb_maxpacket(dev, pipe), PTD_NUM * 16);
+}
+
+/* Do an USB transfer
+ */
+static int isp116x_submit_job(struct usb_device *dev, unsigned long pipe,
+ int dir, void *buffer, int len)
+{
+ struct isp116x *isp116x = &isp116x_dev;
+ int type = usb_pipetype(pipe);
+ int epnum = usb_pipeendpoint(pipe);
+ int max = usb_maxpacket(dev, pipe);
+ int dir_out = usb_pipeout(pipe);
+ int speed_low = usb_pipeslow(pipe);
+ int i, done, stat, timeout, cc;
+ int retries = 10;
+
+ DBG("------------------------------------------------");
+ dump_msg(dev, pipe, buffer, len, "SUBMIT");
+ DBG("------------------------------------------------");
+
+ if (isp116x->disabled) {
+ ERR("EPIPE");
+ dev->status = USB_ST_CRC_ERR;
+ return -1;
+ }
+
+ /* device pulled? Shortcut the action. */
+ if (devgone == dev) {
+ ERR("ENODEV");
+ dev->status = USB_ST_CRC_ERR;
+ return USB_ST_CRC_ERR;
+ }
+
+ if (!max) {
+ ERR("pipesize for pipe %lx is zero", pipe);
+ dev->status = USB_ST_CRC_ERR;
+ return -1;
+ }
+
+ if (type == PIPE_ISOCHRONOUS) {
+ ERR("isochronous transfers not supported");
+ dev->status = USB_ST_CRC_ERR;
+ return -1;
+ }
+
+ /* FIFO not empty? */
+ if (isp116x_read_reg16(isp116x, HCBUFSTAT) & HCBUFSTAT_ATL_FULL) {
+ ERR("****** FIFO not empty! ******");
+ dev->status = USB_ST_BUF_ERR;
+ return -1;
+ }
+
+ retry:
+ isp116x_write_reg32(isp116x, HCINTSTAT, 0xff);
+
+ /* Prepare the PTD data */
+ done = 0;
+ i = 0;
+ do {
+ ptd[i].count = PTD_CC_MSK | PTD_ACTIVE_MSK |
+ PTD_TOGGLE(usb_gettoggle(dev, epnum, dir_out));
+ ptd[i].mps = PTD_MPS(max) | PTD_SPD(speed_low) | PTD_EP(epnum);
+ ptd[i].len = PTD_LEN(max > len - done ? len - done : max) |
+ PTD_DIR(dir);
+ ptd[i].faddr = PTD_FA(usb_pipedevice(pipe));
+
+ usb_dotoggle(dev, epnum, dir_out);
+ done += PTD_GET_LEN(&ptd[i]);
+ i++;
+ if (i >= PTD_NUM) {
+ ERR("****** Cannot pack buffer! ******");
+ dev->status = USB_ST_BUF_ERR;
+ return -1;
+ }
+ } while (done < len);
+ ptd[i - 1].mps |= PTD_LAST_MSK;
+
+ /* Pack data into FIFO ram */
+ pack_fifo(isp116x, dev, pipe, ptd, i, buffer, len);
+#ifdef EXTRA_DELAY
+ wait_ms(EXTRA_DELAY);
+#endif
+
+ /* Start the data transfer */
+
+ /* Allow more time for a BULK device to react - some are slow */
+ if (usb_pipetype(pipe) == PIPE_BULK)
+ timeout = 5000;
+ else
+ timeout = 100;
+
+ /* Wait for it to complete */
+ for (;;) {
+ /* Check whether the controller is done */
+ stat = isp116x_interrupt(isp116x);
+
+ if (stat < 0) {
+ dev->status = USB_ST_CRC_ERR;
+ break;
+ }
+ if (stat > 0)
+ break;
+
+ /* Check the timeout */
+ if (--timeout)
+ udelay(1);
+ else {
+ ERR("CTL:TIMEOUT ");
+ stat = USB_ST_CRC_ERR;
+ break;
+ }
+ }
+
+ /* We got an Root Hub Status Change interrupt */
+ if (got_rhsc) {
+ isp116x_show_regs(isp116x);
+
+ got_rhsc = 0;
+
+ /* Abuse timeout */
+ timeout = rh_check_port_status(isp116x);
+ if (timeout >= 0) {
+ /*
+ * FIXME! NOTE! AAAARGH!
+ * This is potentially dangerous because it assumes
+ * that only one device is ever plugged in!
+ */
+ devgone = dev;
+ }
+ }
+
+ /* Ok, now we can read transfer status */
+
+ /* FIFO not ready? */
+ if (!(isp116x_read_reg16(isp116x, HCBUFSTAT) & HCBUFSTAT_ATL_DONE)) {
+ ERR("****** FIFO not ready! ******");
+ dev->status = USB_ST_BUF_ERR;
+ return -1;
+ }
+
+ /* Unpack data from FIFO ram */
+ cc = unpack_fifo(isp116x, dev, pipe, ptd, i, buffer, len);
+
+ /* Mmm... sometime we get 0x0f as cc which is a non sense!
+ * Just retry the transfer...
+ */
+ if (cc == 0x0f && retries-- > 0) {
+ usb_dotoggle(dev, epnum, dir_out);
+ goto retry;
+ }
+
+ if (cc != TD_CC_NOERROR) {
+ DBG("****** completition code error %x ******", cc);
+ switch (cc) {
+ case TD_CC_BITSTUFFING:
+ dev->status = USB_ST_BIT_ERR;
+ break;
+ case TD_CC_STALL:
+ dev->status = USB_ST_STALLED;
+ break;
+ case TD_BUFFEROVERRUN:
+ case TD_BUFFERUNDERRUN:
+ dev->status = USB_ST_BUF_ERR;
+ break;
+ default:
+ dev->status = USB_ST_CRC_ERR;
+ }
+ return -cc;
+ }
+
+ dump_msg(dev, pipe, buffer, len, "SUBMIT(ret)");
+
+ dev->status = 0;
+ return done;
+}
+
+/* Adapted from au1x00_usb_ohci.c
+ */
+static int isp116x_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
+ void *buffer, int transfer_len,
+ struct devrequest *cmd)
+{
+ struct isp116x *isp116x = &isp116x_dev;
+ u32 tmp = 0;
+
+ int leni = transfer_len;
+ int len = 0;
+ int stat = 0;
+ u32 datab[4];
+ u8 *data_buf = (u8 *) datab;
+ u16 bmRType_bReq;
+ u16 wValue;
+ u16 wIndex;
+ u16 wLength;
+
+ if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {
+ INFO("Root-Hub submit IRQ: NOT implemented");
+ return 0;
+ }
+
+ bmRType_bReq = cmd->requesttype | (cmd->request << 8);
+ wValue = swap_16(cmd->value);
+ wIndex = swap_16(cmd->index);
+ wLength = swap_16(cmd->length);
+
+ DBG("--- HUB ----------------------------------------");
+ DBG("submit rh urb, req=%x val=%#x index=%#x len=%d",
+ bmRType_bReq, wValue, wIndex, wLength);
+ dump_msg(dev, pipe, buffer, transfer_len, "RH");
+ DBG("------------------------------------------------");
+
+ switch (bmRType_bReq) {
+ case RH_GET_STATUS:
+ DBG("RH_GET_STATUS");
+
+ *(__u16 *) data_buf = swap_16(1);
+ len = 2;
+ break;
+
+ case RH_GET_STATUS | RH_INTERFACE:
+ DBG("RH_GET_STATUS | RH_INTERFACE");
+
+ *(__u16 *) data_buf = swap_16(0);
+ len = 2;
+ break;
+
+ case RH_GET_STATUS | RH_ENDPOINT:
+ DBG("RH_GET_STATUS | RH_ENDPOINT");
+
+ *(__u16 *) data_buf = swap_16(0);
+ len = 2;
+ break;
+
+ case RH_GET_STATUS | RH_CLASS:
+ DBG("RH_GET_STATUS | RH_CLASS");
+
+ tmp = isp116x_read_reg32(isp116x, HCRHSTATUS);
+
+ *(__u32 *) data_buf = swap_32(tmp & ~(RH_HS_CRWE | RH_HS_DRWE));
+ len = 4;
+ break;
+
+ case RH_GET_STATUS | RH_OTHER | RH_CLASS:
+ DBG("RH_GET_STATUS | RH_OTHER | RH_CLASS");
+
+ tmp = isp116x_read_reg32(isp116x, HCRHPORT1 + wIndex - 1);
+ *(__u32 *) data_buf = swap_32(tmp);
+ isp116x_show_regs(isp116x);
+ len = 4;
+ break;
+
+ case RH_CLEAR_FEATURE | RH_ENDPOINT:
+ DBG("RH_CLEAR_FEATURE | RH_ENDPOINT");
+
+ switch (wValue) {
+ case RH_ENDPOINT_STALL:
+ DBG("C_HUB_ENDPOINT_STALL");
+ len = 0;
+ break;
+ }
+ break;
+
+ case RH_CLEAR_FEATURE | RH_CLASS:
+ DBG("RH_CLEAR_FEATURE | RH_CLASS");
+
+ switch (wValue) {
+ case RH_C_HUB_LOCAL_POWER:
+ DBG("C_HUB_LOCAL_POWER");
+ len = 0;
+ break;
+
+ case RH_C_HUB_OVER_CURRENT:
+ DBG("C_HUB_OVER_CURRENT");
+ isp116x_write_reg32(isp116x, HCRHSTATUS, RH_HS_OCIC);
+ len = 0;
+ break;
+ }
+ break;
+
+ case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
+ DBG("RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS");
+
+ switch (wValue) {
+ case RH_PORT_ENABLE:
+ isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+ RH_PS_CCS);
+ len = 0;
+ break;
+
+ case RH_PORT_SUSPEND:
+ isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+ RH_PS_POCI);
+ len = 0;
+ break;
+
+ case RH_PORT_POWER:
+ isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+ RH_PS_LSDA);
+ len = 0;
+ break;
+
+ case RH_C_PORT_CONNECTION:
+ isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+ RH_PS_CSC);
+ len = 0;
+ break;
+
+ case RH_C_PORT_ENABLE:
+ isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+ RH_PS_PESC);
+ len = 0;
+ break;
+
+ case RH_C_PORT_SUSPEND:
+ isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+ RH_PS_PSSC);
+ len = 0;
+ break;
+
+ case RH_C_PORT_OVER_CURRENT:
+ isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+ RH_PS_POCI);
+ len = 0;
+ break;
+
+ case RH_C_PORT_RESET:
+ isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+ RH_PS_PRSC);
+ len = 0;
+ break;
+
+ default:
+ ERR("invalid wValue");
+ stat = USB_ST_STALLED;
+ }
+
+ isp116x_show_regs(isp116x);
+
+ break;
+
+ case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
+ DBG("RH_SET_FEATURE | RH_OTHER | RH_CLASS");
+
+ switch (wValue) {
+ case RH_PORT_SUSPEND:
+ isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+ RH_PS_PSS);
+ len = 0;
+ break;
+
+ case RH_PORT_RESET:
+ /* Spin until any current reset finishes */
+ while (1) {
+ tmp =
+ isp116x_read_reg32(isp116x,
+ HCRHPORT1 + wIndex - 1);
+ if (!(tmp & RH_PS_PRS))
+ break;
+ wait_ms(1);
+ }
+ isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+ RH_PS_PRS);
+ wait_ms(10);
+
+ len = 0;
+ break;
+
+ case RH_PORT_POWER:
+ isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+ RH_PS_PPS);
+ len = 0;
+ break;
+
+ case RH_PORT_ENABLE:
+ isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+ RH_PS_PES);
+ len = 0;
+ break;
+
+ default:
+ ERR("invalid wValue");
+ stat = USB_ST_STALLED;
+ }
+
+ isp116x_show_regs(isp116x);
+
+ break;
+
+ case RH_SET_ADDRESS:
+ DBG("RH_SET_ADDRESS");
+
+ rh_devnum = wValue;
+ len = 0;
+ break;
+
+ case RH_GET_DESCRIPTOR:
+ DBG("RH_GET_DESCRIPTOR: %x, %d", wValue, wLength);
+
+ switch (wValue) {
+ case (USB_DT_DEVICE << 8): /* device descriptor */
+ len = min_t(unsigned int,
+ leni, min_t(unsigned int,
+ sizeof(root_hub_dev_des),
+ wLength));
+ data_buf = root_hub_dev_des;
+ break;
+
+ case (USB_DT_CONFIG << 8): /* configuration descriptor */
+ len = min_t(unsigned int,
+ leni, min_t(unsigned int,
+ sizeof(root_hub_config_des),
+ wLength));
+ data_buf = root_hub_config_des;
+ break;
+
+ case ((USB_DT_STRING << 8) | 0x00): /* string 0 descriptors */
+ len = min_t(unsigned int,
+ leni, min_t(unsigned int,
+ sizeof(root_hub_str_index0),
+ wLength));
+ data_buf = root_hub_str_index0;
+ break;
+
+ case ((USB_DT_STRING << 8) | 0x01): /* string 1 descriptors */
+ len = min_t(unsigned int,
+ leni, min_t(unsigned int,
+ sizeof(root_hub_str_index1),
+ wLength));
+ data_buf = root_hub_str_index1;
+ break;
+
+ default:
+ ERR("invalid wValue");
+ stat = USB_ST_STALLED;
+ }
+
+ break;
+
+ case RH_GET_DESCRIPTOR | RH_CLASS:
+ DBG("RH_GET_DESCRIPTOR | RH_CLASS");
+
+ tmp = isp116x_read_reg32(isp116x, HCRHDESCA);
+
+ data_buf[0] = 0x09; /* min length; */
+ data_buf[1] = 0x29;
+ data_buf[2] = tmp & RH_A_NDP;
+ data_buf[3] = 0;
+ if (tmp & RH_A_PSM) /* per-port power switching? */
+ data_buf[3] |= 0x01;
+ if (tmp & RH_A_NOCP) /* no overcurrent reporting? */
+ data_buf[3] |= 0x10;
+ else if (tmp & RH_A_OCPM) /* per-port overcurrent rep? */
+ data_buf[3] |= 0x08;
+
+ /* Corresponds to data_buf[4-7] */
+ datab[1] = 0;
+ data_buf[5] = (tmp & RH_A_POTPGT) >> 24;
+
+ tmp = isp116x_read_reg32(isp116x, HCRHDESCB);
+
+ data_buf[7] = tmp & RH_B_DR;
+ if (data_buf[2] < 7)
+ data_buf[8] = 0xff;
+ else {
+ data_buf[0] += 2;
+ data_buf[8] = (tmp & RH_B_DR) >> 8;
+ data_buf[10] = data_buf[9] = 0xff;
+ }
+
+ len = min_t(unsigned int, leni,
+ min_t(unsigned int, data_buf[0], wLength));
+ break;
+
+ case RH_GET_CONFIGURATION:
+ DBG("RH_GET_CONFIGURATION");
+
+ *(__u8 *) data_buf = 0x01;
+ len = 1;
+ break;
+
+ case RH_SET_CONFIGURATION:
+ DBG("RH_SET_CONFIGURATION");
+
+ isp116x_write_reg32(isp116x, HCRHSTATUS, RH_HS_LPSC);
+ len = 0;
+ break;
+
+ default:
+ ERR("*** *** *** unsupported root hub command *** *** ***");
+ stat = USB_ST_STALLED;
+ }
+
+ len = min_t(int, len, leni);
+ if (buffer != data_buf)
+ memcpy(buffer, data_buf, len);
+
+ dev->act_len = len;
+ dev->status = stat;
+ DBG("dev act_len %d, status %d", dev->act_len, dev->status);
+
+ dump_msg(dev, pipe, buffer, transfer_len, "RH(ret)");
+
+ return stat;
+}
+
+/* --- Transfer functions -------------------------------------------------- */
+
+int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+ int len, int interval)
+{
+ DBG("dev=%p pipe=%#lx buf=%p size=%d int=%d",
+ dev, pipe, buffer, len, interval);
+
+ return -1;
+}
+
+int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+ int len, struct devrequest *setup)
+{
+ int devnum = usb_pipedevice(pipe);
+ int epnum = usb_pipeendpoint(pipe);
+ int max = max_transfer_len(dev, pipe);
+ int dir_in = usb_pipein(pipe);
+ int done, ret;
+
+ /* Control message is for the HUB? */
+ if (devnum == rh_devnum)
+ return isp116x_submit_rh_msg(dev, pipe, buffer, len, setup);
+
+ /* Ok, no HUB message so send the message to the device */
+
+ /* Setup phase */
+ DBG("--- SETUP PHASE --------------------------------");
+ usb_settoggle(dev, epnum, 1, 0);
+ ret = isp116x_submit_job(dev, pipe,
+ PTD_DIR_SETUP,
+ setup, sizeof(struct devrequest));
+ if (ret < 0) {
+ DBG("control setup phase error (ret = %d", ret);
+ return -1;
+ }
+
+ /* Data phase */
+ DBG("--- DATA PHASE ---------------------------------");
+ done = 0;
+ usb_settoggle(dev, epnum, !dir_in, 1);
+ while (done < len) {
+ ret = isp116x_submit_job(dev, pipe,
+ dir_in ? PTD_DIR_IN : PTD_DIR_OUT,
+ (__u8 *) buffer + done,
+ max > len - done ? len - done : max);
+ if (ret < 0) {
+ DBG("control data phase error (ret = %d)", ret);
+ return -1;
+ }
+ done += ret;
+
+ if (dir_in && ret < max) /* short packet */
+ break;
+ }
+
+ /* Status phase */
+ DBG("--- STATUS PHASE -------------------------------");
+ usb_settoggle(dev, epnum, !dir_in, 1);
+ ret = isp116x_submit_job(dev, pipe,
+ !dir_in ? PTD_DIR_IN : PTD_DIR_OUT, NULL, 0);
+ if (ret < 0) {
+ DBG("control status phase error (ret = %d", ret);
+ return -1;
+ }
+
+ dev->act_len = done;
+
+ dump_msg(dev, pipe, buffer, len, "DEV(ret)");
+
+ return done;
+}
+
+int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+ int len)
+{
+ int dir_out = usb_pipeout(pipe);
+ int max = max_transfer_len(dev, pipe);
+ int done, ret;
+
+ DBG("--- BULK ---------------------------------------");
+ DBG("dev=%ld pipe=%ld buf=%p size=%d dir_out=%d",
+ usb_pipedevice(pipe), usb_pipeendpoint(pipe), buffer, len, dir_out);
+
+ done = 0;
+ while (done < len) {
+ ret = isp116x_submit_job(dev, pipe,
+ !dir_out ? PTD_DIR_IN : PTD_DIR_OUT,
+ (__u8 *) buffer + done,
+ max > len - done ? len - done : max);
+ if (ret < 0) {
+ DBG("error on bulk message (ret = %d)", ret);
+ return -1;
+ }
+
+ done += ret;
+
+ if (!dir_out && ret < max) /* short packet */
+ break;
+ }
+
+ dev->act_len = done;
+
+ return 0;
+}
+
+/* --- Basic functions ----------------------------------------------------- */
+
+static int isp116x_sw_reset(struct isp116x *isp116x)
+{
+ int retries = 15;
+ int ret = 0;
+
+ DBG("");
+
+ isp116x->disabled = 1;
+
+ isp116x_write_reg16(isp116x, HCSWRES, HCSWRES_MAGIC);
+ isp116x_write_reg32(isp116x, HCCMDSTAT, HCCMDSTAT_HCR);
+ while (--retries) {
+ /* It usually resets within 1 ms */
+ wait_ms(1);
+ if (!(isp116x_read_reg32(isp116x, HCCMDSTAT) & HCCMDSTAT_HCR))
+ break;
+ }
+ if (!retries) {
+ ERR("software reset timeout");
+ ret = -1;
+ }
+ return ret;
+}
+
+static int isp116x_reset(struct isp116x *isp116x)
+{
+ unsigned long t;
+ u16 clkrdy = 0;
+ int ret, timeout = 15 /* ms */ ;
+
+ DBG("");
+
+ ret = isp116x_sw_reset(isp116x);
+ if (ret)
+ return ret;
+
+ for (t = 0; t < timeout; t++) {
+ clkrdy = isp116x_read_reg16(isp116x, HCuPINT) & HCuPINT_CLKRDY;
+ if (clkrdy)
+ break;
+ wait_ms(1);
+ }
+ if (!clkrdy) {
+ ERR("clock not ready after %dms", timeout);
+ /* After sw_reset the clock won't report to be ready, if
+ H_WAKEUP pin is high. */
+ ERR("please make sure that the H_WAKEUP pin is pulled low!");
+ ret = -1;
+ }
+ return ret;
+}
+
+static void isp116x_stop(struct isp116x *isp116x)
+{
+ u32 val;
+
+ DBG("");
+
+ isp116x_write_reg16(isp116x, HCuPINTENB, 0);
+
+ /* Switch off ports' power, some devices don't come up
+ after next 'start' without this */
+ val = isp116x_read_reg32(isp116x, HCRHDESCA);
+ val &= ~(RH_A_NPS | RH_A_PSM);
+ isp116x_write_reg32(isp116x, HCRHDESCA, val);
+ isp116x_write_reg32(isp116x, HCRHSTATUS, RH_HS_LPS);
+
+ isp116x_sw_reset(isp116x);
+}
+
+/*
+ * Configure the chip. The chip must be successfully reset by now.
+ */
+static int isp116x_start(struct isp116x *isp116x)
+{
+ struct isp116x_platform_data *board = isp116x->board;
+ u32 val;
+
+ DBG("");
+
+ /* Clear interrupt status and disable all interrupt sources */
+ isp116x_write_reg16(isp116x, HCuPINT, 0xff);
+ isp116x_write_reg16(isp116x, HCuPINTENB, 0);
+
+ isp116x_write_reg16(isp116x, HCITLBUFLEN, ISP116x_ITL_BUFSIZE);
+ isp116x_write_reg16(isp116x, HCATLBUFLEN, ISP116x_ATL_BUFSIZE);
+
+ /* Hardware configuration */
+ val = HCHWCFG_DBWIDTH(1);
+ if (board->sel15Kres)
+ val |= HCHWCFG_15KRSEL;
+ /* Remote wakeup won't work without working clock */
+ if (board->remote_wakeup_enable)
+ val |= HCHWCFG_CLKNOTSTOP;
+ if (board->oc_enable)
+ val |= HCHWCFG_ANALOG_OC;
+ isp116x_write_reg16(isp116x, HCHWCFG, val);
+
+ /* --- Root hub configuration */
+ val = (25 << 24) & RH_A_POTPGT;
+ /* AN10003_1.pdf recommends RH_A_NPS (no power switching) to
+ be always set. Yet, instead, we request individual port
+ power switching. */
+ val |= RH_A_PSM;
+ /* Report overcurrent per port */
+ val |= RH_A_OCPM;
+ isp116x_write_reg32(isp116x, HCRHDESCA, val);
+ isp116x->rhdesca = isp116x_read_reg32(isp116x, HCRHDESCA);
+
+ val = RH_B_PPCM;
+ isp116x_write_reg32(isp116x, HCRHDESCB, val);
+ isp116x->rhdescb = isp116x_read_reg32(isp116x, HCRHDESCB);
+
+ val = 0;
+ if (board->remote_wakeup_enable)
+ val |= RH_HS_DRWE;
+ isp116x_write_reg32(isp116x, HCRHSTATUS, val);
+ isp116x->rhstatus = isp116x_read_reg32(isp116x, HCRHSTATUS);
+
+ isp116x_write_reg32(isp116x, HCFMINTVL, 0x27782edf);
+
+ /* Go operational */
+ val = HCCONTROL_USB_OPER;
+ if (board->remote_wakeup_enable)
+ val |= HCCONTROL_RWE;
+ isp116x_write_reg32(isp116x, HCCONTROL, val);
+
+ /* Disable ports to avoid race in device enumeration */
+ isp116x_write_reg32(isp116x, HCRHPORT1, RH_PS_CCS);
+ isp116x_write_reg32(isp116x, HCRHPORT2, RH_PS_CCS);
+
+ isp116x_show_regs(isp116x);
+
+ isp116x->disabled = 0;
+
+ return 0;
+}
+
+/* --- Init functions ------------------------------------------------------ */
+
+int isp116x_check_id(struct isp116x *isp116x)
+{
+ int val;
+
+ val = isp116x_read_reg16(isp116x, HCCHIPID);
+ if ((val & HCCHIPID_MASK) != HCCHIPID_MAGIC) {
+ ERR("invalid chip ID %04x", val);
+ return -1;
+ }
+
+ return 0;
+}
+
+int usb_lowlevel_init(void)
+{
+ struct isp116x *isp116x = &isp116x_dev;
+
+ DBG("");
+
+ /* Init device registers addr */
+ isp116x->addr_reg = (u16 *) ISP116X_HCD_ADDR;
+ isp116x->data_reg = (u16 *) ISP116X_HCD_DATA;
+
+ /* Setup specific board settings */
+#ifdef ISP116X_HCD_SEL15kRES
+ isp116x_board.sel15Kres = 1;
+#endif
+#ifdef ISP116X_HCD_OC_ENABLE
+ isp116x_board.oc_enable = 1;
+#endif
+#ifdef ISP116X_HCD_REMOTE_WAKEUP_ENABLE
+ isp116x_board.remote_wakeup_enable = 1;
+#endif
+ isp116x->board = &isp116x_board;
+
+ /* Try to get ISP116x silicon chip ID */
+ if (isp116x_check_id(isp116x) < 0)
+ return -1;
+
+ isp116x->disabled = 1;
+ isp116x->sleeping = 0;
+
+ isp116x_reset(isp116x);
+ isp116x_start(isp116x);
+
+ return 0;
+}
+
+int usb_lowlevel_stop(void)
+{
+ struct isp116x *isp116x = &isp116x_dev;
+
+ DBG("");
+
+ if (!isp116x->disabled)
+ isp116x_stop(isp116x);
+
+ return 0;
+}
+
+#endif /* CONFIG_USB_ISP116X_HCD */
diff --git a/drivers/isp116x.h b/drivers/isp116x.h
new file mode 100644
index 0000000..a3ce3b5
--- /dev/null
+++ b/drivers/isp116x.h
@@ -0,0 +1,489 @@
+/*
+ * ISP116x register declarations and HCD data structures
+ *
+ * Copyright (C) 2007 Rodolfo Giometti <giometti@linux.it>
+ * Copyright (C) 2007 Eurotech S.p.A. <info@eurotech.it>
+ * Copyright (C) 2005 Olav Kongas <ok@artecdesign.ee>
+ * Portions:
+ * Copyright (C) 2004 Lothar Wassmann
+ * Copyright (C) 2004 Psion Teklogix
+ * Copyright (C) 2004 David Brownell
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifdef DEBUG
+#define DBG(fmt, args...) \
+ printf("isp116x: %s: " fmt "\n" , __FUNCTION__ , ## args)
+#else
+#define DBG(fmt, args...) do {} while (0)
+#endif
+
+#ifdef VERBOSE
+# define VDBG DBG
+#else
+# define VDBG(fmt, args...) do {} while (0)
+#endif
+
+#define ERR(fmt, args...) \
+ printf("isp116x: %s: " fmt "\n" , __FUNCTION__ , ## args)
+#define WARN(fmt, args...) \
+ printf("isp116x: %s: " fmt "\n" , __FUNCTION__ , ## args)
+#define INFO(fmt, args...) \
+ printf("isp116x: " fmt "\n" , ## args)
+
+/* ------------------------------------------------------------------------- */
+
+/* us of 1ms frame */
+#define MAX_LOAD_LIMIT 850
+
+/* Full speed: max # of bytes to transfer for a single urb
+ at a time must be < 1024 && must be multiple of 64.
+ 832 allows transfering 4kiB within 5 frames. */
+#define MAX_TRANSFER_SIZE_FULLSPEED 832
+
+/* Low speed: there is no reason to schedule in very big
+ chunks; often the requested long transfers are for
+ string descriptors containing short strings. */
+#define MAX_TRANSFER_SIZE_LOWSPEED 64
+
+/* Bytetime (us), a rough indication of how much time it
+ would take to transfer a byte of useful data over USB */
+#define BYTE_TIME_FULLSPEED 1
+#define BYTE_TIME_LOWSPEED 20
+
+/* Buffer sizes */
+#define ISP116x_BUF_SIZE 4096
+#define ISP116x_ITL_BUFSIZE 0
+#define ISP116x_ATL_BUFSIZE ((ISP116x_BUF_SIZE) - 2*(ISP116x_ITL_BUFSIZE))
+
+#define ISP116x_WRITE_OFFSET 0x80
+
+/* --- ISP116x registers/bits ---------------------------------------------- */
+
+#define HCREVISION 0x00
+#define HCCONTROL 0x01
+#define HCCONTROL_HCFS (3 << 6) /* host controller
+ functional state */
+#define HCCONTROL_USB_RESET (0 << 6)
+#define HCCONTROL_USB_RESUME (1 << 6)
+#define HCCONTROL_USB_OPER (2 << 6)
+#define HCCONTROL_USB_SUSPEND (3 << 6)
+#define HCCONTROL_RWC (1 << 9) /* remote wakeup connected */
+#define HCCONTROL_RWE (1 << 10) /* remote wakeup enable */
+#define HCCMDSTAT 0x02
+#define HCCMDSTAT_HCR (1 << 0) /* host controller reset */
+#define HCCMDSTAT_SOC (3 << 16) /* scheduling overrun count */
+#define HCINTSTAT 0x03
+#define HCINT_SO (1 << 0) /* scheduling overrun */
+#define HCINT_WDH (1 << 1) /* writeback of done_head */
+#define HCINT_SF (1 << 2) /* start frame */
+#define HCINT_RD (1 << 3) /* resume detect */
+#define HCINT_UE (1 << 4) /* unrecoverable error */
+#define HCINT_FNO (1 << 5) /* frame number overflow */
+#define HCINT_RHSC (1 << 6) /* root hub status change */
+#define HCINT_OC (1 << 30) /* ownership change */
+#define HCINT_MIE (1 << 31) /* master interrupt enable */
+#define HCINTENB 0x04
+#define HCINTDIS 0x05
+#define HCFMINTVL 0x0d
+#define HCFMREM 0x0e
+#define HCFMNUM 0x0f
+#define HCLSTHRESH 0x11
+#define HCRHDESCA 0x12
+#define RH_A_NDP (0x3 << 0) /* # downstream ports */
+#define RH_A_PSM (1 << 8) /* power switching mode */
+#define RH_A_NPS (1 << 9) /* no power switching */
+#define RH_A_DT (1 << 10) /* device type (mbz) */
+#define RH_A_OCPM (1 << 11) /* overcurrent protection
+ mode */
+#define RH_A_NOCP (1 << 12) /* no overcurrent protection */
+#define RH_A_POTPGT (0xff << 24) /* power on -> power good
+ time */
+#define HCRHDESCB 0x13
+#define RH_B_DR (0xffff << 0) /* device removable flags */
+#define RH_B_PPCM (0xffff << 16) /* port power control mask */
+#define HCRHSTATUS 0x14
+#define RH_HS_LPS (1 << 0) /* local power status */
+#define RH_HS_OCI (1 << 1) /* over current indicator */
+#define RH_HS_DRWE (1 << 15) /* device remote wakeup
+ enable */
+#define RH_HS_LPSC (1 << 16) /* local power status change */
+#define RH_HS_OCIC (1 << 17) /* over current indicator
+ change */
+#define RH_HS_CRWE (1 << 31) /* clear remote wakeup
+ enable */
+#define HCRHPORT1 0x15
+#define RH_PS_CCS (1 << 0) /* current connect status */
+#define RH_PS_PES (1 << 1) /* port enable status */
+#define RH_PS_PSS (1 << 2) /* port suspend status */
+#define RH_PS_POCI (1 << 3) /* port over current
+ indicator */
+#define RH_PS_PRS (1 << 4) /* port reset status */
+#define RH_PS_PPS (1 << 8) /* port power status */
+#define RH_PS_LSDA (1 << 9) /* low speed device attached */
+#define RH_PS_CSC (1 << 16) /* connect status change */
+#define RH_PS_PESC (1 << 17) /* port enable status change */
+#define RH_PS_PSSC (1 << 18) /* port suspend status
+ change */
+#define RH_PS_OCIC (1 << 19) /* over current indicator
+ change */
+#define RH_PS_PRSC (1 << 20) /* port reset status change */
+#define HCRHPORT_CLRMASK (0x1f << 16)
+#define HCRHPORT2 0x16
+#define HCHWCFG 0x20
+#define HCHWCFG_15KRSEL (1 << 12)
+#define HCHWCFG_CLKNOTSTOP (1 << 11)
+#define HCHWCFG_ANALOG_OC (1 << 10)
+#define HCHWCFG_DACK_MODE (1 << 8)
+#define HCHWCFG_EOT_POL (1 << 7)
+#define HCHWCFG_DACK_POL (1 << 6)
+#define HCHWCFG_DREQ_POL (1 << 5)
+#define HCHWCFG_DBWIDTH_MASK (0x03 << 3)
+#define HCHWCFG_DBWIDTH(n) (((n) << 3) & HCHWCFG_DBWIDTH_MASK)
+#define HCHWCFG_INT_POL (1 << 2)
+#define HCHWCFG_INT_TRIGGER (1 << 1)
+#define HCHWCFG_INT_ENABLE (1 << 0)
+#define HCDMACFG 0x21
+#define HCDMACFG_BURST_LEN_MASK (0x03 << 5)
+#define HCDMACFG_BURST_LEN(n) (((n) << 5) & HCDMACFG_BURST_LEN_MASK)
+#define HCDMACFG_BURST_LEN_1 HCDMACFG_BURST_LEN(0)
+#define HCDMACFG_BURST_LEN_4 HCDMACFG_BURST_LEN(1)
+#define HCDMACFG_BURST_LEN_8 HCDMACFG_BURST_LEN(2)
+#define HCDMACFG_DMA_ENABLE (1 << 4)
+#define HCDMACFG_BUF_TYPE_MASK (0x07 << 1)
+#define HCDMACFG_CTR_SEL (1 << 2)
+#define HCDMACFG_ITLATL_SEL (1 << 1)
+#define HCDMACFG_DMA_RW_SELECT (1 << 0)
+#define HCXFERCTR 0x22
+#define HCuPINT 0x24
+#define HCuPINT_SOF (1 << 0)
+#define HCuPINT_ATL (1 << 1)
+#define HCuPINT_AIIEOT (1 << 2)
+#define HCuPINT_OPR (1 << 4)
+#define HCuPINT_SUSP (1 << 5)
+#define HCuPINT_CLKRDY (1 << 6)
+#define HCuPINTENB 0x25
+#define HCCHIPID 0x27
+#define HCCHIPID_MASK 0xff00
+#define HCCHIPID_MAGIC 0x6100
+#define HCSCRATCH 0x28
+#define HCSWRES 0x29
+#define HCSWRES_MAGIC 0x00f6
+#define HCITLBUFLEN 0x2a
+#define HCATLBUFLEN 0x2b
+#define HCBUFSTAT 0x2c
+#define HCBUFSTAT_ITL0_FULL (1 << 0)
+#define HCBUFSTAT_ITL1_FULL (1 << 1)
+#define HCBUFSTAT_ATL_FULL (1 << 2)
+#define HCBUFSTAT_ITL0_DONE (1 << 3)
+#define HCBUFSTAT_ITL1_DONE (1 << 4)
+#define HCBUFSTAT_ATL_DONE (1 << 5)
+#define HCRDITL0LEN 0x2d
+#define HCRDITL1LEN 0x2e
+#define HCITLPORT 0x40
+#define HCATLPORT 0x41
+
+/* PTD accessor macros. */
+#define PTD_GET_COUNT(p) (((p)->count & PTD_COUNT_MSK) >> 0)
+#define PTD_COUNT(v) (((v) << 0) & PTD_COUNT_MSK)
+#define PTD_GET_TOGGLE(p) (((p)->count & PTD_TOGGLE_MSK) >> 10)
+#define PTD_TOGGLE(v) (((v) << 10) & PTD_TOGGLE_MSK)
+#define PTD_GET_ACTIVE(p) (((p)->count & PTD_ACTIVE_MSK) >> 11)
+#define PTD_ACTIVE(v) (((v) << 11) & PTD_ACTIVE_MSK)
+#define PTD_GET_CC(p) (((p)->count & PTD_CC_MSK) >> 12)
+#define PTD_CC(v) (((v) << 12) & PTD_CC_MSK)
+#define PTD_GET_MPS(p) (((p)->mps & PTD_MPS_MSK) >> 0)
+#define PTD_MPS(v) (((v) << 0) & PTD_MPS_MSK)
+#define PTD_GET_SPD(p) (((p)->mps & PTD_SPD_MSK) >> 10)
+#define PTD_SPD(v) (((v) << 10) & PTD_SPD_MSK)
+#define PTD_GET_LAST(p) (((p)->mps & PTD_LAST_MSK) >> 11)
+#define PTD_LAST(v) (((v) << 11) & PTD_LAST_MSK)
+#define PTD_GET_EP(p) (((p)->mps & PTD_EP_MSK) >> 12)
+#define PTD_EP(v) (((v) << 12) & PTD_EP_MSK)
+#define PTD_GET_LEN(p) (((p)->len & PTD_LEN_MSK) >> 0)
+#define PTD_LEN(v) (((v) << 0) & PTD_LEN_MSK)
+#define PTD_GET_DIR(p) (((p)->len & PTD_DIR_MSK) >> 10)
+#define PTD_DIR(v) (((v) << 10) & PTD_DIR_MSK)
+#define PTD_GET_B5_5(p) (((p)->len & PTD_B5_5_MSK) >> 13)
+#define PTD_B5_5(v) (((v) << 13) & PTD_B5_5_MSK)
+#define PTD_GET_FA(p) (((p)->faddr & PTD_FA_MSK) >> 0)
+#define PTD_FA(v) (((v) << 0) & PTD_FA_MSK)
+#define PTD_GET_FMT(p) (((p)->faddr & PTD_FMT_MSK) >> 7)
+#define PTD_FMT(v) (((v) << 7) & PTD_FMT_MSK)
+
+/* Hardware transfer status codes -- CC from ptd->count */
+#define TD_CC_NOERROR 0x00
+#define TD_CC_CRC 0x01
+#define TD_CC_BITSTUFFING 0x02
+#define TD_CC_DATATOGGLEM 0x03
+#define TD_CC_STALL 0x04
+#define TD_DEVNOTRESP 0x05
+#define TD_PIDCHECKFAIL 0x06
+#define TD_UNEXPECTEDPID 0x07
+#define TD_DATAOVERRUN 0x08
+#define TD_DATAUNDERRUN 0x09
+ /* 0x0A, 0x0B reserved for hardware */
+#define TD_BUFFEROVERRUN 0x0C
+#define TD_BUFFERUNDERRUN 0x0D
+ /* 0x0E, 0x0F reserved for HCD */
+#define TD_NOTACCESSED 0x0F
+
+/* ------------------------------------------------------------------------- */
+
+#define LOG2_PERIODIC_SIZE 5 /* arbitrary; this matches OHCI */
+#define PERIODIC_SIZE (1 << LOG2_PERIODIC_SIZE)
+
+/* Philips transfer descriptor */
+struct ptd {
+ u16 count;
+#define PTD_COUNT_MSK (0x3ff << 0)
+#define PTD_TOGGLE_MSK (1 << 10)
+#define PTD_ACTIVE_MSK (1 << 11)
+#define PTD_CC_MSK (0xf << 12)
+ u16 mps;
+#define PTD_MPS_MSK (0x3ff << 0)
+#define PTD_SPD_MSK (1 << 10)
+#define PTD_LAST_MSK (1 << 11)
+#define PTD_EP_MSK (0xf << 12)
+ u16 len;
+#define PTD_LEN_MSK (0x3ff << 0)
+#define PTD_DIR_MSK (3 << 10)
+#define PTD_DIR_SETUP (0)
+#define PTD_DIR_OUT (1)
+#define PTD_DIR_IN (2)
+#define PTD_B5_5_MSK (1 << 13)
+ u16 faddr;
+#define PTD_FA_MSK (0x7f << 0)
+#define PTD_FMT_MSK (1 << 7)
+} __attribute__ ((packed, aligned(2)));
+
+struct isp116x_ep {
+ struct usb_device *udev;
+ struct ptd ptd;
+
+ u8 maxpacket;
+ u8 epnum;
+ u8 nextpid;
+
+ u16 length; /* of current packet */
+ unsigned char *data; /* to databuf */
+
+ u16 error_count;
+};
+
+/* URB struct */
+#define N_URB_TD 48
+#define URB_DEL 1
+typedef struct {
+ struct isp116x_ep *ed;
+ void *transfer_buffer; /* (in) associated data buffer */
+ int actual_length; /* (return) actual transfer length */
+ unsigned long pipe; /* (in) pipe information */
+#if 0
+ int state;
+#endif
+} urb_priv_t;
+
+struct isp116x_platform_data {
+ /* Enable internal resistors on downstream ports */
+ unsigned sel15Kres:1;
+ /* On-chip overcurrent detection */
+ unsigned oc_enable:1;
+ /* Enable wakeup by devices on usb bus (e.g. wakeup
+ by attachment/detachment or by device activity
+ such as moving a mouse). When chosen, this option
+ prevents stopping internal clock, increasing
+ thereby power consumption in suspended state. */
+ unsigned remote_wakeup_enable:1;
+};
+
+struct isp116x {
+ u16 *addr_reg;
+ u16 *data_reg;
+
+ struct isp116x_platform_data *board;
+
+ struct dentry *dentry;
+ unsigned long stat1, stat2, stat4, stat8, stat16;
+
+ /* Status flags */
+ unsigned disabled:1;
+ unsigned sleeping:1;
+
+ /* Root hub registers */
+ u32 rhdesca;
+ u32 rhdescb;
+ u32 rhstatus;
+ u32 rhport[2];
+
+ /* Schedule for the current frame */
+ struct isp116x_ep *atl_active;
+ int atl_buflen;
+ int atl_bufshrt;
+ int atl_last_dir;
+ int atl_finishing;
+};
+
+/* ------------------------------------------------- */
+
+/* Inter-io delay (ns). The chip is picky about access timings; it
+ * expects at least:
+ * 150ns delay between consecutive accesses to DATA_REG,
+ * 300ns delay between access to ADDR_REG and DATA_REG
+ * OE, WE MUST NOT be changed during these intervals
+ */
+#if defined(UDELAY)
+#define isp116x_delay(h,d) udelay(d)
+#else
+#define isp116x_delay(h,d) do {} while (0)
+#endif
+
+static inline void isp116x_write_addr(struct isp116x *isp116x, unsigned reg)
+{
+ writew(reg & 0xff, isp116x->addr_reg);
+ isp116x_delay(isp116x, UDELAY);
+}
+
+static inline void isp116x_write_data16(struct isp116x *isp116x, u16 val)
+{
+ writew(val, isp116x->data_reg);
+ isp116x_delay(isp116x, UDELAY);
+}
+
+static inline void isp116x_raw_write_data16(struct isp116x *isp116x, u16 val)
+{
+ __raw_writew(val, isp116x->data_reg);
+ isp116x_delay(isp116x, UDELAY);
+}
+
+static inline u16 isp116x_read_data16(struct isp116x *isp116x)
+{
+ u16 val;
+
+ val = readw(isp116x->data_reg);
+ isp116x_delay(isp116x, UDELAY);
+ return val;
+}
+
+static inline u16 isp116x_raw_read_data16(struct isp116x *isp116x)
+{
+ u16 val;
+
+ val = __raw_readw(isp116x->data_reg);
+ isp116x_delay(isp116x, UDELAY);
+ return val;
+}
+
+static inline void isp116x_write_data32(struct isp116x *isp116x, u32 val)
+{
+ writew(val & 0xffff, isp116x->data_reg);
+ isp116x_delay(isp116x, UDELAY);
+ writew(val >> 16, isp116x->data_reg);
+ isp116x_delay(isp116x, UDELAY);
+}
+
+static inline u32 isp116x_read_data32(struct isp116x *isp116x)
+{
+ u32 val;
+
+ val = (u32) readw(isp116x->data_reg);
+ isp116x_delay(isp116x, UDELAY);
+ val |= ((u32) readw(isp116x->data_reg)) << 16;
+ isp116x_delay(isp116x, UDELAY);
+ return val;
+}
+
+/* Let's keep register access functions out of line. Hint:
+ we wait at least 150 ns at every access.
+*/
+static u16 isp116x_read_reg16(struct isp116x *isp116x, unsigned reg)
+{
+ isp116x_write_addr(isp116x, reg);
+ return isp116x_read_data16(isp116x);
+}
+
+static u32 isp116x_read_reg32(struct isp116x *isp116x, unsigned reg)
+{
+ isp116x_write_addr(isp116x, reg);
+ return isp116x_read_data32(isp116x);
+}
+
+static void isp116x_write_reg16(struct isp116x *isp116x, unsigned reg,
+ unsigned val)
+{
+ isp116x_write_addr(isp116x, reg | ISP116x_WRITE_OFFSET);
+ isp116x_write_data16(isp116x, (u16) (val & 0xffff));
+}
+
+static void isp116x_write_reg32(struct isp116x *isp116x, unsigned reg,
+ unsigned val)
+{
+ isp116x_write_addr(isp116x, reg | ISP116x_WRITE_OFFSET);
+ isp116x_write_data32(isp116x, (u32) val);
+}
+
+/* --- USB HUB constants (not OHCI-specific; see hub.h) -------------------- */
+
+/* destination of request */
+#define RH_INTERFACE 0x01
+#define RH_ENDPOINT 0x02
+#define RH_OTHER 0x03
+
+#define RH_CLASS 0x20
+#define RH_VENDOR 0x40
+
+/* Requests: bRequest << 8 | bmRequestType */
+#define RH_GET_STATUS 0x0080
+#define RH_CLEAR_FEATURE 0x0100
+#define RH_SET_FEATURE 0x0300
+#define RH_SET_ADDRESS 0x0500
+#define RH_GET_DESCRIPTOR 0x0680
+#define RH_SET_DESCRIPTOR 0x0700
+#define RH_GET_CONFIGURATION 0x0880
+#define RH_SET_CONFIGURATION 0x0900
+#define RH_GET_STATE 0x0280
+#define RH_GET_INTERFACE 0x0A80
+#define RH_SET_INTERFACE 0x0B00
+#define RH_SYNC_FRAME 0x0C80
+/* Our Vendor Specific Request */
+#define RH_SET_EP 0x2000
+
+/* Hub port features */
+#define RH_PORT_CONNECTION 0x00
+#define RH_PORT_ENABLE 0x01
+#define RH_PORT_SUSPEND 0x02
+#define RH_PORT_OVER_CURRENT 0x03
+#define RH_PORT_RESET 0x04
+#define RH_PORT_POWER 0x08
+#define RH_PORT_LOW_SPEED 0x09
+
+#define RH_C_PORT_CONNECTION 0x10
+#define RH_C_PORT_ENABLE 0x11
+#define RH_C_PORT_SUSPEND 0x12
+#define RH_C_PORT_OVER_CURRENT 0x13
+#define RH_C_PORT_RESET 0x14
+
+/* Hub features */
+#define RH_C_HUB_LOCAL_POWER 0x00
+#define RH_C_HUB_OVER_CURRENT 0x01
+
+#define RH_DEVICE_REMOTE_WAKEUP 0x00
+#define RH_ENDPOINT_STALL 0x01
+
+#define RH_ACK 0x01
+#define RH_REQ_ERR -1
+#define RH_NACK 0x00
diff --git a/drivers/macb.c b/drivers/macb.c
index bf7853a..95cdc49 100644
--- a/drivers/macb.c
+++ b/drivers/macb.c
@@ -52,6 +52,8 @@
#include "macb.h"
+#define barrier() asm volatile("" ::: "memory")
+
#define CFG_MACB_RX_BUFFER_SIZE 4096
#define CFG_MACB_RX_RING_SIZE (CFG_MACB_RX_BUFFER_SIZE / 128)
#define CFG_MACB_TX_RING_SIZE 16
@@ -186,31 +188,31 @@ static int macb_send(struct eth_device *netdev, volatile void *packet,
macb->tx_ring[tx_head].ctrl = ctrl;
macb->tx_ring[tx_head].addr = paddr;
+ barrier();
macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
/*
* I guess this is necessary because the networking core may
* re-use the transmit buffer as soon as we return...
*/
- i = 0;
- while (!(macb->tx_ring[tx_head].ctrl & TXBUF_USED)) {
- if (i > CFG_MACB_TX_TIMEOUT) {
- printf("%s: TX timeout\n", netdev->name);
+ for (i = 0; i <= CFG_MACB_TX_TIMEOUT; i++) {
+ barrier();
+ ctrl = macb->tx_ring[tx_head].ctrl;
+ if (ctrl & TXBUF_USED)
break;
- }
udelay(1);
- i++;
}
dma_unmap_single(packet, length, paddr);
if (i <= CFG_MACB_TX_TIMEOUT) {
- ctrl = macb->tx_ring[tx_head].ctrl;
if (ctrl & TXBUF_UNDERRUN)
printf("%s: TX underrun\n", netdev->name);
if (ctrl & TXBUF_EXHAUSTED)
printf("%s: TX buffers exhausted in mid frame\n",
netdev->name);
+ } else {
+ printf("%s: TX timeout\n", netdev->name);
}
/* No one cares anyway */
@@ -235,6 +237,7 @@ static void reclaim_rx_buffers(struct macb_device *macb,
i++;
}
+ barrier();
macb->rx_tail = new_tail;
}
@@ -284,25 +287,17 @@ static int macb_recv(struct eth_device *netdev)
rx_tail = 0;
}
}
+ barrier();
}
return 0;
}
-static int macb_phy_init(struct macb_device *macb)
+static void macb_phy_reset(struct macb_device *macb)
{
struct eth_device *netdev = &macb->netdev;
- u32 ncfgr;
- u16 phy_id, status, adv, lpa;
- int media, speed, duplex;
int i;
-
- /* Check if the PHY is up to snuff... */
- phy_id = macb_mdio_read(macb, MII_PHYSID1);
- if (phy_id == 0xffff) {
- printf("%s: No PHY present\n", netdev->name);
- return 0;
- }
+ u16 status, adv;
adv = ADVERTISE_CSMA | ADVERTISE_ALL;
macb_mdio_write(macb, MII_ADVERTISE, adv);
@@ -310,11 +305,6 @@ static int macb_phy_init(struct macb_device *macb)
macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE
| BMCR_ANRESTART));
-#if 0
- for (i = 0; i < 9; i++)
- printf("mii%d: 0x%04x\n", i, macb_mdio_read(macb, i));
-#endif
-
for (i = 0; i < CFG_MACB_AUTONEG_TIMEOUT / 100; i++) {
status = macb_mdio_read(macb, MII_BMSR);
if (status & BMSR_ANEGCOMPLETE)
@@ -327,13 +317,33 @@ static int macb_phy_init(struct macb_device *macb)
else
printf("%s: Autonegotiation timed out (status=0x%04x)\n",
netdev->name, status);
+}
+
+static int macb_phy_init(struct macb_device *macb)
+{
+ struct eth_device *netdev = &macb->netdev;
+ u32 ncfgr;
+ u16 phy_id, status, adv, lpa;
+ int media, speed, duplex;
+ int i;
+ /* Check if the PHY is up to snuff... */
+ phy_id = macb_mdio_read(macb, MII_PHYSID1);
+ if (phy_id == 0xffff) {
+ printf("%s: No PHY present\n", netdev->name);
+ return 0;
+ }
+
+ status = macb_mdio_read(macb, MII_BMSR);
if (!(status & BMSR_LSTATUS)) {
+ /* Try to re-negotiate if we don't have link already. */
+ macb_phy_reset(macb);
+
for (i = 0; i < CFG_MACB_AUTONEG_TIMEOUT / 100; i++) {
- udelay(100);
status = macb_mdio_read(macb, MII_BMSR);
if (status & BMSR_LSTATUS)
break;
+ udelay(100);
}
}
@@ -342,6 +352,7 @@ static int macb_phy_init(struct macb_device *macb)
netdev->name, status);
return 0;
} else {
+ adv = macb_mdio_read(macb, MII_ADVERTISE);
lpa = macb_mdio_read(macb, MII_LPA);
media = mii_nway_result(lpa & adv);
speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
diff --git a/drivers/nand/nand_util.c b/drivers/nand/nand_util.c
index 88c1df6..cf05043 100644
--- a/drivers/nand/nand_util.c
+++ b/drivers/nand/nand_util.c
@@ -37,6 +37,7 @@
#include <command.h>
#include <watchdog.h>
#include <malloc.h>
+#include <div64.h>
#include <nand.h>
#include <jffs2/jffs2.h>
@@ -208,10 +209,10 @@ int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts)
}
if (!opts->quiet) {
- int percent = (int)
- ((unsigned long long)
+ unsigned long long n =(unsigned long long)
(erase.addr+meminfo->erasesize-opts->offset)
- * 100 / erase_length);
+ * 100;
+ int percent = (int)do_div(n, erase_length);
/* output progress message only at whole percent
* steps to reduce the number of messages printed
@@ -475,10 +476,9 @@ int nand_write_opts(nand_info_t *meminfo, const nand_write_options_t *opts)
imglen -= readlen;
if (!opts->quiet) {
- int percent = (int)
- ((unsigned long long)
- (opts->length-imglen) * 100
- / opts->length);
+ unsigned long long n = (unsigned long long)
+ (opts->length-imglen) * 100;
+ int percent = (int)do_div(n, opts->length);
/* output progress message only at whole percent
* steps to reduce the number of messages printed
* on (slow) serial consoles
@@ -651,10 +651,9 @@ int nand_read_opts(nand_info_t *meminfo, const nand_read_options_t *opts)
}
if (!opts->quiet) {
- int percent = (int)
- ((unsigned long long)
- (opts->length-imglen) * 100
- / opts->length);
+ unsigned long long n = (unsigned long long)
+ (opts->length-imglen) * 100;
+ int percent = (int)do_div(n ,opts->length);
/* output progress message only at whole percent
* steps to reduce the number of messages printed
* on (slow) serial consoles
diff --git a/drivers/pci_auto.c b/drivers/pci_auto.c
index a3c609b..2378553 100644
--- a/drivers/pci_auto.c
+++ b/drivers/pci_auto.c
@@ -94,7 +94,7 @@ void pciauto_setup_device(struct pci_controller *hose,
pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER;
- for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_0 + (bars_num*4); bar += 4) {
+ for (bar = PCI_BASE_ADDRESS_0; bar < PCI_BASE_ADDRESS_0 + (bars_num*4); bar += 4) {
/* Tickle the BAR and get the response */
pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
pci_hose_read_config_dword(hose, dev, bar, &bar_response);
diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index 5f20962..0f5232a 100644
--- a/drivers/qe/qe.c
+++ b/drivers/qe/qe.c
@@ -98,7 +98,7 @@ static void qe_sdma_init(void)
out_be32(&p->sdaqmr, 0);
/* Allocate 2KB temporary buffer for sdma */
- sdma_buffer_base = qe_muram_alloc(2048, 64);
+ sdma_buffer_base = qe_muram_alloc(2048, 4096);
out_be32(&p->sdwbcr, sdma_buffer_base & QE_SDEBCR_BA_MASK);
/* Clear sdma status */
diff --git a/drivers/qe/qe.h b/drivers/qe/qe.h
index 0bcd0a9..400b1a6 100644
--- a/drivers/qe/qe.h
+++ b/drivers/qe/qe.h
@@ -29,7 +29,7 @@
#define QE_NUM_OF_BRGS 16
#define UCC_MAX_NUM 8
-#define QE_DATAONLY_BASE (uint)(128)
+#define QE_DATAONLY_BASE 0
#define QE_DATAONLY_SIZE (QE_MURAM_SIZE - QE_DATAONLY_BASE)
/* QE threads SNUM
diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
index c416a67..89a7279 100644
--- a/drivers/qe/uec.c
+++ b/drivers/qe/uec.c
@@ -391,17 +391,17 @@ static int uec_set_mac_if_mode(uec_private_t *uec, enet_interface_e if_mode)
return 0;
}
-static int init_mii_management_configuration(uec_t *uec_regs)
+static int init_mii_management_configuration(uec_mii_t *uec_mii_regs)
{
uint timeout = 0x1000;
u32 miimcfg = 0;
- miimcfg = in_be32(&uec_regs->miimcfg);
+ miimcfg = in_be32(&uec_mii_regs->miimcfg);
miimcfg |= MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE;
- out_be32(&uec_regs->miimcfg, miimcfg);
+ out_be32(&uec_mii_regs->miimcfg, miimcfg);
/* Wait until the bus is free */
- while ((in_be32(&uec_regs->miimcfg) & MIIMIND_BUSY) && timeout--);
+ while ((in_be32(&uec_mii_regs->miimcfg) & MIIMIND_BUSY) && timeout--);
if (timeout <= 0) {
printf("%s: The MII Bus is stuck!", __FUNCTION__);
return -ETIMEDOUT;
@@ -413,13 +413,13 @@ static int init_mii_management_configuration(uec_t *uec_regs)
static int init_phy(struct eth_device *dev)
{
uec_private_t *uec;
- uec_t *uec_regs;
+ uec_mii_t *umii_regs;
struct uec_mii_info *mii_info;
struct phy_info *curphy;
int err;
uec = (uec_private_t *)dev->priv;
- uec_regs = uec->uec_regs;
+ umii_regs = uec->uec_mii_regs;
uec->oldlink = 0;
uec->oldspeed = 0;
@@ -451,19 +451,19 @@ static int init_phy(struct eth_device *dev)
mii_info->mii_id = uec->uec_info->phy_address;
mii_info->dev = dev;
- mii_info->mdio_read = &read_phy_reg;
- mii_info->mdio_write = &write_phy_reg;
+ mii_info->mdio_read = &uec_read_phy_reg;
+ mii_info->mdio_write = &uec_write_phy_reg;
uec->mii_info = mii_info;
- if (init_mii_management_configuration(uec_regs)) {
+ if (init_mii_management_configuration(umii_regs)) {
printf("%s: The MII Bus is stuck!", dev->name);
err = -1;
goto bus_fail;
}
/* get info for this PHY */
- curphy = get_phy_info(uec->mii_info);
+ curphy = uec_get_phy_info(uec->mii_info);
if (!curphy) {
printf("%s: No PHY found", dev->name);
err = -1;
@@ -989,6 +989,13 @@ static int uec_startup(uec_private_t *uec)
/* Setup MAC interface mode */
uec_set_mac_if_mode(uec, uec_info->enet_interface);
+ /* Setup MII management base */
+#ifndef CONFIG_eTSEC_MDIO_BUS
+ uec->uec_mii_regs = (uec_mii_t *)(&uec_regs->miimcfg);
+#else
+ uec->uec_mii_regs = (uec_mii_t *) CONFIG_MIIM_ADDRESS;
+#endif
+
/* Setup MII master clock source */
qe_set_mii_clk_src(uec_info->uf_info.ucc_num);
diff --git a/drivers/qe/uec.h b/drivers/qe/uec.h
index 0495026..c384055 100644
--- a/drivers/qe/uec.h
+++ b/drivers/qe/uec.h
@@ -675,6 +675,7 @@ typedef struct uec_private {
ucc_fast_private_t *uccf;
struct eth_device *dev;
uec_t *uec_regs;
+ uec_mii_t *uec_mii_regs;
/* enet init command parameter */
uec_init_cmd_pram_t *p_init_enet_param;
u32 init_enet_param_offset;
diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c
index 76fd388..ca6faa6 100644
--- a/drivers/qe/uec_phy.c
+++ b/drivers/qe/uec_phy.c
@@ -60,14 +60,14 @@ void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val);
/* Write value to the PHY for this device to the register at regnum, */
/* waiting until the write is done before it returns. All PHY */
/* configuration has to be done through the TSEC1 MIIM regs */
-void write_phy_reg (struct eth_device *dev, int mii_id, int regnum, int value)
+void uec_write_phy_reg (struct eth_device *dev, int mii_id, int regnum, int value)
{
uec_private_t *ugeth = (uec_private_t *) dev->priv;
- uec_t *ug_regs;
+ uec_mii_t *ug_regs;
enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum;
u32 tmp_reg;
- ug_regs = ugeth->uec_regs;
+ ug_regs = ugeth->uec_mii_regs;
/* Stop the MII management read cycle */
out_be32 (&ug_regs->miimcom, 0);
@@ -87,15 +87,15 @@ void write_phy_reg (struct eth_device *dev, int mii_id, int regnum, int value)
/* Reads from register regnum in the PHY for device dev, */
/* returning the value. Clears miimcom first. All PHY */
/* configuration has to be done through the TSEC1 MIIM regs */
-int read_phy_reg (struct eth_device *dev, int mii_id, int regnum)
+int uec_read_phy_reg (struct eth_device *dev, int mii_id, int regnum)
{
uec_private_t *ugeth = (uec_private_t *) dev->priv;
- uec_t *ug_regs;
+ uec_mii_t *ug_regs;
enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum;
u32 tmp_reg;
u16 value;
- ug_regs = ugeth->uec_regs;
+ ug_regs = ugeth->uec_mii_regs;
/* Setting up the MII Mangement Address Register */
tmp_reg = ((u32) mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg;
@@ -521,7 +521,7 @@ void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val)
/* Use the PHY ID registers to determine what type of PHY is attached
* to device dev. return a struct phy_info structure describing that PHY
*/
-struct phy_info *get_phy_info (struct uec_mii_info *mii_info)
+struct phy_info *uec_get_phy_info (struct uec_mii_info *mii_info)
{
u16 phy_reg;
u32 phy_ID;
diff --git a/drivers/qe/uec_phy.h b/drivers/qe/uec_phy.h
index 9bd926d..e59a940 100644
--- a/drivers/qe/uec_phy.h
+++ b/drivers/qe/uec_phy.h
@@ -249,10 +249,10 @@ struct phy_info {
void (*close) (struct uec_mii_info * mii_info);
};
-struct phy_info *get_phy_info (struct uec_mii_info *mii_info);
-void write_phy_reg (struct eth_device *dev, int mii_id, int regnum,
+struct phy_info *uec_get_phy_info (struct uec_mii_info *mii_info);
+void uec_write_phy_reg (struct eth_device *dev, int mii_id, int regnum,
int value);
-int read_phy_reg (struct eth_device *dev, int mii_id, int regnum);
+int uec_read_phy_reg (struct eth_device *dev, int mii_id, int regnum);
void mii_clear_phy_interrupt (struct uec_mii_info *mii_info);
void mii_configure_phy_interrupt (struct uec_mii_info *mii_info,
u32 interrupts);
diff --git a/drivers/rtl8139.c b/drivers/rtl8139.c
index 9045523..2367180 100644
--- a/drivers/rtl8139.c
+++ b/drivers/rtl8139.c
@@ -193,6 +193,12 @@ static void rtl_reset(struct eth_device *dev);
static int rtl_transmit(struct eth_device *dev, volatile void *packet, int length);
static int rtl_poll(struct eth_device *dev);
static void rtl_disable(struct eth_device *dev);
+#ifdef CONFIG_MCAST_TFTP/* This driver already accepts all b/mcast */
+static int rtl_bcast_addr (struct eth_device *dev, u8 bcast_mac, u8 set)
+{
+ return (0);
+}
+#endif
static struct pci_device_id supported[] = {
{PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139},
@@ -228,6 +234,9 @@ int rtl8139_initialize(bd_t *bis)
dev->halt = rtl_disable;
dev->send = rtl_transmit;
dev->recv = rtl_poll;
+#ifdef CONFIG_MCAST_TFTP
+ dev->mcast = rtl_bcast_addr;
+#endif
eth_register (dev);
diff --git a/drivers/tigon3.c b/drivers/tigon3.c
index 860a889..5f6a4ec 100644
--- a/drivers/tigon3.c
+++ b/drivers/tigon3.c
@@ -26,69 +26,70 @@
/* Local functions. */
/******************************************************************************/
-LM_STATUS LM_Abort(PLM_DEVICE_BLOCK pDevice);
-LM_STATUS LM_QueueRxPackets(PLM_DEVICE_BLOCK pDevice);
-
-static LM_STATUS LM_TranslateRequestedMediaType(
- LM_REQUESTED_MEDIA_TYPE RequestedMediaType,
- PLM_MEDIA_TYPE pMediaType, PLM_LINE_SPEED pLineSpeed,
- PLM_DUPLEX_MODE pDuplexMode);
-
-static LM_STATUS LM_InitBcm540xPhy(PLM_DEVICE_BLOCK pDevice);
-
-__inline static LM_VOID LM_ServiceRxInterrupt(PLM_DEVICE_BLOCK pDevice);
-__inline static LM_VOID LM_ServiceTxInterrupt(PLM_DEVICE_BLOCK pDevice);
-
-static LM_STATUS LM_ForceAutoNegBcm540xPhy(PLM_DEVICE_BLOCK pDevice,
- LM_REQUESTED_MEDIA_TYPE RequestedMediaType);
-static LM_STATUS LM_ForceAutoNeg(PLM_DEVICE_BLOCK pDevice,
- LM_REQUESTED_MEDIA_TYPE RequestedMediaType);
-static LM_UINT32 GetPhyAdFlowCntrlSettings(PLM_DEVICE_BLOCK pDevice);
-STATIC LM_STATUS LM_SetFlowControl(PLM_DEVICE_BLOCK pDevice,
- LM_UINT32 LocalPhyAd, LM_UINT32 RemotePhyAd);
+LM_STATUS LM_Abort (PLM_DEVICE_BLOCK pDevice);
+LM_STATUS LM_QueueRxPackets (PLM_DEVICE_BLOCK pDevice);
+
+static LM_STATUS LM_TranslateRequestedMediaType (LM_REQUESTED_MEDIA_TYPE
+ RequestedMediaType,
+ PLM_MEDIA_TYPE pMediaType,
+ PLM_LINE_SPEED pLineSpeed,
+ PLM_DUPLEX_MODE pDuplexMode);
+
+static LM_STATUS LM_InitBcm540xPhy (PLM_DEVICE_BLOCK pDevice);
+
+__inline static LM_VOID LM_ServiceRxInterrupt (PLM_DEVICE_BLOCK pDevice);
+__inline static LM_VOID LM_ServiceTxInterrupt (PLM_DEVICE_BLOCK pDevice);
+
+static LM_STATUS LM_ForceAutoNegBcm540xPhy (PLM_DEVICE_BLOCK pDevice,
+ LM_REQUESTED_MEDIA_TYPE
+ RequestedMediaType);
+static LM_STATUS LM_ForceAutoNeg (PLM_DEVICE_BLOCK pDevice,
+ LM_REQUESTED_MEDIA_TYPE RequestedMediaType);
+static LM_UINT32 GetPhyAdFlowCntrlSettings (PLM_DEVICE_BLOCK pDevice);
+STATIC LM_STATUS LM_SetFlowControl (PLM_DEVICE_BLOCK pDevice,
+ LM_UINT32 LocalPhyAd,
+ LM_UINT32 RemotePhyAd);
#if INCLUDE_TBI_SUPPORT
-STATIC LM_STATUS LM_SetupFiberPhy(PLM_DEVICE_BLOCK pDevice);
-STATIC LM_STATUS LM_InitBcm800xPhy(PLM_DEVICE_BLOCK pDevice);
+STATIC LM_STATUS LM_SetupFiberPhy (PLM_DEVICE_BLOCK pDevice);
+STATIC LM_STATUS LM_InitBcm800xPhy (PLM_DEVICE_BLOCK pDevice);
#endif
-STATIC LM_STATUS LM_SetupCopperPhy(PLM_DEVICE_BLOCK pDevice);
-STATIC PLM_ADAPTER_INFO LM_GetAdapterInfoBySsid(LM_UINT16 Svid, LM_UINT16 Ssid);
-STATIC LM_STATUS LM_DmaTest(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pBufferVirt,
- LM_PHYSICAL_ADDRESS BufferPhy, LM_UINT32 BufferSize);
-STATIC LM_STATUS LM_HaltCpu(PLM_DEVICE_BLOCK pDevice,LM_UINT32 cpu_number);
-STATIC LM_STATUS LM_ResetChip(PLM_DEVICE_BLOCK pDevice);
-STATIC LM_STATUS LM_Test4GBoundary(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket,
- PT3_SND_BD pSendBd);
+STATIC LM_STATUS LM_SetupCopperPhy (PLM_DEVICE_BLOCK pDevice);
+STATIC PLM_ADAPTER_INFO LM_GetAdapterInfoBySsid (LM_UINT16 Svid,
+ LM_UINT16 Ssid);
+STATIC LM_STATUS LM_DmaTest (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pBufferVirt,
+ LM_PHYSICAL_ADDRESS BufferPhy,
+ LM_UINT32 BufferSize);
+STATIC LM_STATUS LM_HaltCpu (PLM_DEVICE_BLOCK pDevice, LM_UINT32 cpu_number);
+STATIC LM_STATUS LM_ResetChip (PLM_DEVICE_BLOCK pDevice);
+STATIC LM_STATUS LM_Test4GBoundary (PLM_DEVICE_BLOCK pDevice,
+ PLM_PACKET pPacket, PT3_SND_BD pSendBd);
/******************************************************************************/
/* External functions. */
/******************************************************************************/
-LM_STATUS LM_LoadRlsFirmware(PLM_DEVICE_BLOCK pDevice);
-
+LM_STATUS LM_LoadRlsFirmware (PLM_DEVICE_BLOCK pDevice);
/******************************************************************************/
/* Description: */
/* */
/* Return: */
/******************************************************************************/
-LM_UINT32
-LM_RegRdInd(
-PLM_DEVICE_BLOCK pDevice,
-LM_UINT32 Register) {
- LM_UINT32 Value32;
+LM_UINT32 LM_RegRdInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register)
+{
+ LM_UINT32 Value32;
#if PCIX_TARGET_WORKAROUND
- MM_ACQUIRE_UNDI_LOCK(pDevice);
+ MM_ACQUIRE_UNDI_LOCK (pDevice);
#endif
- MM_WriteConfig32(pDevice, T3_PCI_REG_ADDR_REG, Register);
- MM_ReadConfig32(pDevice, T3_PCI_REG_DATA_REG, &Value32);
+ MM_WriteConfig32 (pDevice, T3_PCI_REG_ADDR_REG, Register);
+ MM_ReadConfig32 (pDevice, T3_PCI_REG_DATA_REG, &Value32);
#if PCIX_TARGET_WORKAROUND
- MM_RELEASE_UNDI_LOCK(pDevice);
+ MM_RELEASE_UNDI_LOCK (pDevice);
#endif
- return Value32;
-} /* LM_RegRdInd */
-
+ return Value32;
+} /* LM_RegRdInd */
/******************************************************************************/
/* Description: */
@@ -96,47 +97,41 @@ LM_UINT32 Register) {
/* Return: */
/******************************************************************************/
LM_VOID
-LM_RegWrInd(
-PLM_DEVICE_BLOCK pDevice,
-LM_UINT32 Register,
-LM_UINT32 Value32) {
+LM_RegWrInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register, LM_UINT32 Value32)
+{
#if PCIX_TARGET_WORKAROUND
- MM_ACQUIRE_UNDI_LOCK(pDevice);
+ MM_ACQUIRE_UNDI_LOCK (pDevice);
#endif
- MM_WriteConfig32(pDevice, T3_PCI_REG_ADDR_REG, Register);
- MM_WriteConfig32(pDevice, T3_PCI_REG_DATA_REG, Value32);
+ MM_WriteConfig32 (pDevice, T3_PCI_REG_ADDR_REG, Register);
+ MM_WriteConfig32 (pDevice, T3_PCI_REG_DATA_REG, Value32);
#if PCIX_TARGET_WORKAROUND
- MM_RELEASE_UNDI_LOCK(pDevice);
+ MM_RELEASE_UNDI_LOCK (pDevice);
#endif
-} /* LM_RegWrInd */
-
+} /* LM_RegWrInd */
/******************************************************************************/
/* Description: */
/* */
/* Return: */
/******************************************************************************/
-LM_UINT32
-LM_MemRdInd(
-PLM_DEVICE_BLOCK pDevice,
-LM_UINT32 MemAddr) {
- LM_UINT32 Value32;
+LM_UINT32 LM_MemRdInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr)
+{
+ LM_UINT32 Value32;
- MM_ACQUIRE_UNDI_LOCK(pDevice);
+ MM_ACQUIRE_UNDI_LOCK (pDevice);
#ifdef BIG_ENDIAN_HOST
- MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_ADDR_REG, MemAddr);
- Value32 = REG_RD(pDevice, PciCfg.MemWindowData);
- /* Value32 = REG_RD(pDevice,uIntMem.Mbuf[(MemAddr & 0x7fff)/4]); */
+ MM_WriteConfig32 (pDevice, T3_PCI_MEM_WIN_ADDR_REG, MemAddr);
+ Value32 = REG_RD (pDevice, PciCfg.MemWindowData);
+ /* Value32 = REG_RD(pDevice,uIntMem.Mbuf[(MemAddr & 0x7fff)/4]); */
#else
- MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_ADDR_REG, MemAddr);
- MM_ReadConfig32(pDevice, T3_PCI_MEM_WIN_DATA_REG, &Value32);
+ MM_WriteConfig32 (pDevice, T3_PCI_MEM_WIN_ADDR_REG, MemAddr);
+ MM_ReadConfig32 (pDevice, T3_PCI_MEM_WIN_DATA_REG, &Value32);
#endif
- MM_RELEASE_UNDI_LOCK(pDevice);
-
- return Value32;
-} /* LM_MemRdInd */
+ MM_RELEASE_UNDI_LOCK (pDevice);
+ return Value32;
+} /* LM_MemRdInd */
/******************************************************************************/
/* Description: */
@@ -144,168 +139,161 @@ LM_UINT32 MemAddr) {
/* Return: */
/******************************************************************************/
LM_VOID
-LM_MemWrInd(
-PLM_DEVICE_BLOCK pDevice,
-LM_UINT32 MemAddr,
-LM_UINT32 Value32) {
- MM_ACQUIRE_UNDI_LOCK(pDevice);
+LM_MemWrInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr, LM_UINT32 Value32)
+{
+ MM_ACQUIRE_UNDI_LOCK (pDevice);
#ifdef BIG_ENDIAN_HOST
- REG_WR(pDevice,PciCfg.MemWindowBaseAddr,MemAddr);
- REG_WR(pDevice,uIntMem.Mbuf[(MemAddr & 0x7fff)/4],Value32);
+ REG_WR (pDevice, PciCfg.MemWindowBaseAddr, MemAddr);
+ REG_WR (pDevice, uIntMem.Mbuf[(MemAddr & 0x7fff) / 4], Value32);
#else
- MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_ADDR_REG, MemAddr);
- MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_DATA_REG, Value32);
+ MM_WriteConfig32 (pDevice, T3_PCI_MEM_WIN_ADDR_REG, MemAddr);
+ MM_WriteConfig32 (pDevice, T3_PCI_MEM_WIN_DATA_REG, Value32);
#endif
- MM_RELEASE_UNDI_LOCK(pDevice);
-} /* LM_MemWrInd */
-
+ MM_RELEASE_UNDI_LOCK (pDevice);
+} /* LM_MemWrInd */
/******************************************************************************/
/* Description: */
/* */
/* Return: */
/******************************************************************************/
-LM_STATUS
-LM_QueueRxPackets(
-PLM_DEVICE_BLOCK pDevice) {
- LM_STATUS Lmstatus;
- PLM_PACKET pPacket;
- PT3_RCV_BD pRcvBd;
- LM_UINT32 StdBdAdded = 0;
+LM_STATUS LM_QueueRxPackets (PLM_DEVICE_BLOCK pDevice)
+{
+ LM_STATUS Lmstatus;
+ PLM_PACKET pPacket;
+ PT3_RCV_BD pRcvBd;
+ LM_UINT32 StdBdAdded = 0;
#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
- LM_UINT32 JumboBdAdded = 0;
-#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
+ LM_UINT32 JumboBdAdded = 0;
+#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
- Lmstatus = LM_STATUS_SUCCESS;
+ Lmstatus = LM_STATUS_SUCCESS;
- pPacket = (PLM_PACKET) QQ_PopHead(&pDevice->RxPacketFreeQ.Container);
- while(pPacket) {
- switch(pPacket->u.Rx.RcvProdRing) {
+ pPacket = (PLM_PACKET) QQ_PopHead (&pDevice->RxPacketFreeQ.Container);
+ while (pPacket) {
+ switch (pPacket->u.Rx.RcvProdRing) {
#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
- case T3_JUMBO_RCV_PROD_RING: /* Jumbo Receive Ring. */
- /* Initialize the buffer descriptor. */
- pRcvBd =
- &pDevice->pRxJumboBdVirt[pDevice->RxJumboProdIdx];
- pRcvBd->Flags = RCV_BD_FLAG_END | RCV_BD_FLAG_JUMBO_RING;
- pRcvBd->Len = (LM_UINT16) pDevice->RxJumboBufferSize;
-
- /* Initialize the receive buffer pointer */
-#if 0 /* Jimmy, deleted in new */
- pRcvBd->HostAddr.Low = pPacket->u.Rx.RxBufferPhy.Low;
- pRcvBd->HostAddr.High = pPacket->u.Rx.RxBufferPhy.High;
+ case T3_JUMBO_RCV_PROD_RING: /* Jumbo Receive Ring. */
+ /* Initialize the buffer descriptor. */
+ pRcvBd =
+ &pDevice->pRxJumboBdVirt[pDevice->RxJumboProdIdx];
+ pRcvBd->Flags =
+ RCV_BD_FLAG_END | RCV_BD_FLAG_JUMBO_RING;
+ pRcvBd->Len = (LM_UINT16) pDevice->RxJumboBufferSize;
+
+ /* Initialize the receive buffer pointer */
+#if 0 /* Jimmy, deleted in new */
+ pRcvBd->HostAddr.Low = pPacket->u.Rx.RxBufferPhy.Low;
+ pRcvBd->HostAddr.High = pPacket->u.Rx.RxBufferPhy.High;
#endif
- MM_MapRxDma(pDevice, pPacket, &pRcvBd->HostAddr);
+ MM_MapRxDma (pDevice, pPacket, &pRcvBd->HostAddr);
- /* The opaque field may point to an offset from a fix addr. */
- pRcvBd->Opaque = (LM_UINT32) (MM_UINT_PTR(pPacket) -
- MM_UINT_PTR(pDevice->pPacketDescBase));
+ /* The opaque field may point to an offset from a fix addr. */
+ pRcvBd->Opaque = (LM_UINT32) (MM_UINT_PTR (pPacket) -
+ MM_UINT_PTR (pDevice->
+ pPacketDescBase));
- /* Update the producer index. */
- pDevice->RxJumboProdIdx = (pDevice->RxJumboProdIdx + 1) &
- T3_JUMBO_RCV_RCB_ENTRY_COUNT_MASK;
+ /* Update the producer index. */
+ pDevice->RxJumboProdIdx =
+ (pDevice->RxJumboProdIdx +
+ 1) & T3_JUMBO_RCV_RCB_ENTRY_COUNT_MASK;
- JumboBdAdded++;
- break;
-#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
-
- case T3_STD_RCV_PROD_RING: /* Standard Receive Ring. */
- /* Initialize the buffer descriptor. */
- pRcvBd = &pDevice->pRxStdBdVirt[pDevice->RxStdProdIdx];
- pRcvBd->Flags = RCV_BD_FLAG_END;
- pRcvBd->Len = MAX_STD_RCV_BUFFER_SIZE;
-
- /* Initialize the receive buffer pointer */
-#if 0 /* Jimmy, deleted in new replaced with MM_MapRxDma */
- pRcvBd->HostAddr.Low = pPacket->u.Rx.RxBufferPhy.Low;
- pRcvBd->HostAddr.High = pPacket->u.Rx.RxBufferPhy.High;
+ JumboBdAdded++;
+ break;
+#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
+
+ case T3_STD_RCV_PROD_RING: /* Standard Receive Ring. */
+ /* Initialize the buffer descriptor. */
+ pRcvBd = &pDevice->pRxStdBdVirt[pDevice->RxStdProdIdx];
+ pRcvBd->Flags = RCV_BD_FLAG_END;
+ pRcvBd->Len = MAX_STD_RCV_BUFFER_SIZE;
+
+ /* Initialize the receive buffer pointer */
+#if 0 /* Jimmy, deleted in new replaced with MM_MapRxDma */
+ pRcvBd->HostAddr.Low = pPacket->u.Rx.RxBufferPhy.Low;
+ pRcvBd->HostAddr.High = pPacket->u.Rx.RxBufferPhy.High;
#endif
- MM_MapRxDma(pDevice, pPacket, &pRcvBd->HostAddr);
+ MM_MapRxDma (pDevice, pPacket, &pRcvBd->HostAddr);
- /* The opaque field may point to an offset from a fix addr. */
- pRcvBd->Opaque = (LM_UINT32) (MM_UINT_PTR(pPacket) -
- MM_UINT_PTR(pDevice->pPacketDescBase));
+ /* The opaque field may point to an offset from a fix addr. */
+ pRcvBd->Opaque = (LM_UINT32) (MM_UINT_PTR (pPacket) -
+ MM_UINT_PTR (pDevice->
+ pPacketDescBase));
- /* Update the producer index. */
- pDevice->RxStdProdIdx = (pDevice->RxStdProdIdx + 1) &
- T3_STD_RCV_RCB_ENTRY_COUNT_MASK;
+ /* Update the producer index. */
+ pDevice->RxStdProdIdx = (pDevice->RxStdProdIdx + 1) &
+ T3_STD_RCV_RCB_ENTRY_COUNT_MASK;
- StdBdAdded++;
- break;
+ StdBdAdded++;
+ break;
- case T3_UNKNOWN_RCV_PROD_RING:
- default:
- Lmstatus = LM_STATUS_FAILURE;
- break;
- } /* switch */
+ case T3_UNKNOWN_RCV_PROD_RING:
+ default:
+ Lmstatus = LM_STATUS_FAILURE;
+ break;
+ } /* switch */
- /* Bail out if there is any error. */
- if(Lmstatus != LM_STATUS_SUCCESS)
- {
- break;
- }
+ /* Bail out if there is any error. */
+ if (Lmstatus != LM_STATUS_SUCCESS) {
+ break;
+ }
- pPacket = (PLM_PACKET) QQ_PopHead(&pDevice->RxPacketFreeQ.Container);
- } /* while */
+ pPacket =
+ (PLM_PACKET) QQ_PopHead (&pDevice->RxPacketFreeQ.Container);
+ } /* while */
- wmb();
- /* Update the procedure index. */
- if(StdBdAdded)
- {
- MB_REG_WR(pDevice, Mailbox.RcvStdProdIdx.Low, pDevice->RxStdProdIdx);
- }
+ wmb ();
+ /* Update the procedure index. */
+ if (StdBdAdded) {
+ MB_REG_WR (pDevice, Mailbox.RcvStdProdIdx.Low,
+ pDevice->RxStdProdIdx);
+ }
#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
- if(JumboBdAdded)
- {
- MB_REG_WR(pDevice, Mailbox.RcvJumboProdIdx.Low,
- pDevice->RxJumboProdIdx);
- }
-#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
-
- return Lmstatus;
-} /* LM_QueueRxPackets */
+ if (JumboBdAdded) {
+ MB_REG_WR (pDevice, Mailbox.RcvJumboProdIdx.Low,
+ pDevice->RxJumboProdIdx);
+ }
+#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
+ return Lmstatus;
+} /* LM_QueueRxPackets */
/******************************************************************************/
/* Description: */
/* */
/* Return: */
/******************************************************************************/
-STATIC LM_VOID
-LM_NvramInit(
- PLM_DEVICE_BLOCK pDevice)
+STATIC LM_VOID LM_NvramInit (PLM_DEVICE_BLOCK pDevice)
{
- LM_UINT32 Value32;
- LM_UINT32 j;
-
- /* Intialize clock period and state machine. */
- Value32 = SEEPROM_ADDR_CLK_PERD(SEEPROM_CLOCK_PERIOD) |
- SEEPROM_ADDR_FSM_RESET;
- REG_WR(pDevice, Grc.EepromAddr, Value32);
-
- for(j = 0; j < 100; j++)
- {
- MM_Wait(10);
- }
-
- /* Serial eeprom access using the Grc.EepromAddr/EepromData registers. */
- Value32 = REG_RD(pDevice, Grc.LocalCtrl);
- REG_WR(pDevice, Grc.LocalCtrl, Value32 | GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM);
-
- /* Set the 5701 compatibility mode if we are using EEPROM. */
- if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700 &&
- T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701)
- {
- Value32 = REG_RD(pDevice, Nvram.Config1);
- if((Value32 & FLASH_INTERFACE_ENABLE) == 0)
- {
- /* Use the new interface to read EEPROM. */
- Value32 &= ~FLASH_COMPAT_BYPASS;
+ LM_UINT32 Value32;
+ LM_UINT32 j;
+
+ /* Intialize clock period and state machine. */
+ Value32 = SEEPROM_ADDR_CLK_PERD (SEEPROM_CLOCK_PERIOD) |
+ SEEPROM_ADDR_FSM_RESET;
+ REG_WR (pDevice, Grc.EepromAddr, Value32);
- REG_WR(pDevice, Nvram.Config1, Value32);
+ for (j = 0; j < 100; j++) {
+ MM_Wait (10);
}
- }
-} /* LM_NvRamInit */
+ /* Serial eeprom access using the Grc.EepromAddr/EepromData registers. */
+ Value32 = REG_RD (pDevice, Grc.LocalCtrl);
+ REG_WR (pDevice, Grc.LocalCtrl,
+ Value32 | GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM);
+
+ /* Set the 5701 compatibility mode if we are using EEPROM. */
+ if (T3_ASIC_REV (pDevice->ChipRevId) != T3_ASIC_REV_5700 &&
+ T3_ASIC_REV (pDevice->ChipRevId) != T3_ASIC_REV_5701) {
+ Value32 = REG_RD (pDevice, Nvram.Config1);
+ if ((Value32 & FLASH_INTERFACE_ENABLE) == 0) {
+ /* Use the new interface to read EEPROM. */
+ Value32 &= ~FLASH_COMPAT_BYPASS;
+
+ REG_WR (pDevice, Nvram.Config1, Value32);
+ }
+ }
+} /* LM_NvRamInit */
/******************************************************************************/
/* Description: */
@@ -313,51 +301,44 @@ LM_NvramInit(
/* Return: */
/******************************************************************************/
STATIC LM_STATUS
-LM_EepromRead(
- PLM_DEVICE_BLOCK pDevice,
- LM_UINT32 Offset,
- LM_UINT32 *pData)
+LM_EepromRead (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, LM_UINT32 * pData)
{
- LM_UINT32 Value32;
- LM_UINT32 Addr;
- LM_UINT32 Dev;
- LM_UINT32 j;
+ LM_UINT32 Value32;
+ LM_UINT32 Addr;
+ LM_UINT32 Dev;
+ LM_UINT32 j;
- if(Offset > SEEPROM_CHIP_SIZE)
- {
- return LM_STATUS_FAILURE;
- }
+ if (Offset > SEEPROM_CHIP_SIZE) {
+ return LM_STATUS_FAILURE;
+ }
- Dev = Offset / SEEPROM_CHIP_SIZE;
- Addr = Offset % SEEPROM_CHIP_SIZE;
+ Dev = Offset / SEEPROM_CHIP_SIZE;
+ Addr = Offset % SEEPROM_CHIP_SIZE;
- Value32 = REG_RD(pDevice, Grc.EepromAddr);
- Value32 &= ~(SEEPROM_ADDR_ADDRESS_MASK | SEEPROM_ADDR_DEV_ID_MASK |
- SEEPROM_ADDR_RW_MASK);
- REG_WR(pDevice, Grc.EepromAddr, Value32 | SEEPROM_ADDR_DEV_ID(Dev) |
- SEEPROM_ADDR_ADDRESS(Addr) | SEEPROM_ADDR_START | SEEPROM_ADDR_READ);
+ Value32 = REG_RD (pDevice, Grc.EepromAddr);
+ Value32 &= ~(SEEPROM_ADDR_ADDRESS_MASK | SEEPROM_ADDR_DEV_ID_MASK |
+ SEEPROM_ADDR_RW_MASK);
+ REG_WR (pDevice, Grc.EepromAddr, Value32 | SEEPROM_ADDR_DEV_ID (Dev) |
+ SEEPROM_ADDR_ADDRESS (Addr) | SEEPROM_ADDR_START |
+ SEEPROM_ADDR_READ);
- for(j = 0; j < 1000; j++)
- {
- Value32 = REG_RD(pDevice, Grc.EepromAddr);
- if(Value32 & SEEPROM_ADDR_COMPLETE)
- {
- break;
+ for (j = 0; j < 1000; j++) {
+ Value32 = REG_RD (pDevice, Grc.EepromAddr);
+ if (Value32 & SEEPROM_ADDR_COMPLETE) {
+ break;
+ }
+ MM_Wait (10);
}
- MM_Wait(10);
- }
-
- if(Value32 & SEEPROM_ADDR_COMPLETE)
- {
- Value32 = REG_RD(pDevice, Grc.EepromData);
- *pData = Value32;
- return LM_STATUS_SUCCESS;
- }
+ if (Value32 & SEEPROM_ADDR_COMPLETE) {
+ Value32 = REG_RD (pDevice, Grc.EepromData);
+ *pData = Value32;
- return LM_STATUS_FAILURE;
-} /* LM_EepromRead */
+ return LM_STATUS_SUCCESS;
+ }
+ return LM_STATUS_FAILURE;
+} /* LM_EepromRead */
/******************************************************************************/
/* Description: */
@@ -365,291 +346,248 @@ LM_EepromRead(
/* Return: */
/******************************************************************************/
STATIC LM_STATUS
-LM_NvramRead(
- PLM_DEVICE_BLOCK pDevice,
- LM_UINT32 Offset,
- LM_UINT32 *pData)
+LM_NvramRead (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, LM_UINT32 * pData)
{
- LM_UINT32 Value32;
- LM_STATUS Status;
- LM_UINT32 j;
-
- if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
- T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)
- {
- Status = LM_EepromRead(pDevice, Offset, pData);
- }
- else
- {
- /* Determine if we have flash or EEPROM. */
- Value32 = REG_RD(pDevice, Nvram.Config1);
- if(Value32 & FLASH_INTERFACE_ENABLE)
- {
- if(Value32 & FLASH_SSRAM_BUFFERRED_MODE)
- {
- Offset = ((Offset/BUFFERED_FLASH_PAGE_SIZE) <<
- BUFFERED_FLASH_PAGE_POS) +
- (Offset % BUFFERED_FLASH_PAGE_SIZE);
- }
- }
+ LM_UINT32 Value32;
+ LM_STATUS Status;
+ LM_UINT32 j;
+
+ if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
+ T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
+ Status = LM_EepromRead (pDevice, Offset, pData);
+ } else {
+ /* Determine if we have flash or EEPROM. */
+ Value32 = REG_RD (pDevice, Nvram.Config1);
+ if (Value32 & FLASH_INTERFACE_ENABLE) {
+ if (Value32 & FLASH_SSRAM_BUFFERRED_MODE) {
+ Offset = ((Offset / BUFFERED_FLASH_PAGE_SIZE) <<
+ BUFFERED_FLASH_PAGE_POS) +
+ (Offset % BUFFERED_FLASH_PAGE_SIZE);
+ }
+ }
- REG_WR(pDevice, Nvram.SwArb, SW_ARB_REQ_SET1);
- for (j = 0; j < 1000; j++)
- {
- if (REG_RD(pDevice, Nvram.SwArb) & SW_ARB_GNT1)
- {
- break;
- }
- MM_Wait(20);
- }
- if (j == 1000)
- {
- return LM_STATUS_FAILURE;
- }
+ REG_WR (pDevice, Nvram.SwArb, SW_ARB_REQ_SET1);
+ for (j = 0; j < 1000; j++) {
+ if (REG_RD (pDevice, Nvram.SwArb) & SW_ARB_GNT1) {
+ break;
+ }
+ MM_Wait (20);
+ }
+ if (j == 1000) {
+ return LM_STATUS_FAILURE;
+ }
- /* Read from flash or EEPROM with the new 5703/02 interface. */
- REG_WR(pDevice, Nvram.Addr, Offset & NVRAM_ADDRESS_MASK);
+ /* Read from flash or EEPROM with the new 5703/02 interface. */
+ REG_WR (pDevice, Nvram.Addr, Offset & NVRAM_ADDRESS_MASK);
- REG_WR(pDevice, Nvram.Cmd, NVRAM_CMD_RD | NVRAM_CMD_DO_IT |
- NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
+ REG_WR (pDevice, Nvram.Cmd, NVRAM_CMD_RD | NVRAM_CMD_DO_IT |
+ NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
- /* Wait for the done bit to clear. */
- for(j = 0; j < 500; j++)
- {
- MM_Wait(10);
+ /* Wait for the done bit to clear. */
+ for (j = 0; j < 500; j++) {
+ MM_Wait (10);
- Value32 = REG_RD(pDevice, Nvram.Cmd);
- if(!(Value32 & NVRAM_CMD_DONE))
- {
- break;
- }
- }
+ Value32 = REG_RD (pDevice, Nvram.Cmd);
+ if (!(Value32 & NVRAM_CMD_DONE)) {
+ break;
+ }
+ }
- /* Wait for the done bit. */
- if(!(Value32 & NVRAM_CMD_DONE))
- {
- for(j = 0; j < 500; j++)
- {
- MM_Wait(10);
+ /* Wait for the done bit. */
+ if (!(Value32 & NVRAM_CMD_DONE)) {
+ for (j = 0; j < 500; j++) {
+ MM_Wait (10);
- Value32 = REG_RD(pDevice, Nvram.Cmd);
- if(Value32 & NVRAM_CMD_DONE)
- {
- MM_Wait(10);
+ Value32 = REG_RD (pDevice, Nvram.Cmd);
+ if (Value32 & NVRAM_CMD_DONE) {
+ MM_Wait (10);
- *pData = REG_RD(pDevice, Nvram.ReadData);
+ *pData =
+ REG_RD (pDevice, Nvram.ReadData);
- /* Change the endianess. */
- *pData = ((*pData & 0xff) << 24)| ((*pData & 0xff00) << 8)|
- ((*pData & 0xff0000) >> 8) | ((*pData >> 24) & 0xff);
+ /* Change the endianess. */
+ *pData =
+ ((*pData & 0xff) << 24) |
+ ((*pData & 0xff00) << 8) |
+ ((*pData & 0xff0000) >> 8) |
+ ((*pData >> 24) & 0xff);
- break;
+ break;
+ }
+ }
}
- }
- }
- REG_WR(pDevice, Nvram.SwArb, SW_ARB_REQ_CLR1);
- if(Value32 & NVRAM_CMD_DONE)
- {
- Status = LM_STATUS_SUCCESS;
- }
- else
- {
- Status = LM_STATUS_FAILURE;
+ REG_WR (pDevice, Nvram.SwArb, SW_ARB_REQ_CLR1);
+ if (Value32 & NVRAM_CMD_DONE) {
+ Status = LM_STATUS_SUCCESS;
+ } else {
+ Status = LM_STATUS_FAILURE;
+ }
}
- }
-
- return Status;
-} /* LM_NvramRead */
+ return Status;
+} /* LM_NvramRead */
-STATIC void
-LM_ReadVPD(PLM_DEVICE_BLOCK pDevice)
+STATIC void LM_ReadVPD (PLM_DEVICE_BLOCK pDevice)
{
- LM_UINT32 Vpd_arr[256/4];
- LM_UINT8 *Vpd = (LM_UINT8 *) &Vpd_arr[0];
- LM_UINT32 *Vpd_dptr = &Vpd_arr[0];
- LM_UINT32 Value32;
- unsigned int j;
-
- /* Read PN from VPD */
- for (j = 0; j < 256; j += 4, Vpd_dptr++ )
- {
- if (LM_NvramRead(pDevice, 0x100 + j, &Value32) != LM_STATUS_SUCCESS) {
- printf("BCM570x: LM_ReadVPD: VPD read failed"
- " (no EEPROM onboard)\n");
- return;
- }
- *Vpd_dptr = cpu_to_le32(Value32);
- }
- for (j = 0; j < 256; )
- {
- unsigned int Vpd_r_len;
- unsigned int Vpd_r_end;
-
- if ((Vpd[j] == 0x82) || (Vpd[j] == 0x91))
- {
- j = j + 3 + Vpd[j + 1] + (Vpd[j + 2] << 8);
- }
- else if (Vpd[j] == 0x90)
- {
- Vpd_r_len = Vpd[j + 1] + (Vpd[j + 2] << 8);
- j += 3;
- Vpd_r_end = Vpd_r_len + j;
- while (j < Vpd_r_end)
- {
- if ((Vpd[j] == 'P') && (Vpd[j + 1] == 'N'))
- {
- unsigned int len = Vpd[j + 2];
-
- if (len <= 24)
- {
- memcpy(pDevice->PartNo, &Vpd[j + 3], len);
- }
- break;
+ LM_UINT32 Vpd_arr[256 / 4];
+ LM_UINT8 *Vpd = (LM_UINT8 *) & Vpd_arr[0];
+ LM_UINT32 *Vpd_dptr = &Vpd_arr[0];
+ LM_UINT32 Value32;
+ unsigned int j;
+
+ /* Read PN from VPD */
+ for (j = 0; j < 256; j += 4, Vpd_dptr++) {
+ if (LM_NvramRead (pDevice, 0x100 + j, &Value32) !=
+ LM_STATUS_SUCCESS) {
+ printf ("BCM570x: LM_ReadVPD: VPD read failed"
+ " (no EEPROM onboard)\n");
+ return;
}
- else
- {
- if (Vpd[j + 2] == 0)
- {
+ *Vpd_dptr = cpu_to_le32 (Value32);
+ }
+ for (j = 0; j < 256;) {
+ unsigned int Vpd_r_len;
+ unsigned int Vpd_r_end;
+
+ if ((Vpd[j] == 0x82) || (Vpd[j] == 0x91)) {
+ j = j + 3 + Vpd[j + 1] + (Vpd[j + 2] << 8);
+ } else if (Vpd[j] == 0x90) {
+ Vpd_r_len = Vpd[j + 1] + (Vpd[j + 2] << 8);
+ j += 3;
+ Vpd_r_end = Vpd_r_len + j;
+ while (j < Vpd_r_end) {
+ if ((Vpd[j] == 'P') && (Vpd[j + 1] == 'N')) {
+ unsigned int len = Vpd[j + 2];
+
+ if (len <= 24) {
+ memcpy (pDevice->PartNo,
+ &Vpd[j + 3], len);
+ }
+ break;
+ } else {
+ if (Vpd[j + 2] == 0) {
+ break;
+ }
+ j = j + Vpd[j + 2];
+ }
+ }
+ break;
+ } else {
break;
- }
- j = j + Vpd[j + 2];
}
- }
- break;
- }
- else {
- break;
}
- }
}
-STATIC void
-LM_ReadBootCodeVersion(PLM_DEVICE_BLOCK pDevice)
+STATIC void LM_ReadBootCodeVersion (PLM_DEVICE_BLOCK pDevice)
{
- LM_UINT32 Value32, offset, ver_offset;
- int i;
-
- if (LM_NvramRead(pDevice, 0x0, &Value32) != LM_STATUS_SUCCESS)
- return;
- if (Value32 != 0xaa559966)
- return;
- if (LM_NvramRead(pDevice, 0xc, &offset) != LM_STATUS_SUCCESS)
- return;
-
- offset = ((offset & 0xff) << 24)| ((offset & 0xff00) << 8)|
- ((offset & 0xff0000) >> 8) | ((offset >> 24) & 0xff);
- if (LM_NvramRead(pDevice, offset, &Value32) != LM_STATUS_SUCCESS)
- return;
- if ((Value32 == 0x0300000e) &&
- (LM_NvramRead(pDevice, offset + 4, &Value32) == LM_STATUS_SUCCESS) &&
- (Value32 == 0)) {
-
- if (LM_NvramRead(pDevice, offset + 8, &ver_offset) != LM_STATUS_SUCCESS)
- return;
- ver_offset = ((ver_offset & 0xff0000) >> 8) |
- ((ver_offset >> 24) & 0xff);
- for (i = 0; i < 16; i += 4) {
- if (LM_NvramRead(pDevice, offset + ver_offset + i, &Value32) !=
- LM_STATUS_SUCCESS)
- {
+ LM_UINT32 Value32, offset, ver_offset;
+ int i;
+
+ if (LM_NvramRead (pDevice, 0x0, &Value32) != LM_STATUS_SUCCESS)
return;
- }
- *((LM_UINT32 *) &pDevice->BootCodeVer[i]) = cpu_to_le32(Value32);
- }
- }
- else {
- char c;
+ if (Value32 != 0xaa559966)
+ return;
+ if (LM_NvramRead (pDevice, 0xc, &offset) != LM_STATUS_SUCCESS)
+ return;
+
+ offset = ((offset & 0xff) << 24) | ((offset & 0xff00) << 8) |
+ ((offset & 0xff0000) >> 8) | ((offset >> 24) & 0xff);
+ if (LM_NvramRead (pDevice, offset, &Value32) != LM_STATUS_SUCCESS)
+ return;
+ if ((Value32 == 0x0300000e) &&
+ (LM_NvramRead (pDevice, offset + 4, &Value32) == LM_STATUS_SUCCESS)
+ && (Value32 == 0)) {
+
+ if (LM_NvramRead (pDevice, offset + 8, &ver_offset) !=
+ LM_STATUS_SUCCESS)
+ return;
+ ver_offset = ((ver_offset & 0xff0000) >> 8) |
+ ((ver_offset >> 24) & 0xff);
+ for (i = 0; i < 16; i += 4) {
+ if (LM_NvramRead
+ (pDevice, offset + ver_offset + i,
+ &Value32) != LM_STATUS_SUCCESS) {
+ return;
+ }
+ *((LM_UINT32 *) & pDevice->BootCodeVer[i]) =
+ cpu_to_le32 (Value32);
+ }
+ } else {
+ char c;
- if (LM_NvramRead(pDevice, 0x94, &Value32) != LM_STATUS_SUCCESS)
- return;
+ if (LM_NvramRead (pDevice, 0x94, &Value32) != LM_STATUS_SUCCESS)
+ return;
- i = 0;
- c = ((Value32 & 0xff0000) >> 16);
+ i = 0;
+ c = ((Value32 & 0xff0000) >> 16);
- if (c < 10) {
- pDevice->BootCodeVer[i++] = c + '0';
- }
- else {
- pDevice->BootCodeVer[i++] = (c / 10) + '0';
- pDevice->BootCodeVer[i++] = (c % 10) + '0';
- }
- pDevice->BootCodeVer[i++] = '.';
- c = (Value32 & 0xff000000) >> 24;
- if (c < 10) {
- pDevice->BootCodeVer[i++] = c + '0';
- }
- else {
- pDevice->BootCodeVer[i++] = (c / 10) + '0';
- pDevice->BootCodeVer[i++] = (c % 10) + '0';
+ if (c < 10) {
+ pDevice->BootCodeVer[i++] = c + '0';
+ } else {
+ pDevice->BootCodeVer[i++] = (c / 10) + '0';
+ pDevice->BootCodeVer[i++] = (c % 10) + '0';
+ }
+ pDevice->BootCodeVer[i++] = '.';
+ c = (Value32 & 0xff000000) >> 24;
+ if (c < 10) {
+ pDevice->BootCodeVer[i++] = c + '0';
+ } else {
+ pDevice->BootCodeVer[i++] = (c / 10) + '0';
+ pDevice->BootCodeVer[i++] = (c % 10) + '0';
+ }
+ pDevice->BootCodeVer[i] = 0;
}
- pDevice->BootCodeVer[i] = 0;
- }
}
-STATIC void
-LM_GetBusSpeed(PLM_DEVICE_BLOCK pDevice)
+STATIC void LM_GetBusSpeed (PLM_DEVICE_BLOCK pDevice)
{
- LM_UINT32 PciState = pDevice->PciState;
- LM_UINT32 ClockCtrl;
- char *SpeedStr = "";
-
- if (PciState & T3_PCI_STATE_32BIT_PCI_BUS)
- {
- strcpy(pDevice->BusSpeedStr, "32-bit ");
- }
- else
- {
- strcpy(pDevice->BusSpeedStr, "64-bit ");
- }
- if (PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)
- {
- strcat(pDevice->BusSpeedStr, "PCI ");
- if (PciState & T3_PCI_STATE_HIGH_BUS_SPEED)
- {
- SpeedStr = "66MHz";
- }
- else
- {
- SpeedStr = "33MHz";
- }
- }
- else
- {
- strcat(pDevice->BusSpeedStr, "PCIX ");
- if (pDevice->BondId == GRC_MISC_BD_ID_5704CIOBE)
- {
- SpeedStr = "133MHz";
- }
- else
- {
- ClockCtrl = REG_RD(pDevice, PciCfg.ClockCtrl) & 0x1f;
- switch (ClockCtrl)
- {
- case 0:
- SpeedStr = "33MHz";
- break;
-
- case 2:
- SpeedStr = "50MHz";
- break;
-
- case 4:
- SpeedStr = "66MHz";
- break;
-
- case 6:
- SpeedStr = "100MHz";
- break;
-
- case 7:
- SpeedStr = "133MHz";
- break;
- }
+ LM_UINT32 PciState = pDevice->PciState;
+ LM_UINT32 ClockCtrl;
+ char *SpeedStr = "";
+
+ if (PciState & T3_PCI_STATE_32BIT_PCI_BUS) {
+ strcpy (pDevice->BusSpeedStr, "32-bit ");
+ } else {
+ strcpy (pDevice->BusSpeedStr, "64-bit ");
+ }
+ if (PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) {
+ strcat (pDevice->BusSpeedStr, "PCI ");
+ if (PciState & T3_PCI_STATE_HIGH_BUS_SPEED) {
+ SpeedStr = "66MHz";
+ } else {
+ SpeedStr = "33MHz";
+ }
+ } else {
+ strcat (pDevice->BusSpeedStr, "PCIX ");
+ if (pDevice->BondId == GRC_MISC_BD_ID_5704CIOBE) {
+ SpeedStr = "133MHz";
+ } else {
+ ClockCtrl = REG_RD (pDevice, PciCfg.ClockCtrl) & 0x1f;
+ switch (ClockCtrl) {
+ case 0:
+ SpeedStr = "33MHz";
+ break;
+
+ case 2:
+ SpeedStr = "50MHz";
+ break;
+
+ case 4:
+ SpeedStr = "66MHz";
+ break;
+
+ case 6:
+ SpeedStr = "100MHz";
+ break;
+
+ case 7:
+ SpeedStr = "133MHz";
+ break;
+ }
+ }
}
- }
- strcat(pDevice->BusSpeedStr, SpeedStr);
+ strcat (pDevice->BusSpeedStr, SpeedStr);
}
/******************************************************************************/
@@ -660,977 +598,890 @@ LM_GetBusSpeed(PLM_DEVICE_BLOCK pDevice)
/* Return: */
/* LM_STATUS_SUCCESS */
/******************************************************************************/
-LM_STATUS
-LM_GetAdapterInfo(
-PLM_DEVICE_BLOCK pDevice)
+LM_STATUS LM_GetAdapterInfo (PLM_DEVICE_BLOCK pDevice)
{
- PLM_ADAPTER_INFO pAdapterInfo;
- LM_UINT32 Value32;
- LM_STATUS Status;
- LM_UINT32 j;
- LM_UINT32 EeSigFound;
- LM_UINT32 EePhyTypeSerdes = 0;
- LM_UINT32 EePhyLedMode = 0;
- LM_UINT32 EePhyId = 0;
-
- /* Get Device Id and Vendor Id */
- Status = MM_ReadConfig32(pDevice, PCI_VENDOR_ID_REG, &Value32);
- if(Status != LM_STATUS_SUCCESS)
- {
- return Status;
- }
- pDevice->PciVendorId = (LM_UINT16) Value32;
- pDevice->PciDeviceId = (LM_UINT16) (Value32 >> 16);
-
- /* If we are not getting the write adapter, exit. */
- if((Value32 != T3_PCI_ID_BCM5700) &&
- (Value32 != T3_PCI_ID_BCM5701) &&
- (Value32 != T3_PCI_ID_BCM5702) &&
- (Value32 != T3_PCI_ID_BCM5702x) &&
- (Value32 != T3_PCI_ID_BCM5702FE) &&
- (Value32 != T3_PCI_ID_BCM5703) &&
- (Value32 != T3_PCI_ID_BCM5703x) &&
- (Value32 != T3_PCI_ID_BCM5704))
- {
- return LM_STATUS_FAILURE;
- }
+ PLM_ADAPTER_INFO pAdapterInfo;
+ LM_UINT32 Value32;
+ LM_STATUS Status;
+ LM_UINT32 j;
+ LM_UINT32 EeSigFound;
+ LM_UINT32 EePhyTypeSerdes = 0;
+ LM_UINT32 EePhyLedMode = 0;
+ LM_UINT32 EePhyId = 0;
+
+ /* Get Device Id and Vendor Id */
+ Status = MM_ReadConfig32 (pDevice, PCI_VENDOR_ID_REG, &Value32);
+ if (Status != LM_STATUS_SUCCESS) {
+ return Status;
+ }
+ pDevice->PciVendorId = (LM_UINT16) Value32;
+ pDevice->PciDeviceId = (LM_UINT16) (Value32 >> 16);
+
+ /* If we are not getting the write adapter, exit. */
+ if ((Value32 != T3_PCI_ID_BCM5700) &&
+ (Value32 != T3_PCI_ID_BCM5701) &&
+ (Value32 != T3_PCI_ID_BCM5702) &&
+ (Value32 != T3_PCI_ID_BCM5702x) &&
+ (Value32 != T3_PCI_ID_BCM5702FE) &&
+ (Value32 != T3_PCI_ID_BCM5703) &&
+ (Value32 != T3_PCI_ID_BCM5703x) && (Value32 != T3_PCI_ID_BCM5704)) {
+ return LM_STATUS_FAILURE;
+ }
- Status = MM_ReadConfig32(pDevice, PCI_REV_ID_REG, &Value32);
- if(Status != LM_STATUS_SUCCESS)
- {
- return Status;
- }
- pDevice->PciRevId = (LM_UINT8) Value32;
+ Status = MM_ReadConfig32 (pDevice, PCI_REV_ID_REG, &Value32);
+ if (Status != LM_STATUS_SUCCESS) {
+ return Status;
+ }
+ pDevice->PciRevId = (LM_UINT8) Value32;
- /* Get IRQ. */
- Status = MM_ReadConfig32(pDevice, PCI_INT_LINE_REG, &Value32);
- if(Status != LM_STATUS_SUCCESS)
- {
- return Status;
- }
- pDevice->Irq = (LM_UINT8) Value32;
+ /* Get IRQ. */
+ Status = MM_ReadConfig32 (pDevice, PCI_INT_LINE_REG, &Value32);
+ if (Status != LM_STATUS_SUCCESS) {
+ return Status;
+ }
+ pDevice->Irq = (LM_UINT8) Value32;
- /* Get interrupt pin. */
- pDevice->IntPin = (LM_UINT8) (Value32 >> 8);
+ /* Get interrupt pin. */
+ pDevice->IntPin = (LM_UINT8) (Value32 >> 8);
- /* Get chip revision id. */
- Status = MM_ReadConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, &Value32);
- pDevice->ChipRevId = Value32 >> 16;
+ /* Get chip revision id. */
+ Status = MM_ReadConfig32 (pDevice, T3_PCI_MISC_HOST_CTRL_REG, &Value32);
+ pDevice->ChipRevId = Value32 >> 16;
- /* Get subsystem vendor. */
- Status = MM_ReadConfig32(pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG, &Value32);
- if(Status != LM_STATUS_SUCCESS)
- {
- return Status;
- }
- pDevice->SubsystemVendorId = (LM_UINT16) Value32;
+ /* Get subsystem vendor. */
+ Status =
+ MM_ReadConfig32 (pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG, &Value32);
+ if (Status != LM_STATUS_SUCCESS) {
+ return Status;
+ }
+ pDevice->SubsystemVendorId = (LM_UINT16) Value32;
- /* Get PCI subsystem id. */
- pDevice->SubsystemId = (LM_UINT16) (Value32 >> 16);
+ /* Get PCI subsystem id. */
+ pDevice->SubsystemId = (LM_UINT16) (Value32 >> 16);
- /* Get the cache line size. */
- MM_ReadConfig32(pDevice, PCI_CACHE_LINE_SIZE_REG, &Value32);
- pDevice->CacheLineSize = (LM_UINT8) Value32;
- pDevice->SavedCacheLineReg = Value32;
+ /* Get the cache line size. */
+ MM_ReadConfig32 (pDevice, PCI_CACHE_LINE_SIZE_REG, &Value32);
+ pDevice->CacheLineSize = (LM_UINT8) Value32;
+ pDevice->SavedCacheLineReg = Value32;
- if(pDevice->ChipRevId != T3_CHIP_ID_5703_A1 &&
- pDevice->ChipRevId != T3_CHIP_ID_5703_A2 &&
- pDevice->ChipRevId != T3_CHIP_ID_5704_A0)
- {
- pDevice->UndiFix = FALSE;
- }
+ if (pDevice->ChipRevId != T3_CHIP_ID_5703_A1 &&
+ pDevice->ChipRevId != T3_CHIP_ID_5703_A2 &&
+ pDevice->ChipRevId != T3_CHIP_ID_5704_A0) {
+ pDevice->UndiFix = FALSE;
+ }
#if !PCIX_TARGET_WORKAROUND
- pDevice->UndiFix = FALSE;
+ pDevice->UndiFix = FALSE;
#endif
- /* Map the memory base to system address space. */
- if (!pDevice->UndiFix)
- {
- Status = MM_MapMemBase(pDevice);
- if(Status != LM_STATUS_SUCCESS)
- {
- return Status;
+ /* Map the memory base to system address space. */
+ if (!pDevice->UndiFix) {
+ Status = MM_MapMemBase (pDevice);
+ if (Status != LM_STATUS_SUCCESS) {
+ return Status;
+ }
+ /* Initialize the memory view pointer. */
+ pDevice->pMemView = (PT3_STD_MEM_MAP) pDevice->pMappedMemBase;
}
- /* Initialize the memory view pointer. */
- pDevice->pMemView = (PT3_STD_MEM_MAP) pDevice->pMappedMemBase;
- }
-
#if PCIX_TARGET_WORKAROUND
- /* store whether we are in PCI are PCI-X mode */
- pDevice->EnablePciXFix = FALSE;
-
- MM_ReadConfig32(pDevice, T3_PCI_STATE_REG, &Value32);
- if((Value32 & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) == 0)
- {
- /* Enable PCI-X workaround only if we are running on 5700 BX. */
- if(T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5700_BX)
- {
- pDevice->EnablePciXFix = TRUE;
+ /* store whether we are in PCI are PCI-X mode */
+ pDevice->EnablePciXFix = FALSE;
+
+ MM_ReadConfig32 (pDevice, T3_PCI_STATE_REG, &Value32);
+ if ((Value32 & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) == 0) {
+ /* Enable PCI-X workaround only if we are running on 5700 BX. */
+ if (T3_CHIP_REV (pDevice->ChipRevId) == T3_CHIP_REV_5700_BX) {
+ pDevice->EnablePciXFix = TRUE;
+ }
+ }
+ if (pDevice->UndiFix) {
+ pDevice->EnablePciXFix = TRUE;
}
- }
- if (pDevice->UndiFix)
- {
- pDevice->EnablePciXFix = TRUE;
- }
#endif
- /* Bx bug: due to the "byte_enable bug" in PCI-X mode, the power */
- /* management register may be clobbered which may cause the */
- /* BCM5700 to go into D3 state. While in this state, we will */
- /* not have memory mapped register access. As a workaround, we */
- /* need to restore the device to D0 state. */
- MM_ReadConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, &Value32);
- Value32 |= T3_PM_PME_ASSERTED;
- Value32 &= ~T3_PM_POWER_STATE_MASK;
- Value32 |= T3_PM_POWER_STATE_D0;
- MM_WriteConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, Value32);
-
- /* read the current PCI command word */
- MM_ReadConfig32(pDevice, PCI_COMMAND_REG, &Value32);
-
- /* Make sure bus-mastering is enabled. */
- Value32 |= PCI_BUSMASTER_ENABLE;
+ /* Bx bug: due to the "byte_enable bug" in PCI-X mode, the power */
+ /* management register may be clobbered which may cause the */
+ /* BCM5700 to go into D3 state. While in this state, we will */
+ /* not have memory mapped register access. As a workaround, we */
+ /* need to restore the device to D0 state. */
+ MM_ReadConfig32 (pDevice, T3_PCI_PM_STATUS_CTRL_REG, &Value32);
+ Value32 |= T3_PM_PME_ASSERTED;
+ Value32 &= ~T3_PM_POWER_STATE_MASK;
+ Value32 |= T3_PM_POWER_STATE_D0;
+ MM_WriteConfig32 (pDevice, T3_PCI_PM_STATUS_CTRL_REG, Value32);
+
+ /* read the current PCI command word */
+ MM_ReadConfig32 (pDevice, PCI_COMMAND_REG, &Value32);
+
+ /* Make sure bus-mastering is enabled. */
+ Value32 |= PCI_BUSMASTER_ENABLE;
#if PCIX_TARGET_WORKAROUND
- /* if we are in PCI-X mode, also make sure mem-mapping and SERR#/PERR#
- are enabled */
- if (pDevice->EnablePciXFix == TRUE) {
- Value32 |= (PCI_MEM_SPACE_ENABLE | PCI_SYSTEM_ERROR_ENABLE |
- PCI_PARITY_ERROR_ENABLE);
- }
- if (pDevice->UndiFix)
- {
- Value32 &= ~PCI_MEM_SPACE_ENABLE;
- }
-
+ /* if we are in PCI-X mode, also make sure mem-mapping and SERR#/PERR#
+ are enabled */
+ if (pDevice->EnablePciXFix == TRUE) {
+ Value32 |= (PCI_MEM_SPACE_ENABLE | PCI_SYSTEM_ERROR_ENABLE |
+ PCI_PARITY_ERROR_ENABLE);
+ }
+ if (pDevice->UndiFix) {
+ Value32 &= ~PCI_MEM_SPACE_ENABLE;
+ }
#endif
- if(pDevice->EnableMWI)
- {
- Value32 |= PCI_MEMORY_WRITE_INVALIDATE;
- }
- else {
- Value32 &= (~PCI_MEMORY_WRITE_INVALIDATE);
- }
-
- /* Error out if mem-mapping is NOT enabled for PCI systems */
- if (!(Value32 | PCI_MEM_SPACE_ENABLE))
- {
- return LM_STATUS_FAILURE;
- }
+ if (pDevice->EnableMWI) {
+ Value32 |= PCI_MEMORY_WRITE_INVALIDATE;
+ } else {
+ Value32 &= (~PCI_MEMORY_WRITE_INVALIDATE);
+ }
- /* save the value we are going to write into the PCI command word */
- pDevice->PciCommandStatusWords = Value32;
+ /* Error out if mem-mapping is NOT enabled for PCI systems */
+ if (!(Value32 | PCI_MEM_SPACE_ENABLE)) {
+ return LM_STATUS_FAILURE;
+ }
- Status = MM_WriteConfig32(pDevice, PCI_COMMAND_REG, Value32);
- if(Status != LM_STATUS_SUCCESS)
- {
- return Status;
- }
+ /* save the value we are going to write into the PCI command word */
+ pDevice->PciCommandStatusWords = Value32;
+
+ Status = MM_WriteConfig32 (pDevice, PCI_COMMAND_REG, Value32);
+ if (Status != LM_STATUS_SUCCESS) {
+ return Status;
+ }
- /* Set power state to D0. */
- LM_SetPowerState(pDevice, LM_POWER_STATE_D0);
+ /* Set power state to D0. */
+ LM_SetPowerState (pDevice, LM_POWER_STATE_D0);
#ifdef BIG_ENDIAN_PCI
- pDevice->MiscHostCtrl =
- MISC_HOST_CTRL_MASK_PCI_INT |
- MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS |
- MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP |
- MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW;
-#else /* No CPU Swap modes for PCI IO */
-
- /* Setup the mode registers. */
- pDevice->MiscHostCtrl =
- MISC_HOST_CTRL_MASK_PCI_INT |
- MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP |
+ pDevice->MiscHostCtrl =
+ MISC_HOST_CTRL_MASK_PCI_INT |
+ MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS |
+ MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP |
+ MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW;
+#else /* No CPU Swap modes for PCI IO */
+
+ /* Setup the mode registers. */
+ pDevice->MiscHostCtrl =
+ MISC_HOST_CTRL_MASK_PCI_INT |
+ MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP |
#ifdef BIG_ENDIAN_HOST
- MISC_HOST_CTRL_ENABLE_ENDIAN_BYTE_SWAP |
-#endif /* BIG_ENDIAN_HOST */
- MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS |
- MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW;
-#endif /* !BIG_ENDIAN_PCI */
+ MISC_HOST_CTRL_ENABLE_ENDIAN_BYTE_SWAP |
+#endif /* BIG_ENDIAN_HOST */
+ MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS |
+ MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW;
+#endif /* !BIG_ENDIAN_PCI */
- /* write to PCI misc host ctr first in order to enable indirect accesses */
- MM_WriteConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, pDevice->MiscHostCtrl);
+ /* write to PCI misc host ctr first in order to enable indirect accesses */
+ MM_WriteConfig32 (pDevice, T3_PCI_MISC_HOST_CTRL_REG,
+ pDevice->MiscHostCtrl);
- REG_WR(pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl);
+ REG_WR (pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl);
#ifdef BIG_ENDIAN_PCI
- Value32 = GRC_MODE_WORD_SWAP_DATA|
- GRC_MODE_WORD_SWAP_NON_FRAME_DATA;
+ Value32 = GRC_MODE_WORD_SWAP_DATA | GRC_MODE_WORD_SWAP_NON_FRAME_DATA;
#else
/* No CPU Swap modes for PCI IO */
#ifdef BIG_ENDIAN_HOST
- Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA |
- GRC_MODE_WORD_SWAP_NON_FRAME_DATA;
+ Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA |
+ GRC_MODE_WORD_SWAP_NON_FRAME_DATA;
#else
- Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | GRC_MODE_BYTE_SWAP_DATA;
+ Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | GRC_MODE_BYTE_SWAP_DATA;
#endif
-#endif /* !BIG_ENDIAN_PCI */
-
- REG_WR(pDevice, Grc.Mode, Value32);
-
- if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
- {
- REG_WR(pDevice, Grc.LocalCtrl, GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 |
- GRC_MISC_LOCAL_CTRL_GPIO_OE1);
- }
- MM_Wait(40);
-
- /* Enable indirect memory access */
- REG_WR(pDevice, MemArbiter.Mode, T3_MEM_ARBITER_MODE_ENABLE);
-
- if (REG_RD(pDevice, PciCfg.ClockCtrl) & T3_PCI_44MHZ_CORE_CLOCK)
- {
- REG_WR(pDevice, PciCfg.ClockCtrl, T3_PCI_44MHZ_CORE_CLOCK |
- T3_PCI_SELECT_ALTERNATE_CLOCK);
- REG_WR(pDevice, PciCfg.ClockCtrl, T3_PCI_SELECT_ALTERNATE_CLOCK);
- MM_Wait(40); /* required delay is 27usec */
- }
- REG_WR(pDevice, PciCfg.ClockCtrl, 0);
- REG_WR(pDevice, PciCfg.MemWindowBaseAddr, 0);
+#endif /* !BIG_ENDIAN_PCI */
+
+ REG_WR (pDevice, Grc.Mode, Value32);
+
+ if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
+ REG_WR (pDevice, Grc.LocalCtrl,
+ GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 |
+ GRC_MISC_LOCAL_CTRL_GPIO_OE1);
+ }
+ MM_Wait (40);
+
+ /* Enable indirect memory access */
+ REG_WR (pDevice, MemArbiter.Mode, T3_MEM_ARBITER_MODE_ENABLE);
+
+ if (REG_RD (pDevice, PciCfg.ClockCtrl) & T3_PCI_44MHZ_CORE_CLOCK) {
+ REG_WR (pDevice, PciCfg.ClockCtrl, T3_PCI_44MHZ_CORE_CLOCK |
+ T3_PCI_SELECT_ALTERNATE_CLOCK);
+ REG_WR (pDevice, PciCfg.ClockCtrl,
+ T3_PCI_SELECT_ALTERNATE_CLOCK);
+ MM_Wait (40); /* required delay is 27usec */
+ }
+ REG_WR (pDevice, PciCfg.ClockCtrl, 0);
+ REG_WR (pDevice, PciCfg.MemWindowBaseAddr, 0);
#if PCIX_TARGET_WORKAROUND
- MM_ReadConfig32(pDevice, T3_PCI_STATE_REG, &Value32);
- if ((pDevice->EnablePciXFix == FALSE) &&
- ((Value32 & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) == 0))
- {
- if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
- pDevice->ChipRevId == T3_CHIP_ID_5701_B0 ||
- pDevice->ChipRevId == T3_CHIP_ID_5701_B2 ||
- pDevice->ChipRevId == T3_CHIP_ID_5701_B5)
- {
- __raw_writel(0, &(pDevice->pMemView->uIntMem.MemBlock32K[0x300]));
- __raw_writel(0, &(pDevice->pMemView->uIntMem.MemBlock32K[0x301]));
- __raw_writel(0xffffffff, &(pDevice->pMemView->uIntMem.MemBlock32K[0x301]));
- if (__raw_readl(&(pDevice->pMemView->uIntMem.MemBlock32K[0x300])))
- {
- pDevice->EnablePciXFix = TRUE;
- }
+ MM_ReadConfig32 (pDevice, T3_PCI_STATE_REG, &Value32);
+ if ((pDevice->EnablePciXFix == FALSE) &&
+ ((Value32 & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) == 0)) {
+ if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
+ pDevice->ChipRevId == T3_CHIP_ID_5701_B0 ||
+ pDevice->ChipRevId == T3_CHIP_ID_5701_B2 ||
+ pDevice->ChipRevId == T3_CHIP_ID_5701_B5) {
+ __raw_writel (0,
+ &(pDevice->pMemView->uIntMem.
+ MemBlock32K[0x300]));
+ __raw_writel (0,
+ &(pDevice->pMemView->uIntMem.
+ MemBlock32K[0x301]));
+ __raw_writel (0xffffffff,
+ &(pDevice->pMemView->uIntMem.
+ MemBlock32K[0x301]));
+ if (__raw_readl
+ (&(pDevice->pMemView->uIntMem.MemBlock32K[0x300])))
+ {
+ pDevice->EnablePciXFix = TRUE;
+ }
+ }
}
- }
#endif
#if 1
- /*
- * This code was at the beginning of else block below, but that's
- * a bug if node address in shared memory.
- */
- MM_Wait(50);
- LM_NvramInit(pDevice);
+ /*
+ * This code was at the beginning of else block below, but that's
+ * a bug if node address in shared memory.
+ */
+ MM_Wait (50);
+ LM_NvramInit (pDevice);
#endif
- /* Get the node address. First try to get in from the shared memory. */
- /* If the signature is not present, then get it from the NVRAM. */
- Value32 = MEM_RD_OFFSET(pDevice, T3_MAC_ADDR_HIGH_MAILBOX);
- if((Value32 >> 16) == 0x484b)
- {
-
- pDevice->NodeAddress[0] = (LM_UINT8) (Value32 >> 8);
- pDevice->NodeAddress[1] = (LM_UINT8) Value32;
-
- Value32 = MEM_RD_OFFSET(pDevice, T3_MAC_ADDR_LOW_MAILBOX);
-
- pDevice->NodeAddress[2] = (LM_UINT8) (Value32 >> 24);
- pDevice->NodeAddress[3] = (LM_UINT8) (Value32 >> 16);
- pDevice->NodeAddress[4] = (LM_UINT8) (Value32 >> 8);
- pDevice->NodeAddress[5] = (LM_UINT8) Value32;
-
- Status = LM_STATUS_SUCCESS;
- }
- else
- {
- Status = LM_NvramRead(pDevice, 0x7c, &Value32);
- if(Status == LM_STATUS_SUCCESS)
- {
- pDevice->NodeAddress[0] = (LM_UINT8) (Value32 >> 16);
- pDevice->NodeAddress[1] = (LM_UINT8) (Value32 >> 24);
-
- Status = LM_NvramRead(pDevice, 0x80, &Value32);
-
- pDevice->NodeAddress[2] = (LM_UINT8) Value32;
- pDevice->NodeAddress[3] = (LM_UINT8) (Value32 >> 8);
- pDevice->NodeAddress[4] = (LM_UINT8) (Value32 >> 16);
- pDevice->NodeAddress[5] = (LM_UINT8) (Value32 >> 24);
+ /* Get the node address. First try to get in from the shared memory. */
+ /* If the signature is not present, then get it from the NVRAM. */
+ Value32 = MEM_RD_OFFSET (pDevice, T3_MAC_ADDR_HIGH_MAILBOX);
+ if ((Value32 >> 16) == 0x484b) {
+
+ pDevice->NodeAddress[0] = (LM_UINT8) (Value32 >> 8);
+ pDevice->NodeAddress[1] = (LM_UINT8) Value32;
+
+ Value32 = MEM_RD_OFFSET (pDevice, T3_MAC_ADDR_LOW_MAILBOX);
+
+ pDevice->NodeAddress[2] = (LM_UINT8) (Value32 >> 24);
+ pDevice->NodeAddress[3] = (LM_UINT8) (Value32 >> 16);
+ pDevice->NodeAddress[4] = (LM_UINT8) (Value32 >> 8);
+ pDevice->NodeAddress[5] = (LM_UINT8) Value32;
+
+ Status = LM_STATUS_SUCCESS;
+ } else {
+ Status = LM_NvramRead (pDevice, 0x7c, &Value32);
+ if (Status == LM_STATUS_SUCCESS) {
+ pDevice->NodeAddress[0] = (LM_UINT8) (Value32 >> 16);
+ pDevice->NodeAddress[1] = (LM_UINT8) (Value32 >> 24);
+
+ Status = LM_NvramRead (pDevice, 0x80, &Value32);
+
+ pDevice->NodeAddress[2] = (LM_UINT8) Value32;
+ pDevice->NodeAddress[3] = (LM_UINT8) (Value32 >> 8);
+ pDevice->NodeAddress[4] = (LM_UINT8) (Value32 >> 16);
+ pDevice->NodeAddress[5] = (LM_UINT8) (Value32 >> 24);
+ }
}
- }
- /* Assign a default address. */
- if(Status != LM_STATUS_SUCCESS)
- {
+ /* Assign a default address. */
+ if (Status != LM_STATUS_SUCCESS) {
#ifndef EMBEDDED
- printk(KERN_ERR "Cannot get MAC addr from NVRAM. Using default.\n");
+ printk (KERN_ERR
+ "Cannot get MAC addr from NVRAM. Using default.\n");
#endif
- pDevice->NodeAddress[0] = 0x00; pDevice->NodeAddress[1] = 0x10;
- pDevice->NodeAddress[2] = 0x18; pDevice->NodeAddress[3] = 0x68;
- pDevice->NodeAddress[4] = 0x61; pDevice->NodeAddress[5] = 0x76;
- }
-
- pDevice->PermanentNodeAddress[0] = pDevice->NodeAddress[0];
- pDevice->PermanentNodeAddress[1] = pDevice->NodeAddress[1];
- pDevice->PermanentNodeAddress[2] = pDevice->NodeAddress[2];
- pDevice->PermanentNodeAddress[3] = pDevice->NodeAddress[3];
- pDevice->PermanentNodeAddress[4] = pDevice->NodeAddress[4];
- pDevice->PermanentNodeAddress[5] = pDevice->NodeAddress[5];
-
- /* Initialize the default values. */
- pDevice->NoTxPseudoHdrChksum = FALSE;
- pDevice->NoRxPseudoHdrChksum = FALSE;
- pDevice->NicSendBd = FALSE;
- pDevice->TxPacketDescCnt = DEFAULT_TX_PACKET_DESC_COUNT;
- pDevice->RxStdDescCnt = DEFAULT_STD_RCV_DESC_COUNT;
- pDevice->RxCoalescingTicks = DEFAULT_RX_COALESCING_TICKS;
- pDevice->TxCoalescingTicks = DEFAULT_TX_COALESCING_TICKS;
- pDevice->RxMaxCoalescedFrames = DEFAULT_RX_MAX_COALESCED_FRAMES;
- pDevice->TxMaxCoalescedFrames = DEFAULT_TX_MAX_COALESCED_FRAMES;
- pDevice->RxCoalescingTicksDuringInt = BAD_DEFAULT_VALUE;
- pDevice->TxCoalescingTicksDuringInt = BAD_DEFAULT_VALUE;
- pDevice->RxMaxCoalescedFramesDuringInt = BAD_DEFAULT_VALUE;
- pDevice->TxMaxCoalescedFramesDuringInt = BAD_DEFAULT_VALUE;
- pDevice->StatsCoalescingTicks = DEFAULT_STATS_COALESCING_TICKS;
- pDevice->EnableMWI = FALSE;
- pDevice->TxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
- pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
- pDevice->DisableAutoNeg = FALSE;
- pDevice->PhyIntMode = T3_PHY_INT_MODE_AUTO;
- pDevice->LinkChngMode = T3_LINK_CHNG_MODE_AUTO;
- pDevice->LedMode = LED_MODE_AUTO;
- pDevice->ResetPhyOnInit = TRUE;
- pDevice->DelayPciGrant = TRUE;
- pDevice->UseTaggedStatus = FALSE;
- pDevice->OneDmaAtOnce = BAD_DEFAULT_VALUE;
-
- pDevice->DmaMbufLowMark = T3_DEF_DMA_MBUF_LOW_WMARK_JUMBO;
- pDevice->RxMacMbufLowMark = T3_DEF_RX_MAC_MBUF_LOW_WMARK_JUMBO;
- pDevice->MbufHighMark = T3_DEF_MBUF_HIGH_WMARK_JUMBO;
-
- pDevice->RequestedMediaType = LM_REQUESTED_MEDIA_TYPE_AUTO;
- pDevice->TaskOffloadCap = LM_TASK_OFFLOAD_NONE;
- pDevice->FlowControlCap = LM_FLOW_CONTROL_AUTO_PAUSE;
- pDevice->EnableTbi = FALSE;
-#if INCLUDE_TBI_SUPPORT
- pDevice->PollTbiLink = BAD_DEFAULT_VALUE;
-#endif
-
- switch (T3_ASIC_REV(pDevice->ChipRevId))
- {
- case T3_ASIC_REV_5704:
- pDevice->MbufBase = T3_NIC_MBUF_POOL_ADDR;
- pDevice->MbufSize = T3_NIC_MBUF_POOL_SIZE64;
- break;
- default:
- pDevice->MbufBase = T3_NIC_MBUF_POOL_ADDR;
- pDevice->MbufSize = T3_NIC_MBUF_POOL_SIZE96;
- break;
- }
-
- pDevice->LinkStatus = LM_STATUS_LINK_DOWN;
- pDevice->QueueRxPackets = TRUE;
+ pDevice->NodeAddress[0] = 0x00;
+ pDevice->NodeAddress[1] = 0x10;
+ pDevice->NodeAddress[2] = 0x18;
+ pDevice->NodeAddress[3] = 0x68;
+ pDevice->NodeAddress[4] = 0x61;
+ pDevice->NodeAddress[5] = 0x76;
+ }
+
+ pDevice->PermanentNodeAddress[0] = pDevice->NodeAddress[0];
+ pDevice->PermanentNodeAddress[1] = pDevice->NodeAddress[1];
+ pDevice->PermanentNodeAddress[2] = pDevice->NodeAddress[2];
+ pDevice->PermanentNodeAddress[3] = pDevice->NodeAddress[3];
+ pDevice->PermanentNodeAddress[4] = pDevice->NodeAddress[4];
+ pDevice->PermanentNodeAddress[5] = pDevice->NodeAddress[5];
+
+ /* Initialize the default values. */
+ pDevice->NoTxPseudoHdrChksum = FALSE;
+ pDevice->NoRxPseudoHdrChksum = FALSE;
+ pDevice->NicSendBd = FALSE;
+ pDevice->TxPacketDescCnt = DEFAULT_TX_PACKET_DESC_COUNT;
+ pDevice->RxStdDescCnt = DEFAULT_STD_RCV_DESC_COUNT;
+ pDevice->RxCoalescingTicks = DEFAULT_RX_COALESCING_TICKS;
+ pDevice->TxCoalescingTicks = DEFAULT_TX_COALESCING_TICKS;
+ pDevice->RxMaxCoalescedFrames = DEFAULT_RX_MAX_COALESCED_FRAMES;
+ pDevice->TxMaxCoalescedFrames = DEFAULT_TX_MAX_COALESCED_FRAMES;
+ pDevice->RxCoalescingTicksDuringInt = BAD_DEFAULT_VALUE;
+ pDevice->TxCoalescingTicksDuringInt = BAD_DEFAULT_VALUE;
+ pDevice->RxMaxCoalescedFramesDuringInt = BAD_DEFAULT_VALUE;
+ pDevice->TxMaxCoalescedFramesDuringInt = BAD_DEFAULT_VALUE;
+ pDevice->StatsCoalescingTicks = DEFAULT_STATS_COALESCING_TICKS;
+ pDevice->EnableMWI = FALSE;
+ pDevice->TxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
+ pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
+ pDevice->DisableAutoNeg = FALSE;
+ pDevice->PhyIntMode = T3_PHY_INT_MODE_AUTO;
+ pDevice->LinkChngMode = T3_LINK_CHNG_MODE_AUTO;
+ pDevice->LedMode = LED_MODE_AUTO;
+ pDevice->ResetPhyOnInit = TRUE;
+ pDevice->DelayPciGrant = TRUE;
+ pDevice->UseTaggedStatus = FALSE;
+ pDevice->OneDmaAtOnce = BAD_DEFAULT_VALUE;
- pDevice->EnableWireSpeed = TRUE;
+ pDevice->DmaMbufLowMark = T3_DEF_DMA_MBUF_LOW_WMARK_JUMBO;
+ pDevice->RxMacMbufLowMark = T3_DEF_RX_MAC_MBUF_LOW_WMARK_JUMBO;
+ pDevice->MbufHighMark = T3_DEF_MBUF_HIGH_WMARK_JUMBO;
-#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
- pDevice->RxJumboDescCnt = DEFAULT_JUMBO_RCV_DESC_COUNT;
-#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
-
- /* Make this is a known adapter. */
- pAdapterInfo = LM_GetAdapterInfoBySsid(pDevice->SubsystemVendorId,
- pDevice->SubsystemId);
-
- pDevice->BondId = REG_RD(pDevice, Grc.MiscCfg) & GRC_MISC_BD_ID_MASK;
- if (pDevice->BondId != GRC_MISC_BD_ID_5700 &&
- pDevice->BondId != GRC_MISC_BD_ID_5701 &&
- pDevice->BondId != GRC_MISC_BD_ID_5702FE &&
- pDevice->BondId != GRC_MISC_BD_ID_5703 &&
- pDevice->BondId != GRC_MISC_BD_ID_5703S &&
- pDevice->BondId != GRC_MISC_BD_ID_5704 &&
- pDevice->BondId != GRC_MISC_BD_ID_5704CIOBE)
- {
- return LM_STATUS_UNKNOWN_ADAPTER;
- }
-
- pDevice->SplitModeEnable = SPLIT_MODE_DISABLE;
- if ((pDevice->ChipRevId == T3_CHIP_ID_5704_A0) &&
- (pDevice->BondId == GRC_MISC_BD_ID_5704CIOBE))
- {
- pDevice->SplitModeEnable = SPLIT_MODE_ENABLE;
- pDevice->SplitModeMaxReq = SPLIT_MODE_5704_MAX_REQ;
- }
-
- /* Get Eeprom info. */
- Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_SIG_ADDR);
- if (Value32 == T3_NIC_DATA_SIG)
- {
- EeSigFound = TRUE;
- Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_NIC_CFG_ADDR);
-
- /* Determine PHY type. */
- switch (Value32 & T3_NIC_CFG_PHY_TYPE_MASK)
- {
- case T3_NIC_CFG_PHY_TYPE_COPPER:
- EePhyTypeSerdes = FALSE;
- break;
+ pDevice->RequestedMediaType = LM_REQUESTED_MEDIA_TYPE_AUTO;
+ pDevice->TaskOffloadCap = LM_TASK_OFFLOAD_NONE;
+ pDevice->FlowControlCap = LM_FLOW_CONTROL_AUTO_PAUSE;
+ pDevice->EnableTbi = FALSE;
+#if INCLUDE_TBI_SUPPORT
+ pDevice->PollTbiLink = BAD_DEFAULT_VALUE;
+#endif
- case T3_NIC_CFG_PHY_TYPE_FIBER:
- EePhyTypeSerdes = TRUE;
+ switch (T3_ASIC_REV (pDevice->ChipRevId)) {
+ case T3_ASIC_REV_5704:
+ pDevice->MbufBase = T3_NIC_MBUF_POOL_ADDR;
+ pDevice->MbufSize = T3_NIC_MBUF_POOL_SIZE64;
break;
-
- default:
- EePhyTypeSerdes = FALSE;
+ default:
+ pDevice->MbufBase = T3_NIC_MBUF_POOL_ADDR;
+ pDevice->MbufSize = T3_NIC_MBUF_POOL_SIZE96;
break;
}
- /* Determine PHY led mode. */
- if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
- T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)
- {
- switch(Value32 & T3_NIC_CFG_LED_MODE_MASK)
- {
- case T3_NIC_CFG_LED_MODE_TRIPLE_SPEED:
- EePhyLedMode = LED_MODE_THREE_LINK;
- break;
+ pDevice->LinkStatus = LM_STATUS_LINK_DOWN;
+ pDevice->QueueRxPackets = TRUE;
- case T3_NIC_CFG_LED_MODE_LINK_SPEED:
- EePhyLedMode = LED_MODE_LINK10;
- break;
+ pDevice->EnableWireSpeed = TRUE;
- default:
- EePhyLedMode = LED_MODE_AUTO;
- break;
- }
- }
- else
- {
- switch(Value32 & T3_NIC_CFG_LED_MODE_MASK)
- {
- case T3_NIC_CFG_LED_MODE_OPEN_DRAIN:
- EePhyLedMode = LED_MODE_OPEN_DRAIN;
- break;
+#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
+ pDevice->RxJumboDescCnt = DEFAULT_JUMBO_RCV_DESC_COUNT;
+#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
+
+ /* Make this is a known adapter. */
+ pAdapterInfo = LM_GetAdapterInfoBySsid (pDevice->SubsystemVendorId,
+ pDevice->SubsystemId);
+
+ pDevice->BondId = REG_RD (pDevice, Grc.MiscCfg) & GRC_MISC_BD_ID_MASK;
+ if (pDevice->BondId != GRC_MISC_BD_ID_5700 &&
+ pDevice->BondId != GRC_MISC_BD_ID_5701 &&
+ pDevice->BondId != GRC_MISC_BD_ID_5702FE &&
+ pDevice->BondId != GRC_MISC_BD_ID_5703 &&
+ pDevice->BondId != GRC_MISC_BD_ID_5703S &&
+ pDevice->BondId != GRC_MISC_BD_ID_5704 &&
+ pDevice->BondId != GRC_MISC_BD_ID_5704CIOBE) {
+ return LM_STATUS_UNKNOWN_ADAPTER;
+ }
+
+ pDevice->SplitModeEnable = SPLIT_MODE_DISABLE;
+ if ((pDevice->ChipRevId == T3_CHIP_ID_5704_A0) &&
+ (pDevice->BondId == GRC_MISC_BD_ID_5704CIOBE)) {
+ pDevice->SplitModeEnable = SPLIT_MODE_ENABLE;
+ pDevice->SplitModeMaxReq = SPLIT_MODE_5704_MAX_REQ;
+ }
+
+ /* Get Eeprom info. */
+ Value32 = MEM_RD_OFFSET (pDevice, T3_NIC_DATA_SIG_ADDR);
+ if (Value32 == T3_NIC_DATA_SIG) {
+ EeSigFound = TRUE;
+ Value32 = MEM_RD_OFFSET (pDevice, T3_NIC_DATA_NIC_CFG_ADDR);
+
+ /* Determine PHY type. */
+ switch (Value32 & T3_NIC_CFG_PHY_TYPE_MASK) {
+ case T3_NIC_CFG_PHY_TYPE_COPPER:
+ EePhyTypeSerdes = FALSE;
+ break;
- case T3_NIC_CFG_LED_MODE_OUTPUT:
- EePhyLedMode = LED_MODE_OUTPUT;
- break;
+ case T3_NIC_CFG_PHY_TYPE_FIBER:
+ EePhyTypeSerdes = TRUE;
+ break;
default:
- EePhyLedMode = LED_MODE_AUTO;
- break;
- }
- }
- if(pDevice->ChipRevId == T3_CHIP_ID_5703_A1 ||
- pDevice->ChipRevId == T3_CHIP_ID_5703_A2)
- {
- /* Enable EEPROM write protection. */
- if(Value32 & T3_NIC_EEPROM_WP)
- {
- pDevice->EepromWp = TRUE;
- }
- }
+ EePhyTypeSerdes = FALSE;
+ break;
+ }
- /* Get the PHY Id. */
- Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_PHY_ID_ADDR);
- if (Value32)
- {
- EePhyId = (((Value32 & T3_NIC_PHY_ID1_MASK) >> 16) &
- PHY_ID1_OUI_MASK) << 10;
+ /* Determine PHY led mode. */
+ if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
+ T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
+ switch (Value32 & T3_NIC_CFG_LED_MODE_MASK) {
+ case T3_NIC_CFG_LED_MODE_TRIPLE_SPEED:
+ EePhyLedMode = LED_MODE_THREE_LINK;
+ break;
+
+ case T3_NIC_CFG_LED_MODE_LINK_SPEED:
+ EePhyLedMode = LED_MODE_LINK10;
+ break;
+
+ default:
+ EePhyLedMode = LED_MODE_AUTO;
+ break;
+ }
+ } else {
+ switch (Value32 & T3_NIC_CFG_LED_MODE_MASK) {
+ case T3_NIC_CFG_LED_MODE_OPEN_DRAIN:
+ EePhyLedMode = LED_MODE_OPEN_DRAIN;
+ break;
+
+ case T3_NIC_CFG_LED_MODE_OUTPUT:
+ EePhyLedMode = LED_MODE_OUTPUT;
+ break;
+
+ default:
+ EePhyLedMode = LED_MODE_AUTO;
+ break;
+ }
+ }
+ if (pDevice->ChipRevId == T3_CHIP_ID_5703_A1 ||
+ pDevice->ChipRevId == T3_CHIP_ID_5703_A2) {
+ /* Enable EEPROM write protection. */
+ if (Value32 & T3_NIC_EEPROM_WP) {
+ pDevice->EepromWp = TRUE;
+ }
+ }
- Value32 = Value32 & T3_NIC_PHY_ID2_MASK;
+ /* Get the PHY Id. */
+ Value32 = MEM_RD_OFFSET (pDevice, T3_NIC_DATA_PHY_ID_ADDR);
+ if (Value32) {
+ EePhyId = (((Value32 & T3_NIC_PHY_ID1_MASK) >> 16) &
+ PHY_ID1_OUI_MASK) << 10;
- EePhyId |= ((Value32 & PHY_ID2_OUI_MASK) << 16) |
- (Value32 & PHY_ID2_MODEL_MASK) | (Value32 & PHY_ID2_REV_MASK);
- }
- else
- {
- EePhyId = 0;
+ Value32 = Value32 & T3_NIC_PHY_ID2_MASK;
+
+ EePhyId |= ((Value32 & PHY_ID2_OUI_MASK) << 16) |
+ (Value32 & PHY_ID2_MODEL_MASK) | (Value32 &
+ PHY_ID2_REV_MASK);
+ } else {
+ EePhyId = 0;
+ }
+ } else {
+ EeSigFound = FALSE;
}
- }
- else
- {
- EeSigFound = FALSE;
- }
- /* Set the PHY address. */
- pDevice->PhyAddr = PHY_DEVICE_ID;
+ /* Set the PHY address. */
+ pDevice->PhyAddr = PHY_DEVICE_ID;
- /* Disable auto polling. */
- pDevice->MiMode = 0xc0000;
- REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode);
- MM_Wait(40);
+ /* Disable auto polling. */
+ pDevice->MiMode = 0xc0000;
+ REG_WR (pDevice, MacCtrl.MiMode, pDevice->MiMode);
+ MM_Wait (40);
- /* Get the PHY id. */
- LM_ReadPhy(pDevice, PHY_ID1_REG, &Value32);
- pDevice->PhyId = (Value32 & PHY_ID1_OUI_MASK) << 10;
+ /* Get the PHY id. */
+ LM_ReadPhy (pDevice, PHY_ID1_REG, &Value32);
+ pDevice->PhyId = (Value32 & PHY_ID1_OUI_MASK) << 10;
- LM_ReadPhy(pDevice, PHY_ID2_REG, &Value32);
- pDevice->PhyId |= ((Value32 & PHY_ID2_OUI_MASK) << 16) |
- (Value32 & PHY_ID2_MODEL_MASK) | (Value32 & PHY_ID2_REV_MASK);
+ LM_ReadPhy (pDevice, PHY_ID2_REG, &Value32);
+ pDevice->PhyId |= ((Value32 & PHY_ID2_OUI_MASK) << 16) |
+ (Value32 & PHY_ID2_MODEL_MASK) | (Value32 & PHY_ID2_REV_MASK);
- /* Set the EnableTbi flag to false if we have a copper PHY. */
- switch(pDevice->PhyId & PHY_ID_MASK)
- {
+ /* Set the EnableTbi flag to false if we have a copper PHY. */
+ switch (pDevice->PhyId & PHY_ID_MASK) {
case PHY_BCM5400_PHY_ID:
- pDevice->EnableTbi = FALSE;
- break;
+ pDevice->EnableTbi = FALSE;
+ break;
case PHY_BCM5401_PHY_ID:
- pDevice->EnableTbi = FALSE;
- break;
+ pDevice->EnableTbi = FALSE;
+ break;
case PHY_BCM5411_PHY_ID:
- pDevice->EnableTbi = FALSE;
- break;
+ pDevice->EnableTbi = FALSE;
+ break;
case PHY_BCM5701_PHY_ID:
- pDevice->EnableTbi = FALSE;
- break;
+ pDevice->EnableTbi = FALSE;
+ break;
case PHY_BCM5703_PHY_ID:
- pDevice->EnableTbi = FALSE;
- break;
+ pDevice->EnableTbi = FALSE;
+ break;
case PHY_BCM5704_PHY_ID:
- pDevice->EnableTbi = FALSE;
- break;
+ pDevice->EnableTbi = FALSE;
+ break;
case PHY_BCM8002_PHY_ID:
- pDevice->EnableTbi = TRUE;
- break;
+ pDevice->EnableTbi = TRUE;
+ break;
default:
- if (pAdapterInfo)
- {
- pDevice->PhyId = pAdapterInfo->PhyId;
- pDevice->EnableTbi = pAdapterInfo->Serdes;
- }
- else if (EeSigFound)
- {
- pDevice->PhyId = EePhyId;
- pDevice->EnableTbi = EePhyTypeSerdes;
- }
- break;
- }
-
- /* Bail out if we don't know the copper PHY id. */
- if(UNKNOWN_PHY_ID(pDevice->PhyId) && !pDevice->EnableTbi)
- {
- return LM_STATUS_FAILURE;
- }
+ if (pAdapterInfo) {
+ pDevice->PhyId = pAdapterInfo->PhyId;
+ pDevice->EnableTbi = pAdapterInfo->Serdes;
+ } else if (EeSigFound) {
+ pDevice->PhyId = EePhyId;
+ pDevice->EnableTbi = EePhyTypeSerdes;
+ }
+ break;
+ }
- if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703)
- {
- if((pDevice->SavedCacheLineReg & 0xff00) < 0x4000)
- {
- pDevice->SavedCacheLineReg &= 0xffff00ff;
- pDevice->SavedCacheLineReg |= 0x4000;
- }
- }
- /* Change driver parameters. */
- Status = MM_GetConfig(pDevice);
- if(Status != LM_STATUS_SUCCESS)
- {
- return Status;
- }
+ /* Bail out if we don't know the copper PHY id. */
+ if (UNKNOWN_PHY_ID (pDevice->PhyId) && !pDevice->EnableTbi) {
+ return LM_STATUS_FAILURE;
+ }
+ if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5703) {
+ if ((pDevice->SavedCacheLineReg & 0xff00) < 0x4000) {
+ pDevice->SavedCacheLineReg &= 0xffff00ff;
+ pDevice->SavedCacheLineReg |= 0x4000;
+ }
+ }
+ /* Change driver parameters. */
+ Status = MM_GetConfig (pDevice);
+ if (Status != LM_STATUS_SUCCESS) {
+ return Status;
+ }
#if INCLUDE_5701_AX_FIX
- if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
- pDevice->ChipRevId == T3_CHIP_ID_5701_B0)
- {
- pDevice->ResetPhyOnInit = TRUE;
- }
+ if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
+ pDevice->ChipRevId == T3_CHIP_ID_5701_B0) {
+ pDevice->ResetPhyOnInit = TRUE;
+ }
#endif
- /* Save the current phy link status. */
- if(!pDevice->EnableTbi)
- {
- LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
- LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
+ /* Save the current phy link status. */
+ if (!pDevice->EnableTbi) {
+ LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
+ LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
- /* If we don't have link reset the PHY. */
- if(!(Value32 & PHY_STATUS_LINK_PASS) || pDevice->ResetPhyOnInit)
- {
+ /* If we don't have link reset the PHY. */
+ if (!(Value32 & PHY_STATUS_LINK_PASS)
+ || pDevice->ResetPhyOnInit) {
- LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_PHY_RESET);
+ LM_WritePhy (pDevice, PHY_CTRL_REG, PHY_CTRL_PHY_RESET);
- for(j = 0; j < 100; j++)
- {
- MM_Wait(10);
-
- LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32);
- if(Value32 && !(Value32 & PHY_CTRL_PHY_RESET))
- {
- MM_Wait(40);
- break;
- }
- }
+ for (j = 0; j < 100; j++) {
+ MM_Wait (10);
+ LM_ReadPhy (pDevice, PHY_CTRL_REG, &Value32);
+ if (Value32 && !(Value32 & PHY_CTRL_PHY_RESET)) {
+ MM_Wait (40);
+ break;
+ }
+ }
#if INCLUDE_5701_AX_FIX
- /* 5701_AX_BX bug: only advertises 10mb speed. */
- if(pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
- pDevice->ChipRevId == T3_CHIP_ID_5701_B0)
- {
-
- Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD |
- PHY_AN_AD_10BASET_HALF | PHY_AN_AD_10BASET_FULL |
- PHY_AN_AD_100BASETX_FULL | PHY_AN_AD_100BASETX_HALF;
- Value32 |= GetPhyAdFlowCntrlSettings(pDevice);
- LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32);
- pDevice->advertising = Value32;
-
- Value32 = BCM540X_AN_AD_1000BASET_HALF |
- BCM540X_AN_AD_1000BASET_FULL | BCM540X_CONFIG_AS_MASTER |
- BCM540X_ENABLE_CONFIG_AS_MASTER;
- LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, Value32);
- pDevice->advertising1000 = Value32;
-
- LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_AUTO_NEG_ENABLE |
- PHY_CTRL_RESTART_AUTO_NEG);
- }
+ /* 5701_AX_BX bug: only advertises 10mb speed. */
+ if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
+ pDevice->ChipRevId == T3_CHIP_ID_5701_B0) {
+
+ Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD |
+ PHY_AN_AD_10BASET_HALF |
+ PHY_AN_AD_10BASET_FULL |
+ PHY_AN_AD_100BASETX_FULL |
+ PHY_AN_AD_100BASETX_HALF;
+ Value32 |= GetPhyAdFlowCntrlSettings (pDevice);
+ LM_WritePhy (pDevice, PHY_AN_AD_REG, Value32);
+ pDevice->advertising = Value32;
+
+ Value32 = BCM540X_AN_AD_1000BASET_HALF |
+ BCM540X_AN_AD_1000BASET_FULL |
+ BCM540X_CONFIG_AS_MASTER |
+ BCM540X_ENABLE_CONFIG_AS_MASTER;
+ LM_WritePhy (pDevice,
+ BCM540X_1000BASET_CTRL_REG,
+ Value32);
+ pDevice->advertising1000 = Value32;
+
+ LM_WritePhy (pDevice, PHY_CTRL_REG,
+ PHY_CTRL_AUTO_NEG_ENABLE |
+ PHY_CTRL_RESTART_AUTO_NEG);
+ }
#endif
- if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703)
- {
- LM_WritePhy(pDevice, 0x18, 0x0c00);
- LM_WritePhy(pDevice, 0x17, 0x201f);
- LM_WritePhy(pDevice, 0x15, 0x2aaa);
- }
- if(pDevice->ChipRevId == T3_CHIP_ID_5704_A0)
- {
- LM_WritePhy(pDevice, 0x1c, 0x8d68);
- LM_WritePhy(pDevice, 0x1c, 0x8d68);
- }
- /* Enable Ethernet@WireSpeed. */
- if(pDevice->EnableWireSpeed)
- {
- LM_WritePhy(pDevice, 0x18, 0x7007);
- LM_ReadPhy(pDevice, 0x18, &Value32);
- LM_WritePhy(pDevice, 0x18, Value32 | BIT_15 | BIT_4);
- }
- }
- }
-
- /* Turn off tap power management. */
- if((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID)
- {
- LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x0c20);
- LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0012);
- LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1804);
- LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0013);
- LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1204);
- LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006);
- LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0132);
- LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006);
- LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0232);
- LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x201f);
- LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0a20);
-
- MM_Wait(40);
- }
+ if (T3_ASIC_REV (pDevice->ChipRevId) ==
+ T3_ASIC_REV_5703) {
+ LM_WritePhy (pDevice, 0x18, 0x0c00);
+ LM_WritePhy (pDevice, 0x17, 0x201f);
+ LM_WritePhy (pDevice, 0x15, 0x2aaa);
+ }
+ if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0) {
+ LM_WritePhy (pDevice, 0x1c, 0x8d68);
+ LM_WritePhy (pDevice, 0x1c, 0x8d68);
+ }
+ /* Enable Ethernet@WireSpeed. */
+ if (pDevice->EnableWireSpeed) {
+ LM_WritePhy (pDevice, 0x18, 0x7007);
+ LM_ReadPhy (pDevice, 0x18, &Value32);
+ LM_WritePhy (pDevice, 0x18,
+ Value32 | BIT_15 | BIT_4);
+ }
+ }
+ }
-#if INCLUDE_TBI_SUPPORT
- pDevice->IgnoreTbiLinkChange = FALSE;
-
- if(pDevice->EnableTbi)
- {
- pDevice->WakeUpModeCap = LM_WAKE_UP_MODE_NONE;
- pDevice->PhyIntMode = T3_PHY_INT_MODE_LINK_READY;
- if ((pDevice->PollTbiLink == BAD_DEFAULT_VALUE) ||
- pDevice->DisableAutoNeg)
- {
- pDevice->PollTbiLink = FALSE;
- }
- }
- else
- {
- pDevice->PollTbiLink = FALSE;
- }
-#endif /* INCLUDE_TBI_SUPPORT */
-
- /* UseTaggedStatus is only valid for 5701 and later. */
- if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
- {
- pDevice->UseTaggedStatus = FALSE;
+ /* Turn off tap power management. */
+ if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID) {
+ LM_WritePhy (pDevice, BCM5401_AUX_CTRL, 0x0c20);
+ LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x0012);
+ LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x1804);
+ LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x0013);
+ LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x1204);
+ LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006);
+ LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x0132);
+ LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006);
+ LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x0232);
+ LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x201f);
+ LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x0a20);
- pDevice->CoalesceMode = 0;
- }
- else
- {
- pDevice->CoalesceMode = HOST_COALESCE_CLEAR_TICKS_ON_RX_BD_EVENT |
- HOST_COALESCE_CLEAR_TICKS_ON_TX_BD_EVENT;
- }
-
- /* Set the status block size. */
- if(T3_CHIP_REV(pDevice->ChipRevId) != T3_CHIP_REV_5700_AX &&
- T3_CHIP_REV(pDevice->ChipRevId) != T3_CHIP_REV_5700_BX)
- {
- pDevice->CoalesceMode |= HOST_COALESCE_32_BYTE_STATUS_MODE;
- }
-
- /* Check the DURING_INT coalescing ticks parameters. */
- if(pDevice->UseTaggedStatus)
- {
- if(pDevice->RxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE)
- {
- pDevice->RxCoalescingTicksDuringInt =
- DEFAULT_RX_COALESCING_TICKS_DURING_INT;
+ MM_Wait (40);
}
-
- if(pDevice->TxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE)
- {
- pDevice->TxCoalescingTicksDuringInt =
- DEFAULT_TX_COALESCING_TICKS_DURING_INT;
+#if INCLUDE_TBI_SUPPORT
+ pDevice->IgnoreTbiLinkChange = FALSE;
+
+ if (pDevice->EnableTbi) {
+ pDevice->WakeUpModeCap = LM_WAKE_UP_MODE_NONE;
+ pDevice->PhyIntMode = T3_PHY_INT_MODE_LINK_READY;
+ if ((pDevice->PollTbiLink == BAD_DEFAULT_VALUE) ||
+ pDevice->DisableAutoNeg) {
+ pDevice->PollTbiLink = FALSE;
+ }
+ } else {
+ pDevice->PollTbiLink = FALSE;
}
+#endif /* INCLUDE_TBI_SUPPORT */
- if(pDevice->RxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE)
- {
- pDevice->RxMaxCoalescedFramesDuringInt =
- DEFAULT_RX_MAX_COALESCED_FRAMES_DURING_INT;
- }
+ /* UseTaggedStatus is only valid for 5701 and later. */
+ if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
+ pDevice->UseTaggedStatus = FALSE;
- if(pDevice->TxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE)
- {
- pDevice->TxMaxCoalescedFramesDuringInt =
- DEFAULT_TX_MAX_COALESCED_FRAMES_DURING_INT;
- }
- }
- else
- {
- if(pDevice->RxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE)
- {
- pDevice->RxCoalescingTicksDuringInt = 0;
+ pDevice->CoalesceMode = 0;
+ } else {
+ pDevice->CoalesceMode =
+ HOST_COALESCE_CLEAR_TICKS_ON_RX_BD_EVENT |
+ HOST_COALESCE_CLEAR_TICKS_ON_TX_BD_EVENT;
}
- if(pDevice->TxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE)
- {
- pDevice->TxCoalescingTicksDuringInt = 0;
+ /* Set the status block size. */
+ if (T3_CHIP_REV (pDevice->ChipRevId) != T3_CHIP_REV_5700_AX &&
+ T3_CHIP_REV (pDevice->ChipRevId) != T3_CHIP_REV_5700_BX) {
+ pDevice->CoalesceMode |= HOST_COALESCE_32_BYTE_STATUS_MODE;
}
- if(pDevice->RxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE)
- {
- pDevice->RxMaxCoalescedFramesDuringInt = 0;
- }
+ /* Check the DURING_INT coalescing ticks parameters. */
+ if (pDevice->UseTaggedStatus) {
+ if (pDevice->RxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) {
+ pDevice->RxCoalescingTicksDuringInt =
+ DEFAULT_RX_COALESCING_TICKS_DURING_INT;
+ }
- if(pDevice->TxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE)
- {
- pDevice->TxMaxCoalescedFramesDuringInt = 0;
+ if (pDevice->TxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) {
+ pDevice->TxCoalescingTicksDuringInt =
+ DEFAULT_TX_COALESCING_TICKS_DURING_INT;
+ }
+
+ if (pDevice->RxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) {
+ pDevice->RxMaxCoalescedFramesDuringInt =
+ DEFAULT_RX_MAX_COALESCED_FRAMES_DURING_INT;
+ }
+
+ if (pDevice->TxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) {
+ pDevice->TxMaxCoalescedFramesDuringInt =
+ DEFAULT_TX_MAX_COALESCED_FRAMES_DURING_INT;
+ }
+ } else {
+ if (pDevice->RxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) {
+ pDevice->RxCoalescingTicksDuringInt = 0;
+ }
+
+ if (pDevice->TxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) {
+ pDevice->TxCoalescingTicksDuringInt = 0;
+ }
+
+ if (pDevice->RxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) {
+ pDevice->RxMaxCoalescedFramesDuringInt = 0;
+ }
+
+ if (pDevice->TxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) {
+ pDevice->TxMaxCoalescedFramesDuringInt = 0;
+ }
}
- }
#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
- if(pDevice->RxMtu <= (MAX_STD_RCV_BUFFER_SIZE - 8 /* CRC */))
- {
- pDevice->RxJumboDescCnt = 0;
- if(pDevice->RxMtu <= MAX_ETHERNET_PACKET_SIZE_NO_CRC)
- {
- pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
- }
- }
- else
- {
- pDevice->RxJumboBufferSize = (pDevice->RxMtu + 8 /* CRC + VLAN */ +
- COMMON_CACHE_LINE_SIZE-1) & ~COMMON_CACHE_LINE_MASK;
+ if (pDevice->RxMtu <= (MAX_STD_RCV_BUFFER_SIZE - 8 /* CRC */ )) {
+ pDevice->RxJumboDescCnt = 0;
+ if (pDevice->RxMtu <= MAX_ETHERNET_PACKET_SIZE_NO_CRC) {
+ pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
+ }
+ } else {
+ pDevice->RxJumboBufferSize =
+ (pDevice->RxMtu + 8 /* CRC + VLAN */ +
+ COMMON_CACHE_LINE_SIZE - 1) & ~COMMON_CACHE_LINE_MASK;
+
+ if (pDevice->RxJumboBufferSize > MAX_JUMBO_RCV_BUFFER_SIZE) {
+ pDevice->RxJumboBufferSize =
+ DEFAULT_JUMBO_RCV_BUFFER_SIZE;
+ pDevice->RxMtu =
+ pDevice->RxJumboBufferSize - 8 /* CRC + VLAN */ ;
+ }
+ pDevice->TxMtu = pDevice->RxMtu;
- if(pDevice->RxJumboBufferSize > MAX_JUMBO_RCV_BUFFER_SIZE)
- {
- pDevice->RxJumboBufferSize = DEFAULT_JUMBO_RCV_BUFFER_SIZE;
- pDevice->RxMtu = pDevice->RxJumboBufferSize - 8 /* CRC + VLAN */;
}
- pDevice->TxMtu = pDevice->RxMtu;
-
- }
#else
- pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
-#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
+ pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
+#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
- pDevice->RxPacketDescCnt =
+ pDevice->RxPacketDescCnt =
#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
- pDevice->RxJumboDescCnt +
-#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
- pDevice->RxStdDescCnt;
-
- if(pDevice->TxMtu < MAX_ETHERNET_PACKET_SIZE_NO_CRC)
- {
- pDevice->TxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
- }
-
- if(pDevice->TxMtu > MAX_JUMBO_TX_BUFFER_SIZE)
- {
- pDevice->TxMtu = MAX_JUMBO_TX_BUFFER_SIZE;
- }
+ pDevice->RxJumboDescCnt +
+#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
+ pDevice->RxStdDescCnt;
- /* Configure the proper ways to get link change interrupt. */
- if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO)
- {
- if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
- {
- pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT;
+ if (pDevice->TxMtu < MAX_ETHERNET_PACKET_SIZE_NO_CRC) {
+ pDevice->TxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
}
- else
- {
- pDevice->PhyIntMode = T3_PHY_INT_MODE_LINK_READY;
+
+ if (pDevice->TxMtu > MAX_JUMBO_TX_BUFFER_SIZE) {
+ pDevice->TxMtu = MAX_JUMBO_TX_BUFFER_SIZE;
}
- }
- else if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING)
- {
- /* Auto-polling does not work on 5700_AX and 5700_BX. */
- if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
- {
- pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT;
+
+ /* Configure the proper ways to get link change interrupt. */
+ if (pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO) {
+ if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
+ pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT;
+ } else {
+ pDevice->PhyIntMode = T3_PHY_INT_MODE_LINK_READY;
+ }
+ } else if (pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) {
+ /* Auto-polling does not work on 5700_AX and 5700_BX. */
+ if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
+ pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT;
+ }
}
- }
- /* Determine the method to get link change status. */
- if(pDevice->LinkChngMode == T3_LINK_CHNG_MODE_AUTO)
- {
- /* The link status bit in the status block does not work on 5700_AX */
- /* and 5700_BX chips. */
- if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
- {
- pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_REG;
+ /* Determine the method to get link change status. */
+ if (pDevice->LinkChngMode == T3_LINK_CHNG_MODE_AUTO) {
+ /* The link status bit in the status block does not work on 5700_AX */
+ /* and 5700_BX chips. */
+ if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
+ pDevice->LinkChngMode =
+ T3_LINK_CHNG_MODE_USE_STATUS_REG;
+ } else {
+ pDevice->LinkChngMode =
+ T3_LINK_CHNG_MODE_USE_STATUS_BLOCK;
+ }
}
- else
- {
- pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_BLOCK;
+
+ if (pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT ||
+ T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
+ pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_REG;
}
- }
- if(pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT ||
- T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
- {
- pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_REG;
- }
+ /* Configure PHY led mode. */
+ if (pDevice->LedMode == LED_MODE_AUTO) {
+ if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
+ T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
+ if (pDevice->SubsystemVendorId == T3_SVID_DELL) {
+ pDevice->LedMode = LED_MODE_LINK10;
+ } else {
+ pDevice->LedMode = LED_MODE_THREE_LINK;
- /* Configure PHY led mode. */
- if(pDevice->LedMode == LED_MODE_AUTO)
- {
- if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
- T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)
- {
- if(pDevice->SubsystemVendorId == T3_SVID_DELL)
- {
- pDevice->LedMode = LED_MODE_LINK10;
- }
- else
- {
- pDevice->LedMode = LED_MODE_THREE_LINK;
-
- if(EeSigFound && EePhyLedMode != LED_MODE_AUTO)
- {
- pDevice->LedMode = EePhyLedMode;
- }
- }
-
- /* bug? 5701 in LINK10 mode does not seem to work when */
- /* PhyIntMode is LINK_READY. */
- if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700 &&
+ if (EeSigFound && EePhyLedMode != LED_MODE_AUTO) {
+ pDevice->LedMode = EePhyLedMode;
+ }
+ }
+
+ /* bug? 5701 in LINK10 mode does not seem to work when */
+ /* PhyIntMode is LINK_READY. */
+ if (T3_ASIC_REV (pDevice->ChipRevId) != T3_ASIC_REV_5700
+ &&
#if INCLUDE_TBI_SUPPORT
- pDevice->EnableTbi == FALSE &&
+ pDevice->EnableTbi == FALSE &&
#endif
- pDevice->LedMode == LED_MODE_LINK10)
- {
- pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT;
- pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_REG;
- }
+ pDevice->LedMode == LED_MODE_LINK10) {
+ pDevice->PhyIntMode =
+ T3_PHY_INT_MODE_MI_INTERRUPT;
+ pDevice->LinkChngMode =
+ T3_LINK_CHNG_MODE_USE_STATUS_REG;
+ }
+
+ if (pDevice->EnableTbi) {
+ pDevice->LedMode = LED_MODE_THREE_LINK;
+ }
+ } else {
+ if (EeSigFound && EePhyLedMode != LED_MODE_AUTO) {
+ pDevice->LedMode = EePhyLedMode;
+ } else {
+ pDevice->LedMode = LED_MODE_OPEN_DRAIN;
+ }
+ }
+ }
- if(pDevice->EnableTbi)
- {
- pDevice->LedMode = LED_MODE_THREE_LINK;
- }
+ /* Enable OneDmaAtOnce. */
+ if (pDevice->OneDmaAtOnce == BAD_DEFAULT_VALUE) {
+ pDevice->OneDmaAtOnce = FALSE;
}
- else
- {
- if(EeSigFound && EePhyLedMode != LED_MODE_AUTO)
- {
- pDevice->LedMode = EePhyLedMode;
- }
- else
- {
- pDevice->LedMode = LED_MODE_OPEN_DRAIN;
- }
- }
- }
-
- /* Enable OneDmaAtOnce. */
- if(pDevice->OneDmaAtOnce == BAD_DEFAULT_VALUE)
- {
- pDevice->OneDmaAtOnce = FALSE;
- }
-
- if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
- pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
- pDevice->ChipRevId == T3_CHIP_ID_5701_B0 ||
- pDevice->ChipRevId == T3_CHIP_ID_5701_B2)
- {
- pDevice->WolSpeed = WOL_SPEED_10MB;
- }
- else
- {
- pDevice->WolSpeed = WOL_SPEED_100MB;
- }
-
- /* Offloadings. */
- pDevice->TaskToOffload = LM_TASK_OFFLOAD_NONE;
-
- /* Turn off task offloading on Ax. */
- if(pDevice->ChipRevId == T3_CHIP_ID_5700_B0)
- {
- pDevice->TaskOffloadCap &= ~(LM_TASK_OFFLOAD_TX_TCP_CHECKSUM |
- LM_TASK_OFFLOAD_TX_UDP_CHECKSUM);
- }
- pDevice->PciState = REG_RD(pDevice, PciCfg.PciState);
- LM_ReadVPD(pDevice);
- LM_ReadBootCodeVersion(pDevice);
- LM_GetBusSpeed(pDevice);
-
- return LM_STATUS_SUCCESS;
-} /* LM_GetAdapterInfo */
-
-STATIC PLM_ADAPTER_INFO
-LM_GetAdapterInfoBySsid(
- LM_UINT16 Svid,
- LM_UINT16 Ssid)
+
+ if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
+ pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
+ pDevice->ChipRevId == T3_CHIP_ID_5701_B0 ||
+ pDevice->ChipRevId == T3_CHIP_ID_5701_B2) {
+ pDevice->WolSpeed = WOL_SPEED_10MB;
+ } else {
+ pDevice->WolSpeed = WOL_SPEED_100MB;
+ }
+
+ /* Offloadings. */
+ pDevice->TaskToOffload = LM_TASK_OFFLOAD_NONE;
+
+ /* Turn off task offloading on Ax. */
+ if (pDevice->ChipRevId == T3_CHIP_ID_5700_B0) {
+ pDevice->TaskOffloadCap &= ~(LM_TASK_OFFLOAD_TX_TCP_CHECKSUM |
+ LM_TASK_OFFLOAD_TX_UDP_CHECKSUM);
+ }
+ pDevice->PciState = REG_RD (pDevice, PciCfg.PciState);
+ LM_ReadVPD (pDevice);
+ LM_ReadBootCodeVersion (pDevice);
+ LM_GetBusSpeed (pDevice);
+
+ return LM_STATUS_SUCCESS;
+} /* LM_GetAdapterInfo */
+
+STATIC PLM_ADAPTER_INFO LM_GetAdapterInfoBySsid (LM_UINT16 Svid, LM_UINT16 Ssid)
{
- static LM_ADAPTER_INFO AdapterArr[] =
- {
- { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700A6, PHY_BCM5401_PHY_ID, 0},
- { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A5, PHY_BCM5701_PHY_ID, 0},
- { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700T6, PHY_BCM8002_PHY_ID, 1},
- { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700A9, 0, 1 },
- { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701T1, PHY_BCM5701_PHY_ID, 0},
- { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701T8, PHY_BCM5701_PHY_ID, 0},
- { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A7, 0, 1},
- { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A10, PHY_BCM5701_PHY_ID, 0},
- { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A12, PHY_BCM5701_PHY_ID, 0},
- { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95703Ax1, PHY_BCM5701_PHY_ID, 0},
- { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95703Ax2, PHY_BCM5701_PHY_ID, 0},
-
- { T3_SVID_3COM, T3_SSID_3COM_3C996T, PHY_BCM5401_PHY_ID, 0 },
- { T3_SVID_3COM, T3_SSID_3COM_3C996BT, PHY_BCM5701_PHY_ID, 0 },
- { T3_SVID_3COM, T3_SSID_3COM_3C996SX, 0, 1 },
- { T3_SVID_3COM, T3_SSID_3COM_3C1000T, PHY_BCM5701_PHY_ID, 0 },
- { T3_SVID_3COM, T3_SSID_3COM_3C940BR01, PHY_BCM5701_PHY_ID, 0 },
-
- { T3_SVID_DELL, T3_SSID_DELL_VIPER, PHY_BCM5401_PHY_ID, 0 },
- { T3_SVID_DELL, T3_SSID_DELL_JAGUAR, PHY_BCM5401_PHY_ID, 0 },
- { T3_SVID_DELL, T3_SSID_DELL_MERLOT, PHY_BCM5411_PHY_ID, 0 },
- { T3_SVID_DELL, T3_SSID_DELL_SLIM_MERLOT, PHY_BCM5411_PHY_ID, 0 },
-
- { T3_SVID_COMPAQ, T3_SSID_COMPAQ_BANSHEE, PHY_BCM5701_PHY_ID, 0 },
- { T3_SVID_COMPAQ, T3_SSID_COMPAQ_BANSHEE_2, PHY_BCM5701_PHY_ID, 0 },
- { T3_SVID_COMPAQ, T3_SSID_COMPAQ_CHANGELING, 0, 1 },
- { T3_SVID_COMPAQ, T3_SSID_COMPAQ_NC7780, PHY_BCM5701_PHY_ID, 0 },
- { T3_SVID_COMPAQ, T3_SSID_COMPAQ_NC7780_2, PHY_BCM5701_PHY_ID, 0 },
-
- };
- LM_UINT32 j;
-
- for(j = 0; j < sizeof(AdapterArr)/sizeof(LM_ADAPTER_INFO); j++)
- {
- if(AdapterArr[j].Svid == Svid && AdapterArr[j].Ssid == Ssid)
- {
- return &AdapterArr[j];
+ static LM_ADAPTER_INFO AdapterArr[] = {
+ {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700A6,
+ PHY_BCM5401_PHY_ID, 0},
+ {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A5,
+ PHY_BCM5701_PHY_ID, 0},
+ {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700T6,
+ PHY_BCM8002_PHY_ID, 1},
+ {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700A9, 0, 1},
+ {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701T1,
+ PHY_BCM5701_PHY_ID, 0},
+ {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701T8,
+ PHY_BCM5701_PHY_ID, 0},
+ {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A7, 0, 1},
+ {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A10,
+ PHY_BCM5701_PHY_ID, 0},
+ {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A12,
+ PHY_BCM5701_PHY_ID, 0},
+ {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95703Ax1,
+ PHY_BCM5701_PHY_ID, 0},
+ {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95703Ax2,
+ PHY_BCM5701_PHY_ID, 0},
+
+ {T3_SVID_3COM, T3_SSID_3COM_3C996T, PHY_BCM5401_PHY_ID, 0},
+ {T3_SVID_3COM, T3_SSID_3COM_3C996BT, PHY_BCM5701_PHY_ID, 0},
+ {T3_SVID_3COM, T3_SSID_3COM_3C996SX, 0, 1},
+ {T3_SVID_3COM, T3_SSID_3COM_3C1000T, PHY_BCM5701_PHY_ID, 0},
+ {T3_SVID_3COM, T3_SSID_3COM_3C940BR01, PHY_BCM5701_PHY_ID, 0},
+
+ {T3_SVID_DELL, T3_SSID_DELL_VIPER, PHY_BCM5401_PHY_ID, 0},
+ {T3_SVID_DELL, T3_SSID_DELL_JAGUAR, PHY_BCM5401_PHY_ID, 0},
+ {T3_SVID_DELL, T3_SSID_DELL_MERLOT, PHY_BCM5411_PHY_ID, 0},
+ {T3_SVID_DELL, T3_SSID_DELL_SLIM_MERLOT, PHY_BCM5411_PHY_ID, 0},
+
+ {T3_SVID_COMPAQ, T3_SSID_COMPAQ_BANSHEE, PHY_BCM5701_PHY_ID, 0},
+ {T3_SVID_COMPAQ, T3_SSID_COMPAQ_BANSHEE_2, PHY_BCM5701_PHY_ID,
+ 0},
+ {T3_SVID_COMPAQ, T3_SSID_COMPAQ_CHANGELING, 0, 1},
+ {T3_SVID_COMPAQ, T3_SSID_COMPAQ_NC7780, PHY_BCM5701_PHY_ID, 0},
+ {T3_SVID_COMPAQ, T3_SSID_COMPAQ_NC7780_2, PHY_BCM5701_PHY_ID,
+ 0},
+
+ };
+ LM_UINT32 j;
+
+ for (j = 0; j < sizeof (AdapterArr) / sizeof (LM_ADAPTER_INFO); j++) {
+ if (AdapterArr[j].Svid == Svid && AdapterArr[j].Ssid == Ssid) {
+ return &AdapterArr[j];
+ }
}
- }
- return NULL;
+ return NULL;
}
-
/******************************************************************************/
/* Description: */
/* This routine sets up receive/transmit buffer descriptions queues. */
@@ -1638,237 +1489,226 @@ LM_GetAdapterInfoBySsid(
/* Return: */
/* LM_STATUS_SUCCESS */
/******************************************************************************/
-LM_STATUS
-LM_InitializeAdapter(
-PLM_DEVICE_BLOCK pDevice)
+LM_STATUS LM_InitializeAdapter (PLM_DEVICE_BLOCK pDevice)
{
- LM_PHYSICAL_ADDRESS MemPhy;
- PLM_UINT8 pMemVirt;
- PLM_PACKET pPacket;
- LM_STATUS Status;
- LM_UINT32 Size;
- LM_UINT32 j;
-
- /* Set power state to D0. */
- LM_SetPowerState(pDevice, LM_POWER_STATE_D0);
-
- /* Intialize the queues. */
- QQ_InitQueue(&pDevice->RxPacketReceivedQ.Container,
- MAX_RX_PACKET_DESC_COUNT);
- QQ_InitQueue(&pDevice->RxPacketFreeQ.Container,
- MAX_RX_PACKET_DESC_COUNT);
-
- QQ_InitQueue(&pDevice->TxPacketFreeQ.Container,MAX_TX_PACKET_DESC_COUNT);
- QQ_InitQueue(&pDevice->TxPacketActiveQ.Container,MAX_TX_PACKET_DESC_COUNT);
- QQ_InitQueue(&pDevice->TxPacketXmittedQ.Container,MAX_TX_PACKET_DESC_COUNT);
-
- /* Allocate shared memory for: status block, the buffers for receive */
- /* rings -- standard, mini, jumbo, and return rings. */
- Size = T3_STATUS_BLOCK_SIZE + sizeof(T3_STATS_BLOCK) +
- T3_STD_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD) +
+ LM_PHYSICAL_ADDRESS MemPhy;
+ PLM_UINT8 pMemVirt;
+ PLM_PACKET pPacket;
+ LM_STATUS Status;
+ LM_UINT32 Size;
+ LM_UINT32 j;
+
+ /* Set power state to D0. */
+ LM_SetPowerState (pDevice, LM_POWER_STATE_D0);
+
+ /* Intialize the queues. */
+ QQ_InitQueue (&pDevice->RxPacketReceivedQ.Container,
+ MAX_RX_PACKET_DESC_COUNT);
+ QQ_InitQueue (&pDevice->RxPacketFreeQ.Container,
+ MAX_RX_PACKET_DESC_COUNT);
+
+ QQ_InitQueue (&pDevice->TxPacketFreeQ.Container,
+ MAX_TX_PACKET_DESC_COUNT);
+ QQ_InitQueue (&pDevice->TxPacketActiveQ.Container,
+ MAX_TX_PACKET_DESC_COUNT);
+ QQ_InitQueue (&pDevice->TxPacketXmittedQ.Container,
+ MAX_TX_PACKET_DESC_COUNT);
+
+ /* Allocate shared memory for: status block, the buffers for receive */
+ /* rings -- standard, mini, jumbo, and return rings. */
+ Size = T3_STATUS_BLOCK_SIZE + sizeof (T3_STATS_BLOCK) +
+ T3_STD_RCV_RCB_ENTRY_COUNT * sizeof (T3_RCV_BD) +
#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
- T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD) +
-#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
- T3_RCV_RETURN_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD);
-
- /* Memory for host based Send BD. */
- if(pDevice->NicSendBd == FALSE)
- {
- Size += sizeof(T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT;
- }
-
- /* Allocate the memory block. */
- Status = MM_AllocateSharedMemory(pDevice, Size, (PLM_VOID) &pMemVirt, &MemPhy, FALSE);
- if(Status != LM_STATUS_SUCCESS)
- {
- return Status;
- }
-
- /* Program DMA Read/Write */
- if (pDevice->PciState & T3_PCI_STATE_NOT_PCI_X_BUS)
- {
- pDevice->DmaReadWriteCtrl = 0x763f000f;
- }
- else
- {
- if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704)
- {
- pDevice->DmaReadWriteCtrl = 0x761f0000;
+ T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof (T3_RCV_BD) +
+#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
+ T3_RCV_RETURN_RCB_ENTRY_COUNT * sizeof (T3_RCV_BD);
+
+ /* Memory for host based Send BD. */
+ if (pDevice->NicSendBd == FALSE) {
+ Size += sizeof (T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT;
+ }
+
+ /* Allocate the memory block. */
+ Status =
+ MM_AllocateSharedMemory (pDevice, Size, (PLM_VOID) & pMemVirt,
+ &MemPhy, FALSE);
+ if (Status != LM_STATUS_SUCCESS) {
+ return Status;
+ }
+
+ /* Program DMA Read/Write */
+ if (pDevice->PciState & T3_PCI_STATE_NOT_PCI_X_BUS) {
+ pDevice->DmaReadWriteCtrl = 0x763f000f;
+ } else {
+ if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5704) {
+ pDevice->DmaReadWriteCtrl = 0x761f0000;
+ } else {
+ pDevice->DmaReadWriteCtrl = 0x761b000f;
+ }
+ if (pDevice->ChipRevId == T3_CHIP_ID_5703_A1 ||
+ pDevice->ChipRevId == T3_CHIP_ID_5703_A2) {
+ pDevice->OneDmaAtOnce = TRUE;
+ }
}
- else
- {
- pDevice->DmaReadWriteCtrl = 0x761b000f;
+ if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5703) {
+ pDevice->DmaReadWriteCtrl &= 0xfffffff0;
}
- if(pDevice->ChipRevId == T3_CHIP_ID_5703_A1 ||
- pDevice->ChipRevId == T3_CHIP_ID_5703_A2)
- {
- pDevice->OneDmaAtOnce = TRUE;
- }
- }
- if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703)
- {
- pDevice->DmaReadWriteCtrl &= 0xfffffff0;
- }
-
- if(pDevice->OneDmaAtOnce)
- {
- pDevice->DmaReadWriteCtrl |= DMA_CTRL_WRITE_ONE_DMA_AT_ONCE;
- }
- REG_WR(pDevice, PciCfg.DmaReadWriteCtrl, pDevice->DmaReadWriteCtrl);
-
- if (LM_DmaTest(pDevice, pMemVirt, MemPhy, 0x400) != LM_STATUS_SUCCESS)
- {
- return LM_STATUS_FAILURE;
- }
- /* Status block. */
- pDevice->pStatusBlkVirt = (PT3_STATUS_BLOCK) pMemVirt;
- pDevice->StatusBlkPhy = MemPhy;
- pMemVirt += T3_STATUS_BLOCK_SIZE;
- LM_INC_PHYSICAL_ADDRESS(&MemPhy, T3_STATUS_BLOCK_SIZE);
+ if (pDevice->OneDmaAtOnce) {
+ pDevice->DmaReadWriteCtrl |= DMA_CTRL_WRITE_ONE_DMA_AT_ONCE;
+ }
+ REG_WR (pDevice, PciCfg.DmaReadWriteCtrl, pDevice->DmaReadWriteCtrl);
+
+ if (LM_DmaTest (pDevice, pMemVirt, MemPhy, 0x400) != LM_STATUS_SUCCESS) {
+ return LM_STATUS_FAILURE;
+ }
- /* Statistics block. */
- pDevice->pStatsBlkVirt = (PT3_STATS_BLOCK) pMemVirt;
- pDevice->StatsBlkPhy = MemPhy;
- pMemVirt += sizeof(T3_STATS_BLOCK);
- LM_INC_PHYSICAL_ADDRESS(&MemPhy, sizeof(T3_STATS_BLOCK));
+ /* Status block. */
+ pDevice->pStatusBlkVirt = (PT3_STATUS_BLOCK) pMemVirt;
+ pDevice->StatusBlkPhy = MemPhy;
+ pMemVirt += T3_STATUS_BLOCK_SIZE;
+ LM_INC_PHYSICAL_ADDRESS (&MemPhy, T3_STATUS_BLOCK_SIZE);
- /* Receive standard BD buffer. */
- pDevice->pRxStdBdVirt = (PT3_RCV_BD) pMemVirt;
- pDevice->RxStdBdPhy = MemPhy;
+ /* Statistics block. */
+ pDevice->pStatsBlkVirt = (PT3_STATS_BLOCK) pMemVirt;
+ pDevice->StatsBlkPhy = MemPhy;
+ pMemVirt += sizeof (T3_STATS_BLOCK);
+ LM_INC_PHYSICAL_ADDRESS (&MemPhy, sizeof (T3_STATS_BLOCK));
- pMemVirt += T3_STD_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD);
- LM_INC_PHYSICAL_ADDRESS(&MemPhy,
- T3_STD_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD));
+ /* Receive standard BD buffer. */
+ pDevice->pRxStdBdVirt = (PT3_RCV_BD) pMemVirt;
+ pDevice->RxStdBdPhy = MemPhy;
+
+ pMemVirt += T3_STD_RCV_RCB_ENTRY_COUNT * sizeof (T3_RCV_BD);
+ LM_INC_PHYSICAL_ADDRESS (&MemPhy,
+ T3_STD_RCV_RCB_ENTRY_COUNT *
+ sizeof (T3_RCV_BD));
#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
- /* Receive jumbo BD buffer. */
- pDevice->pRxJumboBdVirt = (PT3_RCV_BD) pMemVirt;
- pDevice->RxJumboBdPhy = MemPhy;
-
- pMemVirt += T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD);
- LM_INC_PHYSICAL_ADDRESS(&MemPhy,
- T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD));
-#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
-
- /* Receive return BD buffer. */
- pDevice->pRcvRetBdVirt = (PT3_RCV_BD) pMemVirt;
- pDevice->RcvRetBdPhy = MemPhy;
-
- pMemVirt += T3_RCV_RETURN_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD);
- LM_INC_PHYSICAL_ADDRESS(&MemPhy,
- T3_RCV_RETURN_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD));
-
- /* Set up Send BD. */
- if(pDevice->NicSendBd == FALSE)
- {
- pDevice->pSendBdVirt = (PT3_SND_BD) pMemVirt;
- pDevice->SendBdPhy = MemPhy;
-
- pMemVirt += sizeof(T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT;
- LM_INC_PHYSICAL_ADDRESS(&MemPhy,
- sizeof(T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT);
- }
- else
- {
- pDevice->pSendBdVirt = (PT3_SND_BD)
- pDevice->pMemView->uIntMem.First32k.BufferDesc;
- pDevice->SendBdPhy.High = 0;
- pDevice->SendBdPhy.Low = T3_NIC_SND_BUFFER_DESC_ADDR;
- }
-
- /* Allocate memory for packet descriptors. */
- Size = (pDevice->RxPacketDescCnt +
- pDevice->TxPacketDescCnt) * MM_PACKET_DESC_SIZE;
- Status = MM_AllocateMemory(pDevice, Size, (PLM_VOID *) &pPacket);
- if(Status != LM_STATUS_SUCCESS)
- {
- return Status;
- }
- pDevice->pPacketDescBase = (PLM_VOID) pPacket;
-
- /* Create transmit packet descriptors from the memory block and add them */
- /* to the TxPacketFreeQ for each send ring. */
- for(j = 0; j < pDevice->TxPacketDescCnt; j++)
- {
- /* Ring index. */
- pPacket->Flags = 0;
-
- /* Queue the descriptor in the TxPacketFreeQ of the 'k' ring. */
- QQ_PushTail(&pDevice->TxPacketFreeQ.Container, pPacket);
-
- /* Get the pointer to the next descriptor. MM_PACKET_DESC_SIZE */
- /* is the total size of the packet descriptor including the */
- /* os-specific extensions in the UM_PACKET structure. */
- pPacket = (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE);
- } /* for(j.. */
-
- /* Create receive packet descriptors from the memory block and add them */
- /* to the RxPacketFreeQ. Create the Standard packet descriptors. */
- for(j = 0; j < pDevice->RxStdDescCnt; j++)
- {
- /* Receive producer ring. */
- pPacket->u.Rx.RcvProdRing = T3_STD_RCV_PROD_RING;
-
- /* Receive buffer size. */
- pPacket->u.Rx.RxBufferSize = MAX_STD_RCV_BUFFER_SIZE;
-
- /* Add the descriptor to RxPacketFreeQ. */
- QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
-
- /* Get the pointer to the next descriptor. MM_PACKET_DESC_SIZE */
- /* is the total size of the packet descriptor including the */
- /* os-specific extensions in the UM_PACKET structure. */
- pPacket = (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE);
- } /* for */
+ /* Receive jumbo BD buffer. */
+ pDevice->pRxJumboBdVirt = (PT3_RCV_BD) pMemVirt;
+ pDevice->RxJumboBdPhy = MemPhy;
+
+ pMemVirt += T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof (T3_RCV_BD);
+ LM_INC_PHYSICAL_ADDRESS (&MemPhy,
+ T3_JUMBO_RCV_RCB_ENTRY_COUNT *
+ sizeof (T3_RCV_BD));
+#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
+
+ /* Receive return BD buffer. */
+ pDevice->pRcvRetBdVirt = (PT3_RCV_BD) pMemVirt;
+ pDevice->RcvRetBdPhy = MemPhy;
+
+ pMemVirt += T3_RCV_RETURN_RCB_ENTRY_COUNT * sizeof (T3_RCV_BD);
+ LM_INC_PHYSICAL_ADDRESS (&MemPhy,
+ T3_RCV_RETURN_RCB_ENTRY_COUNT *
+ sizeof (T3_RCV_BD));
+
+ /* Set up Send BD. */
+ if (pDevice->NicSendBd == FALSE) {
+ pDevice->pSendBdVirt = (PT3_SND_BD) pMemVirt;
+ pDevice->SendBdPhy = MemPhy;
+
+ pMemVirt += sizeof (T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT;
+ LM_INC_PHYSICAL_ADDRESS (&MemPhy,
+ sizeof (T3_SND_BD) *
+ T3_SEND_RCB_ENTRY_COUNT);
+ } else {
+ pDevice->pSendBdVirt = (PT3_SND_BD)
+ pDevice->pMemView->uIntMem.First32k.BufferDesc;
+ pDevice->SendBdPhy.High = 0;
+ pDevice->SendBdPhy.Low = T3_NIC_SND_BUFFER_DESC_ADDR;
+ }
+
+ /* Allocate memory for packet descriptors. */
+ Size = (pDevice->RxPacketDescCnt +
+ pDevice->TxPacketDescCnt) * MM_PACKET_DESC_SIZE;
+ Status = MM_AllocateMemory (pDevice, Size, (PLM_VOID *) & pPacket);
+ if (Status != LM_STATUS_SUCCESS) {
+ return Status;
+ }
+ pDevice->pPacketDescBase = (PLM_VOID) pPacket;
+
+ /* Create transmit packet descriptors from the memory block and add them */
+ /* to the TxPacketFreeQ for each send ring. */
+ for (j = 0; j < pDevice->TxPacketDescCnt; j++) {
+ /* Ring index. */
+ pPacket->Flags = 0;
+
+ /* Queue the descriptor in the TxPacketFreeQ of the 'k' ring. */
+ QQ_PushTail (&pDevice->TxPacketFreeQ.Container, pPacket);
+
+ /* Get the pointer to the next descriptor. MM_PACKET_DESC_SIZE */
+ /* is the total size of the packet descriptor including the */
+ /* os-specific extensions in the UM_PACKET structure. */
+ pPacket =
+ (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE);
+ } /* for(j.. */
+
+ /* Create receive packet descriptors from the memory block and add them */
+ /* to the RxPacketFreeQ. Create the Standard packet descriptors. */
+ for (j = 0; j < pDevice->RxStdDescCnt; j++) {
+ /* Receive producer ring. */
+ pPacket->u.Rx.RcvProdRing = T3_STD_RCV_PROD_RING;
+
+ /* Receive buffer size. */
+ pPacket->u.Rx.RxBufferSize = MAX_STD_RCV_BUFFER_SIZE;
+
+ /* Add the descriptor to RxPacketFreeQ. */
+ QQ_PushTail (&pDevice->RxPacketFreeQ.Container, pPacket);
+
+ /* Get the pointer to the next descriptor. MM_PACKET_DESC_SIZE */
+ /* is the total size of the packet descriptor including the */
+ /* os-specific extensions in the UM_PACKET structure. */
+ pPacket =
+ (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE);
+ } /* for */
#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
- /* Create the Jumbo packet descriptors. */
- for(j = 0; j < pDevice->RxJumboDescCnt; j++)
- {
- /* Receive producer ring. */
- pPacket->u.Rx.RcvProdRing = T3_JUMBO_RCV_PROD_RING;
-
- /* Receive buffer size. */
- pPacket->u.Rx.RxBufferSize = pDevice->RxJumboBufferSize;
-
- /* Add the descriptor to RxPacketFreeQ. */
- QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
-
- /* Get the pointer to the next descriptor. MM_PACKET_DESC_SIZE */
- /* is the total size of the packet descriptor including the */
- /* os-specific extensions in the UM_PACKET structure. */
- pPacket = (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE);
- } /* for */
-#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
-
- /* Initialize the rest of the packet descriptors. */
- Status = MM_InitializeUmPackets(pDevice);
- if(Status != LM_STATUS_SUCCESS)
- {
- return Status;
- } /* if */
+ /* Create the Jumbo packet descriptors. */
+ for (j = 0; j < pDevice->RxJumboDescCnt; j++) {
+ /* Receive producer ring. */
+ pPacket->u.Rx.RcvProdRing = T3_JUMBO_RCV_PROD_RING;
- /* Default receive mask. */
- pDevice->ReceiveMask = LM_ACCEPT_MULTICAST | LM_ACCEPT_BROADCAST |
- LM_ACCEPT_UNICAST;
+ /* Receive buffer size. */
+ pPacket->u.Rx.RxBufferSize = pDevice->RxJumboBufferSize;
- /* Make sure we are in the first 32k memory window or NicSendBd. */
- REG_WR(pDevice, PciCfg.MemWindowBaseAddr, 0);
+ /* Add the descriptor to RxPacketFreeQ. */
+ QQ_PushTail (&pDevice->RxPacketFreeQ.Container, pPacket);
- /* Initialize the hardware. */
- Status = LM_ResetAdapter(pDevice);
- if(Status != LM_STATUS_SUCCESS)
- {
- return Status;
- }
+ /* Get the pointer to the next descriptor. MM_PACKET_DESC_SIZE */
+ /* is the total size of the packet descriptor including the */
+ /* os-specific extensions in the UM_PACKET structure. */
+ pPacket =
+ (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE);
+ } /* for */
+#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
+
+ /* Initialize the rest of the packet descriptors. */
+ Status = MM_InitializeUmPackets (pDevice);
+ if (Status != LM_STATUS_SUCCESS) {
+ return Status;
+ }
- /* We are done with initialization. */
- pDevice->InitDone = TRUE;
+ /* if */
+ /* Default receive mask. */
+ pDevice->ReceiveMask = LM_ACCEPT_MULTICAST | LM_ACCEPT_BROADCAST |
+ LM_ACCEPT_UNICAST;
- return LM_STATUS_SUCCESS;
-} /* LM_InitializeAdapter */
+ /* Make sure we are in the first 32k memory window or NicSendBd. */
+ REG_WR (pDevice, PciCfg.MemWindowBaseAddr, 0);
+ /* Initialize the hardware. */
+ Status = LM_ResetAdapter (pDevice);
+ if (Status != LM_STATUS_SUCCESS) {
+ return Status;
+ }
+
+ /* We are done with initialization. */
+ pDevice->InitDone = TRUE;
+
+ return LM_STATUS_SUCCESS;
+} /* LM_InitializeAdapter */
/******************************************************************************/
/* Description: */
@@ -1878,414 +1718,408 @@ PLM_DEVICE_BLOCK pDevice)
/* LM_STATUS_SUCCESS */
/******************************************************************************/
LM_STATUS
-LM_CntrlBlock(
-PLM_DEVICE_BLOCK pDevice,
-LM_UINT32 mask,LM_UINT32 cntrl)
+LM_CntrlBlock (PLM_DEVICE_BLOCK pDevice, LM_UINT32 mask, LM_UINT32 cntrl)
{
- LM_UINT32 j,i,data;
- LM_UINT32 MaxWaitCnt;
-
- MaxWaitCnt = 2;
- j = 0;
-
- for(i = 0 ; i < 32; i++)
- {
- if(!(mask & (1 << i)))
- continue;
-
- switch (1 << i)
- {
- case T3_BLOCK_DMA_RD:
- data = REG_RD(pDevice, DmaRead.Mode);
- if (cntrl == LM_DISABLE)
- {
- data &= ~DMA_READ_MODE_ENABLE;
- REG_WR(pDevice, DmaRead.Mode, data);
- for(j = 0; j < MaxWaitCnt; j++)
- {
- if(!(REG_RD(pDevice, DmaRead.Mode) & DMA_READ_MODE_ENABLE))
- break;
- MM_Wait(10);
- }
- }
- else
- REG_WR(pDevice, DmaRead.Mode, data | DMA_READ_MODE_ENABLE);
- break;
-
- case T3_BLOCK_DMA_COMP:
- data = REG_RD(pDevice,DmaComp.Mode);
- if (cntrl == LM_DISABLE)
- {
- data &= ~DMA_COMP_MODE_ENABLE;
- REG_WR(pDevice, DmaComp.Mode, data);
- for(j = 0; j < MaxWaitCnt; j++)
- {
- if(!(REG_RD(pDevice, DmaComp.Mode) & DMA_COMP_MODE_ENABLE))
- break;
- MM_Wait(10);
- }
- }
- else
- REG_WR(pDevice, DmaComp.Mode, data | DMA_COMP_MODE_ENABLE);
- break;
+ LM_UINT32 j, i, data;
+ LM_UINT32 MaxWaitCnt;
+
+ MaxWaitCnt = 2;
+ j = 0;
+
+ for (i = 0; i < 32; i++) {
+ if (!(mask & (1 << i)))
+ continue;
+
+ switch (1 << i) {
+ case T3_BLOCK_DMA_RD:
+ data = REG_RD (pDevice, DmaRead.Mode);
+ if (cntrl == LM_DISABLE) {
+ data &= ~DMA_READ_MODE_ENABLE;
+ REG_WR (pDevice, DmaRead.Mode, data);
+ for (j = 0; j < MaxWaitCnt; j++) {
+ if (!
+ (REG_RD (pDevice, DmaRead.Mode) &
+ DMA_READ_MODE_ENABLE))
+ break;
+ MM_Wait (10);
+ }
+ } else
+ REG_WR (pDevice, DmaRead.Mode,
+ data | DMA_READ_MODE_ENABLE);
+ break;
- case T3_BLOCK_RX_BD_INITIATOR:
- data = REG_RD(pDevice, RcvBdIn.Mode);
- if (cntrl == LM_DISABLE)
- {
- data &= ~RCV_BD_IN_MODE_ENABLE;
- REG_WR(pDevice, RcvBdIn.Mode,data);
- for(j = 0; j < MaxWaitCnt; j++)
- {
- if(!(REG_RD(pDevice, RcvBdIn.Mode) & RCV_BD_IN_MODE_ENABLE))
- break;
- MM_Wait(10);
- }
- }
- else
- REG_WR(pDevice, RcvBdIn.Mode,data | RCV_BD_IN_MODE_ENABLE);
- break;
+ case T3_BLOCK_DMA_COMP:
+ data = REG_RD (pDevice, DmaComp.Mode);
+ if (cntrl == LM_DISABLE) {
+ data &= ~DMA_COMP_MODE_ENABLE;
+ REG_WR (pDevice, DmaComp.Mode, data);
+ for (j = 0; j < MaxWaitCnt; j++) {
+ if (!
+ (REG_RD (pDevice, DmaComp.Mode) &
+ DMA_COMP_MODE_ENABLE))
+ break;
+ MM_Wait (10);
+ }
+ } else
+ REG_WR (pDevice, DmaComp.Mode,
+ data | DMA_COMP_MODE_ENABLE);
+ break;
- case T3_BLOCK_RX_BD_COMP:
- data = REG_RD(pDevice, RcvBdComp.Mode);
- if (cntrl == LM_DISABLE)
- {
- data &= ~RCV_BD_COMP_MODE_ENABLE;
- REG_WR(pDevice, RcvBdComp.Mode,data);
- for(j = 0; j < MaxWaitCnt; j++)
- {
- if(!(REG_RD(pDevice, RcvBdComp.Mode) & RCV_BD_COMP_MODE_ENABLE))
- break;
- MM_Wait(10);
- }
- }
- else
- REG_WR(pDevice, RcvBdComp.Mode,data | RCV_BD_COMP_MODE_ENABLE);
- break;
+ case T3_BLOCK_RX_BD_INITIATOR:
+ data = REG_RD (pDevice, RcvBdIn.Mode);
+ if (cntrl == LM_DISABLE) {
+ data &= ~RCV_BD_IN_MODE_ENABLE;
+ REG_WR (pDevice, RcvBdIn.Mode, data);
+ for (j = 0; j < MaxWaitCnt; j++) {
+ if (!
+ (REG_RD (pDevice, RcvBdIn.Mode) &
+ RCV_BD_IN_MODE_ENABLE))
+ break;
+ MM_Wait (10);
+ }
+ } else
+ REG_WR (pDevice, RcvBdIn.Mode,
+ data | RCV_BD_IN_MODE_ENABLE);
+ break;
- case T3_BLOCK_DMA_WR:
- data = REG_RD(pDevice, DmaWrite.Mode);
- if (cntrl == LM_DISABLE)
- {
- data &= ~DMA_WRITE_MODE_ENABLE;
- REG_WR(pDevice, DmaWrite.Mode,data);
+ case T3_BLOCK_RX_BD_COMP:
+ data = REG_RD (pDevice, RcvBdComp.Mode);
+ if (cntrl == LM_DISABLE) {
+ data &= ~RCV_BD_COMP_MODE_ENABLE;
+ REG_WR (pDevice, RcvBdComp.Mode, data);
+ for (j = 0; j < MaxWaitCnt; j++) {
+ if (!
+ (REG_RD (pDevice, RcvBdComp.Mode) &
+ RCV_BD_COMP_MODE_ENABLE))
+ break;
+ MM_Wait (10);
+ }
+ } else
+ REG_WR (pDevice, RcvBdComp.Mode,
+ data | RCV_BD_COMP_MODE_ENABLE);
+ break;
- for(j = 0; j < MaxWaitCnt; j++)
- {
- if(!(REG_RD(pDevice, DmaWrite.Mode) & DMA_WRITE_MODE_ENABLE))
- break;
- MM_Wait(10);
- }
- }
- else
- REG_WR(pDevice, DmaWrite.Mode,data | DMA_WRITE_MODE_ENABLE);
- break;
+ case T3_BLOCK_DMA_WR:
+ data = REG_RD (pDevice, DmaWrite.Mode);
+ if (cntrl == LM_DISABLE) {
+ data &= ~DMA_WRITE_MODE_ENABLE;
+ REG_WR (pDevice, DmaWrite.Mode, data);
+
+ for (j = 0; j < MaxWaitCnt; j++) {
+ if (!
+ (REG_RD (pDevice, DmaWrite.Mode) &
+ DMA_WRITE_MODE_ENABLE))
+ break;
+ MM_Wait (10);
+ }
+ } else
+ REG_WR (pDevice, DmaWrite.Mode,
+ data | DMA_WRITE_MODE_ENABLE);
+ break;
- case T3_BLOCK_MSI_HANDLER:
- data = REG_RD(pDevice, Msi.Mode);
- if (cntrl == LM_DISABLE)
- {
- data &= ~MSI_MODE_ENABLE;
- REG_WR(pDevice, Msi.Mode, data);
- for(j = 0; j < MaxWaitCnt; j++)
- {
- if(!(REG_RD(pDevice, Msi.Mode) & MSI_MODE_ENABLE))
- break;
- MM_Wait(10);
- }
- }
- else
- REG_WR(pDevice, Msi.Mode, data |MSI_MODE_ENABLE);
- break;
+ case T3_BLOCK_MSI_HANDLER:
+ data = REG_RD (pDevice, Msi.Mode);
+ if (cntrl == LM_DISABLE) {
+ data &= ~MSI_MODE_ENABLE;
+ REG_WR (pDevice, Msi.Mode, data);
+ for (j = 0; j < MaxWaitCnt; j++) {
+ if (!
+ (REG_RD (pDevice, Msi.Mode) &
+ MSI_MODE_ENABLE))
+ break;
+ MM_Wait (10);
+ }
+ } else
+ REG_WR (pDevice, Msi.Mode,
+ data | MSI_MODE_ENABLE);
+ break;
- case T3_BLOCK_RX_LIST_PLMT:
- data = REG_RD(pDevice, RcvListPlmt.Mode);
- if (cntrl == LM_DISABLE)
- {
- data &= ~RCV_LIST_PLMT_MODE_ENABLE;
- REG_WR(pDevice, RcvListPlmt.Mode,data);
- for(j = 0; j < MaxWaitCnt; j++)
- {
- if(!(REG_RD(pDevice, RcvListPlmt.Mode) & RCV_LIST_PLMT_MODE_ENABLE))
- break;
- MM_Wait(10);
- }
- }
- else
- REG_WR(pDevice, RcvListPlmt.Mode,data | RCV_LIST_PLMT_MODE_ENABLE);
- break;
+ case T3_BLOCK_RX_LIST_PLMT:
+ data = REG_RD (pDevice, RcvListPlmt.Mode);
+ if (cntrl == LM_DISABLE) {
+ data &= ~RCV_LIST_PLMT_MODE_ENABLE;
+ REG_WR (pDevice, RcvListPlmt.Mode, data);
+ for (j = 0; j < MaxWaitCnt; j++) {
+ if (!
+ (REG_RD (pDevice, RcvListPlmt.Mode)
+ & RCV_LIST_PLMT_MODE_ENABLE))
+ break;
+ MM_Wait (10);
+ }
+ } else
+ REG_WR (pDevice, RcvListPlmt.Mode,
+ data | RCV_LIST_PLMT_MODE_ENABLE);
+ break;
- case T3_BLOCK_RX_LIST_SELECTOR:
- data = REG_RD(pDevice, RcvListSel.Mode);
- if (cntrl == LM_DISABLE)
- {
- data &= ~RCV_LIST_SEL_MODE_ENABLE;
- REG_WR(pDevice, RcvListSel.Mode,data);
- for(j = 0; j < MaxWaitCnt; j++)
- {
- if(!(REG_RD(pDevice, RcvListSel.Mode) & RCV_LIST_SEL_MODE_ENABLE))
- break;
- MM_Wait(10);
- }
- }
- else
- REG_WR(pDevice, RcvListSel.Mode,data |RCV_LIST_SEL_MODE_ENABLE);
- break;
+ case T3_BLOCK_RX_LIST_SELECTOR:
+ data = REG_RD (pDevice, RcvListSel.Mode);
+ if (cntrl == LM_DISABLE) {
+ data &= ~RCV_LIST_SEL_MODE_ENABLE;
+ REG_WR (pDevice, RcvListSel.Mode, data);
+ for (j = 0; j < MaxWaitCnt; j++) {
+ if (!
+ (REG_RD (pDevice, RcvListSel.Mode) &
+ RCV_LIST_SEL_MODE_ENABLE))
+ break;
+ MM_Wait (10);
+ }
+ } else
+ REG_WR (pDevice, RcvListSel.Mode,
+ data | RCV_LIST_SEL_MODE_ENABLE);
+ break;
- case T3_BLOCK_RX_DATA_INITIATOR:
- data = REG_RD(pDevice, RcvDataBdIn.Mode);
- if (cntrl == LM_DISABLE)
- {
- data &= ~RCV_DATA_BD_IN_MODE_ENABLE;
- REG_WR(pDevice, RcvDataBdIn.Mode,data);
- for(j = 0; j < MaxWaitCnt; j++)
- {
- if(!(REG_RD(pDevice, RcvDataBdIn.Mode) & RCV_DATA_BD_IN_MODE_ENABLE))
- break;
- MM_Wait(10);
- }
- }
- else
- REG_WR(pDevice, RcvDataBdIn.Mode, data | RCV_DATA_BD_IN_MODE_ENABLE);
- break;
+ case T3_BLOCK_RX_DATA_INITIATOR:
+ data = REG_RD (pDevice, RcvDataBdIn.Mode);
+ if (cntrl == LM_DISABLE) {
+ data &= ~RCV_DATA_BD_IN_MODE_ENABLE;
+ REG_WR (pDevice, RcvDataBdIn.Mode, data);
+ for (j = 0; j < MaxWaitCnt; j++) {
+ if (!
+ (REG_RD (pDevice, RcvDataBdIn.Mode)
+ & RCV_DATA_BD_IN_MODE_ENABLE))
+ break;
+ MM_Wait (10);
+ }
+ } else
+ REG_WR (pDevice, RcvDataBdIn.Mode,
+ data | RCV_DATA_BD_IN_MODE_ENABLE);
+ break;
- case T3_BLOCK_RX_DATA_COMP:
- data = REG_RD(pDevice, RcvDataComp.Mode);
- if (cntrl == LM_DISABLE)
- {
- data &= ~RCV_DATA_COMP_MODE_ENABLE;
- REG_WR(pDevice, RcvDataComp.Mode,data);
- for(j = 0; j < MaxWaitCnt; j++)
- {
- if(!(REG_RD(pDevice, RcvDataBdIn.Mode) & RCV_DATA_COMP_MODE_ENABLE))
- break;
- MM_Wait(10);
- }
- }
- else
- REG_WR(pDevice, RcvDataComp.Mode,data | RCV_DATA_COMP_MODE_ENABLE);
- break;
+ case T3_BLOCK_RX_DATA_COMP:
+ data = REG_RD (pDevice, RcvDataComp.Mode);
+ if (cntrl == LM_DISABLE) {
+ data &= ~RCV_DATA_COMP_MODE_ENABLE;
+ REG_WR (pDevice, RcvDataComp.Mode, data);
+ for (j = 0; j < MaxWaitCnt; j++) {
+ if (!
+ (REG_RD (pDevice, RcvDataBdIn.Mode)
+ & RCV_DATA_COMP_MODE_ENABLE))
+ break;
+ MM_Wait (10);
+ }
+ } else
+ REG_WR (pDevice, RcvDataComp.Mode,
+ data | RCV_DATA_COMP_MODE_ENABLE);
+ break;
- case T3_BLOCK_HOST_COALESING:
- data = REG_RD(pDevice, HostCoalesce.Mode);
- if (cntrl == LM_DISABLE)
- {
- data &= ~HOST_COALESCE_ENABLE;
- REG_WR(pDevice, HostCoalesce.Mode, data);
- for(j = 0; j < MaxWaitCnt; j++)
- {
- if(!(REG_RD(pDevice, SndBdIn.Mode) & HOST_COALESCE_ENABLE))
- break;
- MM_Wait(10);
- }
- }
- else
- REG_WR(pDevice, HostCoalesce.Mode, data | HOST_COALESCE_ENABLE);
- break;
+ case T3_BLOCK_HOST_COALESING:
+ data = REG_RD (pDevice, HostCoalesce.Mode);
+ if (cntrl == LM_DISABLE) {
+ data &= ~HOST_COALESCE_ENABLE;
+ REG_WR (pDevice, HostCoalesce.Mode, data);
+ for (j = 0; j < MaxWaitCnt; j++) {
+ if (!
+ (REG_RD (pDevice, SndBdIn.Mode) &
+ HOST_COALESCE_ENABLE))
+ break;
+ MM_Wait (10);
+ }
+ } else
+ REG_WR (pDevice, HostCoalesce.Mode,
+ data | HOST_COALESCE_ENABLE);
+ break;
- case T3_BLOCK_MAC_RX_ENGINE:
- if(cntrl == LM_DISABLE)
- {
- pDevice->RxMode &= ~RX_MODE_ENABLE;
- REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode);
- for(j = 0; j < MaxWaitCnt; j++)
- {
- if(!(REG_RD(pDevice, MacCtrl.RxMode) & RX_MODE_ENABLE))
- {
- break;
+ case T3_BLOCK_MAC_RX_ENGINE:
+ if (cntrl == LM_DISABLE) {
+ pDevice->RxMode &= ~RX_MODE_ENABLE;
+ REG_WR (pDevice, MacCtrl.RxMode,
+ pDevice->RxMode);
+ for (j = 0; j < MaxWaitCnt; j++) {
+ if (!
+ (REG_RD (pDevice, MacCtrl.RxMode) &
+ RX_MODE_ENABLE)) {
+ break;
+ }
+ MM_Wait (10);
+ }
+ } else {
+ pDevice->RxMode |= RX_MODE_ENABLE;
+ REG_WR (pDevice, MacCtrl.RxMode,
+ pDevice->RxMode);
}
- MM_Wait(10);
- }
- }
- else
- {
- pDevice->RxMode |= RX_MODE_ENABLE;
- REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode);
- }
- break;
+ break;
- case T3_BLOCK_MBUF_CLUSTER_FREE:
- data = REG_RD(pDevice, MbufClusterFree.Mode);
- if (cntrl == LM_DISABLE)
- {
- data &= ~MBUF_CLUSTER_FREE_MODE_ENABLE;
- REG_WR(pDevice, MbufClusterFree.Mode,data);
- for(j = 0; j < MaxWaitCnt; j++)
- {
- if(!(REG_RD(pDevice, MbufClusterFree.Mode) & MBUF_CLUSTER_FREE_MODE_ENABLE))
- break;
- MM_Wait(10);
- }
- }
- else
- REG_WR(pDevice, MbufClusterFree.Mode, data | MBUF_CLUSTER_FREE_MODE_ENABLE);
- break;
+ case T3_BLOCK_MBUF_CLUSTER_FREE:
+ data = REG_RD (pDevice, MbufClusterFree.Mode);
+ if (cntrl == LM_DISABLE) {
+ data &= ~MBUF_CLUSTER_FREE_MODE_ENABLE;
+ REG_WR (pDevice, MbufClusterFree.Mode, data);
+ for (j = 0; j < MaxWaitCnt; j++) {
+ if (!
+ (REG_RD
+ (pDevice,
+ MbufClusterFree.
+ Mode) &
+ MBUF_CLUSTER_FREE_MODE_ENABLE))
+ break;
+ MM_Wait (10);
+ }
+ } else
+ REG_WR (pDevice, MbufClusterFree.Mode,
+ data | MBUF_CLUSTER_FREE_MODE_ENABLE);
+ break;
- case T3_BLOCK_SEND_BD_INITIATOR:
- data = REG_RD(pDevice, SndBdIn.Mode);
- if (cntrl == LM_DISABLE)
- {
- data &= ~SND_BD_IN_MODE_ENABLE;
- REG_WR(pDevice, SndBdIn.Mode, data);
- for(j = 0; j < MaxWaitCnt; j++)
- {
- if(!(REG_RD(pDevice, SndBdIn.Mode) & SND_BD_IN_MODE_ENABLE))
- break;
- MM_Wait(10);
- }
- }
- else
- REG_WR(pDevice, SndBdIn.Mode, data | SND_BD_IN_MODE_ENABLE);
- break;
+ case T3_BLOCK_SEND_BD_INITIATOR:
+ data = REG_RD (pDevice, SndBdIn.Mode);
+ if (cntrl == LM_DISABLE) {
+ data &= ~SND_BD_IN_MODE_ENABLE;
+ REG_WR (pDevice, SndBdIn.Mode, data);
+ for (j = 0; j < MaxWaitCnt; j++) {
+ if (!
+ (REG_RD (pDevice, SndBdIn.Mode) &
+ SND_BD_IN_MODE_ENABLE))
+ break;
+ MM_Wait (10);
+ }
+ } else
+ REG_WR (pDevice, SndBdIn.Mode,
+ data | SND_BD_IN_MODE_ENABLE);
+ break;
- case T3_BLOCK_SEND_BD_COMP:
- data = REG_RD(pDevice, SndBdComp.Mode);
- if (cntrl == LM_DISABLE)
- {
- data &= ~SND_BD_COMP_MODE_ENABLE;
- REG_WR(pDevice, SndBdComp.Mode, data);
- for(j = 0; j < MaxWaitCnt; j++)
- {
- if(!(REG_RD(pDevice, SndBdComp.Mode) & SND_BD_COMP_MODE_ENABLE))
- break;
- MM_Wait(10);
- }
- }
- else
- REG_WR(pDevice, SndBdComp.Mode, data | SND_BD_COMP_MODE_ENABLE);
- break;
+ case T3_BLOCK_SEND_BD_COMP:
+ data = REG_RD (pDevice, SndBdComp.Mode);
+ if (cntrl == LM_DISABLE) {
+ data &= ~SND_BD_COMP_MODE_ENABLE;
+ REG_WR (pDevice, SndBdComp.Mode, data);
+ for (j = 0; j < MaxWaitCnt; j++) {
+ if (!
+ (REG_RD (pDevice, SndBdComp.Mode) &
+ SND_BD_COMP_MODE_ENABLE))
+ break;
+ MM_Wait (10);
+ }
+ } else
+ REG_WR (pDevice, SndBdComp.Mode,
+ data | SND_BD_COMP_MODE_ENABLE);
+ break;
- case T3_BLOCK_SEND_BD_SELECTOR:
- data = REG_RD(pDevice, SndBdSel.Mode);
- if (cntrl == LM_DISABLE)
- {
- data &= ~SND_BD_SEL_MODE_ENABLE;
- REG_WR(pDevice, SndBdSel.Mode, data);
- for(j = 0; j < MaxWaitCnt; j++)
- {
- if(!(REG_RD(pDevice, SndBdSel.Mode) & SND_BD_SEL_MODE_ENABLE))
- break;
- MM_Wait(10);
- }
- }
- else
- REG_WR(pDevice, SndBdSel.Mode, data | SND_BD_SEL_MODE_ENABLE);
- break;
+ case T3_BLOCK_SEND_BD_SELECTOR:
+ data = REG_RD (pDevice, SndBdSel.Mode);
+ if (cntrl == LM_DISABLE) {
+ data &= ~SND_BD_SEL_MODE_ENABLE;
+ REG_WR (pDevice, SndBdSel.Mode, data);
+ for (j = 0; j < MaxWaitCnt; j++) {
+ if (!
+ (REG_RD (pDevice, SndBdSel.Mode) &
+ SND_BD_SEL_MODE_ENABLE))
+ break;
+ MM_Wait (10);
+ }
+ } else
+ REG_WR (pDevice, SndBdSel.Mode,
+ data | SND_BD_SEL_MODE_ENABLE);
+ break;
- case T3_BLOCK_SEND_DATA_INITIATOR:
- data = REG_RD(pDevice, SndDataIn.Mode);
- if (cntrl == LM_DISABLE)
- {
- data &= ~T3_SND_DATA_IN_MODE_ENABLE;
- REG_WR(pDevice, SndDataIn.Mode,data);
- for(j = 0; j < MaxWaitCnt; j++)
- {
- if(!(REG_RD(pDevice, SndDataIn.Mode) & T3_SND_DATA_IN_MODE_ENABLE))
- break;
- MM_Wait(10);
- }
- }
- else
- REG_WR(pDevice, SndDataIn.Mode,data | T3_SND_DATA_IN_MODE_ENABLE);
- break;
+ case T3_BLOCK_SEND_DATA_INITIATOR:
+ data = REG_RD (pDevice, SndDataIn.Mode);
+ if (cntrl == LM_DISABLE) {
+ data &= ~T3_SND_DATA_IN_MODE_ENABLE;
+ REG_WR (pDevice, SndDataIn.Mode, data);
+ for (j = 0; j < MaxWaitCnt; j++) {
+ if (!
+ (REG_RD (pDevice, SndDataIn.Mode) &
+ T3_SND_DATA_IN_MODE_ENABLE))
+ break;
+ MM_Wait (10);
+ }
+ } else
+ REG_WR (pDevice, SndDataIn.Mode,
+ data | T3_SND_DATA_IN_MODE_ENABLE);
+ break;
- case T3_BLOCK_SEND_DATA_COMP:
- data = REG_RD(pDevice, SndDataComp.Mode);
- if (cntrl == LM_DISABLE)
- {
- data &= ~SND_DATA_COMP_MODE_ENABLE;
- REG_WR(pDevice, SndDataComp.Mode, data);
- for(j = 0; j < MaxWaitCnt; j++)
- {
- if(!(REG_RD(pDevice, SndDataComp.Mode) & SND_DATA_COMP_MODE_ENABLE))
- break;
- MM_Wait(10);
- }
- }
- else
- REG_WR(pDevice, SndDataComp.Mode,data | SND_DATA_COMP_MODE_ENABLE);
- break;
+ case T3_BLOCK_SEND_DATA_COMP:
+ data = REG_RD (pDevice, SndDataComp.Mode);
+ if (cntrl == LM_DISABLE) {
+ data &= ~SND_DATA_COMP_MODE_ENABLE;
+ REG_WR (pDevice, SndDataComp.Mode, data);
+ for (j = 0; j < MaxWaitCnt; j++) {
+ if (!
+ (REG_RD (pDevice, SndDataComp.Mode)
+ & SND_DATA_COMP_MODE_ENABLE))
+ break;
+ MM_Wait (10);
+ }
+ } else
+ REG_WR (pDevice, SndDataComp.Mode,
+ data | SND_DATA_COMP_MODE_ENABLE);
+ break;
- case T3_BLOCK_MAC_TX_ENGINE:
- if(cntrl == LM_DISABLE)
- {
- pDevice->TxMode &= ~TX_MODE_ENABLE;
- REG_WR(pDevice, MacCtrl.TxMode, pDevice->TxMode);
- for(j = 0; j < MaxWaitCnt; j++)
- {
- if(!(REG_RD(pDevice, MacCtrl.TxMode) & TX_MODE_ENABLE))
- break;
- MM_Wait(10);
- }
- }
- else
- {
- pDevice->TxMode |= TX_MODE_ENABLE;
- REG_WR(pDevice, MacCtrl.TxMode, pDevice->TxMode);
- }
- break;
+ case T3_BLOCK_MAC_TX_ENGINE:
+ if (cntrl == LM_DISABLE) {
+ pDevice->TxMode &= ~TX_MODE_ENABLE;
+ REG_WR (pDevice, MacCtrl.TxMode,
+ pDevice->TxMode);
+ for (j = 0; j < MaxWaitCnt; j++) {
+ if (!
+ (REG_RD (pDevice, MacCtrl.TxMode) &
+ TX_MODE_ENABLE))
+ break;
+ MM_Wait (10);
+ }
+ } else {
+ pDevice->TxMode |= TX_MODE_ENABLE;
+ REG_WR (pDevice, MacCtrl.TxMode,
+ pDevice->TxMode);
+ }
+ break;
- case T3_BLOCK_MEM_ARBITOR:
- data = REG_RD(pDevice, MemArbiter.Mode);
- if (cntrl == LM_DISABLE)
- {
- data &= ~T3_MEM_ARBITER_MODE_ENABLE;
- REG_WR(pDevice, MemArbiter.Mode, data);
- for(j = 0; j < MaxWaitCnt; j++)
- {
- if(!(REG_RD(pDevice, MemArbiter.Mode) & T3_MEM_ARBITER_MODE_ENABLE))
- break;
- MM_Wait(10);
- }
- }
- else
- REG_WR(pDevice, MemArbiter.Mode,data|T3_MEM_ARBITER_MODE_ENABLE);
- break;
+ case T3_BLOCK_MEM_ARBITOR:
+ data = REG_RD (pDevice, MemArbiter.Mode);
+ if (cntrl == LM_DISABLE) {
+ data &= ~T3_MEM_ARBITER_MODE_ENABLE;
+ REG_WR (pDevice, MemArbiter.Mode, data);
+ for (j = 0; j < MaxWaitCnt; j++) {
+ if (!
+ (REG_RD (pDevice, MemArbiter.Mode) &
+ T3_MEM_ARBITER_MODE_ENABLE))
+ break;
+ MM_Wait (10);
+ }
+ } else
+ REG_WR (pDevice, MemArbiter.Mode,
+ data | T3_MEM_ARBITER_MODE_ENABLE);
+ break;
- case T3_BLOCK_MBUF_MANAGER:
- data = REG_RD(pDevice, BufMgr.Mode);
- if (cntrl == LM_DISABLE)
- {
- data &= ~BUFMGR_MODE_ENABLE;
- REG_WR(pDevice, BufMgr.Mode,data);
- for(j = 0; j < MaxWaitCnt; j++)
- {
- if(!(REG_RD(pDevice, BufMgr.Mode) & BUFMGR_MODE_ENABLE))
- break;
- MM_Wait(10);
- }
- }
- else
- REG_WR(pDevice, BufMgr.Mode,data | BUFMGR_MODE_ENABLE);
- break;
+ case T3_BLOCK_MBUF_MANAGER:
+ data = REG_RD (pDevice, BufMgr.Mode);
+ if (cntrl == LM_DISABLE) {
+ data &= ~BUFMGR_MODE_ENABLE;
+ REG_WR (pDevice, BufMgr.Mode, data);
+ for (j = 0; j < MaxWaitCnt; j++) {
+ if (!
+ (REG_RD (pDevice, BufMgr.Mode) &
+ BUFMGR_MODE_ENABLE))
+ break;
+ MM_Wait (10);
+ }
+ } else
+ REG_WR (pDevice, BufMgr.Mode,
+ data | BUFMGR_MODE_ENABLE);
+ break;
- case T3_BLOCK_MAC_GLOBAL:
- if(cntrl == LM_DISABLE)
- {
- pDevice->MacMode &= ~(MAC_MODE_ENABLE_TDE |
- MAC_MODE_ENABLE_RDE |
- MAC_MODE_ENABLE_FHDE);
- }
- else
- {
- pDevice->MacMode |= (MAC_MODE_ENABLE_TDE |
- MAC_MODE_ENABLE_RDE |
- MAC_MODE_ENABLE_FHDE);
- }
- REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
- break;
+ case T3_BLOCK_MAC_GLOBAL:
+ if (cntrl == LM_DISABLE) {
+ pDevice->MacMode &= ~(MAC_MODE_ENABLE_TDE |
+ MAC_MODE_ENABLE_RDE |
+ MAC_MODE_ENABLE_FHDE);
+ } else {
+ pDevice->MacMode |= (MAC_MODE_ENABLE_TDE |
+ MAC_MODE_ENABLE_RDE |
+ MAC_MODE_ENABLE_FHDE);
+ }
+ REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode);
+ break;
- default:
- return LM_STATUS_FAILURE;
- } /* switch */
+ default:
+ return LM_STATUS_FAILURE;
+ } /* switch */
- if(j >= MaxWaitCnt)
- {
- return LM_STATUS_FAILURE;
+ if (j >= MaxWaitCnt) {
+ return LM_STATUS_FAILURE;
+ }
}
- }
- return LM_STATUS_SUCCESS;
+ return LM_STATUS_SUCCESS;
}
/******************************************************************************/
@@ -2295,682 +2129,631 @@ LM_UINT32 mask,LM_UINT32 cntrl)
/* Return: */
/* LM_STATUS_SUCCESS */
/******************************************************************************/
-LM_STATUS
-LM_ResetAdapter(
-PLM_DEVICE_BLOCK pDevice)
+LM_STATUS LM_ResetAdapter (PLM_DEVICE_BLOCK pDevice)
{
- LM_UINT32 Value32;
- LM_UINT16 Value16;
- LM_UINT32 j, k;
+ LM_UINT32 Value32;
+ LM_UINT16 Value16;
+ LM_UINT32 j, k;
- /* Disable interrupt. */
- LM_DisableInterrupt(pDevice);
+ /* Disable interrupt. */
+ LM_DisableInterrupt (pDevice);
- /* May get a spurious interrupt */
- pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED;
+ /* May get a spurious interrupt */
+ pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED;
- /* Disable transmit and receive DMA engines. Abort all pending requests. */
- if(pDevice->InitDone)
- {
- LM_Abort(pDevice);
- }
+ /* Disable transmit and receive DMA engines. Abort all pending requests. */
+ if (pDevice->InitDone) {
+ LM_Abort (pDevice);
+ }
- pDevice->ShuttingDown = FALSE;
+ pDevice->ShuttingDown = FALSE;
- LM_ResetChip(pDevice);
+ LM_ResetChip (pDevice);
- /* Bug: Athlon fix for B3 silicon only. This bit does not do anything */
- /* in other chip revisions. */
- if(pDevice->DelayPciGrant)
- {
- Value32 = REG_RD(pDevice, PciCfg.ClockCtrl);
- REG_WR(pDevice, PciCfg.ClockCtrl, Value32 | BIT_31);
- }
+ /* Bug: Athlon fix for B3 silicon only. This bit does not do anything */
+ /* in other chip revisions. */
+ if (pDevice->DelayPciGrant) {
+ Value32 = REG_RD (pDevice, PciCfg.ClockCtrl);
+ REG_WR (pDevice, PciCfg.ClockCtrl, Value32 | BIT_31);
+ }
- if(pDevice->ChipRevId == T3_CHIP_ID_5704_A0)
- {
- if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE))
- {
- Value32 = REG_RD(pDevice, PciCfg.PciState);
- Value32 |= T3_PCI_STATE_RETRY_SAME_DMA;
- REG_WR(pDevice, PciCfg.PciState, Value32);
- }
- }
-
- /* Enable TaggedStatus mode. */
- if(pDevice->UseTaggedStatus)
- {
- pDevice->MiscHostCtrl |= MISC_HOST_CTRL_ENABLE_TAGGED_STATUS_MODE;
- }
-
- /* Restore PCI configuration registers. */
- MM_WriteConfig32(pDevice, PCI_CACHE_LINE_SIZE_REG,
- pDevice->SavedCacheLineReg);
- MM_WriteConfig32(pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG,
- (pDevice->SubsystemId << 16) | pDevice->SubsystemVendorId);
-
- /* Clear the statistics block. */
- for(j = 0x0300; j < 0x0b00; j++)
- {
- MEM_WR_OFFSET(pDevice, j, 0);
- }
-
- /* Initialize the statistis Block */
- pDevice->pStatusBlkVirt->Status = 0;
- pDevice->pStatusBlkVirt->RcvStdConIdx = 0;
- pDevice->pStatusBlkVirt->RcvJumboConIdx = 0;
- pDevice->pStatusBlkVirt->RcvMiniConIdx = 0;
-
- for(j = 0; j < 16; j++)
- {
- pDevice->pStatusBlkVirt->Idx[j].RcvProdIdx = 0;
- pDevice->pStatusBlkVirt->Idx[j].SendConIdx = 0;
- }
-
- for(k = 0; k < T3_STD_RCV_RCB_ENTRY_COUNT ;k++)
- {
- pDevice->pRxStdBdVirt[k].HostAddr.High = 0;
- pDevice->pRxStdBdVirt[k].HostAddr.Low = 0;
- }
+ if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0) {
+ if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)) {
+ Value32 = REG_RD (pDevice, PciCfg.PciState);
+ Value32 |= T3_PCI_STATE_RETRY_SAME_DMA;
+ REG_WR (pDevice, PciCfg.PciState, Value32);
+ }
+ }
+
+ /* Enable TaggedStatus mode. */
+ if (pDevice->UseTaggedStatus) {
+ pDevice->MiscHostCtrl |=
+ MISC_HOST_CTRL_ENABLE_TAGGED_STATUS_MODE;
+ }
+
+ /* Restore PCI configuration registers. */
+ MM_WriteConfig32 (pDevice, PCI_CACHE_LINE_SIZE_REG,
+ pDevice->SavedCacheLineReg);
+ MM_WriteConfig32 (pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG,
+ (pDevice->SubsystemId << 16) | pDevice->
+ SubsystemVendorId);
+
+ /* Clear the statistics block. */
+ for (j = 0x0300; j < 0x0b00; j++) {
+ MEM_WR_OFFSET (pDevice, j, 0);
+ }
+
+ /* Initialize the statistis Block */
+ pDevice->pStatusBlkVirt->Status = 0;
+ pDevice->pStatusBlkVirt->RcvStdConIdx = 0;
+ pDevice->pStatusBlkVirt->RcvJumboConIdx = 0;
+ pDevice->pStatusBlkVirt->RcvMiniConIdx = 0;
+
+ for (j = 0; j < 16; j++) {
+ pDevice->pStatusBlkVirt->Idx[j].RcvProdIdx = 0;
+ pDevice->pStatusBlkVirt->Idx[j].SendConIdx = 0;
+ }
+
+ for (k = 0; k < T3_STD_RCV_RCB_ENTRY_COUNT; k++) {
+ pDevice->pRxStdBdVirt[k].HostAddr.High = 0;
+ pDevice->pRxStdBdVirt[k].HostAddr.Low = 0;
+ }
#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
- /* Receive jumbo BD buffer. */
- for(k = 0; k < T3_JUMBO_RCV_RCB_ENTRY_COUNT; k++)
- {
- pDevice->pRxJumboBdVirt[k].HostAddr.High = 0;
- pDevice->pRxJumboBdVirt[k].HostAddr.Low = 0;
- }
+ /* Receive jumbo BD buffer. */
+ for (k = 0; k < T3_JUMBO_RCV_RCB_ENTRY_COUNT; k++) {
+ pDevice->pRxJumboBdVirt[k].HostAddr.High = 0;
+ pDevice->pRxJumboBdVirt[k].HostAddr.Low = 0;
+ }
#endif
- REG_WR(pDevice, PciCfg.DmaReadWriteCtrl, pDevice->DmaReadWriteCtrl);
+ REG_WR (pDevice, PciCfg.DmaReadWriteCtrl, pDevice->DmaReadWriteCtrl);
- /* GRC mode control register. */
-#ifdef BIG_ENDIAN_PCI /* Jimmy, this ifdef block deleted in new code! */
- Value32 =
- GRC_MODE_WORD_SWAP_DATA |
- GRC_MODE_WORD_SWAP_NON_FRAME_DATA |
- GRC_MODE_INT_ON_MAC_ATTN |
- GRC_MODE_HOST_STACK_UP;
+ /* GRC mode control register. */
+#ifdef BIG_ENDIAN_PCI /* Jimmy, this ifdef block deleted in new code! */
+ Value32 =
+ GRC_MODE_WORD_SWAP_DATA |
+ GRC_MODE_WORD_SWAP_NON_FRAME_DATA |
+ GRC_MODE_INT_ON_MAC_ATTN | GRC_MODE_HOST_STACK_UP;
#else
- /* No CPU Swap modes for PCI IO */
- Value32 =
+ /* No CPU Swap modes for PCI IO */
+ Value32 =
#ifdef BIG_ENDIAN_HOST
- GRC_MODE_BYTE_SWAP_NON_FRAME_DATA |
- GRC_MODE_WORD_SWAP_NON_FRAME_DATA |
- GRC_MODE_BYTE_SWAP_DATA |
- GRC_MODE_WORD_SWAP_DATA |
+ GRC_MODE_BYTE_SWAP_NON_FRAME_DATA |
+ GRC_MODE_WORD_SWAP_NON_FRAME_DATA |
+ GRC_MODE_BYTE_SWAP_DATA | GRC_MODE_WORD_SWAP_DATA |
#else
- GRC_MODE_WORD_SWAP_NON_FRAME_DATA |
- GRC_MODE_BYTE_SWAP_DATA |
- GRC_MODE_WORD_SWAP_DATA |
+ GRC_MODE_WORD_SWAP_NON_FRAME_DATA |
+ GRC_MODE_BYTE_SWAP_DATA | GRC_MODE_WORD_SWAP_DATA |
#endif
- GRC_MODE_INT_ON_MAC_ATTN |
- GRC_MODE_HOST_STACK_UP;
-#endif /* !BIG_ENDIAN_PCI */
-
- /* Configure send BD mode. */
- if(pDevice->NicSendBd == FALSE)
- {
- Value32 |= GRC_MODE_HOST_SEND_BDS;
- }
- else
- {
- Value32 |= GRC_MODE_4X_NIC_BASED_SEND_RINGS;
- }
-
- /* Configure pseudo checksum mode. */
- if(pDevice->NoTxPseudoHdrChksum)
- {
- Value32 |= GRC_MODE_TX_NO_PSEUDO_HEADER_CHKSUM;
- }
-
- if(pDevice->NoRxPseudoHdrChksum)
- {
- Value32 |= GRC_MODE_RX_NO_PSEUDO_HEADER_CHKSUM;
- }
-
- REG_WR(pDevice, Grc.Mode, Value32);
-
- /* Setup the timer prescalar register. */
- REG_WR(pDevice, Grc.MiscCfg, 65 << 1); /* Clock is alwasy 66Mhz. */
-
- /* Set up the MBUF pool base address and size. */
- REG_WR(pDevice, BufMgr.MbufPoolAddr, pDevice->MbufBase);
- REG_WR(pDevice, BufMgr.MbufPoolSize, pDevice->MbufSize);
-
- /* Set up the DMA descriptor pool base address and size. */
- REG_WR(pDevice, BufMgr.DmaDescPoolAddr, T3_NIC_DMA_DESC_POOL_ADDR);
- REG_WR(pDevice, BufMgr.DmaDescPoolSize, T3_NIC_DMA_DESC_POOL_SIZE);
-
- /* Configure MBUF and Threshold watermarks */
- /* Configure the DMA read MBUF low water mark. */
- if(pDevice->DmaMbufLowMark)
- {
- REG_WR(pDevice, BufMgr.MbufReadDmaLowWaterMark,
- pDevice->DmaMbufLowMark);
- }
- else
- {
- if(pDevice->TxMtu < MAX_ETHERNET_PACKET_BUFFER_SIZE)
- {
- REG_WR(pDevice, BufMgr.MbufReadDmaLowWaterMark,
- T3_DEF_DMA_MBUF_LOW_WMARK);
+ GRC_MODE_INT_ON_MAC_ATTN | GRC_MODE_HOST_STACK_UP;
+#endif /* !BIG_ENDIAN_PCI */
+
+ /* Configure send BD mode. */
+ if (pDevice->NicSendBd == FALSE) {
+ Value32 |= GRC_MODE_HOST_SEND_BDS;
+ } else {
+ Value32 |= GRC_MODE_4X_NIC_BASED_SEND_RINGS;
}
- else
- {
- REG_WR(pDevice, BufMgr.MbufReadDmaLowWaterMark,
- T3_DEF_DMA_MBUF_LOW_WMARK_JUMBO);
- }
- }
-
- /* Configure the MAC Rx MBUF low water mark. */
- if(pDevice->RxMacMbufLowMark)
- {
- REG_WR(pDevice, BufMgr.MbufMacRxLowWaterMark,
- pDevice->RxMacMbufLowMark);
- }
- else
- {
- if(pDevice->TxMtu < MAX_ETHERNET_PACKET_BUFFER_SIZE)
- {
- REG_WR(pDevice, BufMgr.MbufMacRxLowWaterMark,
- T3_DEF_RX_MAC_MBUF_LOW_WMARK);
+
+ /* Configure pseudo checksum mode. */
+ if (pDevice->NoTxPseudoHdrChksum) {
+ Value32 |= GRC_MODE_TX_NO_PSEUDO_HEADER_CHKSUM;
}
- else
- {
- REG_WR(pDevice, BufMgr.MbufMacRxLowWaterMark,
- T3_DEF_RX_MAC_MBUF_LOW_WMARK_JUMBO);
- }
- }
-
- /* Configure the MBUF high water mark. */
- if(pDevice->MbufHighMark)
- {
- REG_WR(pDevice, BufMgr.MbufHighWaterMark, pDevice->MbufHighMark);
- }
- else
- {
- if(pDevice->TxMtu < MAX_ETHERNET_PACKET_BUFFER_SIZE)
- {
- REG_WR(pDevice, BufMgr.MbufHighWaterMark,
- T3_DEF_MBUF_HIGH_WMARK);
+
+ if (pDevice->NoRxPseudoHdrChksum) {
+ Value32 |= GRC_MODE_RX_NO_PSEUDO_HEADER_CHKSUM;
}
- else
- {
- REG_WR(pDevice, BufMgr.MbufHighWaterMark,
- T3_DEF_MBUF_HIGH_WMARK_JUMBO);
+
+ REG_WR (pDevice, Grc.Mode, Value32);
+
+ /* Setup the timer prescalar register. */
+ REG_WR (pDevice, Grc.MiscCfg, 65 << 1); /* Clock is alwasy 66Mhz. */
+
+ /* Set up the MBUF pool base address and size. */
+ REG_WR (pDevice, BufMgr.MbufPoolAddr, pDevice->MbufBase);
+ REG_WR (pDevice, BufMgr.MbufPoolSize, pDevice->MbufSize);
+
+ /* Set up the DMA descriptor pool base address and size. */
+ REG_WR (pDevice, BufMgr.DmaDescPoolAddr, T3_NIC_DMA_DESC_POOL_ADDR);
+ REG_WR (pDevice, BufMgr.DmaDescPoolSize, T3_NIC_DMA_DESC_POOL_SIZE);
+
+ /* Configure MBUF and Threshold watermarks */
+ /* Configure the DMA read MBUF low water mark. */
+ if (pDevice->DmaMbufLowMark) {
+ REG_WR (pDevice, BufMgr.MbufReadDmaLowWaterMark,
+ pDevice->DmaMbufLowMark);
+ } else {
+ if (pDevice->TxMtu < MAX_ETHERNET_PACKET_BUFFER_SIZE) {
+ REG_WR (pDevice, BufMgr.MbufReadDmaLowWaterMark,
+ T3_DEF_DMA_MBUF_LOW_WMARK);
+ } else {
+ REG_WR (pDevice, BufMgr.MbufReadDmaLowWaterMark,
+ T3_DEF_DMA_MBUF_LOW_WMARK_JUMBO);
+ }
+ }
+
+ /* Configure the MAC Rx MBUF low water mark. */
+ if (pDevice->RxMacMbufLowMark) {
+ REG_WR (pDevice, BufMgr.MbufMacRxLowWaterMark,
+ pDevice->RxMacMbufLowMark);
+ } else {
+ if (pDevice->TxMtu < MAX_ETHERNET_PACKET_BUFFER_SIZE) {
+ REG_WR (pDevice, BufMgr.MbufMacRxLowWaterMark,
+ T3_DEF_RX_MAC_MBUF_LOW_WMARK);
+ } else {
+ REG_WR (pDevice, BufMgr.MbufMacRxLowWaterMark,
+ T3_DEF_RX_MAC_MBUF_LOW_WMARK_JUMBO);
+ }
}
- }
- REG_WR(pDevice, BufMgr.DmaLowWaterMark, T3_DEF_DMA_DESC_LOW_WMARK);
- REG_WR(pDevice, BufMgr.DmaHighWaterMark, T3_DEF_DMA_DESC_HIGH_WMARK);
+ /* Configure the MBUF high water mark. */
+ if (pDevice->MbufHighMark) {
+ REG_WR (pDevice, BufMgr.MbufHighWaterMark,
+ pDevice->MbufHighMark);
+ } else {
+ if (pDevice->TxMtu < MAX_ETHERNET_PACKET_BUFFER_SIZE) {
+ REG_WR (pDevice, BufMgr.MbufHighWaterMark,
+ T3_DEF_MBUF_HIGH_WMARK);
+ } else {
+ REG_WR (pDevice, BufMgr.MbufHighWaterMark,
+ T3_DEF_MBUF_HIGH_WMARK_JUMBO);
+ }
+ }
- /* Enable buffer manager. */
- REG_WR(pDevice, BufMgr.Mode, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
+ REG_WR (pDevice, BufMgr.DmaLowWaterMark, T3_DEF_DMA_DESC_LOW_WMARK);
+ REG_WR (pDevice, BufMgr.DmaHighWaterMark, T3_DEF_DMA_DESC_HIGH_WMARK);
- for(j = 0 ;j < 2000; j++)
- {
- if(REG_RD(pDevice, BufMgr.Mode) & BUFMGR_MODE_ENABLE)
- break;
- MM_Wait(10);
- }
+ /* Enable buffer manager. */
+ REG_WR (pDevice, BufMgr.Mode,
+ BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
- if(j >= 2000)
- {
- return LM_STATUS_FAILURE;
- }
-
- /* Enable the FTQs. */
- REG_WR(pDevice, Ftq.Reset, 0xffffffff);
- REG_WR(pDevice, Ftq.Reset, 0);
-
- /* Wait until FTQ is ready */
- for(j = 0; j < 2000; j++)
- {
- if(REG_RD(pDevice, Ftq.Reset) == 0)
- break;
- MM_Wait(10);
- }
-
- if(j >= 2000)
- {
- return LM_STATUS_FAILURE;
- }
-
- /* Initialize the Standard Receive RCB. */
- REG_WR(pDevice, RcvDataBdIn.StdRcvRcb.HostRingAddr.High,
- pDevice->RxStdBdPhy.High);
- REG_WR(pDevice, RcvDataBdIn.StdRcvRcb.HostRingAddr.Low,
- pDevice->RxStdBdPhy.Low);
- REG_WR(pDevice, RcvDataBdIn.StdRcvRcb.u.MaxLen_Flags,
- MAX_STD_RCV_BUFFER_SIZE << 16);
-
- /* Initialize the Jumbo Receive RCB. */
- REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.u.MaxLen_Flags,
- T3_RCB_FLAG_RING_DISABLED);
-#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
- REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.HostRingAddr.High,
- pDevice->RxJumboBdPhy.High);
- REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.HostRingAddr.Low,
- pDevice->RxJumboBdPhy.Low);
+ for (j = 0; j < 2000; j++) {
+ if (REG_RD (pDevice, BufMgr.Mode) & BUFMGR_MODE_ENABLE)
+ break;
+ MM_Wait (10);
+ }
- REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.u.MaxLen_Flags, 0);
+ if (j >= 2000) {
+ return LM_STATUS_FAILURE;
+ }
-#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
+ /* Enable the FTQs. */
+ REG_WR (pDevice, Ftq.Reset, 0xffffffff);
+ REG_WR (pDevice, Ftq.Reset, 0);
- /* Initialize the Mini Receive RCB. */
- REG_WR(pDevice, RcvDataBdIn.MiniRcvRcb.u.MaxLen_Flags,
- T3_RCB_FLAG_RING_DISABLED);
+ /* Wait until FTQ is ready */
+ for (j = 0; j < 2000; j++) {
+ if (REG_RD (pDevice, Ftq.Reset) == 0)
+ break;
+ MM_Wait (10);
+ }
- {
- REG_WR(pDevice, RcvDataBdIn.StdRcvRcb.NicRingAddr,
- (LM_UINT32) T3_NIC_STD_RCV_BUFFER_DESC_ADDR);
- REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.NicRingAddr,
- (LM_UINT32) T3_NIC_JUMBO_RCV_BUFFER_DESC_ADDR);
- }
+ if (j >= 2000) {
+ return LM_STATUS_FAILURE;
+ }
+
+ /* Initialize the Standard Receive RCB. */
+ REG_WR (pDevice, RcvDataBdIn.StdRcvRcb.HostRingAddr.High,
+ pDevice->RxStdBdPhy.High);
+ REG_WR (pDevice, RcvDataBdIn.StdRcvRcb.HostRingAddr.Low,
+ pDevice->RxStdBdPhy.Low);
+ REG_WR (pDevice, RcvDataBdIn.StdRcvRcb.u.MaxLen_Flags,
+ MAX_STD_RCV_BUFFER_SIZE << 16);
- /* Receive BD Ring replenish threshold. */
- REG_WR(pDevice, RcvBdIn.StdRcvThreshold, pDevice->RxStdDescCnt/8);
+ /* Initialize the Jumbo Receive RCB. */
+ REG_WR (pDevice, RcvDataBdIn.JumboRcvRcb.u.MaxLen_Flags,
+ T3_RCB_FLAG_RING_DISABLED);
#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
- REG_WR(pDevice, RcvBdIn.JumboRcvThreshold, pDevice->RxJumboDescCnt/8);
-#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
+ REG_WR (pDevice, RcvDataBdIn.JumboRcvRcb.HostRingAddr.High,
+ pDevice->RxJumboBdPhy.High);
+ REG_WR (pDevice, RcvDataBdIn.JumboRcvRcb.HostRingAddr.Low,
+ pDevice->RxJumboBdPhy.Low);
+
+ REG_WR (pDevice, RcvDataBdIn.JumboRcvRcb.u.MaxLen_Flags, 0);
+
+#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
- /* Disable all the unused rings. */
- for(j = 0; j < T3_MAX_SEND_RCB_COUNT; j++) {
- MEM_WR(pDevice, SendRcb[j].u.MaxLen_Flags, T3_RCB_FLAG_RING_DISABLED);
- } /* for */
+ /* Initialize the Mini Receive RCB. */
+ REG_WR (pDevice, RcvDataBdIn.MiniRcvRcb.u.MaxLen_Flags,
+ T3_RCB_FLAG_RING_DISABLED);
- /* Initialize the indices. */
- pDevice->SendProdIdx = 0;
- pDevice->SendConIdx = 0;
+ {
+ REG_WR (pDevice, RcvDataBdIn.StdRcvRcb.NicRingAddr,
+ (LM_UINT32) T3_NIC_STD_RCV_BUFFER_DESC_ADDR);
+ REG_WR (pDevice, RcvDataBdIn.JumboRcvRcb.NicRingAddr,
+ (LM_UINT32) T3_NIC_JUMBO_RCV_BUFFER_DESC_ADDR);
+ }
+
+ /* Receive BD Ring replenish threshold. */
+ REG_WR (pDevice, RcvBdIn.StdRcvThreshold, pDevice->RxStdDescCnt / 8);
+#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
+ REG_WR (pDevice, RcvBdIn.JumboRcvThreshold,
+ pDevice->RxJumboDescCnt / 8);
+#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
+
+ /* Disable all the unused rings. */
+ for (j = 0; j < T3_MAX_SEND_RCB_COUNT; j++) {
+ MEM_WR (pDevice, SendRcb[j].u.MaxLen_Flags,
+ T3_RCB_FLAG_RING_DISABLED);
+ } /* for */
+
+ /* Initialize the indices. */
+ pDevice->SendProdIdx = 0;
+ pDevice->SendConIdx = 0;
+
+ MB_REG_WR (pDevice, Mailbox.SendHostProdIdx[0].Low, 0);
+ MB_REG_WR (pDevice, Mailbox.SendNicProdIdx[0].Low, 0);
+
+ /* Set up host or NIC based send RCB. */
+ if (pDevice->NicSendBd == FALSE) {
+ MEM_WR (pDevice, SendRcb[0].HostRingAddr.High,
+ pDevice->SendBdPhy.High);
+ MEM_WR (pDevice, SendRcb[0].HostRingAddr.Low,
+ pDevice->SendBdPhy.Low);
+
+ /* Set up the NIC ring address in the RCB. */
+ MEM_WR (pDevice, SendRcb[0].NicRingAddr,
+ T3_NIC_SND_BUFFER_DESC_ADDR);
+
+ /* Setup the RCB. */
+ MEM_WR (pDevice, SendRcb[0].u.MaxLen_Flags,
+ T3_SEND_RCB_ENTRY_COUNT << 16);
+
+ for (k = 0; k < T3_SEND_RCB_ENTRY_COUNT; k++) {
+ pDevice->pSendBdVirt[k].HostAddr.High = 0;
+ pDevice->pSendBdVirt[k].HostAddr.Low = 0;
+ }
+ } else {
+ MEM_WR (pDevice, SendRcb[0].HostRingAddr.High, 0);
+ MEM_WR (pDevice, SendRcb[0].HostRingAddr.Low, 0);
+ MEM_WR (pDevice, SendRcb[0].NicRingAddr,
+ pDevice->SendBdPhy.Low);
+
+ for (k = 0; k < T3_SEND_RCB_ENTRY_COUNT; k++) {
+ __raw_writel (0,
+ &(pDevice->pSendBdVirt[k].HostAddr.High));
+ __raw_writel (0,
+ &(pDevice->pSendBdVirt[k].HostAddr.Low));
+ __raw_writel (0,
+ &(pDevice->pSendBdVirt[k].u1.Len_Flags));
+ pDevice->ShadowSendBd[k].HostAddr.High = 0;
+ pDevice->ShadowSendBd[k].u1.Len_Flags = 0;
+ }
+ }
+ atomic_set (&pDevice->SendBdLeft, T3_SEND_RCB_ENTRY_COUNT - 1);
+
+ /* Configure the receive return rings. */
+ for (j = 0; j < T3_MAX_RCV_RETURN_RCB_COUNT; j++) {
+ MEM_WR (pDevice, RcvRetRcb[j].u.MaxLen_Flags,
+ T3_RCB_FLAG_RING_DISABLED);
+ }
- MB_REG_WR(pDevice, Mailbox.SendHostProdIdx[0].Low, 0);
- MB_REG_WR(pDevice, Mailbox.SendNicProdIdx[0].Low, 0);
+ pDevice->RcvRetConIdx = 0;
- /* Set up host or NIC based send RCB. */
- if(pDevice->NicSendBd == FALSE)
- {
- MEM_WR(pDevice, SendRcb[0].HostRingAddr.High,
- pDevice->SendBdPhy.High);
- MEM_WR(pDevice, SendRcb[0].HostRingAddr.Low,
- pDevice->SendBdPhy.Low);
+ MEM_WR (pDevice, RcvRetRcb[0].HostRingAddr.High,
+ pDevice->RcvRetBdPhy.High);
+ MEM_WR (pDevice, RcvRetRcb[0].HostRingAddr.Low,
+ pDevice->RcvRetBdPhy.Low);
/* Set up the NIC ring address in the RCB. */
- MEM_WR(pDevice, SendRcb[0].NicRingAddr,T3_NIC_SND_BUFFER_DESC_ADDR);
+ /* Not very clear from the spec. I am guessing that for Receive */
+ /* Return Ring, NicRingAddr is not used. */
+ MEM_WR (pDevice, RcvRetRcb[0].NicRingAddr, 0);
/* Setup the RCB. */
- MEM_WR(pDevice, SendRcb[0].u.MaxLen_Flags,
- T3_SEND_RCB_ENTRY_COUNT << 16);
+ MEM_WR (pDevice, RcvRetRcb[0].u.MaxLen_Flags,
+ T3_RCV_RETURN_RCB_ENTRY_COUNT << 16);
- for(k = 0; k < T3_SEND_RCB_ENTRY_COUNT; k++)
- {
- pDevice->pSendBdVirt[k].HostAddr.High = 0;
- pDevice->pSendBdVirt[k].HostAddr.Low = 0;
- }
- }
- else
- {
- MEM_WR(pDevice, SendRcb[0].HostRingAddr.High, 0);
- MEM_WR(pDevice, SendRcb[0].HostRingAddr.Low, 0);
- MEM_WR(pDevice, SendRcb[0].NicRingAddr,
- pDevice->SendBdPhy.Low);
-
- for(k = 0; k < T3_SEND_RCB_ENTRY_COUNT; k++)
- {
- __raw_writel(0, &(pDevice->pSendBdVirt[k].HostAddr.High));
- __raw_writel(0, &(pDevice->pSendBdVirt[k].HostAddr.Low));
- __raw_writel(0, &(pDevice->pSendBdVirt[k].u1.Len_Flags));
- pDevice->ShadowSendBd[k].HostAddr.High = 0;
- pDevice->ShadowSendBd[k].u1.Len_Flags = 0;
- }
- }
- atomic_set(&pDevice->SendBdLeft, T3_SEND_RCB_ENTRY_COUNT-1);
-
- /* Configure the receive return rings. */
- for(j = 0; j < T3_MAX_RCV_RETURN_RCB_COUNT; j++)
- {
- MEM_WR(pDevice, RcvRetRcb[j].u.MaxLen_Flags, T3_RCB_FLAG_RING_DISABLED);
- }
-
- pDevice->RcvRetConIdx = 0;
-
- MEM_WR(pDevice, RcvRetRcb[0].HostRingAddr.High,
- pDevice->RcvRetBdPhy.High);
- MEM_WR(pDevice, RcvRetRcb[0].HostRingAddr.Low,
- pDevice->RcvRetBdPhy.Low);
-
- /* Set up the NIC ring address in the RCB. */
- /* Not very clear from the spec. I am guessing that for Receive */
- /* Return Ring, NicRingAddr is not used. */
- MEM_WR(pDevice, RcvRetRcb[0].NicRingAddr, 0);
-
- /* Setup the RCB. */
- MEM_WR(pDevice, RcvRetRcb[0].u.MaxLen_Flags,
- T3_RCV_RETURN_RCB_ENTRY_COUNT << 16);
-
- /* Reinitialize RX ring producer index */
- MB_REG_WR(pDevice, Mailbox.RcvStdProdIdx.Low, 0);
- MB_REG_WR(pDevice, Mailbox.RcvJumboProdIdx.Low, 0);
- MB_REG_WR(pDevice, Mailbox.RcvMiniProdIdx.Low, 0);
+ /* Reinitialize RX ring producer index */
+ MB_REG_WR (pDevice, Mailbox.RcvStdProdIdx.Low, 0);
+ MB_REG_WR (pDevice, Mailbox.RcvJumboProdIdx.Low, 0);
+ MB_REG_WR (pDevice, Mailbox.RcvMiniProdIdx.Low, 0);
#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
- pDevice->RxJumboProdIdx = 0;
- pDevice->RxJumboQueuedCnt = 0;
+ pDevice->RxJumboProdIdx = 0;
+ pDevice->RxJumboQueuedCnt = 0;
#endif
- /* Reinitialize our copy of the indices. */
- pDevice->RxStdProdIdx = 0;
- pDevice->RxStdQueuedCnt = 0;
+ /* Reinitialize our copy of the indices. */
+ pDevice->RxStdProdIdx = 0;
+ pDevice->RxStdQueuedCnt = 0;
#if T3_JUMBO_RCV_ENTRY_COUNT
- pDevice->RxJumboProdIdx = 0;
-#endif /* T3_JUMBO_RCV_ENTRY_COUNT */
-
- /* Configure the MAC address. */
- LM_SetMacAddress(pDevice, pDevice->NodeAddress);
-
- /* Initialize the transmit random backoff seed. */
- Value32 = (pDevice->NodeAddress[0] + pDevice->NodeAddress[1] +
- pDevice->NodeAddress[2] + pDevice->NodeAddress[3] +
- pDevice->NodeAddress[4] + pDevice->NodeAddress[5]) &
- MAC_TX_BACKOFF_SEED_MASK;
- REG_WR(pDevice, MacCtrl.TxBackoffSeed, Value32);
-
- /* Receive MTU. Frames larger than the MTU is marked as oversized. */
- REG_WR(pDevice, MacCtrl.MtuSize, pDevice->RxMtu + 8); /* CRC + VLAN. */
-
- /* Configure Time slot/IPG per 802.3 */
- REG_WR(pDevice, MacCtrl.TxLengths, 0x2620);
-
- /*
- * Configure Receive Rules so that packets don't match
- * Programmble rule will be queued to Return Ring 1
- */
- REG_WR(pDevice, MacCtrl.RcvRuleCfg, RX_RULE_DEFAULT_CLASS);
-
- /*
- * Configure to have 16 Classes of Services (COS) and one
- * queue per class. Bad frames are queued to RRR#1.
- * And frames don't match rules are also queued to COS#1.
- */
- REG_WR(pDevice, RcvListPlmt.Config, 0x181);
-
- /* Enable Receive Placement Statistics */
- REG_WR(pDevice, RcvListPlmt.StatsEnableMask,0xffffff);
- REG_WR(pDevice, RcvListPlmt.StatsCtrl, RCV_LIST_STATS_ENABLE);
-
- /* Enable Send Data Initator Statistics */
- REG_WR(pDevice, SndDataIn.StatsEnableMask,0xffffff);
- REG_WR(pDevice, SndDataIn.StatsCtrl,
- T3_SND_DATA_IN_STATS_CTRL_ENABLE | \
- T3_SND_DATA_IN_STATS_CTRL_FASTER_UPDATE);
-
- /* Disable the host coalescing state machine before configuring it's */
- /* parameters. */
- REG_WR(pDevice, HostCoalesce.Mode, 0);
- for(j = 0; j < 2000; j++)
- {
- Value32 = REG_RD(pDevice, HostCoalesce.Mode);
- if(!(Value32 & HOST_COALESCE_ENABLE))
- {
- break;
- }
- MM_Wait(10);
- }
-
- /* Host coalescing configurations. */
- REG_WR(pDevice, HostCoalesce.RxCoalescingTicks, pDevice->RxCoalescingTicks);
- REG_WR(pDevice, HostCoalesce.TxCoalescingTicks, pDevice->TxCoalescingTicks);
- REG_WR(pDevice, HostCoalesce.RxMaxCoalescedFrames,
- pDevice->RxMaxCoalescedFrames);
- REG_WR(pDevice, HostCoalesce.TxMaxCoalescedFrames,
- pDevice->TxMaxCoalescedFrames);
- REG_WR(pDevice, HostCoalesce.RxCoalescedTickDuringInt,
- pDevice->RxCoalescingTicksDuringInt);
- REG_WR(pDevice, HostCoalesce.TxCoalescedTickDuringInt,
- pDevice->TxCoalescingTicksDuringInt);
- REG_WR(pDevice, HostCoalesce.RxMaxCoalescedFramesDuringInt,
- pDevice->RxMaxCoalescedFramesDuringInt);
- REG_WR(pDevice, HostCoalesce.TxMaxCoalescedFramesDuringInt,
- pDevice->TxMaxCoalescedFramesDuringInt);
-
- /* Initialize the address of the status block. The NIC will DMA */
- /* the status block to this memory which resides on the host. */
- REG_WR(pDevice, HostCoalesce.StatusBlkHostAddr.High,
- pDevice->StatusBlkPhy.High);
- REG_WR(pDevice, HostCoalesce.StatusBlkHostAddr.Low,
- pDevice->StatusBlkPhy.Low);
-
- /* Initialize the address of the statistics block. The NIC will DMA */
- /* the statistics to this block of memory. */
- REG_WR(pDevice, HostCoalesce.StatsBlkHostAddr.High,
- pDevice->StatsBlkPhy.High);
- REG_WR(pDevice, HostCoalesce.StatsBlkHostAddr.Low,
- pDevice->StatsBlkPhy.Low);
-
- REG_WR(pDevice, HostCoalesce.StatsCoalescingTicks,
- pDevice->StatsCoalescingTicks);
-
- REG_WR(pDevice, HostCoalesce.StatsBlkNicAddr, 0x300);
- REG_WR(pDevice, HostCoalesce.StatusBlkNicAddr,0xb00);
-
- /* Enable Host Coalesing state machine */
- REG_WR(pDevice, HostCoalesce.Mode, HOST_COALESCE_ENABLE |
- pDevice->CoalesceMode);
-
- /* Enable the Receive BD Completion state machine. */
- REG_WR(pDevice, RcvBdComp.Mode, RCV_BD_COMP_MODE_ENABLE |
- RCV_BD_COMP_MODE_ATTN_ENABLE);
-
- /* Enable the Receive List Placement state machine. */
- REG_WR(pDevice, RcvListPlmt.Mode, RCV_LIST_PLMT_MODE_ENABLE);
-
- /* Enable the Receive List Selector state machine. */
- REG_WR(pDevice, RcvListSel.Mode, RCV_LIST_SEL_MODE_ENABLE |
- RCV_LIST_SEL_MODE_ATTN_ENABLE);
-
- /* Enable transmit DMA, clear statistics. */
- pDevice->MacMode = MAC_MODE_ENABLE_TX_STATISTICS |
- MAC_MODE_ENABLE_RX_STATISTICS | MAC_MODE_ENABLE_TDE |
- MAC_MODE_ENABLE_RDE | MAC_MODE_ENABLE_FHDE;
- REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode |
- MAC_MODE_CLEAR_RX_STATISTICS | MAC_MODE_CLEAR_TX_STATISTICS);
-
- /* GRC miscellaneous local control register. */
- pDevice->GrcLocalCtrl = GRC_MISC_LOCAL_CTRL_INT_ON_ATTN |
- GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM;
-
- if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
- {
- pDevice->GrcLocalCtrl |= GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
- GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1;
- }
-
- REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl);
- MM_Wait(40);
-
- /* Reset RX counters. */
- for(j = 0; j < sizeof(LM_RX_COUNTERS); j++)
- {
- ((PLM_UINT8) &pDevice->RxCounters)[j] = 0;
- }
-
- /* Reset TX counters. */
- for(j = 0; j < sizeof(LM_TX_COUNTERS); j++)
- {
- ((PLM_UINT8) &pDevice->TxCounters)[j] = 0;
- }
-
- MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, 0);
-
- /* Enable the DMA Completion state machine. */
- REG_WR(pDevice, DmaComp.Mode, DMA_COMP_MODE_ENABLE);
-
- /* Enable the DMA Write state machine. */
- Value32 = DMA_WRITE_MODE_ENABLE |
- DMA_WRITE_MODE_TARGET_ABORT_ATTN_ENABLE |
- DMA_WRITE_MODE_MASTER_ABORT_ATTN_ENABLE |
- DMA_WRITE_MODE_PARITY_ERROR_ATTN_ENABLE |
- DMA_WRITE_MODE_ADDR_OVERFLOW_ATTN_ENABLE |
- DMA_WRITE_MODE_FIFO_OVERRUN_ATTN_ENABLE |
- DMA_WRITE_MODE_FIFO_UNDERRUN_ATTN_ENABLE |
- DMA_WRITE_MODE_FIFO_OVERREAD_ATTN_ENABLE |
- DMA_WRITE_MODE_LONG_READ_ATTN_ENABLE;
- REG_WR(pDevice, DmaWrite.Mode, Value32);
-
- if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE))
- {
- if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0)
- {
- Value16 = REG_RD(pDevice, PciCfg.PciXCommand);
- Value16 &= ~(PCIX_CMD_MAX_SPLIT_MASK | PCIX_CMD_MAX_BURST_MASK);
- Value16 |= ((PCIX_CMD_MAX_BURST_CPIOB << PCIX_CMD_MAX_BURST_SHL) &
- PCIX_CMD_MAX_BURST_MASK);
- if (pDevice->SplitModeEnable == SPLIT_MODE_ENABLE)
- {
- Value16 |= (pDevice->SplitModeMaxReq << PCIX_CMD_MAX_SPLIT_SHL)
- & PCIX_CMD_MAX_SPLIT_MASK;
- }
- REG_WR(pDevice, PciCfg.PciXCommand, Value16);
- }
- }
-
- /* Enable the Read DMA state machine. */
- Value32 = DMA_READ_MODE_ENABLE |
- DMA_READ_MODE_TARGET_ABORT_ATTN_ENABLE |
- DMA_READ_MODE_MASTER_ABORT_ATTN_ENABLE |
- DMA_READ_MODE_PARITY_ERROR_ATTN_ENABLE |
- DMA_READ_MODE_ADDR_OVERFLOW_ATTN_ENABLE |
- DMA_READ_MODE_FIFO_OVERRUN_ATTN_ENABLE |
- DMA_READ_MODE_FIFO_UNDERRUN_ATTN_ENABLE |
- DMA_READ_MODE_FIFO_OVERREAD_ATTN_ENABLE |
- DMA_READ_MODE_LONG_READ_ATTN_ENABLE;
-
- if (pDevice->SplitModeEnable == SPLIT_MODE_ENABLE)
- {
- Value32 |= DMA_READ_MODE_SPLIT_ENABLE;
- }
- REG_WR(pDevice, DmaRead.Mode, Value32);
-
- /* Enable the Receive Data Completion state machine. */
- REG_WR(pDevice, RcvDataComp.Mode, RCV_DATA_COMP_MODE_ENABLE |
- RCV_DATA_COMP_MODE_ATTN_ENABLE);
-
- /* Enable the Mbuf Cluster Free state machine. */
- REG_WR(pDevice, MbufClusterFree.Mode, MBUF_CLUSTER_FREE_MODE_ENABLE);
-
- /* Enable the Send Data Completion state machine. */
- REG_WR(pDevice, SndDataComp.Mode, SND_DATA_COMP_MODE_ENABLE);
-
- /* Enable the Send BD Completion state machine. */
- REG_WR(pDevice, SndBdComp.Mode, SND_BD_COMP_MODE_ENABLE |
- SND_BD_COMP_MODE_ATTN_ENABLE);
-
- /* Enable the Receive BD Initiator state machine. */
- REG_WR(pDevice, RcvBdIn.Mode, RCV_BD_IN_MODE_ENABLE |
- RCV_BD_IN_MODE_BD_IN_DIABLED_RCB_ATTN_ENABLE);
-
- /* Enable the Receive Data and Receive BD Initiator state machine. */
- REG_WR(pDevice, RcvDataBdIn.Mode, RCV_DATA_BD_IN_MODE_ENABLE |
- RCV_DATA_BD_IN_MODE_INVALID_RING_SIZE);
-
- /* Enable the Send Data Initiator state machine. */
- REG_WR(pDevice, SndDataIn.Mode, T3_SND_DATA_IN_MODE_ENABLE);
-
- /* Enable the Send BD Initiator state machine. */
- REG_WR(pDevice, SndBdIn.Mode, SND_BD_IN_MODE_ENABLE |
- SND_BD_IN_MODE_ATTN_ENABLE);
-
- /* Enable the Send BD Selector state machine. */
- REG_WR(pDevice, SndBdSel.Mode, SND_BD_SEL_MODE_ENABLE |
- SND_BD_SEL_MODE_ATTN_ENABLE);
+ pDevice->RxJumboProdIdx = 0;
+#endif /* T3_JUMBO_RCV_ENTRY_COUNT */
+
+ /* Configure the MAC address. */
+ LM_SetMacAddress (pDevice, pDevice->NodeAddress);
+
+ /* Initialize the transmit random backoff seed. */
+ Value32 = (pDevice->NodeAddress[0] + pDevice->NodeAddress[1] +
+ pDevice->NodeAddress[2] + pDevice->NodeAddress[3] +
+ pDevice->NodeAddress[4] + pDevice->NodeAddress[5]) &
+ MAC_TX_BACKOFF_SEED_MASK;
+ REG_WR (pDevice, MacCtrl.TxBackoffSeed, Value32);
+
+ /* Receive MTU. Frames larger than the MTU is marked as oversized. */
+ REG_WR (pDevice, MacCtrl.MtuSize, pDevice->RxMtu + 8); /* CRC + VLAN. */
+
+ /* Configure Time slot/IPG per 802.3 */
+ REG_WR (pDevice, MacCtrl.TxLengths, 0x2620);
+
+ /*
+ * Configure Receive Rules so that packets don't match
+ * Programmble rule will be queued to Return Ring 1
+ */
+ REG_WR (pDevice, MacCtrl.RcvRuleCfg, RX_RULE_DEFAULT_CLASS);
+
+ /*
+ * Configure to have 16 Classes of Services (COS) and one
+ * queue per class. Bad frames are queued to RRR#1.
+ * And frames don't match rules are also queued to COS#1.
+ */
+ REG_WR (pDevice, RcvListPlmt.Config, 0x181);
+
+ /* Enable Receive Placement Statistics */
+ REG_WR (pDevice, RcvListPlmt.StatsEnableMask, 0xffffff);
+ REG_WR (pDevice, RcvListPlmt.StatsCtrl, RCV_LIST_STATS_ENABLE);
+
+ /* Enable Send Data Initator Statistics */
+ REG_WR (pDevice, SndDataIn.StatsEnableMask, 0xffffff);
+ REG_WR (pDevice, SndDataIn.StatsCtrl,
+ T3_SND_DATA_IN_STATS_CTRL_ENABLE |
+ T3_SND_DATA_IN_STATS_CTRL_FASTER_UPDATE);
+
+ /* Disable the host coalescing state machine before configuring it's */
+ /* parameters. */
+ REG_WR (pDevice, HostCoalesce.Mode, 0);
+ for (j = 0; j < 2000; j++) {
+ Value32 = REG_RD (pDevice, HostCoalesce.Mode);
+ if (!(Value32 & HOST_COALESCE_ENABLE)) {
+ break;
+ }
+ MM_Wait (10);
+ }
+
+ /* Host coalescing configurations. */
+ REG_WR (pDevice, HostCoalesce.RxCoalescingTicks,
+ pDevice->RxCoalescingTicks);
+ REG_WR (pDevice, HostCoalesce.TxCoalescingTicks,
+ pDevice->TxCoalescingTicks);
+ REG_WR (pDevice, HostCoalesce.RxMaxCoalescedFrames,
+ pDevice->RxMaxCoalescedFrames);
+ REG_WR (pDevice, HostCoalesce.TxMaxCoalescedFrames,
+ pDevice->TxMaxCoalescedFrames);
+ REG_WR (pDevice, HostCoalesce.RxCoalescedTickDuringInt,
+ pDevice->RxCoalescingTicksDuringInt);
+ REG_WR (pDevice, HostCoalesce.TxCoalescedTickDuringInt,
+ pDevice->TxCoalescingTicksDuringInt);
+ REG_WR (pDevice, HostCoalesce.RxMaxCoalescedFramesDuringInt,
+ pDevice->RxMaxCoalescedFramesDuringInt);
+ REG_WR (pDevice, HostCoalesce.TxMaxCoalescedFramesDuringInt,
+ pDevice->TxMaxCoalescedFramesDuringInt);
+
+ /* Initialize the address of the status block. The NIC will DMA */
+ /* the status block to this memory which resides on the host. */
+ REG_WR (pDevice, HostCoalesce.StatusBlkHostAddr.High,
+ pDevice->StatusBlkPhy.High);
+ REG_WR (pDevice, HostCoalesce.StatusBlkHostAddr.Low,
+ pDevice->StatusBlkPhy.Low);
+
+ /* Initialize the address of the statistics block. The NIC will DMA */
+ /* the statistics to this block of memory. */
+ REG_WR (pDevice, HostCoalesce.StatsBlkHostAddr.High,
+ pDevice->StatsBlkPhy.High);
+ REG_WR (pDevice, HostCoalesce.StatsBlkHostAddr.Low,
+ pDevice->StatsBlkPhy.Low);
+
+ REG_WR (pDevice, HostCoalesce.StatsCoalescingTicks,
+ pDevice->StatsCoalescingTicks);
+
+ REG_WR (pDevice, HostCoalesce.StatsBlkNicAddr, 0x300);
+ REG_WR (pDevice, HostCoalesce.StatusBlkNicAddr, 0xb00);
+
+ /* Enable Host Coalesing state machine */
+ REG_WR (pDevice, HostCoalesce.Mode, HOST_COALESCE_ENABLE |
+ pDevice->CoalesceMode);
+
+ /* Enable the Receive BD Completion state machine. */
+ REG_WR (pDevice, RcvBdComp.Mode, RCV_BD_COMP_MODE_ENABLE |
+ RCV_BD_COMP_MODE_ATTN_ENABLE);
+
+ /* Enable the Receive List Placement state machine. */
+ REG_WR (pDevice, RcvListPlmt.Mode, RCV_LIST_PLMT_MODE_ENABLE);
+
+ /* Enable the Receive List Selector state machine. */
+ REG_WR (pDevice, RcvListSel.Mode, RCV_LIST_SEL_MODE_ENABLE |
+ RCV_LIST_SEL_MODE_ATTN_ENABLE);
+
+ /* Enable transmit DMA, clear statistics. */
+ pDevice->MacMode = MAC_MODE_ENABLE_TX_STATISTICS |
+ MAC_MODE_ENABLE_RX_STATISTICS | MAC_MODE_ENABLE_TDE |
+ MAC_MODE_ENABLE_RDE | MAC_MODE_ENABLE_FHDE;
+ REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode |
+ MAC_MODE_CLEAR_RX_STATISTICS | MAC_MODE_CLEAR_TX_STATISTICS);
+
+ /* GRC miscellaneous local control register. */
+ pDevice->GrcLocalCtrl = GRC_MISC_LOCAL_CTRL_INT_ON_ATTN |
+ GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM;
+
+ if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
+ pDevice->GrcLocalCtrl |= GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
+ GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1;
+ }
+
+ REG_WR (pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl);
+ MM_Wait (40);
+
+ /* Reset RX counters. */
+ for (j = 0; j < sizeof (LM_RX_COUNTERS); j++) {
+ ((PLM_UINT8) & pDevice->RxCounters)[j] = 0;
+ }
+
+ /* Reset TX counters. */
+ for (j = 0; j < sizeof (LM_TX_COUNTERS); j++) {
+ ((PLM_UINT8) & pDevice->TxCounters)[j] = 0;
+ }
+
+ MB_REG_WR (pDevice, Mailbox.Interrupt[0].Low, 0);
+
+ /* Enable the DMA Completion state machine. */
+ REG_WR (pDevice, DmaComp.Mode, DMA_COMP_MODE_ENABLE);
+
+ /* Enable the DMA Write state machine. */
+ Value32 = DMA_WRITE_MODE_ENABLE |
+ DMA_WRITE_MODE_TARGET_ABORT_ATTN_ENABLE |
+ DMA_WRITE_MODE_MASTER_ABORT_ATTN_ENABLE |
+ DMA_WRITE_MODE_PARITY_ERROR_ATTN_ENABLE |
+ DMA_WRITE_MODE_ADDR_OVERFLOW_ATTN_ENABLE |
+ DMA_WRITE_MODE_FIFO_OVERRUN_ATTN_ENABLE |
+ DMA_WRITE_MODE_FIFO_UNDERRUN_ATTN_ENABLE |
+ DMA_WRITE_MODE_FIFO_OVERREAD_ATTN_ENABLE |
+ DMA_WRITE_MODE_LONG_READ_ATTN_ENABLE;
+ REG_WR (pDevice, DmaWrite.Mode, Value32);
+
+ if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)) {
+ if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0) {
+ Value16 = REG_RD (pDevice, PciCfg.PciXCommand);
+ Value16 &=
+ ~(PCIX_CMD_MAX_SPLIT_MASK |
+ PCIX_CMD_MAX_BURST_MASK);
+ Value16 |=
+ ((PCIX_CMD_MAX_BURST_CPIOB <<
+ PCIX_CMD_MAX_BURST_SHL) &
+ PCIX_CMD_MAX_BURST_MASK);
+ if (pDevice->SplitModeEnable == SPLIT_MODE_ENABLE) {
+ Value16 |=
+ (pDevice->
+ SplitModeMaxReq << PCIX_CMD_MAX_SPLIT_SHL)
+ & PCIX_CMD_MAX_SPLIT_MASK;
+ }
+ REG_WR (pDevice, PciCfg.PciXCommand, Value16);
+ }
+ }
+
+ /* Enable the Read DMA state machine. */
+ Value32 = DMA_READ_MODE_ENABLE |
+ DMA_READ_MODE_TARGET_ABORT_ATTN_ENABLE |
+ DMA_READ_MODE_MASTER_ABORT_ATTN_ENABLE |
+ DMA_READ_MODE_PARITY_ERROR_ATTN_ENABLE |
+ DMA_READ_MODE_ADDR_OVERFLOW_ATTN_ENABLE |
+ DMA_READ_MODE_FIFO_OVERRUN_ATTN_ENABLE |
+ DMA_READ_MODE_FIFO_UNDERRUN_ATTN_ENABLE |
+ DMA_READ_MODE_FIFO_OVERREAD_ATTN_ENABLE |
+ DMA_READ_MODE_LONG_READ_ATTN_ENABLE;
+
+ if (pDevice->SplitModeEnable == SPLIT_MODE_ENABLE) {
+ Value32 |= DMA_READ_MODE_SPLIT_ENABLE;
+ }
+ REG_WR (pDevice, DmaRead.Mode, Value32);
+
+ /* Enable the Receive Data Completion state machine. */
+ REG_WR (pDevice, RcvDataComp.Mode, RCV_DATA_COMP_MODE_ENABLE |
+ RCV_DATA_COMP_MODE_ATTN_ENABLE);
+
+ /* Enable the Mbuf Cluster Free state machine. */
+ REG_WR (pDevice, MbufClusterFree.Mode, MBUF_CLUSTER_FREE_MODE_ENABLE);
+
+ /* Enable the Send Data Completion state machine. */
+ REG_WR (pDevice, SndDataComp.Mode, SND_DATA_COMP_MODE_ENABLE);
+
+ /* Enable the Send BD Completion state machine. */
+ REG_WR (pDevice, SndBdComp.Mode, SND_BD_COMP_MODE_ENABLE |
+ SND_BD_COMP_MODE_ATTN_ENABLE);
+
+ /* Enable the Receive BD Initiator state machine. */
+ REG_WR (pDevice, RcvBdIn.Mode, RCV_BD_IN_MODE_ENABLE |
+ RCV_BD_IN_MODE_BD_IN_DIABLED_RCB_ATTN_ENABLE);
+
+ /* Enable the Receive Data and Receive BD Initiator state machine. */
+ REG_WR (pDevice, RcvDataBdIn.Mode, RCV_DATA_BD_IN_MODE_ENABLE |
+ RCV_DATA_BD_IN_MODE_INVALID_RING_SIZE);
+
+ /* Enable the Send Data Initiator state machine. */
+ REG_WR (pDevice, SndDataIn.Mode, T3_SND_DATA_IN_MODE_ENABLE);
+
+ /* Enable the Send BD Initiator state machine. */
+ REG_WR (pDevice, SndBdIn.Mode, SND_BD_IN_MODE_ENABLE |
+ SND_BD_IN_MODE_ATTN_ENABLE);
+
+ /* Enable the Send BD Selector state machine. */
+ REG_WR (pDevice, SndBdSel.Mode, SND_BD_SEL_MODE_ENABLE |
+ SND_BD_SEL_MODE_ATTN_ENABLE);
#if INCLUDE_5701_AX_FIX
- /* Load the firmware for the 5701_A0 workaround. */
- if(pDevice->ChipRevId == T3_CHIP_ID_5701_A0)
- {
- LM_LoadRlsFirmware(pDevice);
- }
+ /* Load the firmware for the 5701_A0 workaround. */
+ if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0) {
+ LM_LoadRlsFirmware (pDevice);
+ }
#endif
- /* Enable the transmitter. */
- pDevice->TxMode = TX_MODE_ENABLE;
- REG_WR(pDevice, MacCtrl.TxMode, pDevice->TxMode);
-
- /* Enable the receiver. */
- pDevice->RxMode = RX_MODE_ENABLE;
- REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode);
-
- if (pDevice->RestoreOnWakeUp)
- {
- pDevice->RestoreOnWakeUp = FALSE;
- pDevice->DisableAutoNeg = pDevice->WakeUpDisableAutoNeg;
- pDevice->RequestedMediaType = pDevice->WakeUpRequestedMediaType;
- }
-
- /* Disable auto polling. */
- pDevice->MiMode = 0xc0000;
- REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode);
-
- if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
- T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)
- {
- Value32 = LED_CTRL_PHY_MODE_1;
- }
- else
- {
- if(pDevice->LedMode == LED_MODE_OUTPUT)
- {
- Value32 = LED_CTRL_PHY_MODE_2;
- }
- else
- {
- Value32 = LED_CTRL_PHY_MODE_1;
+ /* Enable the transmitter. */
+ pDevice->TxMode = TX_MODE_ENABLE;
+ REG_WR (pDevice, MacCtrl.TxMode, pDevice->TxMode);
+
+ /* Enable the receiver. */
+ pDevice->RxMode = RX_MODE_ENABLE;
+ REG_WR (pDevice, MacCtrl.RxMode, pDevice->RxMode);
+
+ if (pDevice->RestoreOnWakeUp) {
+ pDevice->RestoreOnWakeUp = FALSE;
+ pDevice->DisableAutoNeg = pDevice->WakeUpDisableAutoNeg;
+ pDevice->RequestedMediaType = pDevice->WakeUpRequestedMediaType;
}
- }
- REG_WR(pDevice, MacCtrl.LedCtrl, Value32);
- /* Activate Link to enable MAC state machine */
- REG_WR(pDevice, MacCtrl.MiStatus, MI_STATUS_ENABLE_LINK_STATUS_ATTN);
+ /* Disable auto polling. */
+ pDevice->MiMode = 0xc0000;
+ REG_WR (pDevice, MacCtrl.MiMode, pDevice->MiMode);
- if (pDevice->EnableTbi)
- {
- REG_WR(pDevice, MacCtrl.RxMode, RX_MODE_RESET);
- MM_Wait(10);
- REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode);
- if (pDevice->ChipRevId == T3_CHIP_ID_5703_A1)
- {
- REG_WR(pDevice, MacCtrl.SerdesCfg, 0x616000);
+ if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
+ T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
+ Value32 = LED_CTRL_PHY_MODE_1;
+ } else {
+ if (pDevice->LedMode == LED_MODE_OUTPUT) {
+ Value32 = LED_CTRL_PHY_MODE_2;
+ } else {
+ Value32 = LED_CTRL_PHY_MODE_1;
+ }
}
- }
- /* Setup the phy chip. */
- LM_SetupPhy(pDevice);
+ REG_WR (pDevice, MacCtrl.LedCtrl, Value32);
- if (!pDevice->EnableTbi) {
- /* Clear CRC stats */
- LM_ReadPhy(pDevice, 0x1e, &Value32);
- LM_WritePhy(pDevice, 0x1e, Value32 | 0x8000);
- LM_ReadPhy(pDevice, 0x14, &Value32);
- }
+ /* Activate Link to enable MAC state machine */
+ REG_WR (pDevice, MacCtrl.MiStatus, MI_STATUS_ENABLE_LINK_STATUS_ATTN);
- /* Set up the receive mask. */
- LM_SetReceiveMask(pDevice, pDevice->ReceiveMask);
+ if (pDevice->EnableTbi) {
+ REG_WR (pDevice, MacCtrl.RxMode, RX_MODE_RESET);
+ MM_Wait (10);
+ REG_WR (pDevice, MacCtrl.RxMode, pDevice->RxMode);
+ if (pDevice->ChipRevId == T3_CHIP_ID_5703_A1) {
+ REG_WR (pDevice, MacCtrl.SerdesCfg, 0x616000);
+ }
+ }
+ /* Setup the phy chip. */
+ LM_SetupPhy (pDevice);
- /* Queue Rx packet buffers. */
- if(pDevice->QueueRxPackets)
- {
- LM_QueueRxPackets(pDevice);
- }
+ if (!pDevice->EnableTbi) {
+ /* Clear CRC stats */
+ LM_ReadPhy (pDevice, 0x1e, &Value32);
+ LM_WritePhy (pDevice, 0x1e, Value32 | 0x8000);
+ LM_ReadPhy (pDevice, 0x14, &Value32);
+ }
- /* Enable interrupt to the host. */
- if(pDevice->InitDone)
- {
- LM_EnableInterrupt(pDevice);
- }
+ /* Set up the receive mask. */
+ LM_SetReceiveMask (pDevice, pDevice->ReceiveMask);
- return LM_STATUS_SUCCESS;
-} /* LM_ResetAdapter */
+ /* Queue Rx packet buffers. */
+ if (pDevice->QueueRxPackets) {
+ LM_QueueRxPackets (pDevice);
+ }
+ /* Enable interrupt to the host. */
+ if (pDevice->InitDone) {
+ LM_EnableInterrupt (pDevice);
+ }
+
+ return LM_STATUS_SUCCESS;
+} /* LM_ResetAdapter */
/******************************************************************************/
/* Description: */
@@ -2979,18 +2762,15 @@ PLM_DEVICE_BLOCK pDevice)
/* Return: */
/* LM_STATUS_SUCCESS */
/******************************************************************************/
-LM_STATUS
-LM_DisableInterrupt(
- PLM_DEVICE_BLOCK pDevice)
+LM_STATUS LM_DisableInterrupt (PLM_DEVICE_BLOCK pDevice)
{
- REG_WR(pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl |
- MISC_HOST_CTRL_MASK_PCI_INT);
- MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, 1);
+ REG_WR (pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl |
+ MISC_HOST_CTRL_MASK_PCI_INT);
+ MB_REG_WR (pDevice, Mailbox.Interrupt[0].Low, 1);
- return LM_STATUS_SUCCESS;
+ return LM_STATUS_SUCCESS;
}
-
/******************************************************************************/
/* Description: */
/* This routine enables the adapter to generate interrupts. */
@@ -2998,24 +2778,20 @@ LM_DisableInterrupt(
/* Return: */
/* LM_STATUS_SUCCESS */
/******************************************************************************/
-LM_STATUS
-LM_EnableInterrupt(
- PLM_DEVICE_BLOCK pDevice)
+LM_STATUS LM_EnableInterrupt (PLM_DEVICE_BLOCK pDevice)
{
- REG_WR(pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl &
- ~MISC_HOST_CTRL_MASK_PCI_INT);
- MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, 0);
+ REG_WR (pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl &
+ ~MISC_HOST_CTRL_MASK_PCI_INT);
+ MB_REG_WR (pDevice, Mailbox.Interrupt[0].Low, 0);
- if(pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_UPDATED)
- {
- REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
- GRC_MISC_LOCAL_CTRL_SET_INT);
- }
+ if (pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_UPDATED) {
+ REG_WR (pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
+ GRC_MISC_LOCAL_CTRL_SET_INT);
+ }
- return LM_STATUS_SUCCESS;
+ return LM_STATUS_SUCCESS;
}
-
/******************************************************************************/
/* Description: */
/* This routine puts a packet on the wire if there is a transmit DMA */
@@ -3027,306 +2803,279 @@ LM_EnableInterrupt(
/* LM_STATUS_SUCCESS */
/******************************************************************************/
#if 0
-LM_STATUS
-LM_SendPacket(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket)
+LM_STATUS LM_SendPacket (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket)
{
- LM_UINT32 FragCount;
- PT3_SND_BD pSendBd;
- PT3_SND_BD pShadowSendBd;
- LM_UINT32 Value32, Len;
- LM_UINT32 Idx;
+ LM_UINT32 FragCount;
+ PT3_SND_BD pSendBd;
+ PT3_SND_BD pShadowSendBd;
+ LM_UINT32 Value32, Len;
+ LM_UINT32 Idx;
- if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) {
- return LM_5700SendPacket(pDevice, pPacket);
- }
+ if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
+ return LM_5700SendPacket (pDevice, pPacket);
+ }
- /* Update the SendBdLeft count. */
- atomic_sub(pPacket->u.Tx.FragCount, &pDevice->SendBdLeft);
+ /* Update the SendBdLeft count. */
+ atomic_sub (pPacket->u.Tx.FragCount, &pDevice->SendBdLeft);
- /* Initalize the send buffer descriptors. */
- Idx = pDevice->SendProdIdx;
+ /* Initalize the send buffer descriptors. */
+ Idx = pDevice->SendProdIdx;
- pSendBd = &pDevice->pSendBdVirt[Idx];
+ pSendBd = &pDevice->pSendBdVirt[Idx];
- /* Next producer index. */
- if (pDevice->NicSendBd == TRUE)
- {
- T3_64BIT_HOST_ADDR paddr;
+ /* Next producer index. */
+ if (pDevice->NicSendBd == TRUE) {
+ T3_64BIT_HOST_ADDR paddr;
+
+ pShadowSendBd = &pDevice->ShadowSendBd[Idx];
+ for (FragCount = 0;;) {
+ MM_MapTxDma (pDevice, pPacket, &paddr, &Len, FragCount);
+ /* Initialize the pointer to the send buffer fragment. */
+ if (paddr.High != pShadowSendBd->HostAddr.High) {
+ __raw_writel (paddr.High,
+ &(pSendBd->HostAddr.High));
+ pShadowSendBd->HostAddr.High = paddr.High;
+ }
+ __raw_writel (paddr.Low, &(pSendBd->HostAddr.Low));
+
+ /* Setup the control flags and send buffer size. */
+ Value32 = (Len << 16) | pPacket->Flags;
+
+ Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK;
+
+ FragCount++;
+ if (FragCount >= pPacket->u.Tx.FragCount) {
+ Value32 |= SND_BD_FLAG_END;
+ if (Value32 != pShadowSendBd->u1.Len_Flags) {
+ __raw_writel (Value32,
+ &(pSendBd->u1.Len_Flags));
+ pShadowSendBd->u1.Len_Flags = Value32;
+ }
+ if (pPacket->Flags & SND_BD_FLAG_VLAN_TAG) {
+ __raw_writel (pPacket->VlanTag,
+ &(pSendBd->u2.VlanTag));
+ }
+ break;
+ } else {
+ if (Value32 != pShadowSendBd->u1.Len_Flags) {
+ __raw_writel (Value32,
+ &(pSendBd->u1.Len_Flags));
+ pShadowSendBd->u1.Len_Flags = Value32;
+ }
+ if (pPacket->Flags & SND_BD_FLAG_VLAN_TAG) {
+ __raw_writel (pPacket->VlanTag,
+ &(pSendBd->u2.VlanTag));
+ }
+ }
- pShadowSendBd = &pDevice->ShadowSendBd[Idx];
- for(FragCount = 0; ; )
- {
- MM_MapTxDma(pDevice, pPacket, &paddr, &Len, FragCount);
- /* Initialize the pointer to the send buffer fragment. */
- if (paddr.High != pShadowSendBd->HostAddr.High)
- {
- __raw_writel(paddr.High, &(pSendBd->HostAddr.High));
- pShadowSendBd->HostAddr.High = paddr.High;
- }
- __raw_writel(paddr.Low, &(pSendBd->HostAddr.Low));
-
- /* Setup the control flags and send buffer size. */
- Value32 = (Len << 16) | pPacket->Flags;
-
- Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK;
-
- FragCount++;
- if (FragCount >= pPacket->u.Tx.FragCount)
- {
- Value32 |= SND_BD_FLAG_END;
- if (Value32 != pShadowSendBd->u1.Len_Flags)
- {
- __raw_writel(Value32, &(pSendBd->u1.Len_Flags));
- pShadowSendBd->u1.Len_Flags = Value32;
- }
- if (pPacket->Flags & SND_BD_FLAG_VLAN_TAG) {
- __raw_writel(pPacket->VlanTag, &(pSendBd->u2.VlanTag));
- }
- break;
- }
- else
- {
- if (Value32 != pShadowSendBd->u1.Len_Flags)
- {
- __raw_writel(Value32, &(pSendBd->u1.Len_Flags));
- pShadowSendBd->u1.Len_Flags = Value32;
- }
- if (pPacket->Flags & SND_BD_FLAG_VLAN_TAG) {
- __raw_writel(pPacket->VlanTag, &(pSendBd->u2.VlanTag));
- }
- }
-
- pSendBd++;
- pShadowSendBd++;
- if (Idx == 0)
- {
- pSendBd = &pDevice->pSendBdVirt[0];
- pShadowSendBd = &pDevice->ShadowSendBd[0];
- }
- } /* for */
+ pSendBd++;
+ pShadowSendBd++;
+ if (Idx == 0) {
+ pSendBd = &pDevice->pSendBdVirt[0];
+ pShadowSendBd = &pDevice->ShadowSendBd[0];
+ }
+ } /* for */
- /* Put the packet descriptor in the ActiveQ. */
- QQ_PushTail(&pDevice->TxPacketActiveQ.Container, pPacket);
+ /* Put the packet descriptor in the ActiveQ. */
+ QQ_PushTail (&pDevice->TxPacketActiveQ.Container, pPacket);
- wmb();
- MB_REG_WR(pDevice, Mailbox.SendNicProdIdx[0].Low, Idx);
+ wmb ();
+ MB_REG_WR (pDevice, Mailbox.SendNicProdIdx[0].Low, Idx);
- }
- else
- {
- for(FragCount = 0; ; )
- {
- /* Initialize the pointer to the send buffer fragment. */
- MM_MapTxDma(pDevice, pPacket, &pSendBd->HostAddr, &Len, FragCount);
+ } else {
+ for (FragCount = 0;;) {
+ /* Initialize the pointer to the send buffer fragment. */
+ MM_MapTxDma (pDevice, pPacket, &pSendBd->HostAddr, &Len,
+ FragCount);
- pSendBd->u2.VlanTag = pPacket->VlanTag;
+ pSendBd->u2.VlanTag = pPacket->VlanTag;
- /* Setup the control flags and send buffer size. */
- Value32 = (Len << 16) | pPacket->Flags;
+ /* Setup the control flags and send buffer size. */
+ Value32 = (Len << 16) | pPacket->Flags;
- Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK;
+ Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK;
- FragCount++;
- if (FragCount >= pPacket->u.Tx.FragCount)
- {
- pSendBd->u1.Len_Flags = Value32 | SND_BD_FLAG_END;
- break;
- }
- else
- {
- pSendBd->u1.Len_Flags = Value32;
- }
- pSendBd++;
- if (Idx == 0)
- {
- pSendBd = &pDevice->pSendBdVirt[0];
- }
- } /* for */
+ FragCount++;
+ if (FragCount >= pPacket->u.Tx.FragCount) {
+ pSendBd->u1.Len_Flags =
+ Value32 | SND_BD_FLAG_END;
+ break;
+ } else {
+ pSendBd->u1.Len_Flags = Value32;
+ }
+ pSendBd++;
+ if (Idx == 0) {
+ pSendBd = &pDevice->pSendBdVirt[0];
+ }
+ } /* for */
- /* Put the packet descriptor in the ActiveQ. */
- QQ_PushTail(&pDevice->TxPacketActiveQ.Container, pPacket);
+ /* Put the packet descriptor in the ActiveQ. */
+ QQ_PushTail (&pDevice->TxPacketActiveQ.Container, pPacket);
- wmb();
- MB_REG_WR(pDevice, Mailbox.SendHostProdIdx[0].Low, Idx);
+ wmb ();
+ MB_REG_WR (pDevice, Mailbox.SendHostProdIdx[0].Low, Idx);
- }
+ }
- /* Update the producer index. */
- pDevice->SendProdIdx = Idx;
+ /* Update the producer index. */
+ pDevice->SendProdIdx = Idx;
- return LM_STATUS_SUCCESS;
+ return LM_STATUS_SUCCESS;
}
#endif
-LM_STATUS
-LM_SendPacket(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket)
+LM_STATUS LM_SendPacket (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket)
{
- LM_UINT32 FragCount;
- PT3_SND_BD pSendBd, pTmpSendBd, pShadowSendBd;
- T3_SND_BD NicSendBdArr[MAX_FRAGMENT_COUNT];
- LM_UINT32 StartIdx, Idx;
+ LM_UINT32 FragCount;
+ PT3_SND_BD pSendBd, pTmpSendBd, pShadowSendBd;
+ T3_SND_BD NicSendBdArr[MAX_FRAGMENT_COUNT];
+ LM_UINT32 StartIdx, Idx;
+
+ while (1) {
+ /* Initalize the send buffer descriptors. */
+ StartIdx = Idx = pDevice->SendProdIdx;
+
+ if (pDevice->NicSendBd) {
+ pTmpSendBd = pSendBd = &NicSendBdArr[0];
+ } else {
+ pTmpSendBd = pSendBd = &pDevice->pSendBdVirt[Idx];
+ }
- while (1)
- {
- /* Initalize the send buffer descriptors. */
- StartIdx = Idx = pDevice->SendProdIdx;
+ /* Next producer index. */
+ for (FragCount = 0;;) {
+ LM_UINT32 Value32, Len;
- if (pDevice->NicSendBd)
- {
- pTmpSendBd = pSendBd = &NicSendBdArr[0];
- }
- else
- {
- pTmpSendBd = pSendBd = &pDevice->pSendBdVirt[Idx];
+ /* Initialize the pointer to the send buffer fragment. */
+ MM_MapTxDma (pDevice, pPacket, &pSendBd->HostAddr, &Len,
+ FragCount);
+
+ pSendBd->u2.VlanTag = pPacket->VlanTag;
+
+ /* Setup the control flags and send buffer size. */
+ Value32 = (Len << 16) | pPacket->Flags;
+
+ Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK;
+
+ FragCount++;
+ if (FragCount >= pPacket->u.Tx.FragCount) {
+ pSendBd->u1.Len_Flags =
+ Value32 | SND_BD_FLAG_END;
+ break;
+ } else {
+ pSendBd->u1.Len_Flags = Value32;
+ }
+ pSendBd++;
+ if ((Idx == 0) && !pDevice->NicSendBd) {
+ pSendBd = &pDevice->pSendBdVirt[0];
+ }
+ } /* for */
+ if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
+ if (LM_Test4GBoundary (pDevice, pPacket, pTmpSendBd) ==
+ LM_STATUS_SUCCESS) {
+ if (MM_CoalesceTxBuffer (pDevice, pPacket) !=
+ LM_STATUS_SUCCESS) {
+ QQ_PushHead (&pDevice->TxPacketFreeQ.
+ Container, pPacket);
+ return LM_STATUS_FAILURE;
+ }
+ continue;
+ }
+ }
+ break;
}
+ /* Put the packet descriptor in the ActiveQ. */
+ QQ_PushTail (&pDevice->TxPacketActiveQ.Container, pPacket);
- /* Next producer index. */
- for(FragCount = 0; ; )
- {
- LM_UINT32 Value32, Len;
+ if (pDevice->NicSendBd) {
+ pSendBd = &pDevice->pSendBdVirt[StartIdx];
+ pShadowSendBd = &pDevice->ShadowSendBd[StartIdx];
- /* Initialize the pointer to the send buffer fragment. */
- MM_MapTxDma(pDevice, pPacket, &pSendBd->HostAddr, &Len, FragCount);
+ while (StartIdx != Idx) {
+ LM_UINT32 Value32;
- pSendBd->u2.VlanTag = pPacket->VlanTag;
+ if ((Value32 = pTmpSendBd->HostAddr.High) !=
+ pShadowSendBd->HostAddr.High) {
+ __raw_writel (Value32,
+ &(pSendBd->HostAddr.High));
+ pShadowSendBd->HostAddr.High = Value32;
+ }
- /* Setup the control flags and send buffer size. */
- Value32 = (Len << 16) | pPacket->Flags;
+ __raw_writel (pTmpSendBd->HostAddr.Low,
+ &(pSendBd->HostAddr.Low));
- Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK;
+ if ((Value32 = pTmpSendBd->u1.Len_Flags) !=
+ pShadowSendBd->u1.Len_Flags) {
+ __raw_writel (Value32,
+ &(pSendBd->u1.Len_Flags));
+ pShadowSendBd->u1.Len_Flags = Value32;
+ }
- FragCount++;
- if (FragCount >= pPacket->u.Tx.FragCount)
- {
- pSendBd->u1.Len_Flags = Value32 | SND_BD_FLAG_END;
- break;
- }
- else
- {
- pSendBd->u1.Len_Flags = Value32;
- }
- pSendBd++;
- if ((Idx == 0) && !pDevice->NicSendBd)
- {
- pSendBd = &pDevice->pSendBdVirt[0];
- }
- } /* for */
- if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
- {
- if (LM_Test4GBoundary(pDevice, pPacket, pTmpSendBd) ==
- LM_STATUS_SUCCESS)
- {
- if (MM_CoalesceTxBuffer(pDevice, pPacket) != LM_STATUS_SUCCESS)
- {
- QQ_PushHead(&pDevice->TxPacketFreeQ.Container, pPacket);
- return LM_STATUS_FAILURE;
- }
- continue;
- }
- }
- break;
- }
- /* Put the packet descriptor in the ActiveQ. */
- QQ_PushTail(&pDevice->TxPacketActiveQ.Container, pPacket);
-
- if (pDevice->NicSendBd)
- {
- pSendBd = &pDevice->pSendBdVirt[StartIdx];
- pShadowSendBd = &pDevice->ShadowSendBd[StartIdx];
-
- while (StartIdx != Idx)
- {
- LM_UINT32 Value32;
-
- if ((Value32 = pTmpSendBd->HostAddr.High) !=
- pShadowSendBd->HostAddr.High)
- {
- __raw_writel(Value32, &(pSendBd->HostAddr.High));
- pShadowSendBd->HostAddr.High = Value32;
- }
-
- __raw_writel(pTmpSendBd->HostAddr.Low, &(pSendBd->HostAddr.Low));
-
- if ((Value32 = pTmpSendBd->u1.Len_Flags) !=
- pShadowSendBd->u1.Len_Flags)
- {
- __raw_writel(Value32, &(pSendBd->u1.Len_Flags));
- pShadowSendBd->u1.Len_Flags = Value32;
- }
-
- if (pPacket->Flags & SND_BD_FLAG_VLAN_TAG)
- {
- __raw_writel(pTmpSendBd->u2.VlanTag, &(pSendBd->u2.VlanTag));
- }
-
- StartIdx = (StartIdx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK;
- if (StartIdx == 0)
- pSendBd = &pDevice->pSendBdVirt[0];
- else
- pSendBd++;
- pTmpSendBd++;
- }
- wmb();
- MB_REG_WR(pDevice, Mailbox.SendNicProdIdx[0].Low, Idx);
+ if (pPacket->Flags & SND_BD_FLAG_VLAN_TAG) {
+ __raw_writel (pTmpSendBd->u2.VlanTag,
+ &(pSendBd->u2.VlanTag));
+ }
- if(T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5700_BX)
- {
- MB_REG_WR(pDevice, Mailbox.SendNicProdIdx[0].Low, Idx);
- }
- }
- else
- {
- wmb();
- MB_REG_WR(pDevice, Mailbox.SendHostProdIdx[0].Low, Idx);
+ StartIdx =
+ (StartIdx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK;
+ if (StartIdx == 0)
+ pSendBd = &pDevice->pSendBdVirt[0];
+ else
+ pSendBd++;
+ pTmpSendBd++;
+ }
+ wmb ();
+ MB_REG_WR (pDevice, Mailbox.SendNicProdIdx[0].Low, Idx);
- if(T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5700_BX)
- {
- MB_REG_WR(pDevice, Mailbox.SendHostProdIdx[0].Low, Idx);
+ if (T3_CHIP_REV (pDevice->ChipRevId) == T3_CHIP_REV_5700_BX) {
+ MB_REG_WR (pDevice, Mailbox.SendNicProdIdx[0].Low, Idx);
+ }
+ } else {
+ wmb ();
+ MB_REG_WR (pDevice, Mailbox.SendHostProdIdx[0].Low, Idx);
+
+ if (T3_CHIP_REV (pDevice->ChipRevId) == T3_CHIP_REV_5700_BX) {
+ MB_REG_WR (pDevice, Mailbox.SendHostProdIdx[0].Low,
+ Idx);
+ }
}
- }
- /* Update the SendBdLeft count. */
- atomic_sub(pPacket->u.Tx.FragCount, &pDevice->SendBdLeft);
+ /* Update the SendBdLeft count. */
+ atomic_sub (pPacket->u.Tx.FragCount, &pDevice->SendBdLeft);
- /* Update the producer index. */
- pDevice->SendProdIdx = Idx;
+ /* Update the producer index. */
+ pDevice->SendProdIdx = Idx;
- return LM_STATUS_SUCCESS;
+ return LM_STATUS_SUCCESS;
}
STATIC LM_STATUS
-LM_Test4GBoundary(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket,
- PT3_SND_BD pSendBd)
+LM_Test4GBoundary (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket,
+ PT3_SND_BD pSendBd)
{
- int FragCount;
- LM_UINT32 Idx, Base, Len;
-
- Idx = pDevice->SendProdIdx;
- for(FragCount = 0; ; )
- {
- Len = pSendBd->u1.Len_Flags >> 16;
- if (((Base = pSendBd->HostAddr.Low) > 0xffffdcc0) &&
- (pSendBd->HostAddr.High == 0) &&
- ((Base + 8 + Len) < Base))
- {
- return LM_STATUS_SUCCESS;
- }
- FragCount++;
- if (FragCount >= pPacket->u.Tx.FragCount)
- {
- break;
+ int FragCount;
+ LM_UINT32 Idx, Base, Len;
+
+ Idx = pDevice->SendProdIdx;
+ for (FragCount = 0;;) {
+ Len = pSendBd->u1.Len_Flags >> 16;
+ if (((Base = pSendBd->HostAddr.Low) > 0xffffdcc0) &&
+ (pSendBd->HostAddr.High == 0) &&
+ ((Base + 8 + Len) < Base)) {
+ return LM_STATUS_SUCCESS;
+ }
+ FragCount++;
+ if (FragCount >= pPacket->u.Tx.FragCount) {
+ break;
+ }
+ pSendBd++;
+ if (!pDevice->NicSendBd) {
+ Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK;
+ if (Idx == 0) {
+ pSendBd = &pDevice->pSendBdVirt[0];
+ }
+ }
}
- pSendBd++;
- if (!pDevice->NicSendBd)
- {
- Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK;
- if (Idx == 0)
- {
- pSendBd = &pDevice->pSendBdVirt[0];
- }
- }
- }
- return LM_STATUS_FAILURE;
+ return LM_STATUS_FAILURE;
}
/******************************************************************************/
@@ -3335,35 +3084,30 @@ LM_Test4GBoundary(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket,
/* Return: */
/******************************************************************************/
__inline static unsigned long
-ComputeCrc32(
-unsigned char *pBuffer,
-unsigned long BufferSize) {
- unsigned long Reg;
- unsigned long Tmp;
- unsigned long j, k;
+ComputeCrc32 (unsigned char *pBuffer, unsigned long BufferSize)
+{
+ unsigned long Reg;
+ unsigned long Tmp;
+ unsigned long j, k;
- Reg = 0xffffffff;
+ Reg = 0xffffffff;
- for(j = 0; j < BufferSize; j++)
- {
- Reg ^= pBuffer[j];
+ for (j = 0; j < BufferSize; j++) {
+ Reg ^= pBuffer[j];
- for(k = 0; k < 8; k++)
- {
- Tmp = Reg & 0x01;
+ for (k = 0; k < 8; k++) {
+ Tmp = Reg & 0x01;
- Reg >>= 1;
+ Reg >>= 1;
- if(Tmp)
- {
- Reg ^= 0xedb88320;
- }
+ if (Tmp) {
+ Reg ^= 0xedb88320;
+ }
+ }
}
- }
-
- return ~Reg;
-} /* ComputeCrc32 */
+ return ~Reg;
+} /* ComputeCrc32 */
/******************************************************************************/
/* Description: */
@@ -3372,149 +3116,139 @@ unsigned long BufferSize) {
/* Return: */
/* LM_STATUS_SUCCESS */
/******************************************************************************/
-LM_STATUS
-LM_SetReceiveMask(
-PLM_DEVICE_BLOCK pDevice,
-LM_UINT32 Mask) {
- LM_UINT32 ReceiveMask;
- LM_UINT32 RxMode;
- LM_UINT32 j, k;
-
- ReceiveMask = Mask;
-
- RxMode = pDevice->RxMode;
-
- if(Mask & LM_ACCEPT_UNICAST)
- {
- Mask &= ~LM_ACCEPT_UNICAST;
- }
-
- if(Mask & LM_ACCEPT_MULTICAST)
- {
- Mask &= ~LM_ACCEPT_MULTICAST;
- }
-
- if(Mask & LM_ACCEPT_ALL_MULTICAST)
- {
- Mask &= ~LM_ACCEPT_ALL_MULTICAST;
- }
-
- if(Mask & LM_ACCEPT_BROADCAST)
- {
- Mask &= ~LM_ACCEPT_BROADCAST;
- }
-
- RxMode &= ~RX_MODE_PROMISCUOUS_MODE;
- if(Mask & LM_PROMISCUOUS_MODE)
- {
- RxMode |= RX_MODE_PROMISCUOUS_MODE;
- Mask &= ~LM_PROMISCUOUS_MODE;
- }
-
- RxMode &= ~(RX_MODE_ACCEPT_RUNTS | RX_MODE_ACCEPT_OVERSIZED);
- if(Mask & LM_ACCEPT_ERROR_PACKET)
- {
- RxMode |= RX_MODE_ACCEPT_RUNTS | RX_MODE_ACCEPT_OVERSIZED;
- Mask &= ~LM_ACCEPT_ERROR_PACKET;
- }
-
- /* Make sure all the bits are valid before committing changes. */
- if(Mask)
- {
- return LM_STATUS_FAILURE;
- }
+LM_STATUS LM_SetReceiveMask (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Mask)
+{
+ LM_UINT32 ReceiveMask;
+ LM_UINT32 RxMode;
+ LM_UINT32 j, k;
- /* Commit the new filter. */
- pDevice->RxMode = RxMode;
- REG_WR(pDevice, MacCtrl.RxMode, RxMode);
+ ReceiveMask = Mask;
- pDevice->ReceiveMask = ReceiveMask;
+ RxMode = pDevice->RxMode;
- /* Set up the MC hash table. */
- if(ReceiveMask & LM_ACCEPT_ALL_MULTICAST)
- {
- for(k = 0; k < 4; k++)
- {
- REG_WR(pDevice, MacCtrl.HashReg[k], 0xffffffff);
+ if (Mask & LM_ACCEPT_UNICAST) {
+ Mask &= ~LM_ACCEPT_UNICAST;
}
- }
- else if(ReceiveMask & LM_ACCEPT_MULTICAST)
- {
- LM_UINT32 HashReg[4];
- HashReg[0] = 0; HashReg[1] = 0; HashReg[2] = 0; HashReg[3] = 0;
- for(j = 0; j < pDevice->McEntryCount; j++)
- {
- LM_UINT32 RegIndex;
- LM_UINT32 Bitpos;
- LM_UINT32 Crc32;
+ if (Mask & LM_ACCEPT_MULTICAST) {
+ Mask &= ~LM_ACCEPT_MULTICAST;
+ }
+
+ if (Mask & LM_ACCEPT_ALL_MULTICAST) {
+ Mask &= ~LM_ACCEPT_ALL_MULTICAST;
+ }
- Crc32 = ComputeCrc32(pDevice->McTable[j], ETHERNET_ADDRESS_SIZE);
+ if (Mask & LM_ACCEPT_BROADCAST) {
+ Mask &= ~LM_ACCEPT_BROADCAST;
+ }
- /* The most significant 7 bits of the CRC32 (no inversion), */
- /* are used to index into one of the possible 128 bit positions. */
- Bitpos = ~Crc32 & 0x7f;
+ RxMode &= ~RX_MODE_PROMISCUOUS_MODE;
+ if (Mask & LM_PROMISCUOUS_MODE) {
+ RxMode |= RX_MODE_PROMISCUOUS_MODE;
+ Mask &= ~LM_PROMISCUOUS_MODE;
+ }
- /* Hash register index. */
- RegIndex = (Bitpos & 0x60) >> 5;
+ RxMode &= ~(RX_MODE_ACCEPT_RUNTS | RX_MODE_ACCEPT_OVERSIZED);
+ if (Mask & LM_ACCEPT_ERROR_PACKET) {
+ RxMode |= RX_MODE_ACCEPT_RUNTS | RX_MODE_ACCEPT_OVERSIZED;
+ Mask &= ~LM_ACCEPT_ERROR_PACKET;
+ }
- /* Bit to turn on within a hash register. */
- Bitpos &= 0x1f;
+ /* Make sure all the bits are valid before committing changes. */
+ if (Mask) {
+ return LM_STATUS_FAILURE;
+ }
+
+ /* Commit the new filter. */
+ pDevice->RxMode = RxMode;
+ REG_WR (pDevice, MacCtrl.RxMode, RxMode);
+
+ pDevice->ReceiveMask = ReceiveMask;
+
+ /* Set up the MC hash table. */
+ if (ReceiveMask & LM_ACCEPT_ALL_MULTICAST) {
+ for (k = 0; k < 4; k++) {
+ REG_WR (pDevice, MacCtrl.HashReg[k], 0xffffffff);
+ }
+ } else if (ReceiveMask & LM_ACCEPT_MULTICAST) {
+ LM_UINT32 HashReg[4];
+
+ HashReg[0] = 0;
+ HashReg[1] = 0;
+ HashReg[2] = 0;
+ HashReg[3] = 0;
+ for (j = 0; j < pDevice->McEntryCount; j++) {
+ LM_UINT32 RegIndex;
+ LM_UINT32 Bitpos;
+ LM_UINT32 Crc32;
+
+ Crc32 =
+ ComputeCrc32 (pDevice->McTable[j],
+ ETHERNET_ADDRESS_SIZE);
+
+ /* The most significant 7 bits of the CRC32 (no inversion), */
+ /* are used to index into one of the possible 128 bit positions. */
+ Bitpos = ~Crc32 & 0x7f;
+
+ /* Hash register index. */
+ RegIndex = (Bitpos & 0x60) >> 5;
+
+ /* Bit to turn on within a hash register. */
+ Bitpos &= 0x1f;
+
+ /* Enable the multicast bit. */
+ HashReg[RegIndex] |= (1 << Bitpos);
+ }
- /* Enable the multicast bit. */
- HashReg[RegIndex] |= (1 << Bitpos);
+ /* REV_AX has problem with multicast filtering where it uses both */
+ /* DA and SA to perform hashing. */
+ for (k = 0; k < 4; k++) {
+ REG_WR (pDevice, MacCtrl.HashReg[k], HashReg[k]);
+ }
+ } else {
+ /* Reject all multicast frames. */
+ for (j = 0; j < 4; j++) {
+ REG_WR (pDevice, MacCtrl.HashReg[j], 0);
+ }
}
- /* REV_AX has problem with multicast filtering where it uses both */
- /* DA and SA to perform hashing. */
- for(k = 0; k < 4; k++)
- {
- REG_WR(pDevice, MacCtrl.HashReg[k], HashReg[k]);
+ /* By default, Tigon3 will accept broadcast frames. We need to setup */
+ if (ReceiveMask & LM_ACCEPT_BROADCAST) {
+ REG_WR (pDevice,
+ MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Rule,
+ REJECT_BROADCAST_RULE1_RULE & RCV_DISABLE_RULE_MASK);
+ REG_WR (pDevice,
+ MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Value,
+ REJECT_BROADCAST_RULE1_VALUE & RCV_DISABLE_RULE_MASK);
+ REG_WR (pDevice,
+ MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Rule,
+ REJECT_BROADCAST_RULE1_RULE & RCV_DISABLE_RULE_MASK);
+ REG_WR (pDevice,
+ MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Value,
+ REJECT_BROADCAST_RULE1_VALUE & RCV_DISABLE_RULE_MASK);
+ } else {
+ REG_WR (pDevice,
+ MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Rule,
+ REJECT_BROADCAST_RULE1_RULE);
+ REG_WR (pDevice,
+ MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Value,
+ REJECT_BROADCAST_RULE1_VALUE);
+ REG_WR (pDevice,
+ MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Rule,
+ REJECT_BROADCAST_RULE2_RULE);
+ REG_WR (pDevice,
+ MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Value,
+ REJECT_BROADCAST_RULE2_VALUE);
+ }
+
+ /* disable the rest of the rules. */
+ for (j = RCV_LAST_RULE_IDX; j < 16; j++) {
+ REG_WR (pDevice, MacCtrl.RcvRules[j].Rule, 0);
+ REG_WR (pDevice, MacCtrl.RcvRules[j].Value, 0);
}
- }
- else
- {
- /* Reject all multicast frames. */
- for(j = 0; j < 4; j++)
- {
- REG_WR(pDevice, MacCtrl.HashReg[j], 0);
- }
- }
-
- /* By default, Tigon3 will accept broadcast frames. We need to setup */
- if(ReceiveMask & LM_ACCEPT_BROADCAST)
- {
- REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Rule,
- REJECT_BROADCAST_RULE1_RULE & RCV_DISABLE_RULE_MASK);
- REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Value,
- REJECT_BROADCAST_RULE1_VALUE & RCV_DISABLE_RULE_MASK);
- REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Rule,
- REJECT_BROADCAST_RULE1_RULE & RCV_DISABLE_RULE_MASK);
- REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Value,
- REJECT_BROADCAST_RULE1_VALUE & RCV_DISABLE_RULE_MASK);
- }
- else
- {
- REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Rule,
- REJECT_BROADCAST_RULE1_RULE);
- REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Value,
- REJECT_BROADCAST_RULE1_VALUE);
- REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Rule,
- REJECT_BROADCAST_RULE2_RULE);
- REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Value,
- REJECT_BROADCAST_RULE2_VALUE);
- }
-
- /* disable the rest of the rules. */
- for(j = RCV_LAST_RULE_IDX; j < 16; j++)
- {
- REG_WR(pDevice, MacCtrl.RcvRules[j].Rule, 0);
- REG_WR(pDevice, MacCtrl.RcvRules[j].Value, 0);
- }
-
- return LM_STATUS_SUCCESS;
-} /* LM_SetReceiveMask */
+ return LM_STATUS_SUCCESS;
+} /* LM_SetReceiveMask */
/******************************************************************************/
/* Description: */
@@ -3525,138 +3259,135 @@ LM_UINT32 Mask) {
/* Return: */
/* LM_STATUS_SUCCESS */
/******************************************************************************/
-LM_STATUS
-LM_Abort(
-PLM_DEVICE_BLOCK pDevice)
+LM_STATUS LM_Abort (PLM_DEVICE_BLOCK pDevice)
{
- PLM_PACKET pPacket;
- LM_UINT Idx;
-
- LM_DisableInterrupt(pDevice);
-
- /* Disable all the state machines. */
- LM_CntrlBlock(pDevice,T3_BLOCK_MAC_RX_ENGINE,LM_DISABLE);
- LM_CntrlBlock(pDevice,T3_BLOCK_RX_BD_INITIATOR,LM_DISABLE);
- LM_CntrlBlock(pDevice,T3_BLOCK_RX_LIST_PLMT,LM_DISABLE);
- LM_CntrlBlock(pDevice,T3_BLOCK_RX_LIST_SELECTOR,LM_DISABLE);
- LM_CntrlBlock(pDevice,T3_BLOCK_RX_DATA_INITIATOR,LM_DISABLE);
- LM_CntrlBlock(pDevice,T3_BLOCK_RX_DATA_COMP,LM_DISABLE);
- LM_CntrlBlock(pDevice,T3_BLOCK_RX_BD_COMP,LM_DISABLE);
-
- LM_CntrlBlock(pDevice,T3_BLOCK_SEND_BD_SELECTOR,LM_DISABLE);
- LM_CntrlBlock(pDevice,T3_BLOCK_SEND_BD_INITIATOR,LM_DISABLE);
- LM_CntrlBlock(pDevice,T3_BLOCK_SEND_DATA_INITIATOR,LM_DISABLE);
- LM_CntrlBlock(pDevice,T3_BLOCK_DMA_RD,LM_DISABLE);
- LM_CntrlBlock(pDevice,T3_BLOCK_SEND_DATA_COMP,LM_DISABLE);
- LM_CntrlBlock(pDevice,T3_BLOCK_DMA_COMP,LM_DISABLE);
- LM_CntrlBlock(pDevice,T3_BLOCK_SEND_BD_COMP,LM_DISABLE);
-
- /* Clear TDE bit */
- pDevice->MacMode &= ~MAC_MODE_ENABLE_TDE;
- REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
-
- LM_CntrlBlock(pDevice,T3_BLOCK_MAC_TX_ENGINE,LM_DISABLE);
- LM_CntrlBlock(pDevice,T3_BLOCK_HOST_COALESING,LM_DISABLE);
- LM_CntrlBlock(pDevice,T3_BLOCK_DMA_WR,LM_DISABLE);
- LM_CntrlBlock(pDevice,T3_BLOCK_MBUF_CLUSTER_FREE,LM_DISABLE);
-
- /* Reset all FTQs */
- REG_WR(pDevice, Ftq.Reset, 0xffffffff);
- REG_WR(pDevice, Ftq.Reset, 0x0);
-
- LM_CntrlBlock(pDevice,T3_BLOCK_MBUF_MANAGER,LM_DISABLE);
- LM_CntrlBlock(pDevice,T3_BLOCK_MEM_ARBITOR,LM_DISABLE);
-
- MM_ACQUIRE_INT_LOCK(pDevice);
-
- /* Abort packets that have already queued to go out. */
- pPacket = (PLM_PACKET) QQ_PopHead(&pDevice->TxPacketActiveQ.Container);
- while(pPacket)
- {
-
- pPacket->PacketStatus = LM_STATUS_TRANSMIT_ABORTED;
- pDevice->TxCounters.TxPacketAbortedCnt++;
-
- atomic_add(pPacket->u.Tx.FragCount, &pDevice->SendBdLeft);
-
- QQ_PushTail(&pDevice->TxPacketXmittedQ.Container, pPacket);
-
- pPacket = (PLM_PACKET)
- QQ_PopHead(&pDevice->TxPacketActiveQ.Container);
- }
-
- /* Cleanup the receive return rings. */
- LM_ServiceRxInterrupt(pDevice);
-
- /* Don't want to indicate rx packets in Ndis miniport shutdown context. */
- /* Doing so may cause system crash. */
- if(!pDevice->ShuttingDown)
- {
- /* Indicate packets to the protocol. */
- MM_IndicateTxPackets(pDevice);
-
- /* Indicate received packets to the protocols. */
- MM_IndicateRxPackets(pDevice);
- }
- else
- {
- /* Move the receive packet descriptors in the ReceivedQ to the */
- /* free queue. */
- for(; ;)
- {
- pPacket = (PLM_PACKET) QQ_PopHead(
- &pDevice->RxPacketReceivedQ.Container);
- if(pPacket == NULL)
- {
- break;
- }
- QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
+ PLM_PACKET pPacket;
+ LM_UINT Idx;
+
+ LM_DisableInterrupt (pDevice);
+
+ /* Disable all the state machines. */
+ LM_CntrlBlock (pDevice, T3_BLOCK_MAC_RX_ENGINE, LM_DISABLE);
+ LM_CntrlBlock (pDevice, T3_BLOCK_RX_BD_INITIATOR, LM_DISABLE);
+ LM_CntrlBlock (pDevice, T3_BLOCK_RX_LIST_PLMT, LM_DISABLE);
+ LM_CntrlBlock (pDevice, T3_BLOCK_RX_LIST_SELECTOR, LM_DISABLE);
+ LM_CntrlBlock (pDevice, T3_BLOCK_RX_DATA_INITIATOR, LM_DISABLE);
+ LM_CntrlBlock (pDevice, T3_BLOCK_RX_DATA_COMP, LM_DISABLE);
+ LM_CntrlBlock (pDevice, T3_BLOCK_RX_BD_COMP, LM_DISABLE);
+
+ LM_CntrlBlock (pDevice, T3_BLOCK_SEND_BD_SELECTOR, LM_DISABLE);
+ LM_CntrlBlock (pDevice, T3_BLOCK_SEND_BD_INITIATOR, LM_DISABLE);
+ LM_CntrlBlock (pDevice, T3_BLOCK_SEND_DATA_INITIATOR, LM_DISABLE);
+ LM_CntrlBlock (pDevice, T3_BLOCK_DMA_RD, LM_DISABLE);
+ LM_CntrlBlock (pDevice, T3_BLOCK_SEND_DATA_COMP, LM_DISABLE);
+ LM_CntrlBlock (pDevice, T3_BLOCK_DMA_COMP, LM_DISABLE);
+ LM_CntrlBlock (pDevice, T3_BLOCK_SEND_BD_COMP, LM_DISABLE);
+
+ /* Clear TDE bit */
+ pDevice->MacMode &= ~MAC_MODE_ENABLE_TDE;
+ REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode);
+
+ LM_CntrlBlock (pDevice, T3_BLOCK_MAC_TX_ENGINE, LM_DISABLE);
+ LM_CntrlBlock (pDevice, T3_BLOCK_HOST_COALESING, LM_DISABLE);
+ LM_CntrlBlock (pDevice, T3_BLOCK_DMA_WR, LM_DISABLE);
+ LM_CntrlBlock (pDevice, T3_BLOCK_MBUF_CLUSTER_FREE, LM_DISABLE);
+
+ /* Reset all FTQs */
+ REG_WR (pDevice, Ftq.Reset, 0xffffffff);
+ REG_WR (pDevice, Ftq.Reset, 0x0);
+
+ LM_CntrlBlock (pDevice, T3_BLOCK_MBUF_MANAGER, LM_DISABLE);
+ LM_CntrlBlock (pDevice, T3_BLOCK_MEM_ARBITOR, LM_DISABLE);
+
+ MM_ACQUIRE_INT_LOCK (pDevice);
+
+ /* Abort packets that have already queued to go out. */
+ pPacket = (PLM_PACKET) QQ_PopHead (&pDevice->TxPacketActiveQ.Container);
+ while (pPacket) {
+
+ pPacket->PacketStatus = LM_STATUS_TRANSMIT_ABORTED;
+ pDevice->TxCounters.TxPacketAbortedCnt++;
+
+ atomic_add (pPacket->u.Tx.FragCount, &pDevice->SendBdLeft);
+
+ QQ_PushTail (&pDevice->TxPacketXmittedQ.Container, pPacket);
+
+ pPacket = (PLM_PACKET)
+ QQ_PopHead (&pDevice->TxPacketActiveQ.Container);
+ }
+
+ /* Cleanup the receive return rings. */
+ LM_ServiceRxInterrupt (pDevice);
+
+ /* Don't want to indicate rx packets in Ndis miniport shutdown context. */
+ /* Doing so may cause system crash. */
+ if (!pDevice->ShuttingDown) {
+ /* Indicate packets to the protocol. */
+ MM_IndicateTxPackets (pDevice);
+
+ /* Indicate received packets to the protocols. */
+ MM_IndicateRxPackets (pDevice);
+ } else {
+ /* Move the receive packet descriptors in the ReceivedQ to the */
+ /* free queue. */
+ for (;;) {
+ pPacket =
+ (PLM_PACKET) QQ_PopHead (&pDevice->
+ RxPacketReceivedQ.
+ Container);
+ if (pPacket == NULL) {
+ break;
+ }
+ QQ_PushTail (&pDevice->RxPacketFreeQ.Container,
+ pPacket);
+ }
}
- }
- /* Clean up the Std Receive Producer ring. */
- Idx = pDevice->pStatusBlkVirt->RcvStdConIdx;
+ /* Clean up the Std Receive Producer ring. */
+ Idx = pDevice->pStatusBlkVirt->RcvStdConIdx;
- while(Idx != pDevice->RxStdProdIdx) {
- pPacket = (PLM_PACKET) (MM_UINT_PTR(pDevice->pPacketDescBase) +
- MM_UINT_PTR(pDevice->pRxStdBdVirt[Idx].Opaque));
+ while (Idx != pDevice->RxStdProdIdx) {
+ pPacket = (PLM_PACKET) (MM_UINT_PTR (pDevice->pPacketDescBase) +
+ MM_UINT_PTR (pDevice->pRxStdBdVirt[Idx].
+ Opaque));
- QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
+ QQ_PushTail (&pDevice->RxPacketFreeQ.Container, pPacket);
- Idx = (Idx + 1) & T3_STD_RCV_RCB_ENTRY_COUNT_MASK;
- } /* while */
+ Idx = (Idx + 1) & T3_STD_RCV_RCB_ENTRY_COUNT_MASK;
+ } /* while */
- /* Reinitialize our copy of the indices. */
- pDevice->RxStdProdIdx = 0;
+ /* Reinitialize our copy of the indices. */
+ pDevice->RxStdProdIdx = 0;
#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
- /* Clean up the Jumbo Receive Producer ring. */
- Idx = pDevice->pStatusBlkVirt->RcvJumboConIdx;
-
- while(Idx != pDevice->RxJumboProdIdx) {
- pPacket = (PLM_PACKET) (MM_UINT_PTR(pDevice->pPacketDescBase) +
- MM_UINT_PTR(pDevice->pRxJumboBdVirt[Idx].Opaque));
+ /* Clean up the Jumbo Receive Producer ring. */
+ Idx = pDevice->pStatusBlkVirt->RcvJumboConIdx;
- QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
+ while (Idx != pDevice->RxJumboProdIdx) {
+ pPacket = (PLM_PACKET) (MM_UINT_PTR (pDevice->pPacketDescBase) +
+ MM_UINT_PTR (pDevice->
+ pRxJumboBdVirt[Idx].
+ Opaque));
- Idx = (Idx + 1) & T3_JUMBO_RCV_RCB_ENTRY_COUNT_MASK;
- } /* while */
+ QQ_PushTail (&pDevice->RxPacketFreeQ.Container, pPacket);
- /* Reinitialize our copy of the indices. */
- pDevice->RxJumboProdIdx = 0;
-#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
+ Idx = (Idx + 1) & T3_JUMBO_RCV_RCB_ENTRY_COUNT_MASK;
+ } /* while */
- MM_RELEASE_INT_LOCK(pDevice);
+ /* Reinitialize our copy of the indices. */
+ pDevice->RxJumboProdIdx = 0;
+#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
- /* Initialize the statistis Block */
- pDevice->pStatusBlkVirt->Status = 0;
- pDevice->pStatusBlkVirt->RcvStdConIdx = 0;
- pDevice->pStatusBlkVirt->RcvJumboConIdx = 0;
- pDevice->pStatusBlkVirt->RcvMiniConIdx = 0;
+ MM_RELEASE_INT_LOCK (pDevice);
- return LM_STATUS_SUCCESS;
-} /* LM_Abort */
+ /* Initialize the statistis Block */
+ pDevice->pStatusBlkVirt->Status = 0;
+ pDevice->pStatusBlkVirt->RcvStdConIdx = 0;
+ pDevice->pStatusBlkVirt->RcvJumboConIdx = 0;
+ pDevice->pStatusBlkVirt->RcvMiniConIdx = 0;
+ return LM_STATUS_SUCCESS;
+} /* LM_Abort */
/******************************************************************************/
/* Description: */
@@ -3667,140 +3398,130 @@ PLM_DEVICE_BLOCK pDevice)
/* Return: */
/* LM_STATUS_SUCCESS */
/******************************************************************************/
-LM_STATUS
-LM_Halt(
-PLM_DEVICE_BLOCK pDevice) {
- PLM_PACKET pPacket;
- LM_UINT32 EntryCnt;
-
- LM_Abort(pDevice);
+LM_STATUS LM_Halt (PLM_DEVICE_BLOCK pDevice)
+{
+ PLM_PACKET pPacket;
+ LM_UINT32 EntryCnt;
- /* Get the number of entries in the queue. */
- EntryCnt = QQ_GetEntryCnt(&pDevice->RxPacketFreeQ.Container);
+ LM_Abort (pDevice);
- /* Make sure all the packets have been accounted for. */
- for(EntryCnt = 0; EntryCnt < pDevice->RxPacketDescCnt; EntryCnt++)
- {
- pPacket = (PLM_PACKET) QQ_PopHead(&pDevice->RxPacketFreeQ.Container);
- if (pPacket == 0)
- break;
+ /* Get the number of entries in the queue. */
+ EntryCnt = QQ_GetEntryCnt (&pDevice->RxPacketFreeQ.Container);
- MM_FreeRxBuffer(pDevice, pPacket);
+ /* Make sure all the packets have been accounted for. */
+ for (EntryCnt = 0; EntryCnt < pDevice->RxPacketDescCnt; EntryCnt++) {
+ pPacket =
+ (PLM_PACKET) QQ_PopHead (&pDevice->RxPacketFreeQ.Container);
+ if (pPacket == 0)
+ break;
- QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
- }
+ MM_FreeRxBuffer (pDevice, pPacket);
- LM_ResetChip(pDevice);
+ QQ_PushTail (&pDevice->RxPacketFreeQ.Container, pPacket);
+ }
- /* Restore PCI configuration registers. */
- MM_WriteConfig32(pDevice, PCI_CACHE_LINE_SIZE_REG,
- pDevice->SavedCacheLineReg);
- LM_RegWrInd(pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG,
- (pDevice->SubsystemId << 16) | pDevice->SubsystemVendorId);
+ LM_ResetChip (pDevice);
- /* Reprogram the MAC address. */
- LM_SetMacAddress(pDevice, pDevice->NodeAddress);
+ /* Restore PCI configuration registers. */
+ MM_WriteConfig32 (pDevice, PCI_CACHE_LINE_SIZE_REG,
+ pDevice->SavedCacheLineReg);
+ LM_RegWrInd (pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG,
+ (pDevice->SubsystemId << 16) | pDevice->SubsystemVendorId);
- return LM_STATUS_SUCCESS;
-} /* LM_Halt */
+ /* Reprogram the MAC address. */
+ LM_SetMacAddress (pDevice, pDevice->NodeAddress);
+ return LM_STATUS_SUCCESS;
+} /* LM_Halt */
-STATIC LM_STATUS
-LM_ResetChip(PLM_DEVICE_BLOCK pDevice)
+STATIC LM_STATUS LM_ResetChip (PLM_DEVICE_BLOCK pDevice)
{
- LM_UINT32 Value32;
- LM_UINT32 j;
-
- /* Wait for access to the nvram interface before resetting. This is */
- /* a workaround to prevent EEPROM corruption. */
- if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700 &&
- T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701)
- {
- /* Request access to the flash interface. */
- REG_WR(pDevice, Nvram.SwArb, SW_ARB_REQ_SET1);
-
- for(j = 0; j < 100000; j++)
- {
- Value32 = REG_RD(pDevice, Nvram.SwArb);
- if(Value32 & SW_ARB_GNT1)
- {
- break;
- }
- MM_Wait(10);
+ LM_UINT32 Value32;
+ LM_UINT32 j;
+
+ /* Wait for access to the nvram interface before resetting. This is */
+ /* a workaround to prevent EEPROM corruption. */
+ if (T3_ASIC_REV (pDevice->ChipRevId) != T3_ASIC_REV_5700 &&
+ T3_ASIC_REV (pDevice->ChipRevId) != T3_ASIC_REV_5701) {
+ /* Request access to the flash interface. */
+ REG_WR (pDevice, Nvram.SwArb, SW_ARB_REQ_SET1);
+
+ for (j = 0; j < 100000; j++) {
+ Value32 = REG_RD (pDevice, Nvram.SwArb);
+ if (Value32 & SW_ARB_GNT1) {
+ break;
+ }
+ MM_Wait (10);
+ }
}
- }
- /* Global reset. */
- REG_WR(pDevice, Grc.MiscCfg, GRC_MISC_CFG_CORE_CLOCK_RESET);
- MM_Wait(40); MM_Wait(40); MM_Wait(40);
+ /* Global reset. */
+ REG_WR (pDevice, Grc.MiscCfg, GRC_MISC_CFG_CORE_CLOCK_RESET);
+ MM_Wait (40);
+ MM_Wait (40);
+ MM_Wait (40);
- /* make sure we re-enable indirect accesses */
- MM_WriteConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG,
- pDevice->MiscHostCtrl);
+ /* make sure we re-enable indirect accesses */
+ MM_WriteConfig32 (pDevice, T3_PCI_MISC_HOST_CTRL_REG,
+ pDevice->MiscHostCtrl);
- /* Set MAX PCI retry to zero. */
- Value32 = T3_PCI_STATE_PCI_ROM_ENABLE | T3_PCI_STATE_PCI_ROM_RETRY_ENABLE;
- if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0)
- {
- if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE))
- {
- Value32 |= T3_PCI_STATE_RETRY_SAME_DMA;
+ /* Set MAX PCI retry to zero. */
+ Value32 =
+ T3_PCI_STATE_PCI_ROM_ENABLE | T3_PCI_STATE_PCI_ROM_RETRY_ENABLE;
+ if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0) {
+ if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)) {
+ Value32 |= T3_PCI_STATE_RETRY_SAME_DMA;
+ }
}
- }
- MM_WriteConfig32(pDevice, T3_PCI_STATE_REG, Value32);
+ MM_WriteConfig32 (pDevice, T3_PCI_STATE_REG, Value32);
- /* Restore PCI command register. */
- MM_WriteConfig32(pDevice, PCI_COMMAND_REG,
- pDevice->PciCommandStatusWords);
+ /* Restore PCI command register. */
+ MM_WriteConfig32 (pDevice, PCI_COMMAND_REG,
+ pDevice->PciCommandStatusWords);
- /* Disable PCI-X relaxed ordering bit. */
- MM_ReadConfig32(pDevice, PCIX_CAP_REG, &Value32);
- Value32 &= ~PCIX_ENABLE_RELAXED_ORDERING;
- MM_WriteConfig32(pDevice, PCIX_CAP_REG, Value32);
+ /* Disable PCI-X relaxed ordering bit. */
+ MM_ReadConfig32 (pDevice, PCIX_CAP_REG, &Value32);
+ Value32 &= ~PCIX_ENABLE_RELAXED_ORDERING;
+ MM_WriteConfig32 (pDevice, PCIX_CAP_REG, Value32);
- /* Enable memory arbiter. */
- REG_WR(pDevice, MemArbiter.Mode, T3_MEM_ARBITER_MODE_ENABLE);
+ /* Enable memory arbiter. */
+ REG_WR (pDevice, MemArbiter.Mode, T3_MEM_ARBITER_MODE_ENABLE);
-#ifdef BIG_ENDIAN_PCI /* This from jfd */
- Value32 = GRC_MODE_WORD_SWAP_DATA|
- GRC_MODE_WORD_SWAP_NON_FRAME_DATA;
+#ifdef BIG_ENDIAN_PCI /* This from jfd */
+ Value32 = GRC_MODE_WORD_SWAP_DATA | GRC_MODE_WORD_SWAP_NON_FRAME_DATA;
#else
#ifdef BIG_ENDIAN_HOST
- /* Reconfigure the mode register. */
- Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA |
- GRC_MODE_WORD_SWAP_NON_FRAME_DATA |
- GRC_MODE_BYTE_SWAP_DATA |
- GRC_MODE_WORD_SWAP_DATA;
+ /* Reconfigure the mode register. */
+ Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA |
+ GRC_MODE_WORD_SWAP_NON_FRAME_DATA |
+ GRC_MODE_BYTE_SWAP_DATA | GRC_MODE_WORD_SWAP_DATA;
#else
- /* Reconfigure the mode register. */
- Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | GRC_MODE_BYTE_SWAP_DATA;
+ /* Reconfigure the mode register. */
+ Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | GRC_MODE_BYTE_SWAP_DATA;
#endif
#endif
- REG_WR(pDevice, Grc.Mode, Value32);
-
- /* Prevent PXE from restarting. */
- MEM_WR_OFFSET(pDevice, 0x0b50, T3_MAGIC_NUM);
-
- if(pDevice->EnableTbi) {
- pDevice->MacMode = MAC_MODE_PORT_MODE_TBI;
- REG_WR(pDevice, MacCtrl.Mode, MAC_MODE_PORT_MODE_TBI);
- }
- else {
- REG_WR(pDevice, MacCtrl.Mode, 0);
- }
-
- /* Wait for the firmware to finish initialization. */
- for(j = 0; j < 100000; j++)
- {
- MM_Wait(10);
-
- Value32 = MEM_RD_OFFSET(pDevice, 0x0b50);
- if(Value32 == ~T3_MAGIC_NUM)
- {
- break;
+ REG_WR (pDevice, Grc.Mode, Value32);
+
+ /* Prevent PXE from restarting. */
+ MEM_WR_OFFSET (pDevice, 0x0b50, T3_MAGIC_NUM);
+
+ if (pDevice->EnableTbi) {
+ pDevice->MacMode = MAC_MODE_PORT_MODE_TBI;
+ REG_WR (pDevice, MacCtrl.Mode, MAC_MODE_PORT_MODE_TBI);
+ } else {
+ REG_WR (pDevice, MacCtrl.Mode, 0);
+ }
+
+ /* Wait for the firmware to finish initialization. */
+ for (j = 0; j < 100000; j++) {
+ MM_Wait (10);
+
+ Value32 = MEM_RD_OFFSET (pDevice, 0x0b50);
+ if (Value32 == ~T3_MAGIC_NUM) {
+ break;
+ }
}
- }
- return LM_STATUS_SUCCESS;
+ return LM_STATUS_SUCCESS;
}
/******************************************************************************/
@@ -3808,161 +3529,143 @@ LM_ResetChip(PLM_DEVICE_BLOCK pDevice)
/* */
/* Return: */
/******************************************************************************/
-__inline static void
-LM_ServiceTxInterrupt(
-PLM_DEVICE_BLOCK pDevice) {
- PLM_PACKET pPacket;
- LM_UINT32 HwConIdx;
- LM_UINT32 SwConIdx;
-
- HwConIdx = pDevice->pStatusBlkVirt->Idx[0].SendConIdx;
-
- /* Get our copy of the consumer index. The buffer descriptors */
- /* that are in between the consumer indices are freed. */
- SwConIdx = pDevice->SendConIdx;
-
- /* Move the packets from the TxPacketActiveQ that are sent out to */
- /* the TxPacketXmittedQ. Packets that are sent use the */
- /* descriptors that are between SwConIdx and HwConIdx. */
- while(SwConIdx != HwConIdx)
- {
- /* Get the packet that was sent from the TxPacketActiveQ. */
- pPacket = (PLM_PACKET) QQ_PopHead(
- &pDevice->TxPacketActiveQ.Container);
-
- /* Set the return status. */
- pPacket->PacketStatus = LM_STATUS_SUCCESS;
-
- /* Put the packet in the TxPacketXmittedQ for indication later. */
- QQ_PushTail(&pDevice->TxPacketXmittedQ.Container, pPacket);
-
- /* Move to the next packet's BD. */
- SwConIdx = (SwConIdx + pPacket->u.Tx.FragCount) &
- T3_SEND_RCB_ENTRY_COUNT_MASK;
-
- /* Update the number of unused BDs. */
- atomic_add(pPacket->u.Tx.FragCount, &pDevice->SendBdLeft);
-
- /* Get the new updated HwConIdx. */
+__inline static void LM_ServiceTxInterrupt (PLM_DEVICE_BLOCK pDevice)
+{
+ PLM_PACKET pPacket;
+ LM_UINT32 HwConIdx;
+ LM_UINT32 SwConIdx;
+
HwConIdx = pDevice->pStatusBlkVirt->Idx[0].SendConIdx;
- } /* while */
- /* Save the new SwConIdx. */
- pDevice->SendConIdx = SwConIdx;
+ /* Get our copy of the consumer index. The buffer descriptors */
+ /* that are in between the consumer indices are freed. */
+ SwConIdx = pDevice->SendConIdx;
+
+ /* Move the packets from the TxPacketActiveQ that are sent out to */
+ /* the TxPacketXmittedQ. Packets that are sent use the */
+ /* descriptors that are between SwConIdx and HwConIdx. */
+ while (SwConIdx != HwConIdx) {
+ /* Get the packet that was sent from the TxPacketActiveQ. */
+ pPacket =
+ (PLM_PACKET) QQ_PopHead (&pDevice->TxPacketActiveQ.
+ Container);
+
+ /* Set the return status. */
+ pPacket->PacketStatus = LM_STATUS_SUCCESS;
+
+ /* Put the packet in the TxPacketXmittedQ for indication later. */
+ QQ_PushTail (&pDevice->TxPacketXmittedQ.Container, pPacket);
+
+ /* Move to the next packet's BD. */
+ SwConIdx = (SwConIdx + pPacket->u.Tx.FragCount) &
+ T3_SEND_RCB_ENTRY_COUNT_MASK;
+
+ /* Update the number of unused BDs. */
+ atomic_add (pPacket->u.Tx.FragCount, &pDevice->SendBdLeft);
-} /* LM_ServiceTxInterrupt */
+ /* Get the new updated HwConIdx. */
+ HwConIdx = pDevice->pStatusBlkVirt->Idx[0].SendConIdx;
+ } /* while */
+ /* Save the new SwConIdx. */
+ pDevice->SendConIdx = SwConIdx;
+
+} /* LM_ServiceTxInterrupt */
/******************************************************************************/
/* Description: */
/* */
/* Return: */
/******************************************************************************/
-__inline static void
-LM_ServiceRxInterrupt(
-PLM_DEVICE_BLOCK pDevice) {
- PLM_PACKET pPacket;
- PT3_RCV_BD pRcvBd;
- LM_UINT32 HwRcvRetProdIdx;
- LM_UINT32 SwRcvRetConIdx;
-
- /* Loop thru the receive return rings for received packets. */
- HwRcvRetProdIdx = pDevice->pStatusBlkVirt->Idx[0].RcvProdIdx;
-
- SwRcvRetConIdx = pDevice->RcvRetConIdx;
- while(SwRcvRetConIdx != HwRcvRetProdIdx)
- {
- pRcvBd = &pDevice->pRcvRetBdVirt[SwRcvRetConIdx];
-
- /* Get the received packet descriptor. */
- pPacket = (PLM_PACKET) (MM_UINT_PTR(pDevice->pPacketDescBase) +
- MM_UINT_PTR(pRcvBd->Opaque));
-
- /* Check the error flag. */
- if(pRcvBd->ErrorFlag &&
- pRcvBd->ErrorFlag != RCV_BD_ERR_ODD_NIBBLED_RCVD_MII)
- {
- pPacket->PacketStatus = LM_STATUS_FAILURE;
-
- pDevice->RxCounters.RxPacketErrCnt++;
-
- if(pRcvBd->ErrorFlag & RCV_BD_ERR_BAD_CRC)
- {
- pDevice->RxCounters.RxErrCrcCnt++;
- }
-
- if(pRcvBd->ErrorFlag & RCV_BD_ERR_COLL_DETECT)
- {
- pDevice->RxCounters.RxErrCollCnt++;
- }
-
- if(pRcvBd->ErrorFlag & RCV_BD_ERR_LINK_LOST_DURING_PKT)
- {
- pDevice->RxCounters.RxErrLinkLostCnt++;
- }
-
- if(pRcvBd->ErrorFlag & RCV_BD_ERR_PHY_DECODE_ERR)
- {
- pDevice->RxCounters.RxErrPhyDecodeCnt++;
- }
-
- if(pRcvBd->ErrorFlag & RCV_BD_ERR_ODD_NIBBLED_RCVD_MII)
- {
- pDevice->RxCounters.RxErrOddNibbleCnt++;
- }
-
- if(pRcvBd->ErrorFlag & RCV_BD_ERR_MAC_ABORT)
- {
- pDevice->RxCounters.RxErrMacAbortCnt++;
- }
-
- if(pRcvBd->ErrorFlag & RCV_BD_ERR_LEN_LT_64)
- {
- pDevice->RxCounters.RxErrShortPacketCnt++;
- }
-
- if(pRcvBd->ErrorFlag & RCV_BD_ERR_TRUNC_NO_RESOURCES)
- {
- pDevice->RxCounters.RxErrNoResourceCnt++;
- }
-
- if(pRcvBd->ErrorFlag & RCV_BD_ERR_GIANT_FRAME_RCVD)
- {
- pDevice->RxCounters.RxErrLargePacketCnt++;
- }
- }
- else
- {
- pPacket->PacketStatus = LM_STATUS_SUCCESS;
- pPacket->PacketSize = pRcvBd->Len - 4;
+__inline static void LM_ServiceRxInterrupt (PLM_DEVICE_BLOCK pDevice)
+{
+ PLM_PACKET pPacket;
+ PT3_RCV_BD pRcvBd;
+ LM_UINT32 HwRcvRetProdIdx;
+ LM_UINT32 SwRcvRetConIdx;
- pPacket->Flags = pRcvBd->Flags;
- if(pRcvBd->Flags & RCV_BD_FLAG_VLAN_TAG)
- {
- pPacket->VlanTag = pRcvBd->VlanTag;
- }
+ /* Loop thru the receive return rings for received packets. */
+ HwRcvRetProdIdx = pDevice->pStatusBlkVirt->Idx[0].RcvProdIdx;
- pPacket->u.Rx.TcpUdpChecksum = pRcvBd->TcpUdpCksum;
- }
+ SwRcvRetConIdx = pDevice->RcvRetConIdx;
+ while (SwRcvRetConIdx != HwRcvRetProdIdx) {
+ pRcvBd = &pDevice->pRcvRetBdVirt[SwRcvRetConIdx];
- /* Put the packet descriptor containing the received packet */
- /* buffer in the RxPacketReceivedQ for indication later. */
- QQ_PushTail(&pDevice->RxPacketReceivedQ.Container, pPacket);
+ /* Get the received packet descriptor. */
+ pPacket = (PLM_PACKET) (MM_UINT_PTR (pDevice->pPacketDescBase) +
+ MM_UINT_PTR (pRcvBd->Opaque));
- /* Go to the next buffer descriptor. */
- SwRcvRetConIdx = (SwRcvRetConIdx + 1) &
- T3_RCV_RETURN_RCB_ENTRY_COUNT_MASK;
+ /* Check the error flag. */
+ if (pRcvBd->ErrorFlag &&
+ pRcvBd->ErrorFlag != RCV_BD_ERR_ODD_NIBBLED_RCVD_MII) {
+ pPacket->PacketStatus = LM_STATUS_FAILURE;
- /* Get the updated HwRcvRetProdIdx. */
- HwRcvRetProdIdx = pDevice->pStatusBlkVirt->Idx[0].RcvProdIdx;
- } /* while */
+ pDevice->RxCounters.RxPacketErrCnt++;
+
+ if (pRcvBd->ErrorFlag & RCV_BD_ERR_BAD_CRC) {
+ pDevice->RxCounters.RxErrCrcCnt++;
+ }
+
+ if (pRcvBd->ErrorFlag & RCV_BD_ERR_COLL_DETECT) {
+ pDevice->RxCounters.RxErrCollCnt++;
+ }
+
+ if (pRcvBd->ErrorFlag & RCV_BD_ERR_LINK_LOST_DURING_PKT) {
+ pDevice->RxCounters.RxErrLinkLostCnt++;
+ }
+
+ if (pRcvBd->ErrorFlag & RCV_BD_ERR_PHY_DECODE_ERR) {
+ pDevice->RxCounters.RxErrPhyDecodeCnt++;
+ }
+
+ if (pRcvBd->ErrorFlag & RCV_BD_ERR_ODD_NIBBLED_RCVD_MII) {
+ pDevice->RxCounters.RxErrOddNibbleCnt++;
+ }
+
+ if (pRcvBd->ErrorFlag & RCV_BD_ERR_MAC_ABORT) {
+ pDevice->RxCounters.RxErrMacAbortCnt++;
+ }
+
+ if (pRcvBd->ErrorFlag & RCV_BD_ERR_LEN_LT_64) {
+ pDevice->RxCounters.RxErrShortPacketCnt++;
+ }
+
+ if (pRcvBd->ErrorFlag & RCV_BD_ERR_TRUNC_NO_RESOURCES) {
+ pDevice->RxCounters.RxErrNoResourceCnt++;
+ }
+
+ if (pRcvBd->ErrorFlag & RCV_BD_ERR_GIANT_FRAME_RCVD) {
+ pDevice->RxCounters.RxErrLargePacketCnt++;
+ }
+ } else {
+ pPacket->PacketStatus = LM_STATUS_SUCCESS;
+ pPacket->PacketSize = pRcvBd->Len - 4;
- pDevice->RcvRetConIdx = SwRcvRetConIdx;
+ pPacket->Flags = pRcvBd->Flags;
+ if (pRcvBd->Flags & RCV_BD_FLAG_VLAN_TAG) {
+ pPacket->VlanTag = pRcvBd->VlanTag;
+ }
+
+ pPacket->u.Rx.TcpUdpChecksum = pRcvBd->TcpUdpCksum;
+ }
+
+ /* Put the packet descriptor containing the received packet */
+ /* buffer in the RxPacketReceivedQ for indication later. */
+ QQ_PushTail (&pDevice->RxPacketReceivedQ.Container, pPacket);
+
+ /* Go to the next buffer descriptor. */
+ SwRcvRetConIdx = (SwRcvRetConIdx + 1) &
+ T3_RCV_RETURN_RCB_ENTRY_COUNT_MASK;
- /* Update the receive return ring consumer index. */
- MB_REG_WR(pDevice, Mailbox.RcvRetConIdx[0].Low, SwRcvRetConIdx);
-} /* LM_ServiceRxInterrupt */
+ /* Get the updated HwRcvRetProdIdx. */
+ HwRcvRetProdIdx = pDevice->pStatusBlkVirt->Idx[0].RcvProdIdx;
+ } /* while */
+ pDevice->RcvRetConIdx = SwRcvRetConIdx;
+
+ /* Update the receive return ring consumer index. */
+ MB_REG_WR (pDevice, Mailbox.RcvRetConIdx[0].Low, SwRcvRetConIdx);
+} /* LM_ServiceRxInterrupt */
/******************************************************************************/
/* Description: */
@@ -3972,206 +3675,179 @@ PLM_DEVICE_BLOCK pDevice) {
/* Return: */
/* LM_STATUS_SUCCESS */
/******************************************************************************/
-LM_STATUS
-LM_ServiceInterrupts(
- PLM_DEVICE_BLOCK pDevice)
+LM_STATUS LM_ServiceInterrupts (PLM_DEVICE_BLOCK pDevice)
{
- LM_UINT32 Value32;
- int ServicePhyInt = FALSE;
-
- /* Setup the phy chip whenever the link status changes. */
- if(pDevice->LinkChngMode == T3_LINK_CHNG_MODE_USE_STATUS_REG)
- {
- Value32 = REG_RD(pDevice, MacCtrl.Status);
- if(pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT)
- {
- if (Value32 & MAC_STATUS_MI_INTERRUPT)
- {
- ServicePhyInt = TRUE;
- }
- }
- else if(Value32 & MAC_STATUS_LINK_STATE_CHANGED)
- {
- ServicePhyInt = TRUE;
- }
- }
- else
- {
- if(pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_LINK_CHANGED_STATUS)
- {
- pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED |
- (pDevice->pStatusBlkVirt->Status & ~STATUS_BLOCK_LINK_CHANGED_STATUS);
- ServicePhyInt = TRUE;
+ LM_UINT32 Value32;
+ int ServicePhyInt = FALSE;
+
+ /* Setup the phy chip whenever the link status changes. */
+ if (pDevice->LinkChngMode == T3_LINK_CHNG_MODE_USE_STATUS_REG) {
+ Value32 = REG_RD (pDevice, MacCtrl.Status);
+ if (pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT) {
+ if (Value32 & MAC_STATUS_MI_INTERRUPT) {
+ ServicePhyInt = TRUE;
+ }
+ } else if (Value32 & MAC_STATUS_LINK_STATE_CHANGED) {
+ ServicePhyInt = TRUE;
+ }
+ } else {
+ if (pDevice->pStatusBlkVirt->
+ Status & STATUS_BLOCK_LINK_CHANGED_STATUS) {
+ pDevice->pStatusBlkVirt->Status =
+ STATUS_BLOCK_UPDATED | (pDevice->pStatusBlkVirt->
+ Status &
+ ~STATUS_BLOCK_LINK_CHANGED_STATUS);
+ ServicePhyInt = TRUE;
+ }
}
- }
#if INCLUDE_TBI_SUPPORT
- if (pDevice->IgnoreTbiLinkChange == TRUE)
- {
- ServicePhyInt = FALSE;
- }
+ if (pDevice->IgnoreTbiLinkChange == TRUE) {
+ ServicePhyInt = FALSE;
+ }
#endif
- if (ServicePhyInt == TRUE)
- {
- LM_SetupPhy(pDevice);
- }
-
- /* Service receive and transmit interrupts. */
- LM_ServiceRxInterrupt(pDevice);
- LM_ServiceTxInterrupt(pDevice);
+ if (ServicePhyInt == TRUE) {
+ LM_SetupPhy (pDevice);
+ }
- /* No spinlock for this queue since this routine is serialized. */
- if(!QQ_Empty(&pDevice->RxPacketReceivedQ.Container))
- {
- /* Indicate receive packets. */
- MM_IndicateRxPackets(pDevice);
- /* LM_QueueRxPackets(pDevice); */
- }
+ /* Service receive and transmit interrupts. */
+ LM_ServiceRxInterrupt (pDevice);
+ LM_ServiceTxInterrupt (pDevice);
- /* No spinlock for this queue since this routine is serialized. */
- if(!QQ_Empty(&pDevice->TxPacketXmittedQ.Container))
- {
- MM_IndicateTxPackets(pDevice);
- }
+ /* No spinlock for this queue since this routine is serialized. */
+ if (!QQ_Empty (&pDevice->RxPacketReceivedQ.Container)) {
+ /* Indicate receive packets. */
+ MM_IndicateRxPackets (pDevice);
+ /* LM_QueueRxPackets(pDevice); */
+ }
- return LM_STATUS_SUCCESS;
-} /* LM_ServiceInterrupts */
+ /* No spinlock for this queue since this routine is serialized. */
+ if (!QQ_Empty (&pDevice->TxPacketXmittedQ.Container)) {
+ MM_IndicateTxPackets (pDevice);
+ }
+ return LM_STATUS_SUCCESS;
+} /* LM_ServiceInterrupts */
/******************************************************************************/
/* Description: */
/* */
/* Return: */
/******************************************************************************/
-LM_STATUS
-LM_MulticastAdd(
-PLM_DEVICE_BLOCK pDevice,
-PLM_UINT8 pMcAddress) {
- PLM_UINT8 pEntry;
- LM_UINT32 j;
-
- pEntry = pDevice->McTable[0];
- for(j = 0; j < pDevice->McEntryCount; j++)
- {
- if(IS_ETH_ADDRESS_EQUAL(pEntry, pMcAddress))
- {
- /* Found a match, increment the instance count. */
- pEntry[LM_MC_INSTANCE_COUNT_INDEX] += 1;
+LM_STATUS LM_MulticastAdd (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMcAddress)
+{
+ PLM_UINT8 pEntry;
+ LM_UINT32 j;
- return LM_STATUS_SUCCESS;
- }
+ pEntry = pDevice->McTable[0];
+ for (j = 0; j < pDevice->McEntryCount; j++) {
+ if (IS_ETH_ADDRESS_EQUAL (pEntry, pMcAddress)) {
+ /* Found a match, increment the instance count. */
+ pEntry[LM_MC_INSTANCE_COUNT_INDEX] += 1;
- pEntry += LM_MC_ENTRY_SIZE;
- }
+ return LM_STATUS_SUCCESS;
+ }
- if(pDevice->McEntryCount >= LM_MAX_MC_TABLE_SIZE)
- {
- return LM_STATUS_FAILURE;
- }
+ pEntry += LM_MC_ENTRY_SIZE;
+ }
- pEntry = pDevice->McTable[pDevice->McEntryCount];
+ if (pDevice->McEntryCount >= LM_MAX_MC_TABLE_SIZE) {
+ return LM_STATUS_FAILURE;
+ }
- COPY_ETH_ADDRESS(pMcAddress, pEntry);
- pEntry[LM_MC_INSTANCE_COUNT_INDEX] = 1;
+ pEntry = pDevice->McTable[pDevice->McEntryCount];
- pDevice->McEntryCount++;
+ COPY_ETH_ADDRESS (pMcAddress, pEntry);
+ pEntry[LM_MC_INSTANCE_COUNT_INDEX] = 1;
- LM_SetReceiveMask(pDevice, pDevice->ReceiveMask | LM_ACCEPT_MULTICAST);
+ pDevice->McEntryCount++;
- return LM_STATUS_SUCCESS;
-} /* LM_MulticastAdd */
+ LM_SetReceiveMask (pDevice, pDevice->ReceiveMask | LM_ACCEPT_MULTICAST);
+ return LM_STATUS_SUCCESS;
+} /* LM_MulticastAdd */
/******************************************************************************/
/* Description: */
/* */
/* Return: */
/******************************************************************************/
-LM_STATUS
-LM_MulticastDel(
-PLM_DEVICE_BLOCK pDevice,
-PLM_UINT8 pMcAddress) {
- PLM_UINT8 pEntry;
- LM_UINT32 j;
-
- pEntry = pDevice->McTable[0];
- for(j = 0; j < pDevice->McEntryCount; j++)
- {
- if(IS_ETH_ADDRESS_EQUAL(pEntry, pMcAddress))
- {
- /* Found a match, decrement the instance count. */
- pEntry[LM_MC_INSTANCE_COUNT_INDEX] -= 1;
-
- /* No more instance left, remove the address from the table. */
- /* Move the last entry in the table to the delete slot. */
- if(pEntry[LM_MC_INSTANCE_COUNT_INDEX] == 0 &&
- pDevice->McEntryCount > 1)
- {
-
- COPY_ETH_ADDRESS(
- pDevice->McTable[pDevice->McEntryCount-1], pEntry);
- pEntry[LM_MC_INSTANCE_COUNT_INDEX] =
- pDevice->McTable[pDevice->McEntryCount-1]
- [LM_MC_INSTANCE_COUNT_INDEX];
- }
- pDevice->McEntryCount--;
+LM_STATUS LM_MulticastDel (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMcAddress)
+{
+ PLM_UINT8 pEntry;
+ LM_UINT32 j;
+
+ pEntry = pDevice->McTable[0];
+ for (j = 0; j < pDevice->McEntryCount; j++) {
+ if (IS_ETH_ADDRESS_EQUAL (pEntry, pMcAddress)) {
+ /* Found a match, decrement the instance count. */
+ pEntry[LM_MC_INSTANCE_COUNT_INDEX] -= 1;
+
+ /* No more instance left, remove the address from the table. */
+ /* Move the last entry in the table to the delete slot. */
+ if (pEntry[LM_MC_INSTANCE_COUNT_INDEX] == 0 &&
+ pDevice->McEntryCount > 1) {
+
+ COPY_ETH_ADDRESS (pDevice->
+ McTable[pDevice->
+ McEntryCount - 1],
+ pEntry);
+ pEntry[LM_MC_INSTANCE_COUNT_INDEX] =
+ pDevice->McTable[pDevice->McEntryCount - 1]
+ [LM_MC_INSTANCE_COUNT_INDEX];
+ }
+ pDevice->McEntryCount--;
+
+ /* Update the receive mask if the table is empty. */
+ if (pDevice->McEntryCount == 0) {
+ LM_SetReceiveMask (pDevice,
+ pDevice->
+ ReceiveMask &
+ ~LM_ACCEPT_MULTICAST);
+ }
- /* Update the receive mask if the table is empty. */
- if(pDevice->McEntryCount == 0)
- {
- LM_SetReceiveMask(pDevice,
- pDevice->ReceiveMask & ~LM_ACCEPT_MULTICAST);
- }
+ return LM_STATUS_SUCCESS;
+ }
- return LM_STATUS_SUCCESS;
+ pEntry += LM_MC_ENTRY_SIZE;
}
- pEntry += LM_MC_ENTRY_SIZE;
- }
-
- return LM_STATUS_FAILURE;
-} /* LM_MulticastDel */
-
+ return LM_STATUS_FAILURE;
+} /* LM_MulticastDel */
/******************************************************************************/
/* Description: */
/* */
/* Return: */
/******************************************************************************/
-LM_STATUS
-LM_MulticastClear(
-PLM_DEVICE_BLOCK pDevice) {
- pDevice->McEntryCount = 0;
-
- LM_SetReceiveMask(pDevice, pDevice->ReceiveMask & ~LM_ACCEPT_MULTICAST);
+LM_STATUS LM_MulticastClear (PLM_DEVICE_BLOCK pDevice)
+{
+ pDevice->McEntryCount = 0;
- return LM_STATUS_SUCCESS;
-} /* LM_MulticastClear */
+ LM_SetReceiveMask (pDevice,
+ pDevice->ReceiveMask & ~LM_ACCEPT_MULTICAST);
+ return LM_STATUS_SUCCESS;
+} /* LM_MulticastClear */
/******************************************************************************/
/* Description: */
/* */
/* Return: */
/******************************************************************************/
-LM_STATUS
-LM_SetMacAddress(
- PLM_DEVICE_BLOCK pDevice,
- PLM_UINT8 pMacAddress)
+LM_STATUS LM_SetMacAddress (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMacAddress)
{
- LM_UINT32 j;
-
- for(j = 0; j < 4; j++)
- {
- REG_WR(pDevice, MacCtrl.MacAddr[j].High,
- (pMacAddress[0] << 8) | pMacAddress[1]);
- REG_WR(pDevice, MacCtrl.MacAddr[j].Low,
- (pMacAddress[2] << 24) | (pMacAddress[3] << 16) |
- (pMacAddress[4] << 8) | pMacAddress[5]);
- }
-
- return LM_STATUS_SUCCESS;
-}
+ LM_UINT32 j;
+ for (j = 0; j < 4; j++) {
+ REG_WR (pDevice, MacCtrl.MacAddr[j].High,
+ (pMacAddress[0] << 8) | pMacAddress[1]);
+ REG_WR (pDevice, MacCtrl.MacAddr[j].Low,
+ (pMacAddress[2] << 24) | (pMacAddress[3] << 16) |
+ (pMacAddress[4] << 8) | pMacAddress[5]);
+ }
+
+ return LM_STATUS_SUCCESS;
+}
/******************************************************************************/
/* Description: */
@@ -4182,93 +3858,93 @@ LM_SetMacAddress(
/* None. */
/******************************************************************************/
static LM_STATUS
-LM_TranslateRequestedMediaType(
-LM_REQUESTED_MEDIA_TYPE RequestedMediaType,
-PLM_MEDIA_TYPE pMediaType,
-PLM_LINE_SPEED pLineSpeed,
-PLM_DUPLEX_MODE pDuplexMode) {
- *pMediaType = LM_MEDIA_TYPE_AUTO;
- *pLineSpeed = LM_LINE_SPEED_UNKNOWN;
- *pDuplexMode = LM_DUPLEX_MODE_UNKNOWN;
-
- /* determine media type */
- switch(RequestedMediaType) {
+LM_TranslateRequestedMediaType (LM_REQUESTED_MEDIA_TYPE RequestedMediaType,
+ PLM_MEDIA_TYPE pMediaType,
+ PLM_LINE_SPEED pLineSpeed,
+ PLM_DUPLEX_MODE pDuplexMode)
+{
+ *pMediaType = LM_MEDIA_TYPE_AUTO;
+ *pLineSpeed = LM_LINE_SPEED_UNKNOWN;
+ *pDuplexMode = LM_DUPLEX_MODE_UNKNOWN;
+
+ /* determine media type */
+ switch (RequestedMediaType) {
case LM_REQUESTED_MEDIA_TYPE_BNC:
- *pMediaType = LM_MEDIA_TYPE_BNC;
- *pLineSpeed = LM_LINE_SPEED_10MBPS;
- *pDuplexMode = LM_DUPLEX_MODE_HALF;
- break;
+ *pMediaType = LM_MEDIA_TYPE_BNC;
+ *pLineSpeed = LM_LINE_SPEED_10MBPS;
+ *pDuplexMode = LM_DUPLEX_MODE_HALF;
+ break;
case LM_REQUESTED_MEDIA_TYPE_UTP_AUTO:
- *pMediaType = LM_MEDIA_TYPE_UTP;
- break;
+ *pMediaType = LM_MEDIA_TYPE_UTP;
+ break;
case LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS:
- *pMediaType = LM_MEDIA_TYPE_UTP;
- *pLineSpeed = LM_LINE_SPEED_10MBPS;
- *pDuplexMode = LM_DUPLEX_MODE_HALF;
- break;
+ *pMediaType = LM_MEDIA_TYPE_UTP;
+ *pLineSpeed = LM_LINE_SPEED_10MBPS;
+ *pDuplexMode = LM_DUPLEX_MODE_HALF;
+ break;
case LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS_FULL_DUPLEX:
- *pMediaType = LM_MEDIA_TYPE_UTP;
- *pLineSpeed = LM_LINE_SPEED_10MBPS;
- *pDuplexMode = LM_DUPLEX_MODE_FULL;
- break;
+ *pMediaType = LM_MEDIA_TYPE_UTP;
+ *pLineSpeed = LM_LINE_SPEED_10MBPS;
+ *pDuplexMode = LM_DUPLEX_MODE_FULL;
+ break;
case LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS:
- *pMediaType = LM_MEDIA_TYPE_UTP;
- *pLineSpeed = LM_LINE_SPEED_100MBPS;
- *pDuplexMode = LM_DUPLEX_MODE_HALF;
- break;
+ *pMediaType = LM_MEDIA_TYPE_UTP;
+ *pLineSpeed = LM_LINE_SPEED_100MBPS;
+ *pDuplexMode = LM_DUPLEX_MODE_HALF;
+ break;
case LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS_FULL_DUPLEX:
- *pMediaType = LM_MEDIA_TYPE_UTP;
- *pLineSpeed = LM_LINE_SPEED_100MBPS;
- *pDuplexMode = LM_DUPLEX_MODE_FULL;
- break;
+ *pMediaType = LM_MEDIA_TYPE_UTP;
+ *pLineSpeed = LM_LINE_SPEED_100MBPS;
+ *pDuplexMode = LM_DUPLEX_MODE_FULL;
+ break;
case LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS:
- *pMediaType = LM_MEDIA_TYPE_UTP;
- *pLineSpeed = LM_LINE_SPEED_1000MBPS;
- *pDuplexMode = LM_DUPLEX_MODE_HALF;
- break;
+ *pMediaType = LM_MEDIA_TYPE_UTP;
+ *pLineSpeed = LM_LINE_SPEED_1000MBPS;
+ *pDuplexMode = LM_DUPLEX_MODE_HALF;
+ break;
case LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS_FULL_DUPLEX:
- *pMediaType = LM_MEDIA_TYPE_UTP;
- *pLineSpeed = LM_LINE_SPEED_1000MBPS;
- *pDuplexMode = LM_DUPLEX_MODE_FULL;
- break;
+ *pMediaType = LM_MEDIA_TYPE_UTP;
+ *pLineSpeed = LM_LINE_SPEED_1000MBPS;
+ *pDuplexMode = LM_DUPLEX_MODE_FULL;
+ break;
case LM_REQUESTED_MEDIA_TYPE_FIBER_100MBPS:
- *pMediaType = LM_MEDIA_TYPE_FIBER;
- *pLineSpeed = LM_LINE_SPEED_100MBPS;
- *pDuplexMode = LM_DUPLEX_MODE_HALF;
- break;
+ *pMediaType = LM_MEDIA_TYPE_FIBER;
+ *pLineSpeed = LM_LINE_SPEED_100MBPS;
+ *pDuplexMode = LM_DUPLEX_MODE_HALF;
+ break;
case LM_REQUESTED_MEDIA_TYPE_FIBER_100MBPS_FULL_DUPLEX:
- *pMediaType = LM_MEDIA_TYPE_FIBER;
- *pLineSpeed = LM_LINE_SPEED_100MBPS;
- *pDuplexMode = LM_DUPLEX_MODE_FULL;
- break;
+ *pMediaType = LM_MEDIA_TYPE_FIBER;
+ *pLineSpeed = LM_LINE_SPEED_100MBPS;
+ *pDuplexMode = LM_DUPLEX_MODE_FULL;
+ break;
case LM_REQUESTED_MEDIA_TYPE_FIBER_1000MBPS:
- *pMediaType = LM_MEDIA_TYPE_FIBER;
- *pLineSpeed = LM_LINE_SPEED_1000MBPS;
- *pDuplexMode = LM_DUPLEX_MODE_HALF;
- break;
+ *pMediaType = LM_MEDIA_TYPE_FIBER;
+ *pLineSpeed = LM_LINE_SPEED_1000MBPS;
+ *pDuplexMode = LM_DUPLEX_MODE_HALF;
+ break;
case LM_REQUESTED_MEDIA_TYPE_FIBER_1000MBPS_FULL_DUPLEX:
- *pMediaType = LM_MEDIA_TYPE_FIBER;
- *pLineSpeed = LM_LINE_SPEED_1000MBPS;
- *pDuplexMode = LM_DUPLEX_MODE_FULL;
- break;
+ *pMediaType = LM_MEDIA_TYPE_FIBER;
+ *pLineSpeed = LM_LINE_SPEED_1000MBPS;
+ *pDuplexMode = LM_DUPLEX_MODE_FULL;
+ break;
default:
- break;
- } /* switch */
+ break;
+ } /* switch */
- return LM_STATUS_SUCCESS;
-} /* LM_TranslateRequestedMediaType */
+ return LM_STATUS_SUCCESS;
+} /* LM_TranslateRequestedMediaType */
/******************************************************************************/
/* Description: */
@@ -4277,285 +3953,284 @@ PLM_DUPLEX_MODE pDuplexMode) {
/* LM_STATUS_LINK_ACTIVE */
/* LM_STATUS_LINK_DOWN */
/******************************************************************************/
-static LM_STATUS
-LM_InitBcm540xPhy(
-PLM_DEVICE_BLOCK pDevice)
+static LM_STATUS LM_InitBcm540xPhy (PLM_DEVICE_BLOCK pDevice)
{
- LM_LINE_SPEED CurrentLineSpeed;
- LM_DUPLEX_MODE CurrentDuplexMode;
- LM_STATUS CurrentLinkStatus;
- LM_UINT32 Value32;
- LM_UINT32 j;
-
-#if 1 /* jmb: bugfix -- moved here, out of code that sets initial pwr state */
- LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x2);
+ LM_LINE_SPEED CurrentLineSpeed;
+ LM_DUPLEX_MODE CurrentDuplexMode;
+ LM_STATUS CurrentLinkStatus;
+ LM_UINT32 Value32;
+ LM_UINT32 j;
+
+#if 1 /* jmb: bugfix -- moved here, out of code that sets initial pwr state */
+ LM_WritePhy (pDevice, BCM5401_AUX_CTRL, 0x2);
#endif
- if((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID)
- {
- LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
- LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
-
- if(!pDevice->InitDone)
- {
- Value32 = 0;
- }
+ if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID) {
+ LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
+ LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
- if(!(Value32 & PHY_STATUS_LINK_PASS))
- {
- LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x0c20);
+ if (!pDevice->InitDone) {
+ Value32 = 0;
+ }
- LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0012);
- LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1804);
+ if (!(Value32 & PHY_STATUS_LINK_PASS)) {
+ LM_WritePhy (pDevice, BCM5401_AUX_CTRL, 0x0c20);
- LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0013);
- LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1204);
+ LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x0012);
+ LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x1804);
- LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006);
- LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0132);
+ LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x0013);
+ LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x1204);
- LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006);
- LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0232);
+ LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006);
+ LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x0132);
- LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x201f);
- LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0a20);
+ LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006);
+ LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x0232);
- LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
- for(j = 0; j < 1000; j++)
- {
- MM_Wait(10);
+ LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x201f);
+ LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x0a20);
- LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
- if(Value32 & PHY_STATUS_LINK_PASS)
- {
- MM_Wait(40);
- break;
- }
- }
+ LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
+ for (j = 0; j < 1000; j++) {
+ MM_Wait (10);
- if((pDevice->PhyId & PHY_ID_REV_MASK) == PHY_BCM5401_B0_REV)
- {
- if(!(Value32 & PHY_STATUS_LINK_PASS) &&
- (pDevice->OldLineSpeed == LM_LINE_SPEED_1000MBPS))
- {
- LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_PHY_RESET);
- for(j = 0; j < 100; j++)
- {
- MM_Wait(10);
-
- LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32);
- if(!(Value32 & PHY_CTRL_PHY_RESET))
- {
- MM_Wait(40);
- break;
+ LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
+ if (Value32 & PHY_STATUS_LINK_PASS) {
+ MM_Wait (40);
+ break;
+ }
}
- }
-
- LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x0c20);
-
- LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0012);
- LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1804);
-
- LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0013);
- LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1204);
-
- LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006);
- LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0132);
- LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006);
- LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0232);
-
- LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x201f);
- LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0a20);
+ if ((pDevice->PhyId & PHY_ID_REV_MASK) ==
+ PHY_BCM5401_B0_REV) {
+ if (!(Value32 & PHY_STATUS_LINK_PASS)
+ && (pDevice->OldLineSpeed ==
+ LM_LINE_SPEED_1000MBPS)) {
+ LM_WritePhy (pDevice, PHY_CTRL_REG,
+ PHY_CTRL_PHY_RESET);
+ for (j = 0; j < 100; j++) {
+ MM_Wait (10);
+
+ LM_ReadPhy (pDevice,
+ PHY_CTRL_REG,
+ &Value32);
+ if (!
+ (Value32 &
+ PHY_CTRL_PHY_RESET)) {
+ MM_Wait (40);
+ break;
+ }
+ }
+
+ LM_WritePhy (pDevice, BCM5401_AUX_CTRL,
+ 0x0c20);
+
+ LM_WritePhy (pDevice,
+ BCM540X_DSP_ADDRESS_REG,
+ 0x0012);
+ LM_WritePhy (pDevice,
+ BCM540X_DSP_RW_PORT,
+ 0x1804);
+
+ LM_WritePhy (pDevice,
+ BCM540X_DSP_ADDRESS_REG,
+ 0x0013);
+ LM_WritePhy (pDevice,
+ BCM540X_DSP_RW_PORT,
+ 0x1204);
+
+ LM_WritePhy (pDevice,
+ BCM540X_DSP_ADDRESS_REG,
+ 0x8006);
+ LM_WritePhy (pDevice,
+ BCM540X_DSP_RW_PORT,
+ 0x0132);
+
+ LM_WritePhy (pDevice,
+ BCM540X_DSP_ADDRESS_REG,
+ 0x8006);
+ LM_WritePhy (pDevice,
+ BCM540X_DSP_RW_PORT,
+ 0x0232);
+
+ LM_WritePhy (pDevice,
+ BCM540X_DSP_ADDRESS_REG,
+ 0x201f);
+ LM_WritePhy (pDevice,
+ BCM540X_DSP_RW_PORT,
+ 0x0a20);
+ }
+ }
+ }
+ } else if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
+ pDevice->ChipRevId == T3_CHIP_ID_5701_B0) {
+ /* Bug: 5701 A0, B0 TX CRC workaround. */
+ LM_WritePhy (pDevice, 0x15, 0x0a75);
+ LM_WritePhy (pDevice, 0x1c, 0x8c68);
+ LM_WritePhy (pDevice, 0x1c, 0x8d68);
+ LM_WritePhy (pDevice, 0x1c, 0x8c68);
+ }
+
+ /* Acknowledge interrupts. */
+ LM_ReadPhy (pDevice, BCM540X_INT_STATUS_REG, &Value32);
+ LM_ReadPhy (pDevice, BCM540X_INT_STATUS_REG, &Value32);
+
+ /* Configure the interrupt mask. */
+ if (pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT) {
+ LM_WritePhy (pDevice, BCM540X_INT_MASK_REG,
+ ~BCM540X_INT_LINK_CHANGE);
+ }
+
+ /* Configure PHY led mode. */
+ if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701 ||
+ (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700)) {
+ if (pDevice->LedMode == LED_MODE_THREE_LINK) {
+ LM_WritePhy (pDevice, BCM540X_EXT_CTRL_REG,
+ BCM540X_EXT_CTRL_LINK3_LED_MODE);
+ } else {
+ LM_WritePhy (pDevice, BCM540X_EXT_CTRL_REG, 0);
}
- }
- }
- }
- else if(pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
- pDevice->ChipRevId == T3_CHIP_ID_5701_B0)
- {
- /* Bug: 5701 A0, B0 TX CRC workaround. */
- LM_WritePhy(pDevice, 0x15, 0x0a75);
- LM_WritePhy(pDevice, 0x1c, 0x8c68);
- LM_WritePhy(pDevice, 0x1c, 0x8d68);
- LM_WritePhy(pDevice, 0x1c, 0x8c68);
- }
-
- /* Acknowledge interrupts. */
- LM_ReadPhy(pDevice, BCM540X_INT_STATUS_REG, &Value32);
- LM_ReadPhy(pDevice, BCM540X_INT_STATUS_REG, &Value32);
-
- /* Configure the interrupt mask. */
- if(pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT)
- {
- LM_WritePhy(pDevice, BCM540X_INT_MASK_REG, ~BCM540X_INT_LINK_CHANGE);
- }
-
- /* Configure PHY led mode. */
- if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701 ||
- (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700))
- {
- if(pDevice->LedMode == LED_MODE_THREE_LINK)
- {
- LM_WritePhy(pDevice, BCM540X_EXT_CTRL_REG,
- BCM540X_EXT_CTRL_LINK3_LED_MODE);
- }
- else
- {
- LM_WritePhy(pDevice, BCM540X_EXT_CTRL_REG, 0);
}
- }
- CurrentLinkStatus = LM_STATUS_LINK_DOWN;
+ CurrentLinkStatus = LM_STATUS_LINK_DOWN;
- /* Get current link and duplex mode. */
- for(j = 0; j < 100; j++)
- {
- LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
- LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
+ /* Get current link and duplex mode. */
+ for (j = 0; j < 100; j++) {
+ LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
+ LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
- if(Value32 & PHY_STATUS_LINK_PASS)
- {
- break;
+ if (Value32 & PHY_STATUS_LINK_PASS) {
+ break;
+ }
+ MM_Wait (40);
}
- MM_Wait(40);
- }
-
- if(Value32 & PHY_STATUS_LINK_PASS)
- {
-
- /* Determine the current line and duplex settings. */
- LM_ReadPhy(pDevice, BCM540X_AUX_STATUS_REG, &Value32);
- for(j = 0; j < 2000; j++)
- {
- MM_Wait(10);
- LM_ReadPhy(pDevice, BCM540X_AUX_STATUS_REG, &Value32);
- if(Value32)
- {
- break;
- }
- }
+ if (Value32 & PHY_STATUS_LINK_PASS) {
- switch(Value32 & BCM540X_AUX_SPEED_MASK)
- {
- case BCM540X_AUX_10BASET_HD:
- CurrentLineSpeed = LM_LINE_SPEED_10MBPS;
- CurrentDuplexMode = LM_DUPLEX_MODE_HALF;
- break;
+ /* Determine the current line and duplex settings. */
+ LM_ReadPhy (pDevice, BCM540X_AUX_STATUS_REG, &Value32);
+ for (j = 0; j < 2000; j++) {
+ MM_Wait (10);
- case BCM540X_AUX_10BASET_FD:
- CurrentLineSpeed = LM_LINE_SPEED_10MBPS;
- CurrentDuplexMode = LM_DUPLEX_MODE_FULL;
- break;
+ LM_ReadPhy (pDevice, BCM540X_AUX_STATUS_REG, &Value32);
+ if (Value32) {
+ break;
+ }
+ }
- case BCM540X_AUX_100BASETX_HD:
- CurrentLineSpeed = LM_LINE_SPEED_100MBPS;
- CurrentDuplexMode = LM_DUPLEX_MODE_HALF;
- break;
+ switch (Value32 & BCM540X_AUX_SPEED_MASK) {
+ case BCM540X_AUX_10BASET_HD:
+ CurrentLineSpeed = LM_LINE_SPEED_10MBPS;
+ CurrentDuplexMode = LM_DUPLEX_MODE_HALF;
+ break;
- case BCM540X_AUX_100BASETX_FD:
- CurrentLineSpeed = LM_LINE_SPEED_100MBPS;
- CurrentDuplexMode = LM_DUPLEX_MODE_FULL;
- break;
+ case BCM540X_AUX_10BASET_FD:
+ CurrentLineSpeed = LM_LINE_SPEED_10MBPS;
+ CurrentDuplexMode = LM_DUPLEX_MODE_FULL;
+ break;
- case BCM540X_AUX_100BASET_HD:
- CurrentLineSpeed = LM_LINE_SPEED_1000MBPS;
- CurrentDuplexMode = LM_DUPLEX_MODE_HALF;
- break;
+ case BCM540X_AUX_100BASETX_HD:
+ CurrentLineSpeed = LM_LINE_SPEED_100MBPS;
+ CurrentDuplexMode = LM_DUPLEX_MODE_HALF;
+ break;
- case BCM540X_AUX_100BASET_FD:
- CurrentLineSpeed = LM_LINE_SPEED_1000MBPS;
- CurrentDuplexMode = LM_DUPLEX_MODE_FULL;
- break;
+ case BCM540X_AUX_100BASETX_FD:
+ CurrentLineSpeed = LM_LINE_SPEED_100MBPS;
+ CurrentDuplexMode = LM_DUPLEX_MODE_FULL;
+ break;
- default:
+ case BCM540X_AUX_100BASET_HD:
+ CurrentLineSpeed = LM_LINE_SPEED_1000MBPS;
+ CurrentDuplexMode = LM_DUPLEX_MODE_HALF;
+ break;
- CurrentLineSpeed = LM_LINE_SPEED_UNKNOWN;
- CurrentDuplexMode = LM_DUPLEX_MODE_UNKNOWN;
- break;
- }
+ case BCM540X_AUX_100BASET_FD:
+ CurrentLineSpeed = LM_LINE_SPEED_1000MBPS;
+ CurrentDuplexMode = LM_DUPLEX_MODE_FULL;
+ break;
- /* Make sure we are in auto-neg mode. */
- for (j = 0; j < 200; j++)
- {
- LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32);
- if(Value32 && Value32 != 0x7fff)
- {
- break;
- }
+ default:
- if(Value32 == 0 && pDevice->RequestedMediaType ==
- LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS)
- {
- break;
- }
+ CurrentLineSpeed = LM_LINE_SPEED_UNKNOWN;
+ CurrentDuplexMode = LM_DUPLEX_MODE_UNKNOWN;
+ break;
+ }
- MM_Wait(10);
- }
+ /* Make sure we are in auto-neg mode. */
+ for (j = 0; j < 200; j++) {
+ LM_ReadPhy (pDevice, PHY_CTRL_REG, &Value32);
+ if (Value32 && Value32 != 0x7fff) {
+ break;
+ }
- /* Use the current line settings for "auto" mode. */
- if(pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_AUTO ||
- pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_UTP_AUTO)
- {
- if(Value32 & PHY_CTRL_AUTO_NEG_ENABLE)
- {
- CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
+ if (Value32 == 0 && pDevice->RequestedMediaType ==
+ LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS) {
+ break;
+ }
- /* We may be exiting low power mode and the link is in */
- /* 10mb. In this case, we need to restart autoneg. */
- LM_ReadPhy(pDevice, BCM540X_1000BASET_CTRL_REG, &Value32);
- pDevice->advertising1000 = Value32;
- /* 5702FE supports 10/100Mb only. */
- if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5703 ||
- pDevice->BondId != GRC_MISC_BD_ID_5702FE)
- {
- if(!(Value32 & (BCM540X_AN_AD_1000BASET_HALF |
- BCM540X_AN_AD_1000BASET_FULL)))
- {
- CurrentLinkStatus = LM_STATUS_LINK_SETTING_MISMATCH;
- }
- }
- }
- else
- {
- CurrentLinkStatus = LM_STATUS_LINK_SETTING_MISMATCH;
- }
- }
- else
- {
- /* Force line settings. */
- /* Use the current setting if it matches the user's requested */
- /* setting. */
- LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32);
- if((pDevice->LineSpeed == CurrentLineSpeed) &&
- (pDevice->DuplexMode == CurrentDuplexMode))
- {
- if ((pDevice->DisableAutoNeg &&
- !(Value32 & PHY_CTRL_AUTO_NEG_ENABLE)) ||
- (!pDevice->DisableAutoNeg &&
- (Value32 & PHY_CTRL_AUTO_NEG_ENABLE)))
- {
- CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
+ MM_Wait (10);
}
- else
- {
- CurrentLinkStatus = LM_STATUS_LINK_SETTING_MISMATCH;
+
+ /* Use the current line settings for "auto" mode. */
+ if (pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_AUTO
+ || pDevice->RequestedMediaType ==
+ LM_REQUESTED_MEDIA_TYPE_UTP_AUTO) {
+ if (Value32 & PHY_CTRL_AUTO_NEG_ENABLE) {
+ CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
+
+ /* We may be exiting low power mode and the link is in */
+ /* 10mb. In this case, we need to restart autoneg. */
+ LM_ReadPhy (pDevice, BCM540X_1000BASET_CTRL_REG,
+ &Value32);
+ pDevice->advertising1000 = Value32;
+ /* 5702FE supports 10/100Mb only. */
+ if (T3_ASIC_REV (pDevice->ChipRevId) !=
+ T3_ASIC_REV_5703
+ || pDevice->BondId !=
+ GRC_MISC_BD_ID_5702FE) {
+ if (!
+ (Value32 &
+ (BCM540X_AN_AD_1000BASET_HALF |
+ BCM540X_AN_AD_1000BASET_FULL))) {
+ CurrentLinkStatus =
+ LM_STATUS_LINK_SETTING_MISMATCH;
+ }
+ }
+ } else {
+ CurrentLinkStatus =
+ LM_STATUS_LINK_SETTING_MISMATCH;
+ }
+ } else {
+ /* Force line settings. */
+ /* Use the current setting if it matches the user's requested */
+ /* setting. */
+ LM_ReadPhy (pDevice, PHY_CTRL_REG, &Value32);
+ if ((pDevice->LineSpeed == CurrentLineSpeed) &&
+ (pDevice->DuplexMode == CurrentDuplexMode)) {
+ if ((pDevice->DisableAutoNeg &&
+ !(Value32 & PHY_CTRL_AUTO_NEG_ENABLE)) ||
+ (!pDevice->DisableAutoNeg &&
+ (Value32 & PHY_CTRL_AUTO_NEG_ENABLE))) {
+ CurrentLinkStatus =
+ LM_STATUS_LINK_ACTIVE;
+ } else {
+ CurrentLinkStatus =
+ LM_STATUS_LINK_SETTING_MISMATCH;
+ }
+ } else {
+ CurrentLinkStatus =
+ LM_STATUS_LINK_SETTING_MISMATCH;
+ }
}
- }
- else
- {
- CurrentLinkStatus = LM_STATUS_LINK_SETTING_MISMATCH;
- }
- }
- /* Save line settings. */
- pDevice->LineSpeed = CurrentLineSpeed;
- pDevice->DuplexMode = CurrentDuplexMode;
- pDevice->MediaType = LM_MEDIA_TYPE_UTP;
- }
+ /* Save line settings. */
+ pDevice->LineSpeed = CurrentLineSpeed;
+ pDevice->DuplexMode = CurrentDuplexMode;
+ pDevice->MediaType = LM_MEDIA_TYPE_UTP;
+ }
- return CurrentLinkStatus;
-} /* LM_InitBcm540xPhy */
+ return CurrentLinkStatus;
+} /* LM_InitBcm540xPhy */
/******************************************************************************/
/* Description: */
@@ -4563,83 +4238,69 @@ PLM_DEVICE_BLOCK pDevice)
/* Return: */
/******************************************************************************/
LM_STATUS
-LM_SetFlowControl(
- PLM_DEVICE_BLOCK pDevice,
- LM_UINT32 LocalPhyAd,
- LM_UINT32 RemotePhyAd)
+LM_SetFlowControl (PLM_DEVICE_BLOCK pDevice,
+ LM_UINT32 LocalPhyAd, LM_UINT32 RemotePhyAd)
{
- LM_FLOW_CONTROL FlowCap;
+ LM_FLOW_CONTROL FlowCap;
- /* Resolve flow control. */
- FlowCap = LM_FLOW_CONTROL_NONE;
+ /* Resolve flow control. */
+ FlowCap = LM_FLOW_CONTROL_NONE;
- /* See Table 28B-3 of 802.3ab-1999 spec. */
- if(pDevice->FlowControlCap & LM_FLOW_CONTROL_AUTO_PAUSE)
- {
- if(LocalPhyAd & PHY_AN_AD_PAUSE_CAPABLE)
- {
- if(LocalPhyAd & PHY_AN_AD_ASYM_PAUSE)
- {
- if(RemotePhyAd & PHY_LINK_PARTNER_PAUSE_CAPABLE)
- {
- FlowCap = LM_FLOW_CONTROL_TRANSMIT_PAUSE |
- LM_FLOW_CONTROL_RECEIVE_PAUSE;
- }
- else if(RemotePhyAd & PHY_LINK_PARTNER_ASYM_PAUSE)
- {
- FlowCap = LM_FLOW_CONTROL_RECEIVE_PAUSE;
- }
- }
- else
- {
- if(RemotePhyAd & PHY_LINK_PARTNER_PAUSE_CAPABLE)
- {
- FlowCap = LM_FLOW_CONTROL_TRANSMIT_PAUSE |
- LM_FLOW_CONTROL_RECEIVE_PAUSE;
- }
- }
- }
- else if(LocalPhyAd & PHY_AN_AD_ASYM_PAUSE)
- {
- if((RemotePhyAd & PHY_LINK_PARTNER_PAUSE_CAPABLE) &&
- (RemotePhyAd & PHY_LINK_PARTNER_ASYM_PAUSE))
- {
- FlowCap = LM_FLOW_CONTROL_TRANSMIT_PAUSE;
- }
- }
- }
- else
- {
- FlowCap = pDevice->FlowControlCap;
- }
-
- /* Enable/disable rx PAUSE. */
- pDevice->RxMode &= ~RX_MODE_ENABLE_FLOW_CONTROL;
- if(FlowCap & LM_FLOW_CONTROL_RECEIVE_PAUSE &&
- (pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE ||
- pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE))
- {
- pDevice->FlowControl |= LM_FLOW_CONTROL_RECEIVE_PAUSE;
- pDevice->RxMode |= RX_MODE_ENABLE_FLOW_CONTROL;
-
- }
- REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode);
-
- /* Enable/disable tx PAUSE. */
- pDevice->TxMode &= ~TX_MODE_ENABLE_FLOW_CONTROL;
- if(FlowCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE &&
- (pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE ||
- pDevice->FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE))
- {
- pDevice->FlowControl |= LM_FLOW_CONTROL_TRANSMIT_PAUSE;
- pDevice->TxMode |= TX_MODE_ENABLE_FLOW_CONTROL;
-
- }
- REG_WR(pDevice, MacCtrl.TxMode, pDevice->TxMode);
-
- return LM_STATUS_SUCCESS;
-}
+ /* See Table 28B-3 of 802.3ab-1999 spec. */
+ if (pDevice->FlowControlCap & LM_FLOW_CONTROL_AUTO_PAUSE) {
+ if (LocalPhyAd & PHY_AN_AD_PAUSE_CAPABLE) {
+ if (LocalPhyAd & PHY_AN_AD_ASYM_PAUSE) {
+ if (RemotePhyAd &
+ PHY_LINK_PARTNER_PAUSE_CAPABLE) {
+ FlowCap =
+ LM_FLOW_CONTROL_TRANSMIT_PAUSE |
+ LM_FLOW_CONTROL_RECEIVE_PAUSE;
+ } else if (RemotePhyAd &
+ PHY_LINK_PARTNER_ASYM_PAUSE) {
+ FlowCap = LM_FLOW_CONTROL_RECEIVE_PAUSE;
+ }
+ } else {
+ if (RemotePhyAd &
+ PHY_LINK_PARTNER_PAUSE_CAPABLE) {
+ FlowCap =
+ LM_FLOW_CONTROL_TRANSMIT_PAUSE |
+ LM_FLOW_CONTROL_RECEIVE_PAUSE;
+ }
+ }
+ } else if (LocalPhyAd & PHY_AN_AD_ASYM_PAUSE) {
+ if ((RemotePhyAd & PHY_LINK_PARTNER_PAUSE_CAPABLE) &&
+ (RemotePhyAd & PHY_LINK_PARTNER_ASYM_PAUSE)) {
+ FlowCap = LM_FLOW_CONTROL_TRANSMIT_PAUSE;
+ }
+ }
+ } else {
+ FlowCap = pDevice->FlowControlCap;
+ }
+
+ /* Enable/disable rx PAUSE. */
+ pDevice->RxMode &= ~RX_MODE_ENABLE_FLOW_CONTROL;
+ if (FlowCap & LM_FLOW_CONTROL_RECEIVE_PAUSE &&
+ (pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE ||
+ pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE)) {
+ pDevice->FlowControl |= LM_FLOW_CONTROL_RECEIVE_PAUSE;
+ pDevice->RxMode |= RX_MODE_ENABLE_FLOW_CONTROL;
+
+ }
+ REG_WR (pDevice, MacCtrl.RxMode, pDevice->RxMode);
+
+ /* Enable/disable tx PAUSE. */
+ pDevice->TxMode &= ~TX_MODE_ENABLE_FLOW_CONTROL;
+ if (FlowCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE &&
+ (pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE ||
+ pDevice->FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE)) {
+ pDevice->FlowControl |= LM_FLOW_CONTROL_TRANSMIT_PAUSE;
+ pDevice->TxMode |= TX_MODE_ENABLE_FLOW_CONTROL;
+
+ }
+ REG_WR (pDevice, MacCtrl.TxMode, pDevice->TxMode);
+ return LM_STATUS_SUCCESS;
+}
#if INCLUDE_TBI_SUPPORT
/******************************************************************************/
@@ -4647,583 +4308,520 @@ LM_SetFlowControl(
/* */
/* Return: */
/******************************************************************************/
-STATIC LM_STATUS
-LM_InitBcm800xPhy(
- PLM_DEVICE_BLOCK pDevice)
+STATIC LM_STATUS LM_InitBcm800xPhy (PLM_DEVICE_BLOCK pDevice)
{
- LM_UINT32 Value32;
- LM_UINT32 j;
+ LM_UINT32 Value32;
+ LM_UINT32 j;
- Value32 = REG_RD(pDevice, MacCtrl.Status);
+ Value32 = REG_RD (pDevice, MacCtrl.Status);
- /* Reset the SERDES during init and when we have link. */
- if(!pDevice->InitDone || Value32 & MAC_STATUS_PCS_SYNCED)
- {
- /* Set PLL lock range. */
- LM_WritePhy(pDevice, 0x16, 0x8007);
+ /* Reset the SERDES during init and when we have link. */
+ if (!pDevice->InitDone || Value32 & MAC_STATUS_PCS_SYNCED) {
+ /* Set PLL lock range. */
+ LM_WritePhy (pDevice, 0x16, 0x8007);
- /* Software reset. */
- LM_WritePhy(pDevice, 0x00, 0x8000);
+ /* Software reset. */
+ LM_WritePhy (pDevice, 0x00, 0x8000);
- /* Wait for reset to complete. */
- for(j = 0; j < 500; j++)
- {
- MM_Wait(10);
- }
+ /* Wait for reset to complete. */
+ for (j = 0; j < 500; j++) {
+ MM_Wait (10);
+ }
- /* Config mode; seletct PMA/Ch 1 regs. */
- LM_WritePhy(pDevice, 0x10, 0x8411);
+ /* Config mode; seletct PMA/Ch 1 regs. */
+ LM_WritePhy (pDevice, 0x10, 0x8411);
- /* Enable auto-lock and comdet, select txclk for tx. */
- LM_WritePhy(pDevice, 0x11, 0x0a10);
+ /* Enable auto-lock and comdet, select txclk for tx. */
+ LM_WritePhy (pDevice, 0x11, 0x0a10);
- LM_WritePhy(pDevice, 0x18, 0x00a0);
- LM_WritePhy(pDevice, 0x16, 0x41ff);
+ LM_WritePhy (pDevice, 0x18, 0x00a0);
+ LM_WritePhy (pDevice, 0x16, 0x41ff);
- /* Assert and deassert POR. */
- LM_WritePhy(pDevice, 0x13, 0x0400);
- MM_Wait(40);
- LM_WritePhy(pDevice, 0x13, 0x0000);
+ /* Assert and deassert POR. */
+ LM_WritePhy (pDevice, 0x13, 0x0400);
+ MM_Wait (40);
+ LM_WritePhy (pDevice, 0x13, 0x0000);
- LM_WritePhy(pDevice, 0x11, 0x0a50);
- MM_Wait(40);
- LM_WritePhy(pDevice, 0x11, 0x0a10);
+ LM_WritePhy (pDevice, 0x11, 0x0a50);
+ MM_Wait (40);
+ LM_WritePhy (pDevice, 0x11, 0x0a10);
- /* Delay for signal to stabilize. */
- for(j = 0; j < 15000; j++)
- {
- MM_Wait(10);
- }
+ /* Delay for signal to stabilize. */
+ for (j = 0; j < 15000; j++) {
+ MM_Wait (10);
+ }
- /* Deselect the channel register so we can read the PHY id later. */
- LM_WritePhy(pDevice, 0x10, 0x8011);
- }
+ /* Deselect the channel register so we can read the PHY id later. */
+ LM_WritePhy (pDevice, 0x10, 0x8011);
+ }
- return LM_STATUS_SUCCESS;
+ return LM_STATUS_SUCCESS;
}
-
/******************************************************************************/
/* Description: */
/* */
/* Return: */
/******************************************************************************/
-STATIC LM_STATUS
-LM_SetupFiberPhy(
- PLM_DEVICE_BLOCK pDevice)
+STATIC LM_STATUS LM_SetupFiberPhy (PLM_DEVICE_BLOCK pDevice)
{
- LM_STATUS CurrentLinkStatus;
- AUTONEG_STATUS AnStatus = 0;
- LM_UINT32 Value32;
- LM_UINT32 Cnt;
- LM_UINT32 j, k;
+ LM_STATUS CurrentLinkStatus;
+ AUTONEG_STATUS AnStatus = 0;
+ LM_UINT32 Value32;
+ LM_UINT32 Cnt;
+ LM_UINT32 j, k;
- pDevice->MacMode &= ~(MAC_MODE_HALF_DUPLEX | MAC_MODE_PORT_MODE_MASK);
+ pDevice->MacMode &= ~(MAC_MODE_HALF_DUPLEX | MAC_MODE_PORT_MODE_MASK);
- /* Initialize the send_config register. */
- REG_WR(pDevice, MacCtrl.TxAutoNeg, 0);
+ /* Initialize the send_config register. */
+ REG_WR (pDevice, MacCtrl.TxAutoNeg, 0);
- /* Enable TBI and full duplex mode. */
- pDevice->MacMode |= MAC_MODE_PORT_MODE_TBI;
- REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
+ /* Enable TBI and full duplex mode. */
+ pDevice->MacMode |= MAC_MODE_PORT_MODE_TBI;
+ REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode);
- /* Initialize the BCM8002 SERDES PHY. */
- switch(pDevice->PhyId & PHY_ID_MASK)
- {
+ /* Initialize the BCM8002 SERDES PHY. */
+ switch (pDevice->PhyId & PHY_ID_MASK) {
case PHY_BCM8002_PHY_ID:
- LM_InitBcm800xPhy(pDevice);
- break;
+ LM_InitBcm800xPhy (pDevice);
+ break;
default:
- break;
- }
-
- /* Enable link change interrupt. */
- REG_WR(pDevice, MacCtrl.MacEvent, MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN);
-
- /* Default to link down. */
- CurrentLinkStatus = LM_STATUS_LINK_DOWN;
+ break;
+ }
- /* Get the link status. */
- Value32 = REG_RD(pDevice, MacCtrl.Status);
- if(Value32 & MAC_STATUS_PCS_SYNCED)
- {
- if((pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_AUTO) ||
- (pDevice->DisableAutoNeg == FALSE))
- {
- /* auto-negotiation mode. */
- /* Initialize the autoneg default capaiblities. */
- AutonegInit(&pDevice->AnInfo);
-
- /* Set the context pointer to point to the main device structure. */
- pDevice->AnInfo.pContext = pDevice;
-
- /* Setup flow control advertisement register. */
- Value32 = GetPhyAdFlowCntrlSettings(pDevice);
- if(Value32 & PHY_AN_AD_PAUSE_CAPABLE)
- {
- pDevice->AnInfo.mr_adv_sym_pause = 1;
- }
- else
- {
- pDevice->AnInfo.mr_adv_sym_pause = 0;
- }
-
- if(Value32 & PHY_AN_AD_ASYM_PAUSE)
- {
- pDevice->AnInfo.mr_adv_asym_pause = 1;
- }
- else
- {
- pDevice->AnInfo.mr_adv_asym_pause = 0;
- }
-
- /* Try to autoneg up to six times. */
- if (pDevice->IgnoreTbiLinkChange)
- {
- Cnt = 1;
- }
- else
- {
- Cnt = 6;
- }
- for (j = 0; j < Cnt; j++)
- {
- REG_WR(pDevice, MacCtrl.TxAutoNeg, 0);
-
- Value32 = pDevice->MacMode & ~MAC_MODE_PORT_MODE_MASK;
- REG_WR(pDevice, MacCtrl.Mode, Value32);
- MM_Wait(20);
-
- REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode |
- MAC_MODE_SEND_CONFIGS);
-
- MM_Wait(20);
-
- pDevice->AnInfo.State = AN_STATE_UNKNOWN;
- pDevice->AnInfo.CurrentTime_us = 0;
-
- REG_WR(pDevice, Grc.Timer, 0);
- for(k = 0; (pDevice->AnInfo.CurrentTime_us < 75000) &&
- (k < 75000); k++)
- {
- AnStatus = Autoneg8023z(&pDevice->AnInfo);
-
- if((AnStatus == AUTONEG_STATUS_DONE) ||
- (AnStatus == AUTONEG_STATUS_FAILED))
- {
- break;
- }
+ /* Enable link change interrupt. */
+ REG_WR (pDevice, MacCtrl.MacEvent,
+ MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN);
- pDevice->AnInfo.CurrentTime_us = REG_RD(pDevice, Grc.Timer);
+ /* Default to link down. */
+ CurrentLinkStatus = LM_STATUS_LINK_DOWN;
- }
- if((AnStatus == AUTONEG_STATUS_DONE) ||
- (AnStatus == AUTONEG_STATUS_FAILED))
- {
- break;
- }
- if (j >= 1)
- {
- if (!(REG_RD(pDevice, MacCtrl.Status) &
- MAC_STATUS_PCS_SYNCED)) {
- break;
- }
- }
- }
+ /* Get the link status. */
+ Value32 = REG_RD (pDevice, MacCtrl.Status);
+ if (Value32 & MAC_STATUS_PCS_SYNCED) {
+ if ((pDevice->RequestedMediaType ==
+ LM_REQUESTED_MEDIA_TYPE_AUTO)
+ || (pDevice->DisableAutoNeg == FALSE)) {
+ /* auto-negotiation mode. */
+ /* Initialize the autoneg default capaiblities. */
+ AutonegInit (&pDevice->AnInfo);
+
+ /* Set the context pointer to point to the main device structure. */
+ pDevice->AnInfo.pContext = pDevice;
+
+ /* Setup flow control advertisement register. */
+ Value32 = GetPhyAdFlowCntrlSettings (pDevice);
+ if (Value32 & PHY_AN_AD_PAUSE_CAPABLE) {
+ pDevice->AnInfo.mr_adv_sym_pause = 1;
+ } else {
+ pDevice->AnInfo.mr_adv_sym_pause = 0;
+ }
- /* Stop sending configs. */
- MM_AnTxIdle(&pDevice->AnInfo);
+ if (Value32 & PHY_AN_AD_ASYM_PAUSE) {
+ pDevice->AnInfo.mr_adv_asym_pause = 1;
+ } else {
+ pDevice->AnInfo.mr_adv_asym_pause = 0;
+ }
- /* Resolve flow control settings. */
- if((AnStatus == AUTONEG_STATUS_DONE) &&
- pDevice->AnInfo.mr_an_complete && pDevice->AnInfo.mr_link_ok &&
- pDevice->AnInfo.mr_lp_adv_full_duplex)
- {
- LM_UINT32 RemotePhyAd;
- LM_UINT32 LocalPhyAd;
+ /* Try to autoneg up to six times. */
+ if (pDevice->IgnoreTbiLinkChange) {
+ Cnt = 1;
+ } else {
+ Cnt = 6;
+ }
+ for (j = 0; j < Cnt; j++) {
+ REG_WR (pDevice, MacCtrl.TxAutoNeg, 0);
+
+ Value32 =
+ pDevice->MacMode & ~MAC_MODE_PORT_MODE_MASK;
+ REG_WR (pDevice, MacCtrl.Mode, Value32);
+ MM_Wait (20);
+
+ REG_WR (pDevice, MacCtrl.Mode,
+ pDevice->
+ MacMode | MAC_MODE_SEND_CONFIGS);
+
+ MM_Wait (20);
+
+ pDevice->AnInfo.State = AN_STATE_UNKNOWN;
+ pDevice->AnInfo.CurrentTime_us = 0;
+
+ REG_WR (pDevice, Grc.Timer, 0);
+ for (k = 0;
+ (pDevice->AnInfo.CurrentTime_us < 75000)
+ && (k < 75000); k++) {
+ AnStatus =
+ Autoneg8023z (&pDevice->AnInfo);
+
+ if ((AnStatus == AUTONEG_STATUS_DONE) ||
+ (AnStatus == AUTONEG_STATUS_FAILED))
+ {
+ break;
+ }
+
+ pDevice->AnInfo.CurrentTime_us =
+ REG_RD (pDevice, Grc.Timer);
+
+ }
+ if ((AnStatus == AUTONEG_STATUS_DONE) ||
+ (AnStatus == AUTONEG_STATUS_FAILED)) {
+ break;
+ }
+ if (j >= 1) {
+ if (!(REG_RD (pDevice, MacCtrl.Status) &
+ MAC_STATUS_PCS_SYNCED)) {
+ break;
+ }
+ }
+ }
- LocalPhyAd = 0;
- if(pDevice->AnInfo.mr_adv_sym_pause)
- {
- LocalPhyAd |= PHY_AN_AD_PAUSE_CAPABLE;
+ /* Stop sending configs. */
+ MM_AnTxIdle (&pDevice->AnInfo);
+
+ /* Resolve flow control settings. */
+ if ((AnStatus == AUTONEG_STATUS_DONE) &&
+ pDevice->AnInfo.mr_an_complete
+ && pDevice->AnInfo.mr_link_ok
+ && pDevice->AnInfo.mr_lp_adv_full_duplex) {
+ LM_UINT32 RemotePhyAd;
+ LM_UINT32 LocalPhyAd;
+
+ LocalPhyAd = 0;
+ if (pDevice->AnInfo.mr_adv_sym_pause) {
+ LocalPhyAd |= PHY_AN_AD_PAUSE_CAPABLE;
+ }
+
+ if (pDevice->AnInfo.mr_adv_asym_pause) {
+ LocalPhyAd |= PHY_AN_AD_ASYM_PAUSE;
+ }
+
+ RemotePhyAd = 0;
+ if (pDevice->AnInfo.mr_lp_adv_sym_pause) {
+ RemotePhyAd |=
+ PHY_LINK_PARTNER_PAUSE_CAPABLE;
+ }
+
+ if (pDevice->AnInfo.mr_lp_adv_asym_pause) {
+ RemotePhyAd |=
+ PHY_LINK_PARTNER_ASYM_PAUSE;
+ }
+
+ LM_SetFlowControl (pDevice, LocalPhyAd,
+ RemotePhyAd);
+
+ CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
+ }
+ for (j = 0; j < 30; j++) {
+ MM_Wait (20);
+ REG_WR (pDevice, MacCtrl.Status,
+ MAC_STATUS_SYNC_CHANGED |
+ MAC_STATUS_CFG_CHANGED);
+ MM_Wait (20);
+ if ((REG_RD (pDevice, MacCtrl.Status) &
+ (MAC_STATUS_SYNC_CHANGED |
+ MAC_STATUS_CFG_CHANGED)) == 0)
+ break;
+ }
+ if (pDevice->PollTbiLink) {
+ Value32 = REG_RD (pDevice, MacCtrl.Status);
+ if (Value32 & MAC_STATUS_RECEIVING_CFG) {
+ pDevice->IgnoreTbiLinkChange = TRUE;
+ } else {
+ pDevice->IgnoreTbiLinkChange = FALSE;
+ }
+ }
+ Value32 = REG_RD (pDevice, MacCtrl.Status);
+ if (CurrentLinkStatus == LM_STATUS_LINK_DOWN &&
+ (Value32 & MAC_STATUS_PCS_SYNCED) &&
+ ((Value32 & MAC_STATUS_RECEIVING_CFG) == 0)) {
+ CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
+ }
+ } else {
+ /* We are forcing line speed. */
+ pDevice->FlowControlCap &= ~LM_FLOW_CONTROL_AUTO_PAUSE;
+ LM_SetFlowControl (pDevice, 0, 0);
+
+ CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
+ REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode |
+ MAC_MODE_SEND_CONFIGS);
}
+ }
+ /* Set the link polarity bit. */
+ pDevice->MacMode &= ~MAC_MODE_LINK_POLARITY;
+ REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode);
- if(pDevice->AnInfo.mr_adv_asym_pause)
- {
- LocalPhyAd |= PHY_AN_AD_ASYM_PAUSE;
- }
+ pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED |
+ (pDevice->pStatusBlkVirt->
+ Status & ~STATUS_BLOCK_LINK_CHANGED_STATUS);
- RemotePhyAd = 0;
- if(pDevice->AnInfo.mr_lp_adv_sym_pause)
- {
- RemotePhyAd |= PHY_LINK_PARTNER_PAUSE_CAPABLE;
- }
+ for (j = 0; j < 100; j++) {
+ REG_WR (pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED |
+ MAC_STATUS_CFG_CHANGED);
+ MM_Wait (5);
+ if ((REG_RD (pDevice, MacCtrl.Status) &
+ (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED)) == 0)
+ break;
+ }
- if(pDevice->AnInfo.mr_lp_adv_asym_pause)
- {
- RemotePhyAd |= PHY_LINK_PARTNER_ASYM_PAUSE;
+ Value32 = REG_RD (pDevice, MacCtrl.Status);
+ if ((Value32 & MAC_STATUS_PCS_SYNCED) == 0) {
+ CurrentLinkStatus = LM_STATUS_LINK_DOWN;
+ if (pDevice->DisableAutoNeg == FALSE) {
+ REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode |
+ MAC_MODE_SEND_CONFIGS);
+ MM_Wait (1);
+ REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode);
}
+ }
- LM_SetFlowControl(pDevice, LocalPhyAd, RemotePhyAd);
+ /* Initialize the current link status. */
+ if (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) {
+ pDevice->LineSpeed = LM_LINE_SPEED_1000MBPS;
+ pDevice->DuplexMode = LM_DUPLEX_MODE_FULL;
+ REG_WR (pDevice, MacCtrl.LedCtrl, LED_CTRL_OVERRIDE_LINK_LED |
+ LED_CTRL_1000MBPS_LED_ON);
+ } else {
+ pDevice->LineSpeed = LM_LINE_SPEED_UNKNOWN;
+ pDevice->DuplexMode = LM_DUPLEX_MODE_UNKNOWN;
+ REG_WR (pDevice, MacCtrl.LedCtrl, LED_CTRL_OVERRIDE_LINK_LED |
+ LED_CTRL_OVERRIDE_TRAFFIC_LED);
+ }
- CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
- }
- for (j = 0; j < 30; j++)
- {
- MM_Wait(20);
- REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED |
- MAC_STATUS_CFG_CHANGED);
- MM_Wait(20);
- if ((REG_RD(pDevice, MacCtrl.Status) &
- (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED)) == 0)
- break;
- }
- if (pDevice->PollTbiLink)
- {
- Value32 = REG_RD(pDevice, MacCtrl.Status);
- if (Value32 & MAC_STATUS_RECEIVING_CFG)
- {
- pDevice->IgnoreTbiLinkChange = TRUE;
- }
- else
- {
- pDevice->IgnoreTbiLinkChange = FALSE;
- }
- }
- Value32 = REG_RD(pDevice, MacCtrl.Status);
- if (CurrentLinkStatus == LM_STATUS_LINK_DOWN &&
- (Value32 & MAC_STATUS_PCS_SYNCED) &&
- ((Value32 & MAC_STATUS_RECEIVING_CFG) == 0))
- {
- CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
- }
+ /* Indicate link status. */
+ if (pDevice->LinkStatus != CurrentLinkStatus) {
+ pDevice->LinkStatus = CurrentLinkStatus;
+ MM_IndicateStatus (pDevice, CurrentLinkStatus);
}
- else
- {
- /* We are forcing line speed. */
- pDevice->FlowControlCap &= ~LM_FLOW_CONTROL_AUTO_PAUSE;
- LM_SetFlowControl(pDevice, 0, 0);
-
- CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
- REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode |
- MAC_MODE_SEND_CONFIGS);
- }
- }
- /* Set the link polarity bit. */
- pDevice->MacMode &= ~MAC_MODE_LINK_POLARITY;
- REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
-
- pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED |
- (pDevice->pStatusBlkVirt->Status & ~STATUS_BLOCK_LINK_CHANGED_STATUS);
-
- for (j = 0; j < 100; j++)
- {
- REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED |
- MAC_STATUS_CFG_CHANGED);
- MM_Wait(5);
- if ((REG_RD(pDevice, MacCtrl.Status) &
- (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED)) == 0)
- break;
- }
-
- Value32 = REG_RD(pDevice, MacCtrl.Status);
- if((Value32 & MAC_STATUS_PCS_SYNCED) == 0)
- {
- CurrentLinkStatus = LM_STATUS_LINK_DOWN;
- if (pDevice->DisableAutoNeg == FALSE)
- {
- REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode |
- MAC_MODE_SEND_CONFIGS);
- MM_Wait(1);
- REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
- }
- }
-
- /* Initialize the current link status. */
- if(CurrentLinkStatus == LM_STATUS_LINK_ACTIVE)
- {
- pDevice->LineSpeed = LM_LINE_SPEED_1000MBPS;
- pDevice->DuplexMode = LM_DUPLEX_MODE_FULL;
- REG_WR(pDevice, MacCtrl.LedCtrl, LED_CTRL_OVERRIDE_LINK_LED |
- LED_CTRL_1000MBPS_LED_ON);
- }
- else
- {
- pDevice->LineSpeed = LM_LINE_SPEED_UNKNOWN;
- pDevice->DuplexMode = LM_DUPLEX_MODE_UNKNOWN;
- REG_WR(pDevice, MacCtrl.LedCtrl, LED_CTRL_OVERRIDE_LINK_LED |
- LED_CTRL_OVERRIDE_TRAFFIC_LED);
- }
-
- /* Indicate link status. */
- if (pDevice->LinkStatus != CurrentLinkStatus) {
- pDevice->LinkStatus = CurrentLinkStatus;
- MM_IndicateStatus(pDevice, CurrentLinkStatus);
- }
-
- return LM_STATUS_SUCCESS;
-}
-#endif /* INCLUDE_TBI_SUPPORT */
+ return LM_STATUS_SUCCESS;
+}
+#endif /* INCLUDE_TBI_SUPPORT */
/******************************************************************************/
/* Description: */
/* */
/* Return: */
/******************************************************************************/
-LM_STATUS
-LM_SetupCopperPhy(
- PLM_DEVICE_BLOCK pDevice)
+LM_STATUS LM_SetupCopperPhy (PLM_DEVICE_BLOCK pDevice)
{
- LM_STATUS CurrentLinkStatus;
- LM_UINT32 Value32;
+ LM_STATUS CurrentLinkStatus;
+ LM_UINT32 Value32;
- /* Assume there is not link first. */
- CurrentLinkStatus = LM_STATUS_LINK_DOWN;
+ /* Assume there is not link first. */
+ CurrentLinkStatus = LM_STATUS_LINK_DOWN;
- /* Disable phy link change attention. */
- REG_WR(pDevice, MacCtrl.MacEvent, 0);
+ /* Disable phy link change attention. */
+ REG_WR (pDevice, MacCtrl.MacEvent, 0);
- /* Clear link change attention. */
- REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED |
- MAC_STATUS_CFG_CHANGED);
+ /* Clear link change attention. */
+ REG_WR (pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED |
+ MAC_STATUS_CFG_CHANGED);
- /* Disable auto-polling for the moment. */
- pDevice->MiMode = 0xc0000;
- REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode);
- MM_Wait(40);
+ /* Disable auto-polling for the moment. */
+ pDevice->MiMode = 0xc0000;
+ REG_WR (pDevice, MacCtrl.MiMode, pDevice->MiMode);
+ MM_Wait (40);
- /* Determine the requested line speed and duplex. */
- pDevice->OldLineSpeed = pDevice->LineSpeed;
- LM_TranslateRequestedMediaType(pDevice->RequestedMediaType,
- &pDevice->MediaType, &pDevice->LineSpeed, &pDevice->DuplexMode);
+ /* Determine the requested line speed and duplex. */
+ pDevice->OldLineSpeed = pDevice->LineSpeed;
+ LM_TranslateRequestedMediaType (pDevice->RequestedMediaType,
+ &pDevice->MediaType,
+ &pDevice->LineSpeed,
+ &pDevice->DuplexMode);
- /* Initialize the phy chip. */
- switch(pDevice->PhyId & PHY_ID_MASK)
- {
+ /* Initialize the phy chip. */
+ switch (pDevice->PhyId & PHY_ID_MASK) {
case PHY_BCM5400_PHY_ID:
case PHY_BCM5401_PHY_ID:
case PHY_BCM5411_PHY_ID:
case PHY_BCM5701_PHY_ID:
case PHY_BCM5703_PHY_ID:
case PHY_BCM5704_PHY_ID:
- CurrentLinkStatus = LM_InitBcm540xPhy(pDevice);
- break;
+ CurrentLinkStatus = LM_InitBcm540xPhy (pDevice);
+ break;
default:
- break;
- }
-
- if(CurrentLinkStatus == LM_STATUS_LINK_SETTING_MISMATCH)
- {
- CurrentLinkStatus = LM_STATUS_LINK_DOWN;
- }
+ break;
+ }
- /* Setup flow control. */
- pDevice->FlowControl = LM_FLOW_CONTROL_NONE;
- if(CurrentLinkStatus == LM_STATUS_LINK_ACTIVE)
- {
- LM_FLOW_CONTROL FlowCap; /* Flow control capability. */
+ if (CurrentLinkStatus == LM_STATUS_LINK_SETTING_MISMATCH) {
+ CurrentLinkStatus = LM_STATUS_LINK_DOWN;
+ }
+
+ /* Setup flow control. */
+ pDevice->FlowControl = LM_FLOW_CONTROL_NONE;
+ if (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) {
+ LM_FLOW_CONTROL FlowCap; /* Flow control capability. */
+
+ FlowCap = LM_FLOW_CONTROL_NONE;
+
+ if (pDevice->DuplexMode == LM_DUPLEX_MODE_FULL) {
+ if (pDevice->DisableAutoNeg == FALSE ||
+ pDevice->RequestedMediaType ==
+ LM_REQUESTED_MEDIA_TYPE_AUTO
+ || pDevice->RequestedMediaType ==
+ LM_REQUESTED_MEDIA_TYPE_UTP_AUTO) {
+ LM_UINT32 ExpectedPhyAd;
+ LM_UINT32 LocalPhyAd;
+ LM_UINT32 RemotePhyAd;
+
+ LM_ReadPhy (pDevice, PHY_AN_AD_REG,
+ &LocalPhyAd);
+ pDevice->advertising = LocalPhyAd;
+ LocalPhyAd &=
+ (PHY_AN_AD_ASYM_PAUSE |
+ PHY_AN_AD_PAUSE_CAPABLE);
+
+ ExpectedPhyAd =
+ GetPhyAdFlowCntrlSettings (pDevice);
+
+ if (LocalPhyAd != ExpectedPhyAd) {
+ CurrentLinkStatus = LM_STATUS_LINK_DOWN;
+ } else {
+ LM_ReadPhy (pDevice,
+ PHY_LINK_PARTNER_ABILITY_REG,
+ &RemotePhyAd);
+
+ LM_SetFlowControl (pDevice, LocalPhyAd,
+ RemotePhyAd);
+ }
+ } else {
+ pDevice->FlowControlCap &=
+ ~LM_FLOW_CONTROL_AUTO_PAUSE;
+ LM_SetFlowControl (pDevice, 0, 0);
+ }
+ }
+ }
- FlowCap = LM_FLOW_CONTROL_NONE;
+ if (CurrentLinkStatus == LM_STATUS_LINK_DOWN) {
+ LM_ForceAutoNeg (pDevice, pDevice->RequestedMediaType);
- if(pDevice->DuplexMode == LM_DUPLEX_MODE_FULL)
- {
- if(pDevice->DisableAutoNeg == FALSE ||
- pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_AUTO ||
- pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_UTP_AUTO)
- {
- LM_UINT32 ExpectedPhyAd;
- LM_UINT32 LocalPhyAd;
- LM_UINT32 RemotePhyAd;
+ /* If we force line speed, we make get link right away. */
+ LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
+ LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
+ if (Value32 & PHY_STATUS_LINK_PASS) {
+ CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
+ }
+ }
- LM_ReadPhy(pDevice, PHY_AN_AD_REG, &LocalPhyAd);
- pDevice->advertising = LocalPhyAd;
- LocalPhyAd &= (PHY_AN_AD_ASYM_PAUSE | PHY_AN_AD_PAUSE_CAPABLE);
+ /* GMII interface. */
+ pDevice->MacMode &= ~MAC_MODE_PORT_MODE_MASK;
+ if (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) {
+ if (pDevice->LineSpeed == LM_LINE_SPEED_100MBPS ||
+ pDevice->LineSpeed == LM_LINE_SPEED_10MBPS) {
+ pDevice->MacMode |= MAC_MODE_PORT_MODE_MII;
+ } else {
+ pDevice->MacMode |= MAC_MODE_PORT_MODE_GMII;
+ }
+ } else {
+ pDevice->MacMode |= MAC_MODE_PORT_MODE_GMII;
+ }
- ExpectedPhyAd = GetPhyAdFlowCntrlSettings(pDevice);
+ /* Set the MAC to operate in the appropriate duplex mode. */
+ pDevice->MacMode &= ~MAC_MODE_HALF_DUPLEX;
+ if (pDevice->DuplexMode == LM_DUPLEX_MODE_HALF) {
+ pDevice->MacMode |= MAC_MODE_HALF_DUPLEX;
+ }
- if(LocalPhyAd != ExpectedPhyAd)
- {
- CurrentLinkStatus = LM_STATUS_LINK_DOWN;
+ /* Set the link polarity bit. */
+ pDevice->MacMode &= ~MAC_MODE_LINK_POLARITY;
+ if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
+ if ((pDevice->LedMode == LED_MODE_LINK10) ||
+ (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE &&
+ pDevice->LineSpeed == LM_LINE_SPEED_10MBPS)) {
+ pDevice->MacMode |= MAC_MODE_LINK_POLARITY;
+ }
+ } else {
+ if (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) {
+ pDevice->MacMode |= MAC_MODE_LINK_POLARITY;
}
- else
- {
- LM_ReadPhy(pDevice, PHY_LINK_PARTNER_ABILITY_REG,
- &RemotePhyAd);
- LM_SetFlowControl(pDevice, LocalPhyAd, RemotePhyAd);
+ /* Set LED mode. */
+ if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
+ T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
+ Value32 = LED_CTRL_PHY_MODE_1;
+ } else {
+ if (pDevice->LedMode == LED_MODE_OUTPUT) {
+ Value32 = LED_CTRL_PHY_MODE_2;
+ } else {
+ Value32 = LED_CTRL_PHY_MODE_1;
+ }
}
- }
- else
- {
- pDevice->FlowControlCap &= ~LM_FLOW_CONTROL_AUTO_PAUSE;
- LM_SetFlowControl(pDevice, 0, 0);
- }
+ REG_WR (pDevice, MacCtrl.LedCtrl, Value32);
}
- }
- if(CurrentLinkStatus == LM_STATUS_LINK_DOWN)
- {
- LM_ForceAutoNeg(pDevice, pDevice->RequestedMediaType);
+ REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode);
- /* If we force line speed, we make get link right away. */
- LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
- LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
- if(Value32 & PHY_STATUS_LINK_PASS)
- {
- CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
+ /* Enable auto polling. */
+ if (pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) {
+ pDevice->MiMode |= MI_MODE_AUTO_POLLING_ENABLE;
+ REG_WR (pDevice, MacCtrl.MiMode, pDevice->MiMode);
}
- }
- /* GMII interface. */
- pDevice->MacMode &= ~MAC_MODE_PORT_MODE_MASK;
- if(CurrentLinkStatus == LM_STATUS_LINK_ACTIVE)
- {
- if(pDevice->LineSpeed == LM_LINE_SPEED_100MBPS ||
- pDevice->LineSpeed == LM_LINE_SPEED_10MBPS)
- {
- pDevice->MacMode |= MAC_MODE_PORT_MODE_MII;
+ /* Enable phy link change attention. */
+ if (pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT) {
+ REG_WR (pDevice, MacCtrl.MacEvent,
+ MAC_EVENT_ENABLE_MI_INTERRUPT);
+ } else {
+ REG_WR (pDevice, MacCtrl.MacEvent,
+ MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN);
}
- else
- {
- pDevice->MacMode |= MAC_MODE_PORT_MODE_GMII;
- }
- }
- else {
- pDevice->MacMode |= MAC_MODE_PORT_MODE_GMII;
- }
-
- /* Set the MAC to operate in the appropriate duplex mode. */
- pDevice->MacMode &= ~MAC_MODE_HALF_DUPLEX;
- if(pDevice->DuplexMode == LM_DUPLEX_MODE_HALF)
- {
- pDevice->MacMode |= MAC_MODE_HALF_DUPLEX;
- }
-
- /* Set the link polarity bit. */
- pDevice->MacMode &= ~MAC_MODE_LINK_POLARITY;
- if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
- {
- if((pDevice->LedMode == LED_MODE_LINK10) ||
- (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE &&
- pDevice->LineSpeed == LM_LINE_SPEED_10MBPS))
- {
- pDevice->MacMode |= MAC_MODE_LINK_POLARITY;
- }
- }
- else
- {
- if (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE)
- {
- pDevice->MacMode |= MAC_MODE_LINK_POLARITY;
+ if ((T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) &&
+ (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) &&
+ (pDevice->LineSpeed == LM_LINE_SPEED_1000MBPS) &&
+ (((pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) &&
+ (pDevice->PciState & T3_PCI_STATE_BUS_SPEED_HIGH)) ||
+ !(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE))) {
+ MM_Wait (120);
+ REG_WR (pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED |
+ MAC_STATUS_CFG_CHANGED);
+ MEM_WR_OFFSET (pDevice, T3_FIRMWARE_MAILBOX,
+ T3_MAGIC_NUM_DISABLE_DMAW_ON_LINK_CHANGE);
}
- /* Set LED mode. */
- if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
- T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)
- {
- Value32 = LED_CTRL_PHY_MODE_1;
+ /* Indicate link status. */
+ if (pDevice->LinkStatus != CurrentLinkStatus) {
+ pDevice->LinkStatus = CurrentLinkStatus;
+ MM_IndicateStatus (pDevice, CurrentLinkStatus);
}
- else
- {
- if(pDevice->LedMode == LED_MODE_OUTPUT)
- {
- Value32 = LED_CTRL_PHY_MODE_2;
- }
- else
- {
- Value32 = LED_CTRL_PHY_MODE_1;
- }
- }
- REG_WR(pDevice, MacCtrl.LedCtrl, Value32);
- }
-
- REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
-
- /* Enable auto polling. */
- if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING)
- {
- pDevice->MiMode |= MI_MODE_AUTO_POLLING_ENABLE;
- REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode);
- }
-
- /* Enable phy link change attention. */
- if(pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT)
- {
- REG_WR(pDevice, MacCtrl.MacEvent, MAC_EVENT_ENABLE_MI_INTERRUPT);
- }
- else
- {
- REG_WR(pDevice, MacCtrl.MacEvent,
- MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN);
- }
- if ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) &&
- (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) &&
- (pDevice->LineSpeed == LM_LINE_SPEED_1000MBPS) &&
- (((pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) &&
- (pDevice->PciState & T3_PCI_STATE_BUS_SPEED_HIGH)) ||
- !(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)))
- {
- MM_Wait(120);
- REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED |
- MAC_STATUS_CFG_CHANGED);
- MEM_WR_OFFSET(pDevice, T3_FIRMWARE_MAILBOX,
- T3_MAGIC_NUM_DISABLE_DMAW_ON_LINK_CHANGE);
- }
-
- /* Indicate link status. */
- if (pDevice->LinkStatus != CurrentLinkStatus) {
- pDevice->LinkStatus = CurrentLinkStatus;
- MM_IndicateStatus(pDevice, CurrentLinkStatus);
- }
-
- return LM_STATUS_SUCCESS;
-} /* LM_SetupCopperPhy */
+
+ return LM_STATUS_SUCCESS;
+} /* LM_SetupCopperPhy */
/******************************************************************************/
/* Description: */
/* */
/* Return: */
/******************************************************************************/
-LM_STATUS
-LM_SetupPhy(
- PLM_DEVICE_BLOCK pDevice)
+LM_STATUS LM_SetupPhy (PLM_DEVICE_BLOCK pDevice)
{
- LM_STATUS LmStatus;
- LM_UINT32 Value32;
+ LM_STATUS LmStatus;
+ LM_UINT32 Value32;
#if INCLUDE_TBI_SUPPORT
- if(pDevice->EnableTbi)
- {
- LmStatus = LM_SetupFiberPhy(pDevice);
- }
- else
-#endif /* INCLUDE_TBI_SUPPORT */
- {
- LmStatus = LM_SetupCopperPhy(pDevice);
- }
- if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0)
- {
- if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE))
- {
- Value32 = REG_RD(pDevice, PciCfg.PciState);
- REG_WR(pDevice, PciCfg.PciState,
- Value32 | T3_PCI_STATE_RETRY_SAME_DMA);
- }
- }
- if ((pDevice->LineSpeed == LM_LINE_SPEED_1000MBPS) &&
- (pDevice->DuplexMode == LM_DUPLEX_MODE_HALF))
- {
- REG_WR(pDevice, MacCtrl.TxLengths, 0x26ff);
- }
- else
- {
- REG_WR(pDevice, MacCtrl.TxLengths, 0x2620);
- }
-
- return LmStatus;
+ if (pDevice->EnableTbi) {
+ LmStatus = LM_SetupFiberPhy (pDevice);
+ } else
+#endif /* INCLUDE_TBI_SUPPORT */
+ {
+ LmStatus = LM_SetupCopperPhy (pDevice);
+ }
+ if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0) {
+ if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)) {
+ Value32 = REG_RD (pDevice, PciCfg.PciState);
+ REG_WR (pDevice, PciCfg.PciState,
+ Value32 | T3_PCI_STATE_RETRY_SAME_DMA);
+ }
+ }
+ if ((pDevice->LineSpeed == LM_LINE_SPEED_1000MBPS) &&
+ (pDevice->DuplexMode == LM_DUPLEX_MODE_HALF)) {
+ REG_WR (pDevice, MacCtrl.TxLengths, 0x26ff);
+ } else {
+ REG_WR (pDevice, MacCtrl.TxLengths, 0x2620);
+ }
+
+ return LmStatus;
}
/******************************************************************************/
@@ -5232,55 +4830,47 @@ LM_SetupPhy(
/* Return: */
/******************************************************************************/
LM_VOID
-LM_ReadPhy(
-PLM_DEVICE_BLOCK pDevice,
-LM_UINT32 PhyReg,
-PLM_UINT32 pData32) {
- LM_UINT32 Value32;
- LM_UINT32 j;
+LM_ReadPhy (PLM_DEVICE_BLOCK pDevice, LM_UINT32 PhyReg, PLM_UINT32 pData32)
+{
+ LM_UINT32 Value32;
+ LM_UINT32 j;
- if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING)
- {
- REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode &
- ~MI_MODE_AUTO_POLLING_ENABLE);
- MM_Wait(40);
- }
+ if (pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) {
+ REG_WR (pDevice, MacCtrl.MiMode, pDevice->MiMode &
+ ~MI_MODE_AUTO_POLLING_ENABLE);
+ MM_Wait (40);
+ }
- Value32 = (pDevice->PhyAddr << MI_COM_FIRST_PHY_ADDR_BIT) |
- ((PhyReg & MI_COM_PHY_REG_ADDR_MASK) << MI_COM_FIRST_PHY_REG_ADDR_BIT) |
- MI_COM_CMD_READ | MI_COM_START;
+ Value32 = (pDevice->PhyAddr << MI_COM_FIRST_PHY_ADDR_BIT) |
+ ((PhyReg & MI_COM_PHY_REG_ADDR_MASK) <<
+ MI_COM_FIRST_PHY_REG_ADDR_BIT) | MI_COM_CMD_READ | MI_COM_START;
- REG_WR(pDevice, MacCtrl.MiCom, Value32);
+ REG_WR (pDevice, MacCtrl.MiCom, Value32);
- for(j = 0; j < 20; j++)
- {
- MM_Wait(25);
+ for (j = 0; j < 20; j++) {
+ MM_Wait (25);
- Value32 = REG_RD(pDevice, MacCtrl.MiCom);
+ Value32 = REG_RD (pDevice, MacCtrl.MiCom);
- if(!(Value32 & MI_COM_BUSY))
- {
- MM_Wait(5);
- Value32 = REG_RD(pDevice, MacCtrl.MiCom);
- Value32 &= MI_COM_PHY_DATA_MASK;
- break;
+ if (!(Value32 & MI_COM_BUSY)) {
+ MM_Wait (5);
+ Value32 = REG_RD (pDevice, MacCtrl.MiCom);
+ Value32 &= MI_COM_PHY_DATA_MASK;
+ break;
+ }
}
- }
- if(Value32 & MI_COM_BUSY)
- {
- Value32 = 0;
- }
-
- *pData32 = Value32;
+ if (Value32 & MI_COM_BUSY) {
+ Value32 = 0;
+ }
- if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING)
- {
- REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode);
- MM_Wait(40);
- }
-} /* LM_ReadPhy */
+ *pData32 = Value32;
+ if (pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) {
+ REG_WR (pDevice, MacCtrl.MiMode, pDevice->MiMode);
+ MM_Wait (40);
+ }
+} /* LM_ReadPhy */
/******************************************************************************/
/* Description: */
@@ -5288,341 +4878,296 @@ PLM_UINT32 pData32) {
/* Return: */
/******************************************************************************/
LM_VOID
-LM_WritePhy(
-PLM_DEVICE_BLOCK pDevice,
-LM_UINT32 PhyReg,
-LM_UINT32 Data32) {
- LM_UINT32 Value32;
- LM_UINT32 j;
+LM_WritePhy (PLM_DEVICE_BLOCK pDevice, LM_UINT32 PhyReg, LM_UINT32 Data32)
+{
+ LM_UINT32 Value32;
+ LM_UINT32 j;
- if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING)
- {
- REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode &
- ~MI_MODE_AUTO_POLLING_ENABLE);
- MM_Wait(40);
- }
+ if (pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) {
+ REG_WR (pDevice, MacCtrl.MiMode, pDevice->MiMode &
+ ~MI_MODE_AUTO_POLLING_ENABLE);
+ MM_Wait (40);
+ }
- Value32 = (pDevice->PhyAddr << MI_COM_FIRST_PHY_ADDR_BIT) |
- ((PhyReg & MI_COM_PHY_REG_ADDR_MASK) << MI_COM_FIRST_PHY_REG_ADDR_BIT) |
- (Data32 & MI_COM_PHY_DATA_MASK) | MI_COM_CMD_WRITE | MI_COM_START;
+ Value32 = (pDevice->PhyAddr << MI_COM_FIRST_PHY_ADDR_BIT) |
+ ((PhyReg & MI_COM_PHY_REG_ADDR_MASK) <<
+ MI_COM_FIRST_PHY_REG_ADDR_BIT) | (Data32 & MI_COM_PHY_DATA_MASK) |
+ MI_COM_CMD_WRITE | MI_COM_START;
- REG_WR(pDevice, MacCtrl.MiCom, Value32);
+ REG_WR (pDevice, MacCtrl.MiCom, Value32);
- for(j = 0; j < 20; j++)
- {
- MM_Wait(25);
+ for (j = 0; j < 20; j++) {
+ MM_Wait (25);
- Value32 = REG_RD(pDevice, MacCtrl.MiCom);
+ Value32 = REG_RD (pDevice, MacCtrl.MiCom);
- if(!(Value32 & MI_COM_BUSY))
- {
- MM_Wait(5);
- break;
+ if (!(Value32 & MI_COM_BUSY)) {
+ MM_Wait (5);
+ break;
+ }
}
- }
-
- if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING)
- {
- REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode);
- MM_Wait(40);
- }
-} /* LM_WritePhy */
+ if (pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) {
+ REG_WR (pDevice, MacCtrl.MiMode, pDevice->MiMode);
+ MM_Wait (40);
+ }
+} /* LM_WritePhy */
/******************************************************************************/
/* Description: */
/* */
/* Return: */
/******************************************************************************/
-LM_STATUS
-LM_SetPowerState(
-PLM_DEVICE_BLOCK pDevice,
-LM_POWER_STATE PowerLevel) {
- LM_UINT32 PmeSupport;
- LM_UINT32 Value32;
- LM_UINT32 PmCtrl;
+LM_STATUS LM_SetPowerState (PLM_DEVICE_BLOCK pDevice, LM_POWER_STATE PowerLevel)
+{
+ LM_UINT32 PmeSupport;
+ LM_UINT32 Value32;
+ LM_UINT32 PmCtrl;
- /* make sureindirect accesses are enabled*/
- MM_WriteConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, pDevice->MiscHostCtrl);
+ /* make sureindirect accesses are enabled */
+ MM_WriteConfig32 (pDevice, T3_PCI_MISC_HOST_CTRL_REG,
+ pDevice->MiscHostCtrl);
- /* Clear the PME_ASSERT bit and the power state bits. Also enable */
- /* the PME bit. */
- MM_ReadConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, &PmCtrl);
+ /* Clear the PME_ASSERT bit and the power state bits. Also enable */
+ /* the PME bit. */
+ MM_ReadConfig32 (pDevice, T3_PCI_PM_STATUS_CTRL_REG, &PmCtrl);
- PmCtrl |= T3_PM_PME_ASSERTED;
- PmCtrl &= ~T3_PM_POWER_STATE_MASK;
+ PmCtrl |= T3_PM_PME_ASSERTED;
+ PmCtrl &= ~T3_PM_POWER_STATE_MASK;
- /* Set the appropriate power state. */
- if(PowerLevel == LM_POWER_STATE_D0)
- {
+ /* Set the appropriate power state. */
+ if (PowerLevel == LM_POWER_STATE_D0) {
- /* Bring the card out of low power mode. */
- PmCtrl |= T3_PM_POWER_STATE_D0;
- MM_WriteConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, PmCtrl);
+ /* Bring the card out of low power mode. */
+ PmCtrl |= T3_PM_POWER_STATE_D0;
+ MM_WriteConfig32 (pDevice, T3_PCI_PM_STATUS_CTRL_REG, PmCtrl);
- REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl);
- MM_Wait (40);
-#if 0 /* Bugfix by jmb...can't call WritePhy here because pDevice not fully initialized */
- LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x02);
+ REG_WR (pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl);
+ MM_Wait (40);
+#if 0 /* Bugfix by jmb...can't call WritePhy here because pDevice not fully initialized */
+ LM_WritePhy (pDevice, BCM5401_AUX_CTRL, 0x02);
#endif
- return LM_STATUS_SUCCESS;
- }
- else if(PowerLevel == LM_POWER_STATE_D1)
- {
- PmCtrl |= T3_PM_POWER_STATE_D1;
- }
- else if(PowerLevel == LM_POWER_STATE_D2)
- {
- PmCtrl |= T3_PM_POWER_STATE_D2;
- }
- else if(PowerLevel == LM_POWER_STATE_D3)
- {
- PmCtrl |= T3_PM_POWER_STATE_D3;
- }
- else
- {
- return LM_STATUS_FAILURE;
- }
- PmCtrl |= T3_PM_PME_ENABLE;
-
- /* Mask out all interrupts so LM_SetupPhy won't be called while we are */
- /* setting new line speed. */
- Value32 = REG_RD(pDevice, PciCfg.MiscHostCtrl);
- REG_WR(pDevice, PciCfg.MiscHostCtrl, Value32 | MISC_HOST_CTRL_MASK_PCI_INT);
-
- if(!pDevice->RestoreOnWakeUp)
- {
- pDevice->RestoreOnWakeUp = TRUE;
- pDevice->WakeUpDisableAutoNeg = pDevice->DisableAutoNeg;
- pDevice->WakeUpRequestedMediaType = pDevice->RequestedMediaType;
- }
-
- /* Force auto-negotiation to 10 line speed. */
- pDevice->DisableAutoNeg = FALSE;
- pDevice->RequestedMediaType = LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS;
- LM_SetupPhy(pDevice);
-
- /* Put the driver in the initial state, and go through the power down */
- /* sequence. */
- LM_Halt(pDevice);
-
- MM_ReadConfig32(pDevice, T3_PCI_PM_CAP_REG, &PmeSupport);
-
- if (pDevice->WakeUpModeCap != LM_WAKE_UP_MODE_NONE)
- {
-
- /* Enable WOL. */
- LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x5a);
- MM_Wait(40);
-
- /* Set LED mode. */
- if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
- T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)
- {
- Value32 = LED_CTRL_PHY_MODE_1;
- }
- else
- {
- if(pDevice->LedMode == LED_MODE_OUTPUT)
- {
- Value32 = LED_CTRL_PHY_MODE_2;
- }
- else
- {
- Value32 = LED_CTRL_PHY_MODE_1;
- }
+ return LM_STATUS_SUCCESS;
+ } else if (PowerLevel == LM_POWER_STATE_D1) {
+ PmCtrl |= T3_PM_POWER_STATE_D1;
+ } else if (PowerLevel == LM_POWER_STATE_D2) {
+ PmCtrl |= T3_PM_POWER_STATE_D2;
+ } else if (PowerLevel == LM_POWER_STATE_D3) {
+ PmCtrl |= T3_PM_POWER_STATE_D3;
+ } else {
+ return LM_STATUS_FAILURE;
}
+ PmCtrl |= T3_PM_PME_ENABLE;
- Value32 = MAC_MODE_PORT_MODE_MII;
- if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
- {
- if(pDevice->LedMode == LED_MODE_LINK10 ||
- pDevice->WolSpeed == WOL_SPEED_10MB)
- {
- Value32 |= MAC_MODE_LINK_POLARITY;
- }
- }
- else
- {
- Value32 |= MAC_MODE_LINK_POLARITY;
- }
- REG_WR(pDevice, MacCtrl.Mode, Value32);
- MM_Wait(40); MM_Wait(40); MM_Wait(40);
+ /* Mask out all interrupts so LM_SetupPhy won't be called while we are */
+ /* setting new line speed. */
+ Value32 = REG_RD (pDevice, PciCfg.MiscHostCtrl);
+ REG_WR (pDevice, PciCfg.MiscHostCtrl,
+ Value32 | MISC_HOST_CTRL_MASK_PCI_INT);
- /* Always enable magic packet wake-up if we have vaux. */
- if((PmeSupport & T3_PCI_PM_CAP_PME_D3COLD) &&
- (pDevice->WakeUpModeCap & LM_WAKE_UP_MODE_MAGIC_PACKET))
- {
- Value32 |= MAC_MODE_DETECT_MAGIC_PACKET_ENABLE;
+ if (!pDevice->RestoreOnWakeUp) {
+ pDevice->RestoreOnWakeUp = TRUE;
+ pDevice->WakeUpDisableAutoNeg = pDevice->DisableAutoNeg;
+ pDevice->WakeUpRequestedMediaType = pDevice->RequestedMediaType;
}
- REG_WR(pDevice, MacCtrl.Mode, Value32);
+ /* Force auto-negotiation to 10 line speed. */
+ pDevice->DisableAutoNeg = FALSE;
+ pDevice->RequestedMediaType = LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS;
+ LM_SetupPhy (pDevice);
- /* Enable the receiver. */
- REG_WR(pDevice, MacCtrl.RxMode, RX_MODE_ENABLE);
- }
-
- /* Disable tx/rx clocks, and seletect an alternate clock. */
- if(pDevice->WolSpeed == WOL_SPEED_100MB)
- {
- if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
- T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)
- {
- Value32 = T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK |
- T3_PCI_SELECT_ALTERNATE_CLOCK;
- }
- else
- {
- Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK;
- }
- REG_WR(pDevice, PciCfg.ClockCtrl, Value32);
+ /* Put the driver in the initial state, and go through the power down */
+ /* sequence. */
+ LM_Halt (pDevice);
- MM_Wait(40);
+ MM_ReadConfig32 (pDevice, T3_PCI_PM_CAP_REG, &PmeSupport);
- if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
- T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)
- {
- Value32 = T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK |
- T3_PCI_SELECT_ALTERNATE_CLOCK | T3_PCI_44MHZ_CORE_CLOCK;
- }
- else
- {
- Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK |
- T3_PCI_44MHZ_CORE_CLOCK;
- }
+ if (pDevice->WakeUpModeCap != LM_WAKE_UP_MODE_NONE) {
- REG_WR(pDevice, PciCfg.ClockCtrl, Value32);
+ /* Enable WOL. */
+ LM_WritePhy (pDevice, BCM5401_AUX_CTRL, 0x5a);
+ MM_Wait (40);
- MM_Wait(40);
+ /* Set LED mode. */
+ if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
+ T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
+ Value32 = LED_CTRL_PHY_MODE_1;
+ } else {
+ if (pDevice->LedMode == LED_MODE_OUTPUT) {
+ Value32 = LED_CTRL_PHY_MODE_2;
+ } else {
+ Value32 = LED_CTRL_PHY_MODE_1;
+ }
+ }
- if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
- T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)
- {
- Value32 = T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK |
- T3_PCI_44MHZ_CORE_CLOCK;
- }
- else
- {
- Value32 = T3_PCI_44MHZ_CORE_CLOCK;
- }
+ Value32 = MAC_MODE_PORT_MODE_MII;
+ if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
+ if (pDevice->LedMode == LED_MODE_LINK10 ||
+ pDevice->WolSpeed == WOL_SPEED_10MB) {
+ Value32 |= MAC_MODE_LINK_POLARITY;
+ }
+ } else {
+ Value32 |= MAC_MODE_LINK_POLARITY;
+ }
+ REG_WR (pDevice, MacCtrl.Mode, Value32);
+ MM_Wait (40);
+ MM_Wait (40);
+ MM_Wait (40);
+
+ /* Always enable magic packet wake-up if we have vaux. */
+ if ((PmeSupport & T3_PCI_PM_CAP_PME_D3COLD) &&
+ (pDevice->WakeUpModeCap & LM_WAKE_UP_MODE_MAGIC_PACKET)) {
+ Value32 |= MAC_MODE_DETECT_MAGIC_PACKET_ENABLE;
+ }
- REG_WR(pDevice, PciCfg.ClockCtrl, Value32);
- }
- else
- {
- if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
- T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)
- {
- Value32 = T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK |
- T3_PCI_SELECT_ALTERNATE_CLOCK |
- T3_PCI_POWER_DOWN_PCI_PLL133;
- }
- else
- {
- Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK |
- T3_PCI_POWER_DOWN_PCI_PLL133;
+ REG_WR (pDevice, MacCtrl.Mode, Value32);
+
+ /* Enable the receiver. */
+ REG_WR (pDevice, MacCtrl.RxMode, RX_MODE_ENABLE);
}
- REG_WR(pDevice, PciCfg.ClockCtrl, Value32);
- }
+ /* Disable tx/rx clocks, and seletect an alternate clock. */
+ if (pDevice->WolSpeed == WOL_SPEED_100MB) {
+ if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
+ T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
+ Value32 =
+ T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK |
+ T3_PCI_SELECT_ALTERNATE_CLOCK;
+ } else {
+ Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK;
+ }
+ REG_WR (pDevice, PciCfg.ClockCtrl, Value32);
+
+ MM_Wait (40);
+
+ if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
+ T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
+ Value32 =
+ T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK |
+ T3_PCI_SELECT_ALTERNATE_CLOCK |
+ T3_PCI_44MHZ_CORE_CLOCK;
+ } else {
+ Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK |
+ T3_PCI_44MHZ_CORE_CLOCK;
+ }
- MM_Wait(40);
+ REG_WR (pDevice, PciCfg.ClockCtrl, Value32);
- if(!pDevice->EepromWp && (pDevice->WakeUpModeCap != LM_WAKE_UP_MODE_NONE))
- {
- /* Switch adapter to auxilliary power. */
- if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
- T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)
- {
- /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 0. */
- REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
- GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
- GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
- GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
- GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 |
- GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1);
- MM_Wait(40);
+ MM_Wait (40);
+
+ if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
+ T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
+ Value32 =
+ T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK |
+ T3_PCI_44MHZ_CORE_CLOCK;
+ } else {
+ Value32 = T3_PCI_44MHZ_CORE_CLOCK;
+ }
+
+ REG_WR (pDevice, PciCfg.ClockCtrl, Value32);
+ } else {
+ if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
+ T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
+ Value32 =
+ T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK |
+ T3_PCI_SELECT_ALTERNATE_CLOCK |
+ T3_PCI_POWER_DOWN_PCI_PLL133;
+ } else {
+ Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK |
+ T3_PCI_POWER_DOWN_PCI_PLL133;
+ }
+
+ REG_WR (pDevice, PciCfg.ClockCtrl, Value32);
}
- else
- {
- /* GPIO0 = 0, GPIO1 = 1, GPIO2 = 1. */
- REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
- GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
- GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
- GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
- GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 |
- GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2);
- MM_Wait(40);
-
- /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 1. */
- REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
- GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
- GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
- GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
- GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 |
- GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 |
- GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2);
- MM_Wait(40);
-
- /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 0. */
- REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
- GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
- GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
- GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
- GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 |
- GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1);
- MM_Wait(40);
- }
- }
-
- /* Set the phy to low power mode. */
- /* Put the the hardware in low power mode. */
- MM_WriteConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, PmCtrl);
-
- return LM_STATUS_SUCCESS;
-} /* LM_SetPowerState */
+ MM_Wait (40);
+
+ if (!pDevice->EepromWp
+ && (pDevice->WakeUpModeCap != LM_WAKE_UP_MODE_NONE)) {
+ /* Switch adapter to auxilliary power. */
+ if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
+ T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
+ /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 0. */
+ REG_WR (pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
+ GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
+ GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
+ GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
+ GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 |
+ GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1);
+ MM_Wait (40);
+ } else {
+ /* GPIO0 = 0, GPIO1 = 1, GPIO2 = 1. */
+ REG_WR (pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
+ GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
+ GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
+ GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
+ GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 |
+ GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2);
+ MM_Wait (40);
+
+ /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 1. */
+ REG_WR (pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
+ GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
+ GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
+ GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
+ GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 |
+ GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 |
+ GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2);
+ MM_Wait (40);
+
+ /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 0. */
+ REG_WR (pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
+ GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
+ GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
+ GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
+ GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 |
+ GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1);
+ MM_Wait (40);
+ }
+ }
+
+ /* Set the phy to low power mode. */
+ /* Put the the hardware in low power mode. */
+ MM_WriteConfig32 (pDevice, T3_PCI_PM_STATUS_CTRL_REG, PmCtrl);
+
+ return LM_STATUS_SUCCESS;
+} /* LM_SetPowerState */
/******************************************************************************/
/* Description: */
/* */
/* Return: */
/******************************************************************************/
-static LM_UINT32
-GetPhyAdFlowCntrlSettings(
- PLM_DEVICE_BLOCK pDevice)
+static LM_UINT32 GetPhyAdFlowCntrlSettings (PLM_DEVICE_BLOCK pDevice)
{
- LM_UINT32 Value32;
-
- Value32 = 0;
-
- /* Auto negotiation flow control only when autonegotiation is enabled. */
- if(pDevice->DisableAutoNeg == FALSE ||
- pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_AUTO ||
- pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_UTP_AUTO)
- {
- /* Please refer to Table 28B-3 of the 802.3ab-1999 spec. */
- if((pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE) ||
- ((pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE) &&
- (pDevice->FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE)))
- {
- Value32 |= PHY_AN_AD_PAUSE_CAPABLE;
- }
- else if(pDevice->FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE)
- {
- Value32 |= PHY_AN_AD_ASYM_PAUSE;
- }
- else if(pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE)
- {
- Value32 |= PHY_AN_AD_PAUSE_CAPABLE | PHY_AN_AD_ASYM_PAUSE;
+ LM_UINT32 Value32;
+
+ Value32 = 0;
+
+ /* Auto negotiation flow control only when autonegotiation is enabled. */
+ if (pDevice->DisableAutoNeg == FALSE ||
+ pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_AUTO ||
+ pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_UTP_AUTO) {
+ /* Please refer to Table 28B-3 of the 802.3ab-1999 spec. */
+ if ((pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE) ||
+ ((pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE)
+ && (pDevice->
+ FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE))) {
+ Value32 |= PHY_AN_AD_PAUSE_CAPABLE;
+ } else if (pDevice->
+ FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE) {
+ Value32 |= PHY_AN_AD_ASYM_PAUSE;
+ } else if (pDevice->
+ FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE) {
+ Value32 |=
+ PHY_AN_AD_PAUSE_CAPABLE | PHY_AN_AD_ASYM_PAUSE;
+ }
}
- }
- return Value32;
+ return Value32;
}
-
/******************************************************************************/
/* Description: */
/* */
@@ -5632,195 +5177,169 @@ GetPhyAdFlowCntrlSettings(
/* */
/******************************************************************************/
static LM_STATUS
-LM_ForceAutoNegBcm540xPhy(
-PLM_DEVICE_BLOCK pDevice,
-LM_REQUESTED_MEDIA_TYPE RequestedMediaType)
+LM_ForceAutoNegBcm540xPhy (PLM_DEVICE_BLOCK pDevice,
+ LM_REQUESTED_MEDIA_TYPE RequestedMediaType)
{
- LM_MEDIA_TYPE MediaType;
- LM_LINE_SPEED LineSpeed;
- LM_DUPLEX_MODE DuplexMode;
- LM_UINT32 NewPhyCtrl;
- LM_UINT32 Value32;
- LM_UINT32 Cnt;
-
- /* Get the interface type, line speed, and duplex mode. */
- LM_TranslateRequestedMediaType(RequestedMediaType, &MediaType, &LineSpeed,
- &DuplexMode);
-
- if (pDevice->RestoreOnWakeUp)
- {
- LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, 0);
- pDevice->advertising1000 = 0;
- Value32 = PHY_AN_AD_10BASET_FULL | PHY_AN_AD_10BASET_HALF;
- if (pDevice->WolSpeed == WOL_SPEED_100MB)
- {
- Value32 |= PHY_AN_AD_100BASETX_FULL | PHY_AN_AD_100BASETX_HALF;
- }
- Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD;
- Value32 |= GetPhyAdFlowCntrlSettings(pDevice);
- LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32);
- pDevice->advertising = Value32;
- }
- /* Setup the auto-negotiation advertisement register. */
- else if(LineSpeed == LM_LINE_SPEED_UNKNOWN)
- {
- /* Setup the 10/100 Mbps auto-negotiation advertisement register. */
- Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD |
- PHY_AN_AD_10BASET_HALF | PHY_AN_AD_10BASET_FULL |
- PHY_AN_AD_100BASETX_FULL | PHY_AN_AD_100BASETX_HALF;
- Value32 |= GetPhyAdFlowCntrlSettings(pDevice);
-
- LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32);
- pDevice->advertising = Value32;
-
- /* Advertise 1000Mbps */
- Value32 = BCM540X_AN_AD_1000BASET_HALF | BCM540X_AN_AD_1000BASET_FULL;
+ LM_MEDIA_TYPE MediaType;
+ LM_LINE_SPEED LineSpeed;
+ LM_DUPLEX_MODE DuplexMode;
+ LM_UINT32 NewPhyCtrl;
+ LM_UINT32 Value32;
+ LM_UINT32 Cnt;
+
+ /* Get the interface type, line speed, and duplex mode. */
+ LM_TranslateRequestedMediaType (RequestedMediaType, &MediaType,
+ &LineSpeed, &DuplexMode);
+
+ if (pDevice->RestoreOnWakeUp) {
+ LM_WritePhy (pDevice, BCM540X_1000BASET_CTRL_REG, 0);
+ pDevice->advertising1000 = 0;
+ Value32 = PHY_AN_AD_10BASET_FULL | PHY_AN_AD_10BASET_HALF;
+ if (pDevice->WolSpeed == WOL_SPEED_100MB) {
+ Value32 |=
+ PHY_AN_AD_100BASETX_FULL | PHY_AN_AD_100BASETX_HALF;
+ }
+ Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD;
+ Value32 |= GetPhyAdFlowCntrlSettings (pDevice);
+ LM_WritePhy (pDevice, PHY_AN_AD_REG, Value32);
+ pDevice->advertising = Value32;
+ }
+ /* Setup the auto-negotiation advertisement register. */
+ else if (LineSpeed == LM_LINE_SPEED_UNKNOWN) {
+ /* Setup the 10/100 Mbps auto-negotiation advertisement register. */
+ Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD |
+ PHY_AN_AD_10BASET_HALF | PHY_AN_AD_10BASET_FULL |
+ PHY_AN_AD_100BASETX_FULL | PHY_AN_AD_100BASETX_HALF;
+ Value32 |= GetPhyAdFlowCntrlSettings (pDevice);
+
+ LM_WritePhy (pDevice, PHY_AN_AD_REG, Value32);
+ pDevice->advertising = Value32;
+
+ /* Advertise 1000Mbps */
+ Value32 =
+ BCM540X_AN_AD_1000BASET_HALF | BCM540X_AN_AD_1000BASET_FULL;
#if INCLUDE_5701_AX_FIX
- /* Bug: workaround for CRC error in gigabit mode when we are in */
- /* slave mode. This will force the PHY to operate in */
- /* master mode. */
- if(pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
- pDevice->ChipRevId == T3_CHIP_ID_5701_B0)
- {
- Value32 |= BCM540X_CONFIG_AS_MASTER |
- BCM540X_ENABLE_CONFIG_AS_MASTER;
- }
+ /* Bug: workaround for CRC error in gigabit mode when we are in */
+ /* slave mode. This will force the PHY to operate in */
+ /* master mode. */
+ if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
+ pDevice->ChipRevId == T3_CHIP_ID_5701_B0) {
+ Value32 |= BCM540X_CONFIG_AS_MASTER |
+ BCM540X_ENABLE_CONFIG_AS_MASTER;
+ }
#endif
- LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, Value32);
- pDevice->advertising1000 = Value32;
- }
- else
- {
- if(LineSpeed == LM_LINE_SPEED_1000MBPS)
- {
- Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD;
- Value32 |= GetPhyAdFlowCntrlSettings(pDevice);
+ LM_WritePhy (pDevice, BCM540X_1000BASET_CTRL_REG, Value32);
+ pDevice->advertising1000 = Value32;
+ } else {
+ if (LineSpeed == LM_LINE_SPEED_1000MBPS) {
+ Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD;
+ Value32 |= GetPhyAdFlowCntrlSettings (pDevice);
+
+ LM_WritePhy (pDevice, PHY_AN_AD_REG, Value32);
+ pDevice->advertising = Value32;
+
+ if (DuplexMode != LM_DUPLEX_MODE_FULL) {
+ Value32 = BCM540X_AN_AD_1000BASET_HALF;
+ } else {
+ Value32 = BCM540X_AN_AD_1000BASET_FULL;
+ }
- LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32);
- pDevice->advertising = Value32;
+ LM_WritePhy (pDevice, BCM540X_1000BASET_CTRL_REG,
+ Value32);
+ pDevice->advertising1000 = Value32;
+ } else if (LineSpeed == LM_LINE_SPEED_100MBPS) {
+ LM_WritePhy (pDevice, BCM540X_1000BASET_CTRL_REG, 0);
+ pDevice->advertising1000 = 0;
+
+ if (DuplexMode != LM_DUPLEX_MODE_FULL) {
+ Value32 = PHY_AN_AD_100BASETX_HALF;
+ } else {
+ Value32 = PHY_AN_AD_100BASETX_FULL;
+ }
- if(DuplexMode != LM_DUPLEX_MODE_FULL)
- {
- Value32 = BCM540X_AN_AD_1000BASET_HALF;
- }
- else
- {
- Value32 = BCM540X_AN_AD_1000BASET_FULL;
- }
+ Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD;
+ Value32 |= GetPhyAdFlowCntrlSettings (pDevice);
- LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, Value32);
- pDevice->advertising1000 = Value32;
- }
- else if(LineSpeed == LM_LINE_SPEED_100MBPS)
- {
- LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, 0);
- pDevice->advertising1000 = 0;
+ LM_WritePhy (pDevice, PHY_AN_AD_REG, Value32);
+ pDevice->advertising = Value32;
+ } else if (LineSpeed == LM_LINE_SPEED_10MBPS) {
+ LM_WritePhy (pDevice, BCM540X_1000BASET_CTRL_REG, 0);
+ pDevice->advertising1000 = 0;
- if(DuplexMode != LM_DUPLEX_MODE_FULL)
- {
- Value32 = PHY_AN_AD_100BASETX_HALF;
- }
- else
- {
- Value32 = PHY_AN_AD_100BASETX_FULL;
- }
+ if (DuplexMode != LM_DUPLEX_MODE_FULL) {
+ Value32 = PHY_AN_AD_10BASET_HALF;
+ } else {
+ Value32 = PHY_AN_AD_10BASET_FULL;
+ }
- Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD;
- Value32 |= GetPhyAdFlowCntrlSettings(pDevice);
+ Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD;
+ Value32 |= GetPhyAdFlowCntrlSettings (pDevice);
- LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32);
- pDevice->advertising = Value32;
- }
- else if(LineSpeed == LM_LINE_SPEED_10MBPS)
- {
- LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, 0);
- pDevice->advertising1000 = 0;
-
- if(DuplexMode != LM_DUPLEX_MODE_FULL)
- {
- Value32 = PHY_AN_AD_10BASET_HALF;
- }
- else
- {
- Value32 = PHY_AN_AD_10BASET_FULL;
- }
-
- Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD;
- Value32 |= GetPhyAdFlowCntrlSettings(pDevice);
-
- LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32);
- pDevice->advertising = Value32;
- }
- }
-
- /* Force line speed if auto-negotiation is disabled. */
- if(pDevice->DisableAutoNeg && LineSpeed != LM_LINE_SPEED_UNKNOWN)
- {
- /* This code path is executed only when there is link. */
- pDevice->MediaType = MediaType;
- pDevice->LineSpeed = LineSpeed;
- pDevice->DuplexMode = DuplexMode;
-
- /* Force line seepd. */
- NewPhyCtrl = 0;
- switch(LineSpeed)
- {
- case LM_LINE_SPEED_10MBPS:
- NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_10MBPS;
- break;
- case LM_LINE_SPEED_100MBPS:
- NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_100MBPS;
- break;
- case LM_LINE_SPEED_1000MBPS:
- NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_1000MBPS;
- break;
- default:
- NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_1000MBPS;
- break;
+ LM_WritePhy (pDevice, PHY_AN_AD_REG, Value32);
+ pDevice->advertising = Value32;
+ }
}
- if(DuplexMode == LM_DUPLEX_MODE_FULL)
- {
- NewPhyCtrl |= PHY_CTRL_FULL_DUPLEX_MODE;
- }
+ /* Force line speed if auto-negotiation is disabled. */
+ if (pDevice->DisableAutoNeg && LineSpeed != LM_LINE_SPEED_UNKNOWN) {
+ /* This code path is executed only when there is link. */
+ pDevice->MediaType = MediaType;
+ pDevice->LineSpeed = LineSpeed;
+ pDevice->DuplexMode = DuplexMode;
- /* Don't do anything if the PHY_CTRL is already what we wanted. */
- LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32);
- if(Value32 != NewPhyCtrl)
- {
- /* Temporary bring the link down before forcing line speed. */
- LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_LOOPBACK_MODE);
+ /* Force line seepd. */
+ NewPhyCtrl = 0;
+ switch (LineSpeed) {
+ case LM_LINE_SPEED_10MBPS:
+ NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_10MBPS;
+ break;
+ case LM_LINE_SPEED_100MBPS:
+ NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_100MBPS;
+ break;
+ case LM_LINE_SPEED_1000MBPS:
+ NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_1000MBPS;
+ break;
+ default:
+ NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_1000MBPS;
+ break;
+ }
- /* Wait for link to go down. */
- for(Cnt = 0; Cnt < 15000; Cnt++)
- {
- MM_Wait(10);
+ if (DuplexMode == LM_DUPLEX_MODE_FULL) {
+ NewPhyCtrl |= PHY_CTRL_FULL_DUPLEX_MODE;
+ }
- LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
- LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
+ /* Don't do anything if the PHY_CTRL is already what we wanted. */
+ LM_ReadPhy (pDevice, PHY_CTRL_REG, &Value32);
+ if (Value32 != NewPhyCtrl) {
+ /* Temporary bring the link down before forcing line speed. */
+ LM_WritePhy (pDevice, PHY_CTRL_REG,
+ PHY_CTRL_LOOPBACK_MODE);
- if(!(Value32 & PHY_STATUS_LINK_PASS))
- {
- MM_Wait(40);
- break;
- }
- }
+ /* Wait for link to go down. */
+ for (Cnt = 0; Cnt < 15000; Cnt++) {
+ MM_Wait (10);
- LM_WritePhy(pDevice, PHY_CTRL_REG, NewPhyCtrl);
- MM_Wait(40);
- }
- }
- else
- {
- LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_AUTO_NEG_ENABLE |
- PHY_CTRL_RESTART_AUTO_NEG);
- }
+ LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
+ LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
- return LM_STATUS_SUCCESS;
-} /* LM_ForceAutoNegBcm540xPhy */
+ if (!(Value32 & PHY_STATUS_LINK_PASS)) {
+ MM_Wait (40);
+ break;
+ }
+ }
+ LM_WritePhy (pDevice, PHY_CTRL_REG, NewPhyCtrl);
+ MM_Wait (40);
+ }
+ } else {
+ LM_WritePhy (pDevice, PHY_CTRL_REG, PHY_CTRL_AUTO_NEG_ENABLE |
+ PHY_CTRL_RESTART_AUTO_NEG);
+ }
+
+ return LM_STATUS_SUCCESS;
+} /* LM_ForceAutoNegBcm540xPhy */
/******************************************************************************/
/* Description: */
@@ -5828,218 +5347,199 @@ LM_REQUESTED_MEDIA_TYPE RequestedMediaType)
/* Return: */
/******************************************************************************/
static LM_STATUS
-LM_ForceAutoNeg(
-PLM_DEVICE_BLOCK pDevice,
-LM_REQUESTED_MEDIA_TYPE RequestedMediaType)
+LM_ForceAutoNeg (PLM_DEVICE_BLOCK pDevice,
+ LM_REQUESTED_MEDIA_TYPE RequestedMediaType)
{
- LM_STATUS LmStatus;
+ LM_STATUS LmStatus;
- /* Initialize the phy chip. */
- switch(pDevice->PhyId & PHY_ID_MASK)
- {
+ /* Initialize the phy chip. */
+ switch (pDevice->PhyId & PHY_ID_MASK) {
case PHY_BCM5400_PHY_ID:
case PHY_BCM5401_PHY_ID:
case PHY_BCM5411_PHY_ID:
case PHY_BCM5701_PHY_ID:
case PHY_BCM5703_PHY_ID:
case PHY_BCM5704_PHY_ID:
- LmStatus = LM_ForceAutoNegBcm540xPhy(pDevice, RequestedMediaType);
- break;
+ LmStatus =
+ LM_ForceAutoNegBcm540xPhy (pDevice, RequestedMediaType);
+ break;
default:
- LmStatus = LM_STATUS_FAILURE;
- break;
- }
+ LmStatus = LM_STATUS_FAILURE;
+ break;
+ }
- return LmStatus;
-} /* LM_ForceAutoNeg */
+ return LmStatus;
+} /* LM_ForceAutoNeg */
/******************************************************************************/
/* Description: */
/* */
/* Return: */
/******************************************************************************/
-LM_STATUS LM_LoadFirmware(PLM_DEVICE_BLOCK pDevice,
- PT3_FWIMG_INFO pFwImg,
- LM_UINT32 LoadCpu,
- LM_UINT32 StartCpu)
+LM_STATUS LM_LoadFirmware (PLM_DEVICE_BLOCK pDevice,
+ PT3_FWIMG_INFO pFwImg,
+ LM_UINT32 LoadCpu, LM_UINT32 StartCpu)
{
- LM_UINT32 i;
- LM_UINT32 address;
+ LM_UINT32 i;
+ LM_UINT32 address;
- if (LoadCpu & T3_RX_CPU_ID)
- {
- if (LM_HaltCpu(pDevice,T3_RX_CPU_ID) != LM_STATUS_SUCCESS)
- {
- return LM_STATUS_FAILURE;
- }
+ if (LoadCpu & T3_RX_CPU_ID) {
+ if (LM_HaltCpu (pDevice, T3_RX_CPU_ID) != LM_STATUS_SUCCESS) {
+ return LM_STATUS_FAILURE;
+ }
- /* First of all clear scrach pad memory */
- for (i = 0; i < T3_RX_CPU_SPAD_SIZE; i+=4)
- {
- LM_RegWrInd(pDevice,T3_RX_CPU_SPAD_ADDR+i,0);
- }
+ /* First of all clear scrach pad memory */
+ for (i = 0; i < T3_RX_CPU_SPAD_SIZE; i += 4) {
+ LM_RegWrInd (pDevice, T3_RX_CPU_SPAD_ADDR + i, 0);
+ }
- /* Copy code first */
- address = T3_RX_CPU_SPAD_ADDR + (pFwImg->Text.Offset & 0xffff);
- for (i = 0; i <= pFwImg->Text.Length; i+=4)
- {
- LM_RegWrInd(pDevice,address+i,
- ((LM_UINT32 *)pFwImg->Text.Buffer)[i/4]);
- }
+ /* Copy code first */
+ address = T3_RX_CPU_SPAD_ADDR + (pFwImg->Text.Offset & 0xffff);
+ for (i = 0; i <= pFwImg->Text.Length; i += 4) {
+ LM_RegWrInd (pDevice, address + i,
+ ((LM_UINT32 *) pFwImg->Text.Buffer)[i /
+ 4]);
+ }
- address = T3_RX_CPU_SPAD_ADDR + (pFwImg->ROnlyData.Offset & 0xffff);
- for (i = 0; i <= pFwImg->ROnlyData.Length; i+=4)
- {
- LM_RegWrInd(pDevice,address+i,
- ((LM_UINT32 *)pFwImg->ROnlyData.Buffer)[i/4]);
- }
+ address =
+ T3_RX_CPU_SPAD_ADDR + (pFwImg->ROnlyData.Offset & 0xffff);
+ for (i = 0; i <= pFwImg->ROnlyData.Length; i += 4) {
+ LM_RegWrInd (pDevice, address + i,
+ ((LM_UINT32 *) pFwImg->ROnlyData.
+ Buffer)[i / 4]);
+ }
- address = T3_RX_CPU_SPAD_ADDR + (pFwImg->Data.Offset & 0xffff);
- for (i= 0; i <= pFwImg->Data.Length; i+=4)
- {
- LM_RegWrInd(pDevice,address+i,
- ((LM_UINT32 *)pFwImg->Data.Buffer)[i/4]);
+ address = T3_RX_CPU_SPAD_ADDR + (pFwImg->Data.Offset & 0xffff);
+ for (i = 0; i <= pFwImg->Data.Length; i += 4) {
+ LM_RegWrInd (pDevice, address + i,
+ ((LM_UINT32 *) pFwImg->Data.Buffer)[i /
+ 4]);
+ }
}
- }
- if (LoadCpu & T3_TX_CPU_ID)
- {
- if (LM_HaltCpu(pDevice,T3_TX_CPU_ID) != LM_STATUS_SUCCESS)
- {
- return LM_STATUS_FAILURE;
- }
+ if (LoadCpu & T3_TX_CPU_ID) {
+ if (LM_HaltCpu (pDevice, T3_TX_CPU_ID) != LM_STATUS_SUCCESS) {
+ return LM_STATUS_FAILURE;
+ }
- /* First of all clear scrach pad memory */
- for (i = 0; i < T3_TX_CPU_SPAD_SIZE; i+=4)
- {
- LM_RegWrInd(pDevice,T3_TX_CPU_SPAD_ADDR+i,0);
- }
+ /* First of all clear scrach pad memory */
+ for (i = 0; i < T3_TX_CPU_SPAD_SIZE; i += 4) {
+ LM_RegWrInd (pDevice, T3_TX_CPU_SPAD_ADDR + i, 0);
+ }
- /* Copy code first */
- address = T3_TX_CPU_SPAD_ADDR + (pFwImg->Text.Offset & 0xffff);
- for (i= 0; i <= pFwImg->Text.Length; i+=4)
- {
- LM_RegWrInd(pDevice,address+i,
- ((LM_UINT32 *)pFwImg->Text.Buffer)[i/4]);
- }
+ /* Copy code first */
+ address = T3_TX_CPU_SPAD_ADDR + (pFwImg->Text.Offset & 0xffff);
+ for (i = 0; i <= pFwImg->Text.Length; i += 4) {
+ LM_RegWrInd (pDevice, address + i,
+ ((LM_UINT32 *) pFwImg->Text.Buffer)[i /
+ 4]);
+ }
- address = T3_TX_CPU_SPAD_ADDR + (pFwImg->ROnlyData.Offset & 0xffff);
- for (i= 0; i <= pFwImg->ROnlyData.Length; i+=4)
- {
- LM_RegWrInd(pDevice,address+i,
- ((LM_UINT32 *)pFwImg->ROnlyData.Buffer)[i/4]);
- }
+ address =
+ T3_TX_CPU_SPAD_ADDR + (pFwImg->ROnlyData.Offset & 0xffff);
+ for (i = 0; i <= pFwImg->ROnlyData.Length; i += 4) {
+ LM_RegWrInd (pDevice, address + i,
+ ((LM_UINT32 *) pFwImg->ROnlyData.
+ Buffer)[i / 4]);
+ }
- address = T3_TX_CPU_SPAD_ADDR + (pFwImg->Data.Offset & 0xffff);
- for (i= 0; i <= pFwImg->Data.Length; i+=4)
- {
- LM_RegWrInd(pDevice,address+i,
- ((LM_UINT32 *)pFwImg->Data.Buffer)[i/4]);
+ address = T3_TX_CPU_SPAD_ADDR + (pFwImg->Data.Offset & 0xffff);
+ for (i = 0; i <= pFwImg->Data.Length; i += 4) {
+ LM_RegWrInd (pDevice, address + i,
+ ((LM_UINT32 *) pFwImg->Data.Buffer)[i /
+ 4]);
+ }
}
- }
- if (StartCpu & T3_RX_CPU_ID)
- {
- /* Start Rx CPU */
- REG_WR(pDevice,rxCpu.reg.state, 0xffffffff);
- REG_WR(pDevice,rxCpu.reg.PC,pFwImg->StartAddress);
- for (i = 0 ; i < 5; i++)
- {
- if (pFwImg->StartAddress == REG_RD(pDevice,rxCpu.reg.PC))
- break;
+ if (StartCpu & T3_RX_CPU_ID) {
+ /* Start Rx CPU */
+ REG_WR (pDevice, rxCpu.reg.state, 0xffffffff);
+ REG_WR (pDevice, rxCpu.reg.PC, pFwImg->StartAddress);
+ for (i = 0; i < 5; i++) {
+ if (pFwImg->StartAddress ==
+ REG_RD (pDevice, rxCpu.reg.PC))
+ break;
- REG_WR(pDevice,rxCpu.reg.state, 0xffffffff);
- REG_WR(pDevice,rxCpu.reg.mode,CPU_MODE_HALT);
- REG_WR(pDevice,rxCpu.reg.PC,pFwImg->StartAddress);
- MM_Wait(1000);
+ REG_WR (pDevice, rxCpu.reg.state, 0xffffffff);
+ REG_WR (pDevice, rxCpu.reg.mode, CPU_MODE_HALT);
+ REG_WR (pDevice, rxCpu.reg.PC, pFwImg->StartAddress);
+ MM_Wait (1000);
+ }
+
+ REG_WR (pDevice, rxCpu.reg.state, 0xffffffff);
+ REG_WR (pDevice, rxCpu.reg.mode, 0);
}
- REG_WR(pDevice,rxCpu.reg.state, 0xffffffff);
- REG_WR(pDevice,rxCpu.reg.mode, 0);
- }
+ if (StartCpu & T3_TX_CPU_ID) {
+ /* Start Tx CPU */
+ REG_WR (pDevice, txCpu.reg.state, 0xffffffff);
+ REG_WR (pDevice, txCpu.reg.PC, pFwImg->StartAddress);
+ for (i = 0; i < 5; i++) {
+ if (pFwImg->StartAddress ==
+ REG_RD (pDevice, txCpu.reg.PC))
+ break;
- if (StartCpu & T3_TX_CPU_ID)
- {
- /* Start Tx CPU */
- REG_WR(pDevice,txCpu.reg.state, 0xffffffff);
- REG_WR(pDevice,txCpu.reg.PC,pFwImg->StartAddress);
- for (i = 0 ; i < 5; i++)
- {
- if (pFwImg->StartAddress == REG_RD(pDevice,txCpu.reg.PC))
- break;
+ REG_WR (pDevice, txCpu.reg.state, 0xffffffff);
+ REG_WR (pDevice, txCpu.reg.mode, CPU_MODE_HALT);
+ REG_WR (pDevice, txCpu.reg.PC, pFwImg->StartAddress);
+ MM_Wait (1000);
+ }
- REG_WR(pDevice,txCpu.reg.state, 0xffffffff);
- REG_WR(pDevice,txCpu.reg.mode,CPU_MODE_HALT);
- REG_WR(pDevice,txCpu.reg.PC,pFwImg->StartAddress);
- MM_Wait(1000);
+ REG_WR (pDevice, txCpu.reg.state, 0xffffffff);
+ REG_WR (pDevice, txCpu.reg.mode, 0);
}
- REG_WR(pDevice,txCpu.reg.state, 0xffffffff);
- REG_WR(pDevice,txCpu.reg.mode, 0);
- }
-
- return LM_STATUS_SUCCESS;
+ return LM_STATUS_SUCCESS;
}
-STATIC LM_STATUS LM_HaltCpu(PLM_DEVICE_BLOCK pDevice,LM_UINT32 cpu_number)
+STATIC LM_STATUS LM_HaltCpu (PLM_DEVICE_BLOCK pDevice, LM_UINT32 cpu_number)
{
- LM_UINT32 i;
+ LM_UINT32 i;
- if (cpu_number == T3_RX_CPU_ID)
- {
- for (i = 0 ; i < 10000; i++)
- {
- REG_WR(pDevice,rxCpu.reg.state, 0xffffffff);
- REG_WR(pDevice,rxCpu.reg.mode,CPU_MODE_HALT);
+ if (cpu_number == T3_RX_CPU_ID) {
+ for (i = 0; i < 10000; i++) {
+ REG_WR (pDevice, rxCpu.reg.state, 0xffffffff);
+ REG_WR (pDevice, rxCpu.reg.mode, CPU_MODE_HALT);
- if (REG_RD(pDevice,rxCpu.reg.mode) & CPU_MODE_HALT)
- break;
- }
+ if (REG_RD (pDevice, rxCpu.reg.mode) & CPU_MODE_HALT)
+ break;
+ }
- REG_WR(pDevice,rxCpu.reg.state, 0xffffffff);
- REG_WR(pDevice,rxCpu.reg.mode,CPU_MODE_HALT);
- MM_Wait(10);
- }
- else
- {
- for (i = 0 ; i < 10000; i++)
- {
- REG_WR(pDevice,txCpu.reg.state, 0xffffffff);
- REG_WR(pDevice,txCpu.reg.mode,CPU_MODE_HALT);
+ REG_WR (pDevice, rxCpu.reg.state, 0xffffffff);
+ REG_WR (pDevice, rxCpu.reg.mode, CPU_MODE_HALT);
+ MM_Wait (10);
+ } else {
+ for (i = 0; i < 10000; i++) {
+ REG_WR (pDevice, txCpu.reg.state, 0xffffffff);
+ REG_WR (pDevice, txCpu.reg.mode, CPU_MODE_HALT);
- if (REG_RD(pDevice,txCpu.reg.mode) & CPU_MODE_HALT)
- break;
+ if (REG_RD (pDevice, txCpu.reg.mode) & CPU_MODE_HALT)
+ break;
+ }
}
- }
- return (( i == 10000) ? LM_STATUS_FAILURE : LM_STATUS_SUCCESS);
+ return ((i == 10000) ? LM_STATUS_FAILURE : LM_STATUS_SUCCESS);
}
-
-int
-LM_BlinkLED(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlinkDurationSec)
+int LM_BlinkLED (PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlinkDurationSec)
{
LM_UINT32 Oldcfg;
int j;
int ret = 0;
- if(BlinkDurationSec == 0)
- {
+ if (BlinkDurationSec == 0) {
return 0;
}
- if(BlinkDurationSec > 120)
- {
+ if (BlinkDurationSec > 120) {
BlinkDurationSec = 120;
}
- Oldcfg = REG_RD(pDevice, MacCtrl.LedCtrl);
- for(j = 0; j < BlinkDurationSec * 2; j++)
- {
- if(j % 2)
- {
+ Oldcfg = REG_RD (pDevice, MacCtrl.LedCtrl);
+ for (j = 0; j < BlinkDurationSec * 2; j++) {
+ if (j % 2) {
/* Turn on the LEDs. */
- REG_WR(pDevice, MacCtrl.LedCtrl,
+ REG_WR (pDevice, MacCtrl.LedCtrl,
LED_CTRL_OVERRIDE_LINK_LED |
LED_CTRL_1000MBPS_LED_ON |
LED_CTRL_100MBPS_LED_ON |
@@ -6047,154 +5547,153 @@ LM_BlinkLED(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlinkDurationSec)
LED_CTRL_OVERRIDE_TRAFFIC_LED |
LED_CTRL_BLINK_TRAFFIC_LED |
LED_CTRL_TRAFFIC_LED);
- }
- else
- {
+ } else {
/* Turn off the LEDs. */
- REG_WR(pDevice, MacCtrl.LedCtrl,
+ REG_WR (pDevice, MacCtrl.LedCtrl,
LED_CTRL_OVERRIDE_LINK_LED |
LED_CTRL_OVERRIDE_TRAFFIC_LED);
}
#ifndef EMBEDDED
current->state = TASK_INTERRUPTIBLE;
- if (schedule_timeout(HZ/2) != 0) {
+ if (schedule_timeout (HZ / 2) != 0) {
ret = -EINTR;
break;
}
#else
- udelay(100000); /* 1s sleep */
+ udelay (100000); /* 1s sleep */
#endif
}
- REG_WR(pDevice, MacCtrl.LedCtrl, Oldcfg);
+ REG_WR (pDevice, MacCtrl.LedCtrl, Oldcfg);
return ret;
}
-int t3_do_dma(PLM_DEVICE_BLOCK pDevice,
- LM_PHYSICAL_ADDRESS host_addr_phy, int length,
- int dma_read)
+int t3_do_dma (PLM_DEVICE_BLOCK pDevice,
+ LM_PHYSICAL_ADDRESS host_addr_phy, int length, int dma_read)
{
- T3_DMA_DESC dma_desc;
- int i;
- LM_UINT32 dma_desc_addr;
- LM_UINT32 value32;
-
- REG_WR(pDevice, BufMgr.Mode, 0);
- REG_WR(pDevice, Ftq.Reset, 0);
-
- dma_desc.host_addr.High = host_addr_phy.High;
- dma_desc.host_addr.Low = host_addr_phy.Low;
- dma_desc.nic_mbuf = 0x2100;
- dma_desc.len = length;
- dma_desc.flags = 0x00000004; /* Generate Rx-CPU event */
-
- if (dma_read)
- {
- dma_desc.cqid_sqid = (T3_QID_RX_BD_COMP << 8) |
- T3_QID_DMA_HIGH_PRI_READ;
- REG_WR(pDevice, DmaRead.Mode, DMA_READ_MODE_ENABLE);
- }
- else
- {
- dma_desc.cqid_sqid = (T3_QID_RX_DATA_COMP << 8) |
- T3_QID_DMA_HIGH_PRI_WRITE;
- REG_WR(pDevice, DmaWrite.Mode, DMA_WRITE_MODE_ENABLE);
- }
-
- dma_desc_addr = T3_NIC_DMA_DESC_POOL_ADDR;
-
- /* Writing this DMA descriptor to DMA memory */
- for (i = 0; i < sizeof(T3_DMA_DESC); i += 4)
- {
- value32 = *((PLM_UINT32) (((PLM_UINT8) &dma_desc) + i));
- MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_ADDR_REG, dma_desc_addr+i);
- MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_DATA_REG, cpu_to_le32(value32));
- }
- MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_ADDR_REG, 0);
-
- if (dma_read)
- REG_WR(pDevice, Ftq.DmaHighReadFtqFifoEnqueueDequeue, dma_desc_addr);
- else
- REG_WR(pDevice, Ftq.DmaHighWriteFtqFifoEnqueueDequeue, dma_desc_addr);
-
- for (i = 0; i < 40; i++)
- {
+ T3_DMA_DESC dma_desc;
+ int i;
+ LM_UINT32 dma_desc_addr;
+ LM_UINT32 value32;
+
+ REG_WR (pDevice, BufMgr.Mode, 0);
+ REG_WR (pDevice, Ftq.Reset, 0);
+
+ dma_desc.host_addr.High = host_addr_phy.High;
+ dma_desc.host_addr.Low = host_addr_phy.Low;
+ dma_desc.nic_mbuf = 0x2100;
+ dma_desc.len = length;
+ dma_desc.flags = 0x00000004; /* Generate Rx-CPU event */
+
+ if (dma_read) {
+ dma_desc.cqid_sqid = (T3_QID_RX_BD_COMP << 8) |
+ T3_QID_DMA_HIGH_PRI_READ;
+ REG_WR (pDevice, DmaRead.Mode, DMA_READ_MODE_ENABLE);
+ } else {
+ dma_desc.cqid_sqid = (T3_QID_RX_DATA_COMP << 8) |
+ T3_QID_DMA_HIGH_PRI_WRITE;
+ REG_WR (pDevice, DmaWrite.Mode, DMA_WRITE_MODE_ENABLE);
+ }
+
+ dma_desc_addr = T3_NIC_DMA_DESC_POOL_ADDR;
+
+ /* Writing this DMA descriptor to DMA memory */
+ for (i = 0; i < sizeof (T3_DMA_DESC); i += 4) {
+ value32 = *((PLM_UINT32) (((PLM_UINT8) & dma_desc) + i));
+ MM_WriteConfig32 (pDevice, T3_PCI_MEM_WIN_ADDR_REG,
+ dma_desc_addr + i);
+ MM_WriteConfig32 (pDevice, T3_PCI_MEM_WIN_DATA_REG,
+ cpu_to_le32 (value32));
+ }
+ MM_WriteConfig32 (pDevice, T3_PCI_MEM_WIN_ADDR_REG, 0);
+
if (dma_read)
- value32 = REG_RD(pDevice, Ftq.RcvBdCompFtqFifoEnqueueDequeue);
+ REG_WR (pDevice, Ftq.DmaHighReadFtqFifoEnqueueDequeue,
+ dma_desc_addr);
else
- value32 = REG_RD(pDevice, Ftq.RcvDataCompFtqFifoEnqueueDequeue);
+ REG_WR (pDevice, Ftq.DmaHighWriteFtqFifoEnqueueDequeue,
+ dma_desc_addr);
+
+ for (i = 0; i < 40; i++) {
+ if (dma_read)
+ value32 =
+ REG_RD (pDevice,
+ Ftq.RcvBdCompFtqFifoEnqueueDequeue);
+ else
+ value32 =
+ REG_RD (pDevice,
+ Ftq.RcvDataCompFtqFifoEnqueueDequeue);
- if ((value32 & 0xffff) == dma_desc_addr)
- break;
+ if ((value32 & 0xffff) == dma_desc_addr)
+ break;
- MM_Wait(10);
- }
+ MM_Wait (10);
+ }
- return LM_STATUS_SUCCESS;
+ return LM_STATUS_SUCCESS;
}
STATIC LM_STATUS
-LM_DmaTest(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pBufferVirt,
- LM_PHYSICAL_ADDRESS BufferPhy, LM_UINT32 BufferSize)
+LM_DmaTest (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pBufferVirt,
+ LM_PHYSICAL_ADDRESS BufferPhy, LM_UINT32 BufferSize)
{
- int j;
- LM_UINT32 *ptr;
- int dma_success = 0;
+ int j;
+ LM_UINT32 *ptr;
+ int dma_success = 0;
+
+ if (T3_ASIC_REV (pDevice->ChipRevId) != T3_ASIC_REV_5700 &&
+ T3_ASIC_REV (pDevice->ChipRevId) != T3_ASIC_REV_5701) {
+ return LM_STATUS_SUCCESS;
+ }
+ while (!dma_success) {
+ /* Fill data with incremental patterns */
+ ptr = (LM_UINT32 *) pBufferVirt;
+ for (j = 0; j < BufferSize / 4; j++)
+ *ptr++ = j;
+
+ if (t3_do_dma (pDevice, BufferPhy, BufferSize, 1) ==
+ LM_STATUS_FAILURE) {
+ return LM_STATUS_FAILURE;
+ }
- if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700 &&
- T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701)
- {
- return LM_STATUS_SUCCESS;
- }
- while (!dma_success)
- {
- /* Fill data with incremental patterns */
- ptr = (LM_UINT32 *)pBufferVirt;
- for (j = 0; j < BufferSize/4; j++)
- *ptr++ = j;
-
- if (t3_do_dma(pDevice,BufferPhy,BufferSize, 1) == LM_STATUS_FAILURE)
- {
- return LM_STATUS_FAILURE;
- }
+ MM_Wait (40);
+ ptr = (LM_UINT32 *) pBufferVirt;
+ /* Fill data with zero */
+ for (j = 0; j < BufferSize / 4; j++)
+ *ptr++ = 0;
- MM_Wait(40);
- ptr = (LM_UINT32 *)pBufferVirt;
- /* Fill data with zero */
- for (j = 0; j < BufferSize/4; j++)
- *ptr++ = 0;
+ if (t3_do_dma (pDevice, BufferPhy, BufferSize, 0) ==
+ LM_STATUS_FAILURE) {
+ return LM_STATUS_FAILURE;
+ }
- if (t3_do_dma(pDevice,BufferPhy,BufferSize, 0) == LM_STATUS_FAILURE)
- {
- return LM_STATUS_FAILURE;
+ MM_Wait (40);
+ /* Check for data */
+ ptr = (LM_UINT32 *) pBufferVirt;
+ for (j = 0; j < BufferSize / 4; j++) {
+ if (*ptr++ != j) {
+ if ((pDevice->
+ DmaReadWriteCtrl &
+ DMA_CTRL_WRITE_BOUNDARY_MASK)
+ == DMA_CTRL_WRITE_BOUNDARY_DISABLE) {
+ pDevice->DmaReadWriteCtrl =
+ (pDevice->
+ DmaReadWriteCtrl &
+ ~DMA_CTRL_WRITE_BOUNDARY_MASK) |
+ DMA_CTRL_WRITE_BOUNDARY_16;
+ REG_WR (pDevice,
+ PciCfg.DmaReadWriteCtrl,
+ pDevice->DmaReadWriteCtrl);
+ break;
+ } else {
+ return LM_STATUS_FAILURE;
+ }
+ }
+ }
+ if (j == (BufferSize / 4))
+ dma_success = 1;
}
-
- MM_Wait(40);
- /* Check for data */
- ptr = (LM_UINT32 *)pBufferVirt;
- for (j = 0; j < BufferSize/4; j++)
- {
- if (*ptr++ != j)
- {
- if ((pDevice->DmaReadWriteCtrl & DMA_CTRL_WRITE_BOUNDARY_MASK)
- == DMA_CTRL_WRITE_BOUNDARY_DISABLE)
- {
- pDevice->DmaReadWriteCtrl = (pDevice->DmaReadWriteCtrl &
- ~DMA_CTRL_WRITE_BOUNDARY_MASK) |
- DMA_CTRL_WRITE_BOUNDARY_16;
- REG_WR(pDevice, PciCfg.DmaReadWriteCtrl,
- pDevice->DmaReadWriteCtrl);
- break;
- }
- else
- {
- return LM_STATUS_FAILURE;
- }
- }
- }
- if (j == (BufferSize/4))
- dma_success = 1;
- }
- return LM_STATUS_SUCCESS;
+ return LM_STATUS_SUCCESS;
}
+
#endif
diff --git a/drivers/tigon3.h b/drivers/tigon3.h
index ea4367d..c03347f 100644
--- a/drivers/tigon3.h
+++ b/drivers/tigon3.h
@@ -21,7 +21,6 @@
#include "bcm570x_autoneg.h"
#endif
-
/* io defines */
#if !defined(BIG_ENDIAN_HOST)
#define readl(addr) \
@@ -29,7 +28,7 @@
#define writel(b,addr) \
((*(volatile unsigned int *)(addr)) = (LONGSWAP(b)))
#else
-#if 0 /* !defined(PPC603) */
+#if 0 /* !defined(PPC603) */
#define readl(addr) (*(volatile unsigned int*)(0xa0000000 + (unsigned long)(addr)))
#define writel(b,addr) ((*(volatile unsigned int *) ((unsigned long)(addr) + 0xa0000000)) = (b))
#else
@@ -37,25 +36,28 @@
#define readl(addr) (*(volatile unsigned int*)(addr))
#define writel(b,addr) ((*(volatile unsigned int *) (addr)) = (b))
#else
-extern int sprintf(char* buf, const char* f, ...);
-static __inline unsigned int readl(void* addr){
- char buf[128];
- unsigned int tmp = (*(volatile unsigned int*)(addr));
- sprintf(buf,"%s:%s: read 0x%x from 0x%x\n",__FILE__,__LINE__,tmp,addr,0,0);
- sysSerialPrintString(buf);
- return tmp;
+extern int sprintf (char *buf, const char *f, ...);
+static __inline unsigned int readl (void *addr)
+{
+ char buf[128];
+ unsigned int tmp = (*(volatile unsigned int *)(addr));
+ sprintf (buf, "%s:%s: read 0x%x from 0x%x\n", __FILE__, __LINE__, tmp,
+ addr, 0, 0);
+ sysSerialPrintString (buf);
+ return tmp;
}
-static __inline void writel(unsigned int b, unsigned int addr){
- char buf[128];
- ((*(volatile unsigned int *) (addr)) = (b));
- sprintf(buf,"%s:%s: write 0x%x to 0x%x\n",__FILE__,__LINE__,b,addr,0,0);
- sysSerialPrintString(buf);
+static __inline void writel (unsigned int b, unsigned int addr)
+{
+ char buf[128];
+ ((*(volatile unsigned int *)(addr)) = (b));
+ sprintf (buf, "%s:%s: write 0x%x to 0x%x\n", __FILE__, __LINE__, b,
+ addr, 0, 0);
+ sysSerialPrintString (buf);
}
#endif
-#endif /* PPC603 */
+#endif /* PPC603 */
#endif
-
/******************************************************************************/
/* Constants. */
/******************************************************************************/
@@ -90,7 +92,7 @@ static __inline void writel(unsigned int b, unsigned int addr){
/* B0 bug. */
#define BCM5700_BX_MIN_FRAG_SIZE 10
-#define BCM5700_BX_MIN_FRAG_BUF_SIZE 16 /* nice aligned size. */
+#define BCM5700_BX_MIN_FRAG_BUF_SIZE 16 /* nice aligned size. */
#define BCM5700_BX_MIN_FRAG_BUF_SIZE_MASK (BCM5700_BX_MIN_FRAG_BUF_SIZE-1)
#define BCM5700_BX_TX_COPY_BUF_SIZE (BCM5700_BX_MIN_FRAG_BUF_SIZE * \
MAX_FRAGMENT_COUNT)
@@ -161,32 +163,32 @@ static __inline void writel(unsigned int b, unsigned int addr){
/* Number of entries in the Standard Receive RCB. Must be 512 entries. */
#define T3_STD_RCV_RCB_ENTRY_COUNT 512
#define T3_STD_RCV_RCB_ENTRY_COUNT_MASK (T3_STD_RCV_RCB_ENTRY_COUNT-1)
-#define DEFAULT_STD_RCV_DESC_COUNT 200 /* Must be < 512. */
+#define DEFAULT_STD_RCV_DESC_COUNT 200 /* Must be < 512. */
#define MAX_STD_RCV_BUFFER_SIZE 0x600
/* Number of entries in the Mini Receive RCB. This value can either be */
/* 0, 1024. Currently Mini Receive RCB is disabled. */
#ifndef T3_MINI_RCV_RCB_ENTRY_COUNT
#define T3_MINI_RCV_RCB_ENTRY_COUNT 0
-#endif /* T3_MINI_RCV_RCB_ENTRY_COUNT */
+#endif /* T3_MINI_RCV_RCB_ENTRY_COUNT */
#define T3_MINI_RCV_RCB_ENTRY_COUNT_MASK (T3_MINI_RCV_RCB_ENTRY_COUNT-1)
#define MAX_MINI_RCV_BUFFER_SIZE 512
#define DEFAULT_MINI_RCV_BUFFER_SIZE 64
-#define DEFAULT_MINI_RCV_DESC_COUNT 100 /* Must be < 1024. */
+#define DEFAULT_MINI_RCV_DESC_COUNT 100 /* Must be < 1024. */
/* Number of entries in the Jumbo Receive RCB. This value must 256 or 0. */
/* Currently, Jumbo Receive RCB is disabled. */
#ifndef T3_JUMBO_RCV_RCB_ENTRY_COUNT
#define T3_JUMBO_RCV_RCB_ENTRY_COUNT 0
-#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
+#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
#define T3_JUMBO_RCV_RCB_ENTRY_COUNT_MASK (T3_JUMBO_RCV_RCB_ENTRY_COUNT-1)
-#define MAX_JUMBO_RCV_BUFFER_SIZE (10 * 1024) /* > 1514 */
-#define DEFAULT_JUMBO_RCV_BUFFER_SIZE (4 * 1024) /* > 1514 */
-#define DEFAULT_JUMBO_RCV_DESC_COUNT 128 /* Must be < 256. */
+#define MAX_JUMBO_RCV_BUFFER_SIZE (10 * 1024) /* > 1514 */
+#define DEFAULT_JUMBO_RCV_BUFFER_SIZE (4 * 1024) /* > 1514 */
+#define DEFAULT_JUMBO_RCV_DESC_COUNT 128 /* Must be < 256. */
-#define MAX_JUMBO_TX_BUFFER_SIZE (8 * 1024) /* > 1514 */
-#define DEFAULT_JUMBO_TX_BUFFER_SIZE (4 * 1024) /* > 1514 */
+#define MAX_JUMBO_TX_BUFFER_SIZE (8 * 1024) /* > 1514 */
+#define DEFAULT_JUMBO_TX_BUFFER_SIZE (4 * 1024) /* > 1514 */
/* Number of receive return RCBs. Maybe 1-16 but for now, only support one. */
#define T3_MAX_RCV_RETURN_RCB_COUNT 16
@@ -195,10 +197,9 @@ static __inline void writel(unsigned int b, unsigned int addr){
/* or 2048. */
#ifndef T3_RCV_RETURN_RCB_ENTRY_COUNT
#define T3_RCV_RETURN_RCB_ENTRY_COUNT 1024
-#endif /* T3_RCV_RETURN_RCB_ENTRY_COUNT */
+#endif /* T3_RCV_RETURN_RCB_ENTRY_COUNT */
#define T3_RCV_RETURN_RCB_ENTRY_COUNT_MASK (T3_RCV_RETURN_RCB_ENTRY_COUNT-1)
-
/* Default coalescing parameters. */
#define DEFAULT_RX_COALESCING_TICKS 100
#define MAX_RX_COALESCING_TICKS 500
@@ -227,7 +228,6 @@ static __inline void writel(unsigned int b, unsigned int addr){
#define DEFAULT_STATS_COALESCING_TICKS 1000000
#define MAX_STATS_COALESCING_TICKS 3600000000U
-
/* Receive BD Replenish thresholds. */
#define DEFAULT_RCV_STD_BD_REPLENISH_THRESHOLD 4
#define DEFAULT_RCV_JUMBO_BD_REPLENISH_THRESHOLD 4
@@ -240,12 +240,10 @@ static __inline void writel(unsigned int b, unsigned int addr){
/* Maximum physical fragment size. */
#define MAX_FRAGMENT_SIZE (64 * 1024)
-
/* Standard view. */
#define T3_STD_VIEW_SIZE (64 * 1024)
#define T3_FLAT_VIEW_SIZE (32 * 1024 * 1024)
-
/* Buffer descriptor base address on the NIC's memory. */
#define T3_NIC_SND_BUFFER_DESC_ADDR 0x4000
@@ -265,19 +263,17 @@ static __inline void writel(unsigned int b, unsigned int addr){
#define T3_NIC_JUMBO_RCV_BUFFER_DESC_SIZE (T3_JUMBO_RCV_RCB_ENTRY_COUNT * \
sizeof(T3_EXT_RCV_BD) / 4)
-
/* MBUF pool. */
#define T3_NIC_MBUF_POOL_ADDR 0x8000
/* #define T3_NIC_MBUF_POOL_SIZE 0x18000 */
#define T3_NIC_MBUF_POOL_SIZE96 0x18000
#define T3_NIC_MBUF_POOL_SIZE64 0x10000
-
#define T3_NIC_MBUF_POOL_ADDR_EXT_MEM 0x20000
/* DMA descriptor pool */
#define T3_NIC_DMA_DESC_POOL_ADDR 0x2000
-#define T3_NIC_DMA_DESC_POOL_SIZE 0x2000 /* 8KB. */
+#define T3_NIC_DMA_DESC_POOL_SIZE 0x2000 /* 8KB. */
#define T3_DEF_DMA_MBUF_LOW_WMARK 0x40
#define T3_DEF_RX_MAC_MBUF_LOW_WMARK 0x20
@@ -301,24 +297,21 @@ static __inline void writel(unsigned int b, unsigned int addr){
#define T3_TX_CPU_SPAD_ADDR 0x34000
#define T3_TX_CPU_SPAD_SIZE 0x4000
-typedef struct T3_DIR_ENTRY
-{
- PLM_UINT8 Buffer;
- LM_UINT32 Offset;
- LM_UINT32 Length;
-} T3_DIR_ENTRY,*PT3_DIR_ENTRY;
-
-typedef struct T3_FWIMG_INFO
-{
- LM_UINT32 StartAddress;
- T3_DIR_ENTRY Text;
- T3_DIR_ENTRY ROnlyData;
- T3_DIR_ENTRY Data;
- T3_DIR_ENTRY Sbss;
- T3_DIR_ENTRY Bss;
+typedef struct T3_DIR_ENTRY {
+ PLM_UINT8 Buffer;
+ LM_UINT32 Offset;
+ LM_UINT32 Length;
+} T3_DIR_ENTRY, *PT3_DIR_ENTRY;
+
+typedef struct T3_FWIMG_INFO {
+ LM_UINT32 StartAddress;
+ T3_DIR_ENTRY Text;
+ T3_DIR_ENTRY ROnlyData;
+ T3_DIR_ENTRY Data;
+ T3_DIR_ENTRY Sbss;
+ T3_DIR_ENTRY Bss;
} T3_FWIMG_INFO, *PT3_FWIMG_INFO;
-
/******************************************************************************/
/* Tigon3 PCI Registers. */
/******************************************************************************/
@@ -362,7 +355,6 @@ typedef struct T3_FWIMG_INFO
#define T3_ASIC_REV_5703 0x01
#define T3_ASIC_REV_5704 0x02
-
/* Chip id and revision. */
#define T3_CHIP_REV(_ChipRevId) ((_ChipRevId) >> 8)
#define T3_CHIP_REV_5700_AX 0x70
@@ -386,7 +378,6 @@ typedef struct T3_FWIMG_INFO
#define T3_PCI_POWER_DOWN_PCI_PLL133 BIT_15
#define T3_PCI_44MHZ_CORE_CLOCK BIT_18
-
#define T3_PCI_REG_ADDR_REG 0x78
#define T3_PCI_REG_DATA_REG 0x80
@@ -409,7 +400,6 @@ typedef struct T3_FWIMG_INFO
#define T3_PM_PME_ENABLE BIT_8
#define T3_PM_PME_ASSERTED BIT_15
-
/* PCI state register. */
#define T3_PCI_STATE_REG 0x70
@@ -419,17 +409,16 @@ typedef struct T3_FWIMG_INFO
#define T3_PCI_STATE_BUS_SPEED_HIGH BIT_3
#define T3_PCI_STATE_32BIT_PCI_BUS BIT_4
-
/* Broadcom subsystem/subvendor IDs. */
#define T3_SVID_BROADCOM 0x14e4
#define T3_SSID_BROADCOM_BCM95700A6 0x1644
#define T3_SSID_BROADCOM_BCM95701A5 0x0001
-#define T3_SSID_BROADCOM_BCM95700T6 0x0002 /* BCM8002 */
-#define T3_SSID_BROADCOM_BCM95700A9 0x0003 /* Agilent */
+#define T3_SSID_BROADCOM_BCM95700T6 0x0002 /* BCM8002 */
+#define T3_SSID_BROADCOM_BCM95700A9 0x0003 /* Agilent */
#define T3_SSID_BROADCOM_BCM95701T1 0x0005
#define T3_SSID_BROADCOM_BCM95701T8 0x0006
-#define T3_SSID_BROADCOM_BCM95701A7 0x0007 /* Agilent */
+#define T3_SSID_BROADCOM_BCM95701A7 0x0007 /* Agilent */
#define T3_SSID_BROADCOM_BCM95701A10 0x0008
#define T3_SSID_BROADCOM_BCM95701A12 0x8008
#define T3_SSID_BROADCOM_BCM95703Ax1 0x0009
@@ -449,7 +438,6 @@ typedef struct T3_FWIMG_INFO
#define T3_SSID_3COM_3C996SX 0x1004
#define T3_SSID_3COM_3C997SX 0x1005
-
/* Dell subsystem/subvendor IDs. */
#define T3_SVID_DELL 0x1028
@@ -469,7 +457,6 @@ typedef struct T3_FWIMG_INFO
#define T3_SSID_COMPAQ_NC7780 0x0085
#define T3_SSID_COMPAQ_NC7780_2 0x0099
-
/******************************************************************************/
/* MII registers. */
/******************************************************************************/
@@ -490,14 +477,12 @@ typedef struct T3_FWIMG_INFO
#define PHY_CTRL_LOOPBACK_MODE BIT_14
#define PHY_CTRL_PHY_RESET BIT_15
-
/* Status register. */
#define PHY_STATUS_REG 0x01
#define PHY_STATUS_LINK_PASS BIT_2
#define PHY_STATUS_AUTO_NEG_COMPLETE BIT_5
-
/* Phy Id registers. */
#define PHY_ID1_REG 0x02
#define PHY_ID1_OUI_MASK 0xffff
@@ -507,7 +492,6 @@ typedef struct T3_FWIMG_INFO
#define PHY_ID2_MODEL_MASK 0x03f0
#define PHY_ID2_OUI_MASK 0xfc00
-
/* Auto-negotiation advertisement register. */
#define PHY_AN_AD_REG 0x04
@@ -519,18 +503,15 @@ typedef struct T3_FWIMG_INFO
#define PHY_AN_AD_100BASETX_FULL BIT_8
#define PHY_AN_AD_PROTOCOL_802_3_CSMA_CD 0x01
-
/* Auto-negotiation Link Partner Ability register. */
#define PHY_LINK_PARTNER_ABILITY_REG 0x05
#define PHY_LINK_PARTNER_ASYM_PAUSE BIT_11
#define PHY_LINK_PARTNER_PAUSE_CAPABLE BIT_10
-
/* Auto-negotiation expansion register. */
#define PHY_AN_EXPANSION_REG 0x06
-
/******************************************************************************/
/* BCM5400 and BCM5401 phy info. */
/******************************************************************************/
@@ -557,7 +538,6 @@ typedef struct T3_FWIMG_INFO
#define PHY_ID_MASK (PHY_ID_OUI_MASK | \
PHY_ID_MODEL_MASK)
-
#define UNKNOWN_PHY_ID(x) ((((x) & PHY_ID_MASK) != PHY_BCM5400_PHY_ID) && \
(((x) & PHY_ID_MASK) != PHY_BCM5401_PHY_ID) && \
(((x) & PHY_ID_MASK) != PHY_BCM5411_PHY_ID) && \
@@ -566,7 +546,6 @@ typedef struct T3_FWIMG_INFO
(((x) & PHY_ID_MASK) != PHY_BCM5704_PHY_ID) && \
(((x) & PHY_ID_MASK) != PHY_BCM8002_PHY_ID))
-
/* 1000Base-T control register. */
#define BCM540X_1000BASET_CTRL_REG 0x09
@@ -575,7 +554,6 @@ typedef struct T3_FWIMG_INFO
#define BCM540X_CONFIG_AS_MASTER BIT_11
#define BCM540X_ENABLE_CONFIG_AS_MASTER BIT_12
-
/* Extended control register. */
#define BCM540X_EXT_CTRL_REG 0x10
@@ -587,11 +565,9 @@ typedef struct T3_FWIMG_INFO
#define BCM540X_EXT_STATUS_LINK_PASS BIT_8
-
/* DSP Coefficient Read/Write Port. */
#define BCM540X_DSP_RW_PORT 0x15
-
/* DSP Coeficient Address Register. */
#define BCM540X_DSP_ADDRESS_REG 0x17
@@ -631,7 +607,6 @@ typedef struct T3_FWIMG_INFO
#define BCM540X_CONTROL_ALL_CHANNELS BIT_15
-
/* Auxilliary Control Register (Shadow Register) */
#define BCM5401_AUX_CTRL 0x18
@@ -644,7 +619,6 @@ typedef struct T3_FWIMG_INFO
#define BCM5401_SHADOW_SEL_MISC_TEST2 0x05
#define BCM5401_SHADOW_SEL_IP_PHONE_SEED 0x06
-
/* Shadow register selector == '000' */
#define BCM5401_SHDW_NORMAL_DIAG_MODE BIT_3
#define BCM5401_SHDW_NORMAL_DISABLE_MBP BIT_4
@@ -664,7 +638,6 @@ typedef struct T3_FWIMG_INFO
#define BCM5401_SHDW_NORMAL_EXT_PACKET_LENGTH BIT_14
#define BCM5401_SHDW_NORMAL_EXTERNAL_LOOPBACK BIT_15
-
/* Auxilliary status summary. */
#define BCM540X_AUX_STATUS_REG 0x19
@@ -678,7 +651,6 @@ typedef struct T3_FWIMG_INFO
#define BCM540X_AUX_100BASET_HD (BIT_9 | BIT_10)
#define BCM540X_AUX_100BASET_FD (BIT_8 | BIT_9 | BIT_10)
-
/* Interrupt status. */
#define BCM540X_INT_STATUS_REG 0x1a
@@ -687,11 +659,9 @@ typedef struct T3_FWIMG_INFO
#define BCM540X_INT_DUPLEX_CHANGE BIT_3
#define BCM540X_INT_AUTO_NEG_PAGE_RX BIT_10
-
/* Interrupt mask register. */
#define BCM540X_INT_MASK_REG 0x1b
-
/******************************************************************************/
/* Register definitions. */
/******************************************************************************/
@@ -701,9 +671,9 @@ typedef volatile LM_UINT16 T3_16BIT_REGISTER, *PT3_16BIT_REGISTER;
typedef volatile LM_UINT32 T3_32BIT_REGISTER, *PT3_32BIT_REGISTER;
typedef struct {
- /* Big endian format. */
- T3_32BIT_REGISTER High;
- T3_32BIT_REGISTER Low;
+ /* Big endian format. */
+ T3_32BIT_REGISTER High;
+ T3_32BIT_REGISTER Low;
} T3_64BIT_REGISTER, *PT3_64BIT_REGISTER;
typedef T3_64BIT_REGISTER T3_64BIT_HOST_ADDR, *PT3_64BIT_HOST_ADDR;
@@ -711,47 +681,44 @@ typedef T3_64BIT_REGISTER T3_64BIT_HOST_ADDR, *PT3_64BIT_HOST_ADDR;
#define T3_NUM_OF_DMA_DESC 256
#define T3_NUM_OF_MBUF 768
-typedef struct
-{
- T3_64BIT_REGISTER host_addr;
- T3_32BIT_REGISTER nic_mbuf;
- T3_16BIT_REGISTER len;
- T3_16BIT_REGISTER cqid_sqid;
- T3_32BIT_REGISTER flags;
- T3_32BIT_REGISTER opaque1;
- T3_32BIT_REGISTER opaque2;
- T3_32BIT_REGISTER opaque3;
-}T3_DMA_DESC, *PT3_DMA_DESC;
-
+typedef struct {
+ T3_64BIT_REGISTER host_addr;
+ T3_32BIT_REGISTER nic_mbuf;
+ T3_16BIT_REGISTER len;
+ T3_16BIT_REGISTER cqid_sqid;
+ T3_32BIT_REGISTER flags;
+ T3_32BIT_REGISTER opaque1;
+ T3_32BIT_REGISTER opaque2;
+ T3_32BIT_REGISTER opaque3;
+} T3_DMA_DESC, *PT3_DMA_DESC;
/******************************************************************************/
/* Ring control block. */
/******************************************************************************/
typedef struct {
- T3_64BIT_REGISTER HostRingAddr;
+ T3_64BIT_REGISTER HostRingAddr;
- union {
- struct {
+ union {
+ struct {
#ifdef BIG_ENDIAN_HOST
- T3_16BIT_REGISTER MaxLen;
- T3_16BIT_REGISTER Flags;
-#else /* BIG_ENDIAN_HOST */
- T3_16BIT_REGISTER Flags;
- T3_16BIT_REGISTER MaxLen;
+ T3_16BIT_REGISTER MaxLen;
+ T3_16BIT_REGISTER Flags;
+#else /* BIG_ENDIAN_HOST */
+ T3_16BIT_REGISTER Flags;
+ T3_16BIT_REGISTER MaxLen;
#endif
- } s;
+ } s;
- T3_32BIT_REGISTER MaxLen_Flags;
- } u;
+ T3_32BIT_REGISTER MaxLen_Flags;
+ } u;
- T3_32BIT_REGISTER NicRingAddr;
+ T3_32BIT_REGISTER NicRingAddr;
} T3_RCB, *PT3_RCB;
#define T3_RCB_FLAG_USE_EXT_RECV_BD BIT_0
#define T3_RCB_FLAG_RING_DISABLED BIT_1
-
/******************************************************************************/
/* Status block. */
/******************************************************************************/
@@ -763,98 +730,95 @@ typedef struct {
#define T3_STATUS_BLOCK_SIZE 0x80
typedef struct {
- volatile LM_UINT32 Status;
- #define STATUS_BLOCK_UPDATED BIT_0
- #define STATUS_BLOCK_LINK_CHANGED_STATUS BIT_1
- #define STATUS_BLOCK_ERROR BIT_2
+ volatile LM_UINT32 Status;
+#define STATUS_BLOCK_UPDATED BIT_0
+#define STATUS_BLOCK_LINK_CHANGED_STATUS BIT_1
+#define STATUS_BLOCK_ERROR BIT_2
- volatile LM_UINT32 StatusTag;
+ volatile LM_UINT32 StatusTag;
#ifdef BIG_ENDIAN_HOST
- volatile LM_UINT16 RcvStdConIdx;
- volatile LM_UINT16 RcvJumboConIdx;
-
- volatile LM_UINT16 Reserved2;
- volatile LM_UINT16 RcvMiniConIdx;
-
- struct {
- volatile LM_UINT16 SendConIdx; /* Send consumer index. */
- volatile LM_UINT16 RcvProdIdx; /* Receive producer index. */
- } Idx[16];
-#else /* BIG_ENDIAN_HOST */
- volatile LM_UINT16 RcvJumboConIdx;
- volatile LM_UINT16 RcvStdConIdx;
-
- volatile LM_UINT16 RcvMiniConIdx;
- volatile LM_UINT16 Reserved2;
-
- struct {
- volatile LM_UINT16 RcvProdIdx; /* Receive producer index. */
- volatile LM_UINT16 SendConIdx; /* Send consumer index. */
- } Idx[16];
+ volatile LM_UINT16 RcvStdConIdx;
+ volatile LM_UINT16 RcvJumboConIdx;
+
+ volatile LM_UINT16 Reserved2;
+ volatile LM_UINT16 RcvMiniConIdx;
+
+ struct {
+ volatile LM_UINT16 SendConIdx; /* Send consumer index. */
+ volatile LM_UINT16 RcvProdIdx; /* Receive producer index. */
+ } Idx[16];
+#else /* BIG_ENDIAN_HOST */
+ volatile LM_UINT16 RcvJumboConIdx;
+ volatile LM_UINT16 RcvStdConIdx;
+
+ volatile LM_UINT16 RcvMiniConIdx;
+ volatile LM_UINT16 Reserved2;
+
+ struct {
+ volatile LM_UINT16 RcvProdIdx; /* Receive producer index. */
+ volatile LM_UINT16 SendConIdx; /* Send consumer index. */
+ } Idx[16];
#endif
} T3_STATUS_BLOCK, *PT3_STATUS_BLOCK;
-
/******************************************************************************/
/* Receive buffer descriptors. */
/******************************************************************************/
typedef struct {
- T3_64BIT_HOST_ADDR HostAddr;
+ T3_64BIT_HOST_ADDR HostAddr;
#ifdef BIG_ENDIAN_HOST
- volatile LM_UINT16 Index;
- volatile LM_UINT16 Len;
+ volatile LM_UINT16 Index;
+ volatile LM_UINT16 Len;
- volatile LM_UINT16 Type;
- volatile LM_UINT16 Flags;
+ volatile LM_UINT16 Type;
+ volatile LM_UINT16 Flags;
- volatile LM_UINT16 IpCksum;
- volatile LM_UINT16 TcpUdpCksum;
+ volatile LM_UINT16 IpCksum;
+ volatile LM_UINT16 TcpUdpCksum;
- volatile LM_UINT16 ErrorFlag;
- volatile LM_UINT16 VlanTag;
-#else /* BIG_ENDIAN_HOST */
- volatile LM_UINT16 Len;
- volatile LM_UINT16 Index;
+ volatile LM_UINT16 ErrorFlag;
+ volatile LM_UINT16 VlanTag;
+#else /* BIG_ENDIAN_HOST */
+ volatile LM_UINT16 Len;
+ volatile LM_UINT16 Index;
- volatile LM_UINT16 Flags;
- volatile LM_UINT16 Type;
+ volatile LM_UINT16 Flags;
+ volatile LM_UINT16 Type;
- volatile LM_UINT16 TcpUdpCksum;
- volatile LM_UINT16 IpCksum;
+ volatile LM_UINT16 TcpUdpCksum;
+ volatile LM_UINT16 IpCksum;
- volatile LM_UINT16 VlanTag;
- volatile LM_UINT16 ErrorFlag;
+ volatile LM_UINT16 VlanTag;
+ volatile LM_UINT16 ErrorFlag;
#endif
- volatile LM_UINT32 Reserved;
- volatile LM_UINT32 Opaque;
+ volatile LM_UINT32 Reserved;
+ volatile LM_UINT32 Opaque;
} T3_RCV_BD, *PT3_RCV_BD;
-
typedef struct {
- T3_64BIT_HOST_ADDR HostAddr[3];
+ T3_64BIT_HOST_ADDR HostAddr[3];
#ifdef BIG_ENDIAN_HOST
- LM_UINT16 Len1;
- LM_UINT16 Len2;
+ LM_UINT16 Len1;
+ LM_UINT16 Len2;
- LM_UINT16 Len3;
- LM_UINT16 Reserved1;
-#else /* BIG_ENDIAN_HOST */
- LM_UINT16 Len2;
- LM_UINT16 Len1;
+ LM_UINT16 Len3;
+ LM_UINT16 Reserved1;
+#else /* BIG_ENDIAN_HOST */
+ LM_UINT16 Len2;
+ LM_UINT16 Len1;
- LM_UINT16 Reserved1;
- LM_UINT16 Len3;
+ LM_UINT16 Reserved1;
+ LM_UINT16 Len3;
#endif
- T3_RCV_BD StdRcvBd;
+ T3_RCV_BD StdRcvBd;
} T3_EXT_RCV_BD, *PT3_EXT_RCV_BD;
-
/* Error flags. */
#define RCV_BD_ERR_BAD_CRC 0x0001
#define RCV_BD_ERR_COLL_DETECT 0x0002
@@ -866,7 +830,6 @@ typedef struct {
#define RCV_BD_ERR_TRUNC_NO_RESOURCES 0x0080
#define RCV_BD_ERR_GIANT_FRAME_RCVD 0x0100
-
/* Buffer descriptor flags. */
#define RCV_BD_FLAG_END 0x0004
#define RCV_BD_FLAG_JUMBO_RING 0x0020
@@ -877,44 +840,42 @@ typedef struct {
#define RCV_BD_FLAG_TCP_UDP_CHKSUM_FIELD 0x2000
#define RCV_BD_FLAG_TCP_PACKET 0x4000
-
/******************************************************************************/
/* Send buffer descriptor. */
/******************************************************************************/
typedef struct {
- T3_64BIT_HOST_ADDR HostAddr;
+ T3_64BIT_HOST_ADDR HostAddr;
- union {
- struct {
+ union {
+ struct {
#ifdef BIG_ENDIAN_HOST
- LM_UINT16 Len;
- LM_UINT16 Flags;
-#else /* BIG_ENDIAN_HOST */
- LM_UINT16 Flags;
- LM_UINT16 Len;
+ LM_UINT16 Len;
+ LM_UINT16 Flags;
+#else /* BIG_ENDIAN_HOST */
+ LM_UINT16 Flags;
+ LM_UINT16 Len;
#endif
- } s1;
+ } s1;
- LM_UINT32 Len_Flags;
- } u1;
+ LM_UINT32 Len_Flags;
+ } u1;
- union {
- struct {
+ union {
+ struct {
#ifdef BIG_ENDIAN_HOST
- LM_UINT16 Reserved;
- LM_UINT16 VlanTag;
-#else /* BIG_ENDIAN_HOST */
- LM_UINT16 VlanTag;
- LM_UINT16 Reserved;
+ LM_UINT16 Reserved;
+ LM_UINT16 VlanTag;
+#else /* BIG_ENDIAN_HOST */
+ LM_UINT16 VlanTag;
+ LM_UINT16 Reserved;
#endif
- } s2;
+ } s2;
- LM_UINT32 VlanTag;
- } u2;
+ LM_UINT32 VlanTag;
+ } u2;
} T3_SND_BD, *PT3_SND_BD;
-
/* Send buffer descriptor flags. */
#define SND_BD_FLAG_TCP_UDP_CKSUM 0x0001
#define SND_BD_FLAG_IP_CKSUM 0x0002
@@ -932,435 +893,426 @@ typedef struct {
/* MBUFs */
typedef struct T3_MBUF_FRAME_DESC {
#ifdef BIG_ENDIAN_HOST
- LM_UINT32 status_control;
- union {
- struct {
- LM_UINT8 cqid;
- LM_UINT8 reserved1;
- LM_UINT16 length;
- }s1;
- LM_UINT32 word;
- }u1;
- union {
- struct
- {
- LM_UINT16 ip_hdr_start;
- LM_UINT16 tcp_udp_hdr_start;
- }s2;
-
- LM_UINT32 word;
- }u2;
-
- union {
- struct {
- LM_UINT16 data_start;
- LM_UINT16 vlan_id;
- }s3;
-
- LM_UINT32 word;
- }u3;
-
- union {
- struct {
- LM_UINT16 ip_checksum;
- LM_UINT16 tcp_udp_checksum;
- }s4;
-
- LM_UINT32 word;
- }u4;
-
- union {
- struct {
- LM_UINT16 pseudo_checksum;
- LM_UINT16 checksum_status;
- }s5;
-
- LM_UINT32 word;
- }u5;
-
- union {
- struct {
- LM_UINT16 rule_match;
- LM_UINT8 class;
- LM_UINT8 rupt;
- }s6;
-
- LM_UINT32 word;
- }u6;
-
- union {
- struct {
- LM_UINT16 reserved2;
- LM_UINT16 mbuf_num;
- }s7;
-
- LM_UINT32 word;
- }u7;
-
- LM_UINT32 reserved3;
- LM_UINT32 reserved4;
+ LM_UINT32 status_control;
+ union {
+ struct {
+ LM_UINT8 cqid;
+ LM_UINT8 reserved1;
+ LM_UINT16 length;
+ } s1;
+ LM_UINT32 word;
+ } u1;
+ union {
+ struct {
+ LM_UINT16 ip_hdr_start;
+ LM_UINT16 tcp_udp_hdr_start;
+ } s2;
+
+ LM_UINT32 word;
+ } u2;
+
+ union {
+ struct {
+ LM_UINT16 data_start;
+ LM_UINT16 vlan_id;
+ } s3;
+
+ LM_UINT32 word;
+ } u3;
+
+ union {
+ struct {
+ LM_UINT16 ip_checksum;
+ LM_UINT16 tcp_udp_checksum;
+ } s4;
+
+ LM_UINT32 word;
+ } u4;
+
+ union {
+ struct {
+ LM_UINT16 pseudo_checksum;
+ LM_UINT16 checksum_status;
+ } s5;
+
+ LM_UINT32 word;
+ } u5;
+
+ union {
+ struct {
+ LM_UINT16 rule_match;
+ LM_UINT8 class;
+ LM_UINT8 rupt;
+ } s6;
+
+ LM_UINT32 word;
+ } u6;
+
+ union {
+ struct {
+ LM_UINT16 reserved2;
+ LM_UINT16 mbuf_num;
+ } s7;
+
+ LM_UINT32 word;
+ } u7;
+
+ LM_UINT32 reserved3;
+ LM_UINT32 reserved4;
#else
- LM_UINT32 status_control;
- union {
- struct {
- LM_UINT16 length;
- LM_UINT8 reserved1;
- LM_UINT8 cqid;
- }s1;
- LM_UINT32 word;
- }u1;
- union {
- struct
- {
- LM_UINT16 tcp_udp_hdr_start;
- LM_UINT16 ip_hdr_start;
- }s2;
-
- LM_UINT32 word;
- }u2;
-
- union {
- struct {
- LM_UINT16 vlan_id;
- LM_UINT16 data_start;
- }s3;
-
- LM_UINT32 word;
- }u3;
-
- union {
- struct {
- LM_UINT16 tcp_udp_checksum;
- LM_UINT16 ip_checksum;
- }s4;
-
- LM_UINT32 word;
- }u4;
-
- union {
- struct {
- LM_UINT16 checksum_status;
- LM_UINT16 pseudo_checksum;
- }s5;
-
- LM_UINT32 word;
- }u5;
-
- union {
- struct {
- LM_UINT8 rupt;
- LM_UINT8 class;
- LM_UINT16 rule_match;
- }s6;
-
- LM_UINT32 word;
- }u6;
-
- union {
- struct {
- LM_UINT16 mbuf_num;
- LM_UINT16 reserved2;
- }s7;
-
- LM_UINT32 word;
- }u7;
-
- LM_UINT32 reserved3;
- LM_UINT32 reserved4;
+ LM_UINT32 status_control;
+ union {
+ struct {
+ LM_UINT16 length;
+ LM_UINT8 reserved1;
+ LM_UINT8 cqid;
+ } s1;
+ LM_UINT32 word;
+ } u1;
+ union {
+ struct {
+ LM_UINT16 tcp_udp_hdr_start;
+ LM_UINT16 ip_hdr_start;
+ } s2;
+
+ LM_UINT32 word;
+ } u2;
+
+ union {
+ struct {
+ LM_UINT16 vlan_id;
+ LM_UINT16 data_start;
+ } s3;
+
+ LM_UINT32 word;
+ } u3;
+
+ union {
+ struct {
+ LM_UINT16 tcp_udp_checksum;
+ LM_UINT16 ip_checksum;
+ } s4;
+
+ LM_UINT32 word;
+ } u4;
+
+ union {
+ struct {
+ LM_UINT16 checksum_status;
+ LM_UINT16 pseudo_checksum;
+ } s5;
+
+ LM_UINT32 word;
+ } u5;
+
+ union {
+ struct {
+ LM_UINT8 rupt;
+ LM_UINT8 class;
+ LM_UINT16 rule_match;
+ } s6;
+
+ LM_UINT32 word;
+ } u6;
+
+ union {
+ struct {
+ LM_UINT16 mbuf_num;
+ LM_UINT16 reserved2;
+ } s7;
+
+ LM_UINT32 word;
+ } u7;
+
+ LM_UINT32 reserved3;
+ LM_UINT32 reserved4;
#endif
-}T3_MBUF_FRAME_DESC,*PT3_MBUF_FRAME_DESC;
+} T3_MBUF_FRAME_DESC, *PT3_MBUF_FRAME_DESC;
typedef struct T3_MBUF_HDR {
- union {
- struct {
- unsigned int C:1;
- unsigned int F:1;
- unsigned int reserved1:7;
- unsigned int next_mbuf:16;
- unsigned int length:7;
- }s1;
-
- LM_UINT32 word;
- }u1;
-
- LM_UINT32 next_frame_ptr;
-}T3_MBUF_HDR, *PT3_MBUF_HDR;
-
-typedef struct T3_MBUF
-{
- T3_MBUF_HDR hdr;
- union
- {
- struct {
- T3_MBUF_FRAME_DESC frame_hdr;
- LM_UINT32 data[20];
- }s1;
-
- struct {
- LM_UINT32 data[30];
- }s2;
- }body;
-}T3_MBUF, *PT3_MBUF;
+ union {
+ struct {
+ unsigned int C:1;
+ unsigned int F:1;
+ unsigned int reserved1:7;
+ unsigned int next_mbuf:16;
+ unsigned int length:7;
+ } s1;
+
+ LM_UINT32 word;
+ } u1;
+
+ LM_UINT32 next_frame_ptr;
+} T3_MBUF_HDR, *PT3_MBUF_HDR;
+
+typedef struct T3_MBUF {
+ T3_MBUF_HDR hdr;
+ union {
+ struct {
+ T3_MBUF_FRAME_DESC frame_hdr;
+ LM_UINT32 data[20];
+ } s1;
+
+ struct {
+ LM_UINT32 data[30];
+ } s2;
+ } body;
+} T3_MBUF, *PT3_MBUF;
#define T3_MBUF_BASE (T3_NIC_MBUF_POOL_ADDR >> 7)
#define T3_MBUF_END ((T3_NIC_MBUF_POOL_ADDR + T3_NIC_MBUF_POOL_SIZE) >> 7)
-
/******************************************************************************/
/* Statistics block. */
/******************************************************************************/
typedef struct {
- LM_UINT8 Reserved0[0x400-0x300];
-
- /* Statistics maintained by Receive MAC. */
- T3_64BIT_REGISTER ifHCInOctets;
- T3_64BIT_REGISTER Reserved1;
- T3_64BIT_REGISTER etherStatsFragments;
- T3_64BIT_REGISTER ifHCInUcastPkts;
- T3_64BIT_REGISTER ifHCInMulticastPkts;
- T3_64BIT_REGISTER ifHCInBroadcastPkts;
- T3_64BIT_REGISTER dot3StatsFCSErrors;
- T3_64BIT_REGISTER dot3StatsAlignmentErrors;
- T3_64BIT_REGISTER xonPauseFramesReceived;
- T3_64BIT_REGISTER xoffPauseFramesReceived;
- T3_64BIT_REGISTER macControlFramesReceived;
- T3_64BIT_REGISTER xoffStateEntered;
- T3_64BIT_REGISTER dot3StatsFramesTooLong;
- T3_64BIT_REGISTER etherStatsJabbers;
- T3_64BIT_REGISTER etherStatsUndersizePkts;
- T3_64BIT_REGISTER inRangeLengthError;
- T3_64BIT_REGISTER outRangeLengthError;
- T3_64BIT_REGISTER etherStatsPkts64Octets;
- T3_64BIT_REGISTER etherStatsPkts65Octetsto127Octets;
- T3_64BIT_REGISTER etherStatsPkts128Octetsto255Octets;
- T3_64BIT_REGISTER etherStatsPkts256Octetsto511Octets;
- T3_64BIT_REGISTER etherStatsPkts512Octetsto1023Octets;
- T3_64BIT_REGISTER etherStatsPkts1024Octetsto1522Octets;
- T3_64BIT_REGISTER etherStatsPkts1523Octetsto2047Octets;
- T3_64BIT_REGISTER etherStatsPkts2048Octetsto4095Octets;
- T3_64BIT_REGISTER etherStatsPkts4096Octetsto8191Octets;
- T3_64BIT_REGISTER etherStatsPkts8192Octetsto9022Octets;
-
- T3_64BIT_REGISTER Unused1[37];
-
- /* Statistics maintained by Transmit MAC. */
- T3_64BIT_REGISTER ifHCOutOctets;
- T3_64BIT_REGISTER Reserved2;
- T3_64BIT_REGISTER etherStatsCollisions;
- T3_64BIT_REGISTER outXonSent;
- T3_64BIT_REGISTER outXoffSent;
- T3_64BIT_REGISTER flowControlDone;
- T3_64BIT_REGISTER dot3StatsInternalMacTransmitErrors;
- T3_64BIT_REGISTER dot3StatsSingleCollisionFrames;
- T3_64BIT_REGISTER dot3StatsMultipleCollisionFrames;
- T3_64BIT_REGISTER dot3StatsDeferredTransmissions;
- T3_64BIT_REGISTER Reserved3;
- T3_64BIT_REGISTER dot3StatsExcessiveCollisions;
- T3_64BIT_REGISTER dot3StatsLateCollisions;
- T3_64BIT_REGISTER dot3Collided2Times;
- T3_64BIT_REGISTER dot3Collided3Times;
- T3_64BIT_REGISTER dot3Collided4Times;
- T3_64BIT_REGISTER dot3Collided5Times;
- T3_64BIT_REGISTER dot3Collided6Times;
- T3_64BIT_REGISTER dot3Collided7Times;
- T3_64BIT_REGISTER dot3Collided8Times;
- T3_64BIT_REGISTER dot3Collided9Times;
- T3_64BIT_REGISTER dot3Collided10Times;
- T3_64BIT_REGISTER dot3Collided11Times;
- T3_64BIT_REGISTER dot3Collided12Times;
- T3_64BIT_REGISTER dot3Collided13Times;
- T3_64BIT_REGISTER dot3Collided14Times;
- T3_64BIT_REGISTER dot3Collided15Times;
- T3_64BIT_REGISTER ifHCOutUcastPkts;
- T3_64BIT_REGISTER ifHCOutMulticastPkts;
- T3_64BIT_REGISTER ifHCOutBroadcastPkts;
- T3_64BIT_REGISTER dot3StatsCarrierSenseErrors;
- T3_64BIT_REGISTER ifOutDiscards;
- T3_64BIT_REGISTER ifOutErrors;
-
- T3_64BIT_REGISTER Unused2[31];
-
- /* Statistics maintained by Receive List Placement. */
- T3_64BIT_REGISTER COSIfHCInPkts[16];
- T3_64BIT_REGISTER COSFramesDroppedDueToFilters;
- T3_64BIT_REGISTER nicDmaWriteQueueFull;
- T3_64BIT_REGISTER nicDmaWriteHighPriQueueFull;
- T3_64BIT_REGISTER nicNoMoreRxBDs;
- T3_64BIT_REGISTER ifInDiscards;
- T3_64BIT_REGISTER ifInErrors;
- T3_64BIT_REGISTER nicRecvThresholdHit;
-
- T3_64BIT_REGISTER Unused3[9];
-
- /* Statistics maintained by Send Data Initiator. */
- T3_64BIT_REGISTER COSIfHCOutPkts[16];
- T3_64BIT_REGISTER nicDmaReadQueueFull;
- T3_64BIT_REGISTER nicDmaReadHighPriQueueFull;
- T3_64BIT_REGISTER nicSendDataCompQueueFull;
-
- /* Statistics maintained by Host Coalescing. */
- T3_64BIT_REGISTER nicRingSetSendProdIndex;
- T3_64BIT_REGISTER nicRingStatusUpdate;
- T3_64BIT_REGISTER nicInterrupts;
- T3_64BIT_REGISTER nicAvoidedInterrupts;
- T3_64BIT_REGISTER nicSendThresholdHit;
-
- LM_UINT8 Reserved4[0xb00-0x9c0];
+ LM_UINT8 Reserved0[0x400 - 0x300];
+
+ /* Statistics maintained by Receive MAC. */
+ T3_64BIT_REGISTER ifHCInOctets;
+ T3_64BIT_REGISTER Reserved1;
+ T3_64BIT_REGISTER etherStatsFragments;
+ T3_64BIT_REGISTER ifHCInUcastPkts;
+ T3_64BIT_REGISTER ifHCInMulticastPkts;
+ T3_64BIT_REGISTER ifHCInBroadcastPkts;
+ T3_64BIT_REGISTER dot3StatsFCSErrors;
+ T3_64BIT_REGISTER dot3StatsAlignmentErrors;
+ T3_64BIT_REGISTER xonPauseFramesReceived;
+ T3_64BIT_REGISTER xoffPauseFramesReceived;
+ T3_64BIT_REGISTER macControlFramesReceived;
+ T3_64BIT_REGISTER xoffStateEntered;
+ T3_64BIT_REGISTER dot3StatsFramesTooLong;
+ T3_64BIT_REGISTER etherStatsJabbers;
+ T3_64BIT_REGISTER etherStatsUndersizePkts;
+ T3_64BIT_REGISTER inRangeLengthError;
+ T3_64BIT_REGISTER outRangeLengthError;
+ T3_64BIT_REGISTER etherStatsPkts64Octets;
+ T3_64BIT_REGISTER etherStatsPkts65Octetsto127Octets;
+ T3_64BIT_REGISTER etherStatsPkts128Octetsto255Octets;
+ T3_64BIT_REGISTER etherStatsPkts256Octetsto511Octets;
+ T3_64BIT_REGISTER etherStatsPkts512Octetsto1023Octets;
+ T3_64BIT_REGISTER etherStatsPkts1024Octetsto1522Octets;
+ T3_64BIT_REGISTER etherStatsPkts1523Octetsto2047Octets;
+ T3_64BIT_REGISTER etherStatsPkts2048Octetsto4095Octets;
+ T3_64BIT_REGISTER etherStatsPkts4096Octetsto8191Octets;
+ T3_64BIT_REGISTER etherStatsPkts8192Octetsto9022Octets;
+
+ T3_64BIT_REGISTER Unused1[37];
+
+ /* Statistics maintained by Transmit MAC. */
+ T3_64BIT_REGISTER ifHCOutOctets;
+ T3_64BIT_REGISTER Reserved2;
+ T3_64BIT_REGISTER etherStatsCollisions;
+ T3_64BIT_REGISTER outXonSent;
+ T3_64BIT_REGISTER outXoffSent;
+ T3_64BIT_REGISTER flowControlDone;
+ T3_64BIT_REGISTER dot3StatsInternalMacTransmitErrors;
+ T3_64BIT_REGISTER dot3StatsSingleCollisionFrames;
+ T3_64BIT_REGISTER dot3StatsMultipleCollisionFrames;
+ T3_64BIT_REGISTER dot3StatsDeferredTransmissions;
+ T3_64BIT_REGISTER Reserved3;
+ T3_64BIT_REGISTER dot3StatsExcessiveCollisions;
+ T3_64BIT_REGISTER dot3StatsLateCollisions;
+ T3_64BIT_REGISTER dot3Collided2Times;
+ T3_64BIT_REGISTER dot3Collided3Times;
+ T3_64BIT_REGISTER dot3Collided4Times;
+ T3_64BIT_REGISTER dot3Collided5Times;
+ T3_64BIT_REGISTER dot3Collided6Times;
+ T3_64BIT_REGISTER dot3Collided7Times;
+ T3_64BIT_REGISTER dot3Collided8Times;
+ T3_64BIT_REGISTER dot3Collided9Times;
+ T3_64BIT_REGISTER dot3Collided10Times;
+ T3_64BIT_REGISTER dot3Collided11Times;
+ T3_64BIT_REGISTER dot3Collided12Times;
+ T3_64BIT_REGISTER dot3Collided13Times;
+ T3_64BIT_REGISTER dot3Collided14Times;
+ T3_64BIT_REGISTER dot3Collided15Times;
+ T3_64BIT_REGISTER ifHCOutUcastPkts;
+ T3_64BIT_REGISTER ifHCOutMulticastPkts;
+ T3_64BIT_REGISTER ifHCOutBroadcastPkts;
+ T3_64BIT_REGISTER dot3StatsCarrierSenseErrors;
+ T3_64BIT_REGISTER ifOutDiscards;
+ T3_64BIT_REGISTER ifOutErrors;
+
+ T3_64BIT_REGISTER Unused2[31];
+
+ /* Statistics maintained by Receive List Placement. */
+ T3_64BIT_REGISTER COSIfHCInPkts[16];
+ T3_64BIT_REGISTER COSFramesDroppedDueToFilters;
+ T3_64BIT_REGISTER nicDmaWriteQueueFull;
+ T3_64BIT_REGISTER nicDmaWriteHighPriQueueFull;
+ T3_64BIT_REGISTER nicNoMoreRxBDs;
+ T3_64BIT_REGISTER ifInDiscards;
+ T3_64BIT_REGISTER ifInErrors;
+ T3_64BIT_REGISTER nicRecvThresholdHit;
+
+ T3_64BIT_REGISTER Unused3[9];
+
+ /* Statistics maintained by Send Data Initiator. */
+ T3_64BIT_REGISTER COSIfHCOutPkts[16];
+ T3_64BIT_REGISTER nicDmaReadQueueFull;
+ T3_64BIT_REGISTER nicDmaReadHighPriQueueFull;
+ T3_64BIT_REGISTER nicSendDataCompQueueFull;
+
+ /* Statistics maintained by Host Coalescing. */
+ T3_64BIT_REGISTER nicRingSetSendProdIndex;
+ T3_64BIT_REGISTER nicRingStatusUpdate;
+ T3_64BIT_REGISTER nicInterrupts;
+ T3_64BIT_REGISTER nicAvoidedInterrupts;
+ T3_64BIT_REGISTER nicSendThresholdHit;
+
+ LM_UINT8 Reserved4[0xb00 - 0x9c0];
} T3_STATS_BLOCK, *PT3_STATS_BLOCK;
-
/******************************************************************************/
/* PCI configuration registers. */
/******************************************************************************/
typedef struct {
- T3_16BIT_REGISTER VendorId;
- T3_16BIT_REGISTER DeviceId;
-
- T3_16BIT_REGISTER Command;
- T3_16BIT_REGISTER Status;
-
- T3_32BIT_REGISTER ClassCodeRevId;
-
- T3_8BIT_REGISTER CacheLineSize;
- T3_8BIT_REGISTER LatencyTimer;
- T3_8BIT_REGISTER HeaderType;
- T3_8BIT_REGISTER Bist;
-
- T3_32BIT_REGISTER MemBaseAddrLow;
- T3_32BIT_REGISTER MemBaseAddrHigh;
-
- LM_UINT8 Unused1[20];
-
- T3_16BIT_REGISTER SubsystemVendorId;
- T3_16BIT_REGISTER SubsystemId;
-
- T3_32BIT_REGISTER RomBaseAddr;
-
- T3_8BIT_REGISTER PciXCapiblityPtr;
- LM_UINT8 Unused2[7];
-
- T3_8BIT_REGISTER IntLine;
- T3_8BIT_REGISTER IntPin;
- T3_8BIT_REGISTER MinGnt;
- T3_8BIT_REGISTER MaxLat;
-
- T3_8BIT_REGISTER PciXCapabilities;
- T3_8BIT_REGISTER PmCapabilityPtr;
- T3_16BIT_REGISTER PciXCommand;
-
- T3_32BIT_REGISTER PciXStatus;
-
- T3_8BIT_REGISTER PmCapabilityId;
- T3_8BIT_REGISTER VpdCapabilityPtr;
- T3_16BIT_REGISTER PmCapabilities;
-
- T3_16BIT_REGISTER PmCtrlStatus;
- #define PM_CTRL_PME_STATUS BIT_15
- #define PM_CTRL_PME_ENABLE BIT_8
- #define PM_CTRL_PME_POWER_STATE_D0 0
- #define PM_CTRL_PME_POWER_STATE_D1 1
- #define PM_CTRL_PME_POWER_STATE_D2 2
- #define PM_CTRL_PME_POWER_STATE_D3H 3
-
- T3_8BIT_REGISTER BridgeSupportExt;
- T3_8BIT_REGISTER PmData;
-
- T3_8BIT_REGISTER VpdCapabilityId;
- T3_8BIT_REGISTER MsiCapabilityPtr;
- T3_16BIT_REGISTER VpdAddrFlag;
- #define VPD_FLAG_WRITE (1 << 15)
- #define VPD_FLAG_RW_MASK (1 << 15)
- #define VPD_FLAG_READ 0
-
-
- T3_32BIT_REGISTER VpdData;
-
- T3_8BIT_REGISTER MsiCapabilityId;
- T3_8BIT_REGISTER NextCapabilityPtr;
- T3_16BIT_REGISTER MsiCtrl;
- #define MSI_CTRL_64BIT_CAP (1 << 7)
- #define MSI_CTRL_MSG_ENABLE(x) (x << 4)
- #define MSI_CTRL_MSG_CAP(x) (x << 1)
- #define MSI_CTRL_ENABLE (1 << 0)
-
-
- T3_32BIT_REGISTER MsiAddrLow;
- T3_32BIT_REGISTER MsiAddrHigh;
-
- T3_16BIT_REGISTER MsiData;
- T3_16BIT_REGISTER Unused3;
-
- T3_32BIT_REGISTER MiscHostCtrl;
- #define MISC_HOST_CTRL_CLEAR_INT BIT_0
- #define MISC_HOST_CTRL_MASK_PCI_INT BIT_1
- #define MISC_HOST_CTRL_ENABLE_ENDIAN_BYTE_SWAP BIT_2
- #define MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP BIT_3
- #define MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW BIT_4
- #define MISC_HOST_CTRL_ENABLE_CLK_REG_RW BIT_5
- #define MISC_HOST_CTRL_ENABLE_REG_WORD_SWAP BIT_6
- #define MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS BIT_7
- #define MISC_HOST_CTRL_ENABLE_INT_MASK_MODE BIT_8
- #define MISC_HOST_CTRL_ENABLE_TAGGED_STATUS_MODE BIT_9
-
- T3_32BIT_REGISTER DmaReadWriteCtrl;
- #define DMA_CTRL_WRITE_BOUNDARY_MASK (BIT_11 | BIT_12 | BIT_13)
- #define DMA_CTRL_WRITE_BOUNDARY_DISABLE 0
- #define DMA_CTRL_WRITE_BOUNDARY_16 BIT_11
- #define DMA_CTRL_WRITE_BOUNDARY_32 BIT_12
- #define DMA_CTRL_WRITE_BOUNDARY_64 (BIT_12 | BIT_11)
- #define DMA_CTRL_WRITE_BOUNDARY_128 BIT_13
- #define DMA_CTRL_WRITE_BOUNDARY_256 (BIT_13 | BIT_11)
- #define DMA_CTRL_WRITE_BOUNDARY_512 (BIT_13 | BIT_12)
- #define DMA_CTRL_WRITE_BOUNDARY_1024 (BIT_13 | BIT_12 | BIT_11)
- #define DMA_CTRL_WRITE_ONE_DMA_AT_ONCE BIT_14
-
-
- T3_32BIT_REGISTER PciState;
- #define T3_PCI_STATE_FORCE_PCI_RESET BIT_0
- #define T3_PCI_STATE_INTERRUPT_NOT_ACTIVE BIT_1
- #define T3_PCI_STATE_NOT_PCI_X_BUS BIT_2
- #define T3_PCI_STATE_HIGH_BUS_SPEED BIT_3
- #define T3_PCI_STATE_32BIT_PCI_BUS BIT_4
- #define T3_PCI_STATE_PCI_ROM_ENABLE BIT_5
- #define T3_PCI_STATE_PCI_ROM_RETRY_ENABLE BIT_6
- #define T3_PCI_STATE_FLAT_VIEW BIT_8
- #define T3_PCI_STATE_RETRY_SAME_DMA BIT_13
-
- T3_32BIT_REGISTER ClockCtrl;
- #define T3_PCI_CLKCTRL_TXCPU_CLK_DISABLE BIT_11
- #define T3_PCI_CLKCTRL_RXCPU_CLK_DISABLE BIT_10
- #define T3_PCI_CLKCTRL_CORE_CLK_DISABLE BIT_9
-
- T3_32BIT_REGISTER RegBaseAddr;
-
- T3_32BIT_REGISTER MemWindowBaseAddr;
+ T3_16BIT_REGISTER VendorId;
+ T3_16BIT_REGISTER DeviceId;
+
+ T3_16BIT_REGISTER Command;
+ T3_16BIT_REGISTER Status;
+
+ T3_32BIT_REGISTER ClassCodeRevId;
+
+ T3_8BIT_REGISTER CacheLineSize;
+ T3_8BIT_REGISTER LatencyTimer;
+ T3_8BIT_REGISTER HeaderType;
+ T3_8BIT_REGISTER Bist;
+
+ T3_32BIT_REGISTER MemBaseAddrLow;
+ T3_32BIT_REGISTER MemBaseAddrHigh;
+
+ LM_UINT8 Unused1[20];
+
+ T3_16BIT_REGISTER SubsystemVendorId;
+ T3_16BIT_REGISTER SubsystemId;
+
+ T3_32BIT_REGISTER RomBaseAddr;
+
+ T3_8BIT_REGISTER PciXCapiblityPtr;
+ LM_UINT8 Unused2[7];
+
+ T3_8BIT_REGISTER IntLine;
+ T3_8BIT_REGISTER IntPin;
+ T3_8BIT_REGISTER MinGnt;
+ T3_8BIT_REGISTER MaxLat;
+
+ T3_8BIT_REGISTER PciXCapabilities;
+ T3_8BIT_REGISTER PmCapabilityPtr;
+ T3_16BIT_REGISTER PciXCommand;
+
+ T3_32BIT_REGISTER PciXStatus;
+
+ T3_8BIT_REGISTER PmCapabilityId;
+ T3_8BIT_REGISTER VpdCapabilityPtr;
+ T3_16BIT_REGISTER PmCapabilities;
+
+ T3_16BIT_REGISTER PmCtrlStatus;
+#define PM_CTRL_PME_STATUS BIT_15
+#define PM_CTRL_PME_ENABLE BIT_8
+#define PM_CTRL_PME_POWER_STATE_D0 0
+#define PM_CTRL_PME_POWER_STATE_D1 1
+#define PM_CTRL_PME_POWER_STATE_D2 2
+#define PM_CTRL_PME_POWER_STATE_D3H 3
+
+ T3_8BIT_REGISTER BridgeSupportExt;
+ T3_8BIT_REGISTER PmData;
+
+ T3_8BIT_REGISTER VpdCapabilityId;
+ T3_8BIT_REGISTER MsiCapabilityPtr;
+ T3_16BIT_REGISTER VpdAddrFlag;
+#define VPD_FLAG_WRITE (1 << 15)
+#define VPD_FLAG_RW_MASK (1 << 15)
+#define VPD_FLAG_READ 0
+
+ T3_32BIT_REGISTER VpdData;
+
+ T3_8BIT_REGISTER MsiCapabilityId;
+ T3_8BIT_REGISTER NextCapabilityPtr;
+ T3_16BIT_REGISTER MsiCtrl;
+#define MSI_CTRL_64BIT_CAP (1 << 7)
+#define MSI_CTRL_MSG_ENABLE(x) (x << 4)
+#define MSI_CTRL_MSG_CAP(x) (x << 1)
+#define MSI_CTRL_ENABLE (1 << 0)
+
+ T3_32BIT_REGISTER MsiAddrLow;
+ T3_32BIT_REGISTER MsiAddrHigh;
+
+ T3_16BIT_REGISTER MsiData;
+ T3_16BIT_REGISTER Unused3;
+
+ T3_32BIT_REGISTER MiscHostCtrl;
+#define MISC_HOST_CTRL_CLEAR_INT BIT_0
+#define MISC_HOST_CTRL_MASK_PCI_INT BIT_1
+#define MISC_HOST_CTRL_ENABLE_ENDIAN_BYTE_SWAP BIT_2
+#define MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP BIT_3
+#define MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW BIT_4
+#define MISC_HOST_CTRL_ENABLE_CLK_REG_RW BIT_5
+#define MISC_HOST_CTRL_ENABLE_REG_WORD_SWAP BIT_6
+#define MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS BIT_7
+#define MISC_HOST_CTRL_ENABLE_INT_MASK_MODE BIT_8
+#define MISC_HOST_CTRL_ENABLE_TAGGED_STATUS_MODE BIT_9
+
+ T3_32BIT_REGISTER DmaReadWriteCtrl;
+#define DMA_CTRL_WRITE_BOUNDARY_MASK (BIT_11 | BIT_12 | BIT_13)
+#define DMA_CTRL_WRITE_BOUNDARY_DISABLE 0
+#define DMA_CTRL_WRITE_BOUNDARY_16 BIT_11
+#define DMA_CTRL_WRITE_BOUNDARY_32 BIT_12
+#define DMA_CTRL_WRITE_BOUNDARY_64 (BIT_12 | BIT_11)
+#define DMA_CTRL_WRITE_BOUNDARY_128 BIT_13
+#define DMA_CTRL_WRITE_BOUNDARY_256 (BIT_13 | BIT_11)
+#define DMA_CTRL_WRITE_BOUNDARY_512 (BIT_13 | BIT_12)
+#define DMA_CTRL_WRITE_BOUNDARY_1024 (BIT_13 | BIT_12 | BIT_11)
+#define DMA_CTRL_WRITE_ONE_DMA_AT_ONCE BIT_14
+
+ T3_32BIT_REGISTER PciState;
+#define T3_PCI_STATE_FORCE_PCI_RESET BIT_0
+#define T3_PCI_STATE_INTERRUPT_NOT_ACTIVE BIT_1
+#define T3_PCI_STATE_NOT_PCI_X_BUS BIT_2
+#define T3_PCI_STATE_HIGH_BUS_SPEED BIT_3
+#define T3_PCI_STATE_32BIT_PCI_BUS BIT_4
+#define T3_PCI_STATE_PCI_ROM_ENABLE BIT_5
+#define T3_PCI_STATE_PCI_ROM_RETRY_ENABLE BIT_6
+#define T3_PCI_STATE_FLAT_VIEW BIT_8
+#define T3_PCI_STATE_RETRY_SAME_DMA BIT_13
+
+ T3_32BIT_REGISTER ClockCtrl;
+#define T3_PCI_CLKCTRL_TXCPU_CLK_DISABLE BIT_11
+#define T3_PCI_CLKCTRL_RXCPU_CLK_DISABLE BIT_10
+#define T3_PCI_CLKCTRL_CORE_CLK_DISABLE BIT_9
+
+ T3_32BIT_REGISTER RegBaseAddr;
+
+ T3_32BIT_REGISTER MemWindowBaseAddr;
#ifdef NIC_CPU_VIEW
- /* These registers are ONLY visible to NIC CPU */
- T3_32BIT_REGISTER PowerConsumed;
- T3_32BIT_REGISTER PowerDissipated;
-#else /* NIC_CPU_VIEW */
- T3_32BIT_REGISTER RegData;
- T3_32BIT_REGISTER MemWindowData;
-#endif /* !NIC_CPU_VIEW */
+ /* These registers are ONLY visible to NIC CPU */
+ T3_32BIT_REGISTER PowerConsumed;
+ T3_32BIT_REGISTER PowerDissipated;
+#else /* NIC_CPU_VIEW */
+ T3_32BIT_REGISTER RegData;
+ T3_32BIT_REGISTER MemWindowData;
+#endif /* !NIC_CPU_VIEW */
- T3_32BIT_REGISTER ModeCtrl;
+ T3_32BIT_REGISTER ModeCtrl;
- T3_32BIT_REGISTER MiscCfg;
+ T3_32BIT_REGISTER MiscCfg;
- T3_32BIT_REGISTER MiscLocalCtrl;
+ T3_32BIT_REGISTER MiscLocalCtrl;
- T3_32BIT_REGISTER Unused4;
+ T3_32BIT_REGISTER Unused4;
- /* NOTE: Big/Little-endian clarification needed. Are these register */
- /* in big or little endian formate. */
- T3_64BIT_REGISTER StdRingProdIdx;
- T3_64BIT_REGISTER RcvRetRingConIdx;
- T3_64BIT_REGISTER SndProdIdx;
+ /* NOTE: Big/Little-endian clarification needed. Are these register */
+ /* in big or little endian formate. */
+ T3_64BIT_REGISTER StdRingProdIdx;
+ T3_64BIT_REGISTER RcvRetRingConIdx;
+ T3_64BIT_REGISTER SndProdIdx;
- LM_UINT8 Unused5[80];
+ LM_UINT8 Unused5[80];
} T3_PCI_CONFIGURATION, *PT3_PCI_CONFIGURATION;
#define PCIX_CMD_MAX_SPLIT_MASK 0x0070
@@ -1374,1382 +1326,1347 @@ typedef struct {
/******************************************************************************/
typedef struct {
- /* MAC mode control. */
- T3_32BIT_REGISTER Mode;
- #define MAC_MODE_GLOBAL_RESET BIT_0
- #define MAC_MODE_HALF_DUPLEX BIT_1
- #define MAC_MODE_PORT_MODE_MASK (BIT_2 | BIT_3)
- #define MAC_MODE_PORT_MODE_TBI (BIT_2 | BIT_3)
- #define MAC_MODE_PORT_MODE_GMII BIT_3
- #define MAC_MODE_PORT_MODE_MII BIT_2
- #define MAC_MODE_PORT_MODE_NONE BIT_NONE
- #define MAC_MODE_PORT_INTERNAL_LOOPBACK BIT_4
- #define MAC_MODE_TAGGED_MAC_CONTROL BIT_7
- #define MAC_MODE_TX_BURSTING BIT_8
- #define MAC_MODE_MAX_DEFER BIT_9
- #define MAC_MODE_LINK_POLARITY BIT_10
- #define MAC_MODE_ENABLE_RX_STATISTICS BIT_11
- #define MAC_MODE_CLEAR_RX_STATISTICS BIT_12
- #define MAC_MODE_FLUSH_RX_STATISTICS BIT_13
- #define MAC_MODE_ENABLE_TX_STATISTICS BIT_14
- #define MAC_MODE_CLEAR_TX_STATISTICS BIT_15
- #define MAC_MODE_FLUSH_TX_STATISTICS BIT_16
- #define MAC_MODE_SEND_CONFIGS BIT_17
- #define MAC_MODE_DETECT_MAGIC_PACKET_ENABLE BIT_18
- #define MAC_MODE_ACPI_POWER_ON_ENABLE BIT_19
- #define MAC_MODE_ENABLE_MIP BIT_20
- #define MAC_MODE_ENABLE_TDE BIT_21
- #define MAC_MODE_ENABLE_RDE BIT_22
- #define MAC_MODE_ENABLE_FHDE BIT_23
-
- /* MAC status */
- T3_32BIT_REGISTER Status;
- #define MAC_STATUS_PCS_SYNCED BIT_0
- #define MAC_STATUS_SIGNAL_DETECTED BIT_1
- #define MAC_STATUS_RECEIVING_CFG BIT_2
- #define MAC_STATUS_CFG_CHANGED BIT_3
- #define MAC_STATUS_SYNC_CHANGED BIT_4
- #define MAC_STATUS_PORT_DECODE_ERROR BIT_10
- #define MAC_STATUS_LINK_STATE_CHANGED BIT_12
- #define MAC_STATUS_MI_COMPLETION BIT_22
- #define MAC_STATUS_MI_INTERRUPT BIT_23
- #define MAC_STATUS_AP_ERROR BIT_24
- #define MAC_STATUS_ODI_ERROR BIT_25
- #define MAC_STATUS_RX_STATS_OVERRUN BIT_26
- #define MAC_STATUS_TX_STATS_OVERRUN BIT_27
-
- /* Event Enable */
- T3_32BIT_REGISTER MacEvent;
- #define MAC_EVENT_ENABLE_PORT_DECODE_ERR BIT_10
- #define MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN BIT_12
- #define MAC_EVENT_ENABLE_MI_COMPLETION BIT_22
- #define MAC_EVENT_ENABLE_MI_INTERRUPT BIT_23
- #define MAC_EVENT_ENABLE_AP_ERROR BIT_24
- #define MAC_EVENT_ENABLE_ODI_ERROR BIT_25
- #define MAC_EVENT_ENABLE_RX_STATS_OVERRUN BIT_26
- #define MAC_EVENT_ENABLE_TX_STATS_OVERRUN BIT_27
-
- /* Led control. */
- T3_32BIT_REGISTER LedCtrl;
- #define LED_CTRL_OVERRIDE_LINK_LED BIT_0
- #define LED_CTRL_1000MBPS_LED_ON BIT_1
- #define LED_CTRL_100MBPS_LED_ON BIT_2
- #define LED_CTRL_10MBPS_LED_ON BIT_3
- #define LED_CTRL_OVERRIDE_TRAFFIC_LED BIT_4
- #define LED_CTRL_BLINK_TRAFFIC_LED BIT_5
- #define LED_CTRL_TRAFFIC_LED BIT_6
- #define LED_CTRL_1000MBPS_LED_STATUS BIT_7
- #define LED_CTRL_100MBPS_LED_STATUS BIT_8
- #define LED_CTRL_10MBPS_LED_STATUS BIT_9
- #define LED_CTRL_TRAFFIC_LED_STATUS BIT_10
- #define LED_CTRL_MAC_MODE BIT_NONE
- #define LED_CTRL_PHY_MODE_1 BIT_11
- #define LED_CTRL_PHY_MODE_2 BIT_12
- #define LED_CTRL_BLINK_RATE_MASK 0x7ff80000
- #define LED_CTRL_OVERRIDE_BLINK_PERIOD BIT_19
- #define LED_CTRL_OVERRIDE_BLINK_RATE BIT_31
-
- /* MAC addresses. */
- struct {
- T3_32BIT_REGISTER High; /* Upper 2 bytes. */
- T3_32BIT_REGISTER Low; /* Lower 4 bytes. */
- } MacAddr[4];
-
- /* ACPI Mbuf pointer. */
- T3_32BIT_REGISTER AcpiMbufPtr;
-
- /* ACPI Length and Offset. */
- T3_32BIT_REGISTER AcpiLengthOffset;
- #define ACPI_LENGTH_MASK 0xffff
- #define ACPI_OFFSET_MASK 0x0fff0000
- #define ACPI_LENGTH(x) x
- #define ACPI_OFFSET(x) ((x) << 16)
-
- /* Transmit random backoff. */
- T3_32BIT_REGISTER TxBackoffSeed;
- #define MAC_TX_BACKOFF_SEED_MASK 0x3ff
-
- /* Receive MTU */
- T3_32BIT_REGISTER MtuSize;
- #define MAC_RX_MTU_MASK 0xffff
-
- /* Gigabit PCS Test. */
- T3_32BIT_REGISTER PcsTest;
- #define MAC_PCS_TEST_DATA_PATTERN_MASK 0x0fffff
- #define MAC_PCS_TEST_ENABLE BIT_20
-
- /* Transmit Gigabit Auto-Negotiation. */
- T3_32BIT_REGISTER TxAutoNeg;
- #define MAC_AN_TX_AN_DATA_MASK 0xffff
-
- /* Receive Gigabit Auto-Negotiation. */
- T3_32BIT_REGISTER RxAutoNeg;
- #define MAC_AN_RX_AN_DATA_MASK 0xffff
-
- /* MI Communication. */
- T3_32BIT_REGISTER MiCom;
- #define MI_COM_CMD_MASK (BIT_26 | BIT_27)
- #define MI_COM_CMD_WRITE BIT_26
- #define MI_COM_CMD_READ BIT_27
- #define MI_COM_READ_FAILED BIT_28
- #define MI_COM_START BIT_29
- #define MI_COM_BUSY BIT_29
-
- #define MI_COM_PHY_ADDR_MASK 0x1f
- #define MI_COM_FIRST_PHY_ADDR_BIT 21
-
- #define MI_COM_PHY_REG_ADDR_MASK 0x1f
- #define MI_COM_FIRST_PHY_REG_ADDR_BIT 16
-
- #define MI_COM_PHY_DATA_MASK 0xffff
-
- /* MI Status. */
- T3_32BIT_REGISTER MiStatus;
- #define MI_STATUS_ENABLE_LINK_STATUS_ATTN BIT_0
-
- /* MI Mode. */
- T3_32BIT_REGISTER MiMode;
- #define MI_MODE_CLOCK_SPEED_10MHZ BIT_0
- #define MI_MODE_USE_SHORT_PREAMBLE BIT_1
- #define MI_MODE_AUTO_POLLING_ENABLE BIT_4
- #define MI_MODE_CORE_CLOCK_SPEED_62MHZ BIT_15
-
- /* Auto-polling status. */
- T3_32BIT_REGISTER AutoPollStatus;
- #define AUTO_POLL_ERROR BIT_0
-
- /* Transmit MAC mode. */
- T3_32BIT_REGISTER TxMode;
- #define TX_MODE_RESET BIT_0
- #define TX_MODE_ENABLE BIT_1
- #define TX_MODE_ENABLE_FLOW_CONTROL BIT_4
- #define TX_MODE_ENABLE_BIG_BACKOFF BIT_5
- #define TX_MODE_ENABLE_LONG_PAUSE BIT_6
-
- /* Transmit MAC status. */
- T3_32BIT_REGISTER TxStatus;
- #define TX_STATUS_RX_CURRENTLY_XOFFED BIT_0
- #define TX_STATUS_SENT_XOFF BIT_1
- #define TX_STATUS_SENT_XON BIT_2
- #define TX_STATUS_LINK_UP BIT_3
- #define TX_STATUS_ODI_UNDERRUN BIT_4
- #define TX_STATUS_ODI_OVERRUN BIT_5
-
- /* Transmit MAC length. */
- T3_32BIT_REGISTER TxLengths;
- #define TX_LEN_SLOT_TIME_MASK 0xff
- #define TX_LEN_IPG_MASK 0x0f00
- #define TX_LEN_IPG_CRS_MASK (BIT_12 | BIT_13)
-
- /* Receive MAC mode. */
- T3_32BIT_REGISTER RxMode;
- #define RX_MODE_RESET BIT_0
- #define RX_MODE_ENABLE BIT_1
- #define RX_MODE_ENABLE_FLOW_CONTROL BIT_2
- #define RX_MODE_KEEP_MAC_CONTROL BIT_3
- #define RX_MODE_KEEP_PAUSE BIT_4
- #define RX_MODE_ACCEPT_OVERSIZED BIT_5
- #define RX_MODE_ACCEPT_RUNTS BIT_6
- #define RX_MODE_LENGTH_CHECK BIT_7
- #define RX_MODE_PROMISCUOUS_MODE BIT_8
- #define RX_MODE_NO_CRC_CHECK BIT_9
- #define RX_MODE_KEEP_VLAN_TAG BIT_10
-
- /* Receive MAC status. */
- T3_32BIT_REGISTER RxStatus;
- #define RX_STATUS_REMOTE_TRANSMITTER_XOFFED BIT_0
- #define RX_STATUS_XOFF_RECEIVED BIT_1
- #define RX_STATUS_XON_RECEIVED BIT_2
-
- /* Hash registers. */
- T3_32BIT_REGISTER HashReg[4];
-
- /* Receive placement rules registers. */
- struct {
- T3_32BIT_REGISTER Rule;
- T3_32BIT_REGISTER Value;
- } RcvRules[16];
-
- #define RCV_DISABLE_RULE_MASK 0x7fffffff
-
- #define RCV_RULE1_REJECT_BROADCAST_IDX 0x00
- #define REJECT_BROADCAST_RULE1_RULE 0xc2000000
- #define REJECT_BROADCAST_RULE1_VALUE 0xffffffff
-
- #define RCV_RULE2_REJECT_BROADCAST_IDX 0x01
- #define REJECT_BROADCAST_RULE2_RULE 0x86000004
- #define REJECT_BROADCAST_RULE2_VALUE 0xffffffff
+ /* MAC mode control. */
+ T3_32BIT_REGISTER Mode;
+#define MAC_MODE_GLOBAL_RESET BIT_0
+#define MAC_MODE_HALF_DUPLEX BIT_1
+#define MAC_MODE_PORT_MODE_MASK (BIT_2 | BIT_3)
+#define MAC_MODE_PORT_MODE_TBI (BIT_2 | BIT_3)
+#define MAC_MODE_PORT_MODE_GMII BIT_3
+#define MAC_MODE_PORT_MODE_MII BIT_2
+#define MAC_MODE_PORT_MODE_NONE BIT_NONE
+#define MAC_MODE_PORT_INTERNAL_LOOPBACK BIT_4
+#define MAC_MODE_TAGGED_MAC_CONTROL BIT_7
+#define MAC_MODE_TX_BURSTING BIT_8
+#define MAC_MODE_MAX_DEFER BIT_9
+#define MAC_MODE_LINK_POLARITY BIT_10
+#define MAC_MODE_ENABLE_RX_STATISTICS BIT_11
+#define MAC_MODE_CLEAR_RX_STATISTICS BIT_12
+#define MAC_MODE_FLUSH_RX_STATISTICS BIT_13
+#define MAC_MODE_ENABLE_TX_STATISTICS BIT_14
+#define MAC_MODE_CLEAR_TX_STATISTICS BIT_15
+#define MAC_MODE_FLUSH_TX_STATISTICS BIT_16
+#define MAC_MODE_SEND_CONFIGS BIT_17
+#define MAC_MODE_DETECT_MAGIC_PACKET_ENABLE BIT_18
+#define MAC_MODE_ACPI_POWER_ON_ENABLE BIT_19
+#define MAC_MODE_ENABLE_MIP BIT_20
+#define MAC_MODE_ENABLE_TDE BIT_21
+#define MAC_MODE_ENABLE_RDE BIT_22
+#define MAC_MODE_ENABLE_FHDE BIT_23
+
+ /* MAC status */
+ T3_32BIT_REGISTER Status;
+#define MAC_STATUS_PCS_SYNCED BIT_0
+#define MAC_STATUS_SIGNAL_DETECTED BIT_1
+#define MAC_STATUS_RECEIVING_CFG BIT_2
+#define MAC_STATUS_CFG_CHANGED BIT_3
+#define MAC_STATUS_SYNC_CHANGED BIT_4
+#define MAC_STATUS_PORT_DECODE_ERROR BIT_10
+#define MAC_STATUS_LINK_STATE_CHANGED BIT_12
+#define MAC_STATUS_MI_COMPLETION BIT_22
+#define MAC_STATUS_MI_INTERRUPT BIT_23
+#define MAC_STATUS_AP_ERROR BIT_24
+#define MAC_STATUS_ODI_ERROR BIT_25
+#define MAC_STATUS_RX_STATS_OVERRUN BIT_26
+#define MAC_STATUS_TX_STATS_OVERRUN BIT_27
+
+ /* Event Enable */
+ T3_32BIT_REGISTER MacEvent;
+#define MAC_EVENT_ENABLE_PORT_DECODE_ERR BIT_10
+#define MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN BIT_12
+#define MAC_EVENT_ENABLE_MI_COMPLETION BIT_22
+#define MAC_EVENT_ENABLE_MI_INTERRUPT BIT_23
+#define MAC_EVENT_ENABLE_AP_ERROR BIT_24
+#define MAC_EVENT_ENABLE_ODI_ERROR BIT_25
+#define MAC_EVENT_ENABLE_RX_STATS_OVERRUN BIT_26
+#define MAC_EVENT_ENABLE_TX_STATS_OVERRUN BIT_27
+
+ /* Led control. */
+ T3_32BIT_REGISTER LedCtrl;
+#define LED_CTRL_OVERRIDE_LINK_LED BIT_0
+#define LED_CTRL_1000MBPS_LED_ON BIT_1
+#define LED_CTRL_100MBPS_LED_ON BIT_2
+#define LED_CTRL_10MBPS_LED_ON BIT_3
+#define LED_CTRL_OVERRIDE_TRAFFIC_LED BIT_4
+#define LED_CTRL_BLINK_TRAFFIC_LED BIT_5
+#define LED_CTRL_TRAFFIC_LED BIT_6
+#define LED_CTRL_1000MBPS_LED_STATUS BIT_7
+#define LED_CTRL_100MBPS_LED_STATUS BIT_8
+#define LED_CTRL_10MBPS_LED_STATUS BIT_9
+#define LED_CTRL_TRAFFIC_LED_STATUS BIT_10
+#define LED_CTRL_MAC_MODE BIT_NONE
+#define LED_CTRL_PHY_MODE_1 BIT_11
+#define LED_CTRL_PHY_MODE_2 BIT_12
+#define LED_CTRL_BLINK_RATE_MASK 0x7ff80000
+#define LED_CTRL_OVERRIDE_BLINK_PERIOD BIT_19
+#define LED_CTRL_OVERRIDE_BLINK_RATE BIT_31
+
+ /* MAC addresses. */
+ struct {
+ T3_32BIT_REGISTER High; /* Upper 2 bytes. */
+ T3_32BIT_REGISTER Low; /* Lower 4 bytes. */
+ } MacAddr[4];
+
+ /* ACPI Mbuf pointer. */
+ T3_32BIT_REGISTER AcpiMbufPtr;
+
+ /* ACPI Length and Offset. */
+ T3_32BIT_REGISTER AcpiLengthOffset;
+#define ACPI_LENGTH_MASK 0xffff
+#define ACPI_OFFSET_MASK 0x0fff0000
+#define ACPI_LENGTH(x) x
+#define ACPI_OFFSET(x) ((x) << 16)
+
+ /* Transmit random backoff. */
+ T3_32BIT_REGISTER TxBackoffSeed;
+#define MAC_TX_BACKOFF_SEED_MASK 0x3ff
+
+ /* Receive MTU */
+ T3_32BIT_REGISTER MtuSize;
+#define MAC_RX_MTU_MASK 0xffff
+
+ /* Gigabit PCS Test. */
+ T3_32BIT_REGISTER PcsTest;
+#define MAC_PCS_TEST_DATA_PATTERN_MASK 0x0fffff
+#define MAC_PCS_TEST_ENABLE BIT_20
+
+ /* Transmit Gigabit Auto-Negotiation. */
+ T3_32BIT_REGISTER TxAutoNeg;
+#define MAC_AN_TX_AN_DATA_MASK 0xffff
+
+ /* Receive Gigabit Auto-Negotiation. */
+ T3_32BIT_REGISTER RxAutoNeg;
+#define MAC_AN_RX_AN_DATA_MASK 0xffff
+
+ /* MI Communication. */
+ T3_32BIT_REGISTER MiCom;
+#define MI_COM_CMD_MASK (BIT_26 | BIT_27)
+#define MI_COM_CMD_WRITE BIT_26
+#define MI_COM_CMD_READ BIT_27
+#define MI_COM_READ_FAILED BIT_28
+#define MI_COM_START BIT_29
+#define MI_COM_BUSY BIT_29
+
+#define MI_COM_PHY_ADDR_MASK 0x1f
+#define MI_COM_FIRST_PHY_ADDR_BIT 21
+
+#define MI_COM_PHY_REG_ADDR_MASK 0x1f
+#define MI_COM_FIRST_PHY_REG_ADDR_BIT 16
+
+#define MI_COM_PHY_DATA_MASK 0xffff
+
+ /* MI Status. */
+ T3_32BIT_REGISTER MiStatus;
+#define MI_STATUS_ENABLE_LINK_STATUS_ATTN BIT_0
+
+ /* MI Mode. */
+ T3_32BIT_REGISTER MiMode;
+#define MI_MODE_CLOCK_SPEED_10MHZ BIT_0
+#define MI_MODE_USE_SHORT_PREAMBLE BIT_1
+#define MI_MODE_AUTO_POLLING_ENABLE BIT_4
+#define MI_MODE_CORE_CLOCK_SPEED_62MHZ BIT_15
+
+ /* Auto-polling status. */
+ T3_32BIT_REGISTER AutoPollStatus;
+#define AUTO_POLL_ERROR BIT_0
+
+ /* Transmit MAC mode. */
+ T3_32BIT_REGISTER TxMode;
+#define TX_MODE_RESET BIT_0
+#define TX_MODE_ENABLE BIT_1
+#define TX_MODE_ENABLE_FLOW_CONTROL BIT_4
+#define TX_MODE_ENABLE_BIG_BACKOFF BIT_5
+#define TX_MODE_ENABLE_LONG_PAUSE BIT_6
+
+ /* Transmit MAC status. */
+ T3_32BIT_REGISTER TxStatus;
+#define TX_STATUS_RX_CURRENTLY_XOFFED BIT_0
+#define TX_STATUS_SENT_XOFF BIT_1
+#define TX_STATUS_SENT_XON BIT_2
+#define TX_STATUS_LINK_UP BIT_3
+#define TX_STATUS_ODI_UNDERRUN BIT_4
+#define TX_STATUS_ODI_OVERRUN BIT_5
+
+ /* Transmit MAC length. */
+ T3_32BIT_REGISTER TxLengths;
+#define TX_LEN_SLOT_TIME_MASK 0xff
+#define TX_LEN_IPG_MASK 0x0f00
+#define TX_LEN_IPG_CRS_MASK (BIT_12 | BIT_13)
+
+ /* Receive MAC mode. */
+ T3_32BIT_REGISTER RxMode;
+#define RX_MODE_RESET BIT_0
+#define RX_MODE_ENABLE BIT_1
+#define RX_MODE_ENABLE_FLOW_CONTROL BIT_2
+#define RX_MODE_KEEP_MAC_CONTROL BIT_3
+#define RX_MODE_KEEP_PAUSE BIT_4
+#define RX_MODE_ACCEPT_OVERSIZED BIT_5
+#define RX_MODE_ACCEPT_RUNTS BIT_6
+#define RX_MODE_LENGTH_CHECK BIT_7
+#define RX_MODE_PROMISCUOUS_MODE BIT_8
+#define RX_MODE_NO_CRC_CHECK BIT_9
+#define RX_MODE_KEEP_VLAN_TAG BIT_10
+
+ /* Receive MAC status. */
+ T3_32BIT_REGISTER RxStatus;
+#define RX_STATUS_REMOTE_TRANSMITTER_XOFFED BIT_0
+#define RX_STATUS_XOFF_RECEIVED BIT_1
+#define RX_STATUS_XON_RECEIVED BIT_2
+
+ /* Hash registers. */
+ T3_32BIT_REGISTER HashReg[4];
+
+ /* Receive placement rules registers. */
+ struct {
+ T3_32BIT_REGISTER Rule;
+ T3_32BIT_REGISTER Value;
+ } RcvRules[16];
+
+#define RCV_DISABLE_RULE_MASK 0x7fffffff
+
+#define RCV_RULE1_REJECT_BROADCAST_IDX 0x00
+#define REJECT_BROADCAST_RULE1_RULE 0xc2000000
+#define REJECT_BROADCAST_RULE1_VALUE 0xffffffff
+
+#define RCV_RULE2_REJECT_BROADCAST_IDX 0x01
+#define REJECT_BROADCAST_RULE2_RULE 0x86000004
+#define REJECT_BROADCAST_RULE2_VALUE 0xffffffff
#if INCLUDE_5701_AX_FIX
- #define RCV_LAST_RULE_IDX 0x04
+#define RCV_LAST_RULE_IDX 0x04
#else
- #define RCV_LAST_RULE_IDX 0x02
+#define RCV_LAST_RULE_IDX 0x02
#endif
- T3_32BIT_REGISTER RcvRuleCfg;
- #define RX_RULE_DEFAULT_CLASS (1 << 3)
+ T3_32BIT_REGISTER RcvRuleCfg;
+#define RX_RULE_DEFAULT_CLASS (1 << 3)
- LM_UINT8 Reserved1[140];
+ LM_UINT8 Reserved1[140];
- T3_32BIT_REGISTER SerdesCfg;
- T3_32BIT_REGISTER SerdesStatus;
+ T3_32BIT_REGISTER SerdesCfg;
+ T3_32BIT_REGISTER SerdesStatus;
- LM_UINT8 Reserved2[104];
+ LM_UINT8 Reserved2[104];
- volatile LM_UINT8 TxMacState[16];
- volatile LM_UINT8 RxMacState[20];
+ volatile LM_UINT8 TxMacState[16];
+ volatile LM_UINT8 RxMacState[20];
- LM_UINT8 Reserved3[476];
+ LM_UINT8 Reserved3[476];
- T3_32BIT_REGISTER RxStats[26];
+ T3_32BIT_REGISTER RxStats[26];
- LM_UINT8 Reserved4[24];
+ LM_UINT8 Reserved4[24];
- T3_32BIT_REGISTER TxStats[28];
+ T3_32BIT_REGISTER TxStats[28];
- LM_UINT8 Reserved5[784];
+ LM_UINT8 Reserved5[784];
} T3_MAC_CONTROL, *PT3_MAC_CONTROL;
-
/******************************************************************************/
/* Send data initiator control registers. */
/******************************************************************************/
typedef struct {
- T3_32BIT_REGISTER Mode;
- #define T3_SND_DATA_IN_MODE_RESET BIT_0
- #define T3_SND_DATA_IN_MODE_ENABLE BIT_1
- #define T3_SND_DATA_IN_MODE_STATS_OFLW_ATTN_ENABLE BIT_2
-
- T3_32BIT_REGISTER Status;
- #define T3_SND_DATA_IN_STATUS_STATS_OFLW_ATTN BIT_2
-
- T3_32BIT_REGISTER StatsCtrl;
- #define T3_SND_DATA_IN_STATS_CTRL_ENABLE BIT_0
- #define T3_SND_DATA_IN_STATS_CTRL_FASTER_UPDATE BIT_1
- #define T3_SND_DATA_IN_STATS_CTRL_CLEAR BIT_2
- #define T3_SND_DATA_IN_STATS_CTRL_FLUSH BIT_3
- #define T3_SND_DATA_IN_STATS_CTRL_FORCE_ZERO BIT_4
-
- T3_32BIT_REGISTER StatsEnableMask;
- T3_32BIT_REGISTER StatsIncMask;
-
- LM_UINT8 Reserved[108];
-
- T3_32BIT_REGISTER ClassOfServCnt[16];
- T3_32BIT_REGISTER DmaReadQFullCnt;
- T3_32BIT_REGISTER DmaPriorityReadQFullCnt;
- T3_32BIT_REGISTER SdcQFullCnt;
-
- T3_32BIT_REGISTER NicRingSetSendProdIdxCnt;
- T3_32BIT_REGISTER StatusUpdatedCnt;
- T3_32BIT_REGISTER InterruptsCnt;
- T3_32BIT_REGISTER AvoidInterruptsCnt;
- T3_32BIT_REGISTER SendThresholdHitCnt;
-
- /* Unused space. */
- LM_UINT8 Unused[800];
-} T3_SEND_DATA_INITIATOR, *PT3_SEND_DATA_INITIATOR;
+ T3_32BIT_REGISTER Mode;
+#define T3_SND_DATA_IN_MODE_RESET BIT_0
+#define T3_SND_DATA_IN_MODE_ENABLE BIT_1
+#define T3_SND_DATA_IN_MODE_STATS_OFLW_ATTN_ENABLE BIT_2
+
+ T3_32BIT_REGISTER Status;
+#define T3_SND_DATA_IN_STATUS_STATS_OFLW_ATTN BIT_2
+
+ T3_32BIT_REGISTER StatsCtrl;
+#define T3_SND_DATA_IN_STATS_CTRL_ENABLE BIT_0
+#define T3_SND_DATA_IN_STATS_CTRL_FASTER_UPDATE BIT_1
+#define T3_SND_DATA_IN_STATS_CTRL_CLEAR BIT_2
+#define T3_SND_DATA_IN_STATS_CTRL_FLUSH BIT_3
+#define T3_SND_DATA_IN_STATS_CTRL_FORCE_ZERO BIT_4
+
+ T3_32BIT_REGISTER StatsEnableMask;
+ T3_32BIT_REGISTER StatsIncMask;
+
+ LM_UINT8 Reserved[108];
+ T3_32BIT_REGISTER ClassOfServCnt[16];
+ T3_32BIT_REGISTER DmaReadQFullCnt;
+ T3_32BIT_REGISTER DmaPriorityReadQFullCnt;
+ T3_32BIT_REGISTER SdcQFullCnt;
+
+ T3_32BIT_REGISTER NicRingSetSendProdIdxCnt;
+ T3_32BIT_REGISTER StatusUpdatedCnt;
+ T3_32BIT_REGISTER InterruptsCnt;
+ T3_32BIT_REGISTER AvoidInterruptsCnt;
+ T3_32BIT_REGISTER SendThresholdHitCnt;
+
+ /* Unused space. */
+ LM_UINT8 Unused[800];
+} T3_SEND_DATA_INITIATOR, *PT3_SEND_DATA_INITIATOR;
/******************************************************************************/
/* Send data completion control registers. */
/******************************************************************************/
typedef struct {
- T3_32BIT_REGISTER Mode;
- #define SND_DATA_COMP_MODE_RESET BIT_0
- #define SND_DATA_COMP_MODE_ENABLE BIT_1
+ T3_32BIT_REGISTER Mode;
+#define SND_DATA_COMP_MODE_RESET BIT_0
+#define SND_DATA_COMP_MODE_ENABLE BIT_1
- /* Unused space. */
- LM_UINT8 Unused[1020];
+ /* Unused space. */
+ LM_UINT8 Unused[1020];
} T3_SEND_DATA_COMPLETION, *PT3_SEND_DATA_COMPLETION;
-
/******************************************************************************/
/* Send BD Ring Selector Control Registers. */
/******************************************************************************/
typedef struct {
- T3_32BIT_REGISTER Mode;
- #define SND_BD_SEL_MODE_RESET BIT_0
- #define SND_BD_SEL_MODE_ENABLE BIT_1
- #define SND_BD_SEL_MODE_ATTN_ENABLE BIT_2
+ T3_32BIT_REGISTER Mode;
+#define SND_BD_SEL_MODE_RESET BIT_0
+#define SND_BD_SEL_MODE_ENABLE BIT_1
+#define SND_BD_SEL_MODE_ATTN_ENABLE BIT_2
- T3_32BIT_REGISTER Status;
- #define SND_BD_SEL_STATUS_ERROR_ATTN BIT_2
+ T3_32BIT_REGISTER Status;
+#define SND_BD_SEL_STATUS_ERROR_ATTN BIT_2
- T3_32BIT_REGISTER HwDiag;
+ T3_32BIT_REGISTER HwDiag;
- /* Unused space. */
- LM_UINT8 Unused1[52];
+ /* Unused space. */
+ LM_UINT8 Unused1[52];
- /* Send BD Ring Selector Local NIC Send BD Consumer Index. */
- T3_32BIT_REGISTER NicSendBdSelConIdx[16];
+ /* Send BD Ring Selector Local NIC Send BD Consumer Index. */
+ T3_32BIT_REGISTER NicSendBdSelConIdx[16];
- /* Unused space. */
- LM_UINT8 Unused2[896];
+ /* Unused space. */
+ LM_UINT8 Unused2[896];
} T3_SEND_BD_SELECTOR, *PT3_SEND_BD_SELECTOR;
-
/******************************************************************************/
/* Send BD initiator control registers. */
/******************************************************************************/
typedef struct {
- T3_32BIT_REGISTER Mode;
- #define SND_BD_IN_MODE_RESET BIT_0
- #define SND_BD_IN_MODE_ENABLE BIT_1
- #define SND_BD_IN_MODE_ATTN_ENABLE BIT_2
+ T3_32BIT_REGISTER Mode;
+#define SND_BD_IN_MODE_RESET BIT_0
+#define SND_BD_IN_MODE_ENABLE BIT_1
+#define SND_BD_IN_MODE_ATTN_ENABLE BIT_2
- T3_32BIT_REGISTER Status;
- #define SND_BD_IN_STATUS_ERROR_ATTN BIT_2
+ T3_32BIT_REGISTER Status;
+#define SND_BD_IN_STATUS_ERROR_ATTN BIT_2
- /* Send BD initiator local NIC send BD producer index. */
- T3_32BIT_REGISTER NicSendBdInProdIdx[16];
+ /* Send BD initiator local NIC send BD producer index. */
+ T3_32BIT_REGISTER NicSendBdInProdIdx[16];
- /* Unused space. */
- LM_UINT8 Unused2[952];
+ /* Unused space. */
+ LM_UINT8 Unused2[952];
} T3_SEND_BD_INITIATOR, *PT3_SEND_BD_INITIATOR;
-
/******************************************************************************/
/* Send BD Completion Control. */
/******************************************************************************/
typedef struct {
- T3_32BIT_REGISTER Mode;
- #define SND_BD_COMP_MODE_RESET BIT_0
- #define SND_BD_COMP_MODE_ENABLE BIT_1
- #define SND_BD_COMP_MODE_ATTN_ENABLE BIT_2
+ T3_32BIT_REGISTER Mode;
+#define SND_BD_COMP_MODE_RESET BIT_0
+#define SND_BD_COMP_MODE_ENABLE BIT_1
+#define SND_BD_COMP_MODE_ATTN_ENABLE BIT_2
- /* Unused space. */
- LM_UINT8 Unused2[1020];
+ /* Unused space. */
+ LM_UINT8 Unused2[1020];
} T3_SEND_BD_COMPLETION, *PT3_SEND_BD_COMPLETION;
-
/******************************************************************************/
/* Receive list placement control registers. */
/******************************************************************************/
typedef struct {
- /* Mode. */
- T3_32BIT_REGISTER Mode;
- #define RCV_LIST_PLMT_MODE_RESET BIT_0
- #define RCV_LIST_PLMT_MODE_ENABLE BIT_1
- #define RCV_LIST_PLMT_MODE_CLASS0_ATTN_ENABLE BIT_2
- #define RCV_LIST_PLMT_MODE_MAPPING_OOR_ATTN_ENABLE BIT_3
- #define RCV_LIST_PLMT_MODE_STATS_OFLOW_ATTN_ENABLE BIT_4
-
- /* Status. */
- T3_32BIT_REGISTER Status;
- #define RCV_LIST_PLMT_STATUS_CLASS0_ATTN BIT_2
- #define RCV_LIST_PLMT_STATUS_MAPPING_ATTN BIT_3
- #define RCV_LIST_PLMT_STATUS_STATS_OFLOW_ATTN BIT_4
-
- /* Receive selector list lock register. */
- T3_32BIT_REGISTER Lock;
- #define RCV_LIST_SEL_LOCK_REQUEST_MASK 0xffff
- #define RCV_LIST_SEL_LOCK_GRANT_MASK 0xffff0000
-
- /* Selector non-empty bits. */
- T3_32BIT_REGISTER NonEmptyBits;
- #define RCV_LIST_SEL_NON_EMPTY_MASK 0xffff
-
- /* Receive list placement configuration register. */
- T3_32BIT_REGISTER Config;
-
- /* Receive List Placement statistics Control. */
- T3_32BIT_REGISTER StatsCtrl;
+ /* Mode. */
+ T3_32BIT_REGISTER Mode;
+#define RCV_LIST_PLMT_MODE_RESET BIT_0
+#define RCV_LIST_PLMT_MODE_ENABLE BIT_1
+#define RCV_LIST_PLMT_MODE_CLASS0_ATTN_ENABLE BIT_2
+#define RCV_LIST_PLMT_MODE_MAPPING_OOR_ATTN_ENABLE BIT_3
+#define RCV_LIST_PLMT_MODE_STATS_OFLOW_ATTN_ENABLE BIT_4
+
+ /* Status. */
+ T3_32BIT_REGISTER Status;
+#define RCV_LIST_PLMT_STATUS_CLASS0_ATTN BIT_2
+#define RCV_LIST_PLMT_STATUS_MAPPING_ATTN BIT_3
+#define RCV_LIST_PLMT_STATUS_STATS_OFLOW_ATTN BIT_4
+
+ /* Receive selector list lock register. */
+ T3_32BIT_REGISTER Lock;
+#define RCV_LIST_SEL_LOCK_REQUEST_MASK 0xffff
+#define RCV_LIST_SEL_LOCK_GRANT_MASK 0xffff0000
+
+ /* Selector non-empty bits. */
+ T3_32BIT_REGISTER NonEmptyBits;
+#define RCV_LIST_SEL_NON_EMPTY_MASK 0xffff
+
+ /* Receive list placement configuration register. */
+ T3_32BIT_REGISTER Config;
+
+ /* Receive List Placement statistics Control. */
+ T3_32BIT_REGISTER StatsCtrl;
#define RCV_LIST_STATS_ENABLE BIT_0
#define RCV_LIST_STATS_FAST_UPDATE BIT_1
- /* Receive List Placement statistics Enable Mask. */
- T3_32BIT_REGISTER StatsEnableMask;
-
- /* Receive List Placement statistics Increment Mask. */
- T3_32BIT_REGISTER StatsIncMask;
-
- /* Unused space. */
- LM_UINT8 Unused1[224];
+ /* Receive List Placement statistics Enable Mask. */
+ T3_32BIT_REGISTER StatsEnableMask;
- struct {
- T3_32BIT_REGISTER Head;
- T3_32BIT_REGISTER Tail;
- T3_32BIT_REGISTER Count;
+ /* Receive List Placement statistics Increment Mask. */
+ T3_32BIT_REGISTER StatsIncMask;
/* Unused space. */
- LM_UINT8 Unused[4];
- } RcvSelectorList[16];
-
- /* Local statistics counter. */
- T3_32BIT_REGISTER ClassOfServCnt[16];
-
- T3_32BIT_REGISTER DropDueToFilterCnt;
- T3_32BIT_REGISTER DmaWriteQFullCnt;
- T3_32BIT_REGISTER DmaHighPriorityWriteQFullCnt;
- T3_32BIT_REGISTER NoMoreReceiveBdCnt;
- T3_32BIT_REGISTER IfInDiscardsCnt;
- T3_32BIT_REGISTER IfInErrorsCnt;
- T3_32BIT_REGISTER RcvThresholdHitCnt;
-
- /* Another unused space. */
- LM_UINT8 Unused2[420];
-} T3_RCV_LIST_PLACEMENT, *PT3_RCV_LIST_PLACEMENT;
+ LM_UINT8 Unused1[224];
+ struct {
+ T3_32BIT_REGISTER Head;
+ T3_32BIT_REGISTER Tail;
+ T3_32BIT_REGISTER Count;
+
+ /* Unused space. */
+ LM_UINT8 Unused[4];
+ } RcvSelectorList[16];
+
+ /* Local statistics counter. */
+ T3_32BIT_REGISTER ClassOfServCnt[16];
+
+ T3_32BIT_REGISTER DropDueToFilterCnt;
+ T3_32BIT_REGISTER DmaWriteQFullCnt;
+ T3_32BIT_REGISTER DmaHighPriorityWriteQFullCnt;
+ T3_32BIT_REGISTER NoMoreReceiveBdCnt;
+ T3_32BIT_REGISTER IfInDiscardsCnt;
+ T3_32BIT_REGISTER IfInErrorsCnt;
+ T3_32BIT_REGISTER RcvThresholdHitCnt;
+
+ /* Another unused space. */
+ LM_UINT8 Unused2[420];
+} T3_RCV_LIST_PLACEMENT, *PT3_RCV_LIST_PLACEMENT;
/******************************************************************************/
/* Receive Data and Receive BD Initiator Control. */
/******************************************************************************/
typedef struct {
- /* Mode. */
- T3_32BIT_REGISTER Mode;
- #define RCV_DATA_BD_IN_MODE_RESET BIT_0
- #define RCV_DATA_BD_IN_MODE_ENABLE BIT_1
- #define RCV_DATA_BD_IN_MODE_JUMBO_BD_NEEDED BIT_2
- #define RCV_DATA_BD_IN_MODE_FRAME_TOO_BIG BIT_3
- #define RCV_DATA_BD_IN_MODE_INVALID_RING_SIZE BIT_4
-
- /* Status. */
- T3_32BIT_REGISTER Status;
- #define RCV_DATA_BD_IN_STATUS_JUMBO_BD_NEEDED BIT_2
- #define RCV_DATA_BD_IN_STATUS_FRAME_TOO_BIG BIT_3
- #define RCV_DATA_BD_IN_STATUS_INVALID_RING_SIZE BIT_4
-
- /* Split frame minium size. */
- T3_32BIT_REGISTER SplitFrameMinSize;
-
- /* Unused space. */
- LM_UINT8 Unused1[0x2440-0x240c];
-
- /* Receive RCBs. */
- T3_RCB JumboRcvRcb;
- T3_RCB StdRcvRcb;
- T3_RCB MiniRcvRcb;
-
- /* Receive Data and Receive BD Ring Initiator Local NIC Receive */
- /* BD Consumber Index. */
- T3_32BIT_REGISTER NicJumboConIdx;
- T3_32BIT_REGISTER NicStdConIdx;
- T3_32BIT_REGISTER NicMiniConIdx;
-
- /* Unused space. */
- LM_UINT8 Unused2[4];
-
- /* Receive Data and Receive BD Initiator Local Receive Return ProdIdx. */
- T3_32BIT_REGISTER RcvDataBdProdIdx[16];
-
- /* Receive Data and Receive BD Initiator Hardware Diagnostic. */
- T3_32BIT_REGISTER HwDiag;
-
- /* Unused space. */
- LM_UINT8 Unused3[828];
-} T3_RCV_DATA_BD_INITIATOR, *PT3_RCV_DATA_BD_INITIATOR;
+ /* Mode. */
+ T3_32BIT_REGISTER Mode;
+#define RCV_DATA_BD_IN_MODE_RESET BIT_0
+#define RCV_DATA_BD_IN_MODE_ENABLE BIT_1
+#define RCV_DATA_BD_IN_MODE_JUMBO_BD_NEEDED BIT_2
+#define RCV_DATA_BD_IN_MODE_FRAME_TOO_BIG BIT_3
+#define RCV_DATA_BD_IN_MODE_INVALID_RING_SIZE BIT_4
+
+ /* Status. */
+ T3_32BIT_REGISTER Status;
+#define RCV_DATA_BD_IN_STATUS_JUMBO_BD_NEEDED BIT_2
+#define RCV_DATA_BD_IN_STATUS_FRAME_TOO_BIG BIT_3
+#define RCV_DATA_BD_IN_STATUS_INVALID_RING_SIZE BIT_4
+
+ /* Split frame minium size. */
+ T3_32BIT_REGISTER SplitFrameMinSize;
+
+ /* Unused space. */
+ LM_UINT8 Unused1[0x2440 - 0x240c];
+
+ /* Receive RCBs. */
+ T3_RCB JumboRcvRcb;
+ T3_RCB StdRcvRcb;
+ T3_RCB MiniRcvRcb;
+
+ /* Receive Data and Receive BD Ring Initiator Local NIC Receive */
+ /* BD Consumber Index. */
+ T3_32BIT_REGISTER NicJumboConIdx;
+ T3_32BIT_REGISTER NicStdConIdx;
+ T3_32BIT_REGISTER NicMiniConIdx;
+
+ /* Unused space. */
+ LM_UINT8 Unused2[4];
+
+ /* Receive Data and Receive BD Initiator Local Receive Return ProdIdx. */
+ T3_32BIT_REGISTER RcvDataBdProdIdx[16];
+ /* Receive Data and Receive BD Initiator Hardware Diagnostic. */
+ T3_32BIT_REGISTER HwDiag;
+
+ /* Unused space. */
+ LM_UINT8 Unused3[828];
+} T3_RCV_DATA_BD_INITIATOR, *PT3_RCV_DATA_BD_INITIATOR;
/******************************************************************************/
/* Receive Data Completion Control Registes. */
/******************************************************************************/
typedef struct {
- T3_32BIT_REGISTER Mode;
- #define RCV_DATA_COMP_MODE_RESET BIT_0
- #define RCV_DATA_COMP_MODE_ENABLE BIT_1
- #define RCV_DATA_COMP_MODE_ATTN_ENABLE BIT_2
+ T3_32BIT_REGISTER Mode;
+#define RCV_DATA_COMP_MODE_RESET BIT_0
+#define RCV_DATA_COMP_MODE_ENABLE BIT_1
+#define RCV_DATA_COMP_MODE_ATTN_ENABLE BIT_2
- /* Unused spaced. */
- LM_UINT8 Unused[1020];
+ /* Unused spaced. */
+ LM_UINT8 Unused[1020];
} T3_RCV_DATA_COMPLETION, *PT3_RCV_DATA_COMPLETION;
-
/******************************************************************************/
/* Receive BD Initiator Control. */
/******************************************************************************/
typedef struct {
- T3_32BIT_REGISTER Mode;
- #define RCV_BD_IN_MODE_RESET BIT_0
- #define RCV_BD_IN_MODE_ENABLE BIT_1
- #define RCV_BD_IN_MODE_BD_IN_DIABLED_RCB_ATTN_ENABLE BIT_2
+ T3_32BIT_REGISTER Mode;
+#define RCV_BD_IN_MODE_RESET BIT_0
+#define RCV_BD_IN_MODE_ENABLE BIT_1
+#define RCV_BD_IN_MODE_BD_IN_DIABLED_RCB_ATTN_ENABLE BIT_2
- T3_32BIT_REGISTER Status;
- #define RCV_BD_IN_STATUS_BD_IN_DIABLED_RCB_ATTN BIT_2
+ T3_32BIT_REGISTER Status;
+#define RCV_BD_IN_STATUS_BD_IN_DIABLED_RCB_ATTN BIT_2
- T3_32BIT_REGISTER NicJumboRcvProdIdx;
- T3_32BIT_REGISTER NicStdRcvProdIdx;
- T3_32BIT_REGISTER NicMiniRcvProdIdx;
+ T3_32BIT_REGISTER NicJumboRcvProdIdx;
+ T3_32BIT_REGISTER NicStdRcvProdIdx;
+ T3_32BIT_REGISTER NicMiniRcvProdIdx;
- T3_32BIT_REGISTER MiniRcvThreshold;
- T3_32BIT_REGISTER StdRcvThreshold;
- T3_32BIT_REGISTER JumboRcvThreshold;
+ T3_32BIT_REGISTER MiniRcvThreshold;
+ T3_32BIT_REGISTER StdRcvThreshold;
+ T3_32BIT_REGISTER JumboRcvThreshold;
- /* Unused space. */
- LM_UINT8 Unused[992];
+ /* Unused space. */
+ LM_UINT8 Unused[992];
} T3_RCV_BD_INITIATOR, *PT3_RCV_BD_INITIATOR;
-
/******************************************************************************/
/* Receive BD Completion Control Registers. */
/******************************************************************************/
typedef struct {
- T3_32BIT_REGISTER Mode;
- #define RCV_BD_COMP_MODE_RESET BIT_0
- #define RCV_BD_COMP_MODE_ENABLE BIT_1
- #define RCV_BD_COMP_MODE_ATTN_ENABLE BIT_2
+ T3_32BIT_REGISTER Mode;
+#define RCV_BD_COMP_MODE_RESET BIT_0
+#define RCV_BD_COMP_MODE_ENABLE BIT_1
+#define RCV_BD_COMP_MODE_ATTN_ENABLE BIT_2
- T3_32BIT_REGISTER Status;
- #define RCV_BD_COMP_STATUS_ERROR_ATTN BIT_2
+ T3_32BIT_REGISTER Status;
+#define RCV_BD_COMP_STATUS_ERROR_ATTN BIT_2
- T3_32BIT_REGISTER NicJumboRcvBdProdIdx;
- T3_32BIT_REGISTER NicStdRcvBdProdIdx;
- T3_32BIT_REGISTER NicMiniRcvBdProdIdx;
+ T3_32BIT_REGISTER NicJumboRcvBdProdIdx;
+ T3_32BIT_REGISTER NicStdRcvBdProdIdx;
+ T3_32BIT_REGISTER NicMiniRcvBdProdIdx;
- /* Unused space. */
- LM_UINT8 Unused[1004];
+ /* Unused space. */
+ LM_UINT8 Unused[1004];
} T3_RCV_BD_COMPLETION, *PT3_RCV_BD_COMPLETION;
-
/******************************************************************************/
/* Receive list selector control register. */
/******************************************************************************/
typedef struct {
- T3_32BIT_REGISTER Mode;
- #define RCV_LIST_SEL_MODE_RESET BIT_0
- #define RCV_LIST_SEL_MODE_ENABLE BIT_1
- #define RCV_LIST_SEL_MODE_ATTN_ENABLE BIT_2
+ T3_32BIT_REGISTER Mode;
+#define RCV_LIST_SEL_MODE_RESET BIT_0
+#define RCV_LIST_SEL_MODE_ENABLE BIT_1
+#define RCV_LIST_SEL_MODE_ATTN_ENABLE BIT_2
- T3_32BIT_REGISTER Status;
- #define RCV_LIST_SEL_STATUS_ERROR_ATTN BIT_2
+ T3_32BIT_REGISTER Status;
+#define RCV_LIST_SEL_STATUS_ERROR_ATTN BIT_2
- /* Unused space. */
- LM_UINT8 Unused[1016];
+ /* Unused space. */
+ LM_UINT8 Unused[1016];
} T3_RCV_LIST_SELECTOR, *PT3_RCV_LIST_SELECTOR;
-
/******************************************************************************/
/* Mbuf cluster free registers. */
/******************************************************************************/
typedef struct {
- T3_32BIT_REGISTER Mode;
+ T3_32BIT_REGISTER Mode;
#define MBUF_CLUSTER_FREE_MODE_RESET BIT_0
#define MBUF_CLUSTER_FREE_MODE_ENABLE BIT_1
- T3_32BIT_REGISTER Status;
+ T3_32BIT_REGISTER Status;
- /* Unused space. */
- LM_UINT8 Unused[1016];
+ /* Unused space. */
+ LM_UINT8 Unused[1016];
} T3_MBUF_CLUSTER_FREE, *PT3_MBUF_CLUSTER_FREE;
-
/******************************************************************************/
/* Host coalescing control registers. */
/******************************************************************************/
typedef struct {
- /* Mode. */
- T3_32BIT_REGISTER Mode;
- #define HOST_COALESCE_RESET BIT_0
- #define HOST_COALESCE_ENABLE BIT_1
- #define HOST_COALESCE_ATTN BIT_2
- #define HOST_COALESCE_NOW BIT_3
- #define HOST_COALESCE_FULL_STATUS_MODE BIT_NONE
- #define HOST_COALESCE_64_BYTE_STATUS_MODE BIT_7
- #define HOST_COALESCE_32_BYTE_STATUS_MODE BIT_8
- #define HOST_COALESCE_CLEAR_TICKS_ON_RX_BD_EVENT BIT_9
- #define HOST_COALESCE_CLEAR_TICKS_ON_TX_BD_EVENT BIT_10
- #define HOST_COALESCE_NO_INT_ON_COALESCE_NOW_MODE BIT_11
- #define HOST_COALESCE_NO_INT_ON_FORCE_DMAD_MODE BIT_12
+ /* Mode. */
+ T3_32BIT_REGISTER Mode;
+#define HOST_COALESCE_RESET BIT_0
+#define HOST_COALESCE_ENABLE BIT_1
+#define HOST_COALESCE_ATTN BIT_2
+#define HOST_COALESCE_NOW BIT_3
+#define HOST_COALESCE_FULL_STATUS_MODE BIT_NONE
+#define HOST_COALESCE_64_BYTE_STATUS_MODE BIT_7
+#define HOST_COALESCE_32_BYTE_STATUS_MODE BIT_8
+#define HOST_COALESCE_CLEAR_TICKS_ON_RX_BD_EVENT BIT_9
+#define HOST_COALESCE_CLEAR_TICKS_ON_TX_BD_EVENT BIT_10
+#define HOST_COALESCE_NO_INT_ON_COALESCE_NOW_MODE BIT_11
+#define HOST_COALESCE_NO_INT_ON_FORCE_DMAD_MODE BIT_12
- /* Status. */
- T3_32BIT_REGISTER Status;
- #define HOST_COALESCE_ERROR_ATTN BIT_2
+ /* Status. */
+ T3_32BIT_REGISTER Status;
+#define HOST_COALESCE_ERROR_ATTN BIT_2
- /* Receive coalescing ticks. */
- T3_32BIT_REGISTER RxCoalescingTicks;
+ /* Receive coalescing ticks. */
+ T3_32BIT_REGISTER RxCoalescingTicks;
- /* Send coalescing ticks. */
- T3_32BIT_REGISTER TxCoalescingTicks;
+ /* Send coalescing ticks. */
+ T3_32BIT_REGISTER TxCoalescingTicks;
- /* Receive max coalesced frames. */
- T3_32BIT_REGISTER RxMaxCoalescedFrames;
+ /* Receive max coalesced frames. */
+ T3_32BIT_REGISTER RxMaxCoalescedFrames;
- /* Send max coalesced frames. */
- T3_32BIT_REGISTER TxMaxCoalescedFrames;
+ /* Send max coalesced frames. */
+ T3_32BIT_REGISTER TxMaxCoalescedFrames;
- /* Receive coalescing ticks during interrupt. */
- T3_32BIT_REGISTER RxCoalescedTickDuringInt;
+ /* Receive coalescing ticks during interrupt. */
+ T3_32BIT_REGISTER RxCoalescedTickDuringInt;
- /* Send coalescing ticks during interrupt. */
- T3_32BIT_REGISTER TxCoalescedTickDuringInt;
+ /* Send coalescing ticks during interrupt. */
+ T3_32BIT_REGISTER TxCoalescedTickDuringInt;
- /* Receive max coalesced frames during interrupt. */
- T3_32BIT_REGISTER RxMaxCoalescedFramesDuringInt;
+ /* Receive max coalesced frames during interrupt. */
+ T3_32BIT_REGISTER RxMaxCoalescedFramesDuringInt;
- /* Send max coalesced frames during interrupt. */
- T3_32BIT_REGISTER TxMaxCoalescedFramesDuringInt;
+ /* Send max coalesced frames during interrupt. */
+ T3_32BIT_REGISTER TxMaxCoalescedFramesDuringInt;
- /* Statistics tick. */
- T3_32BIT_REGISTER StatsCoalescingTicks;
+ /* Statistics tick. */
+ T3_32BIT_REGISTER StatsCoalescingTicks;
- /* Unused space. */
- LM_UINT8 Unused2[4];
+ /* Unused space. */
+ LM_UINT8 Unused2[4];
- /* Statistics host address. */
- T3_64BIT_REGISTER StatsBlkHostAddr;
+ /* Statistics host address. */
+ T3_64BIT_REGISTER StatsBlkHostAddr;
- /* Status block host address.*/
- T3_64BIT_REGISTER StatusBlkHostAddr;
+ /* Status block host address. */
+ T3_64BIT_REGISTER StatusBlkHostAddr;
- /* Statistics NIC address. */
- T3_32BIT_REGISTER StatsBlkNicAddr;
+ /* Statistics NIC address. */
+ T3_32BIT_REGISTER StatsBlkNicAddr;
- /* Statust block NIC address. */
- T3_32BIT_REGISTER StatusBlkNicAddr;
+ /* Statust block NIC address. */
+ T3_32BIT_REGISTER StatusBlkNicAddr;
- /* Flow attention registers. */
- T3_32BIT_REGISTER FlowAttn;
+ /* Flow attention registers. */
+ T3_32BIT_REGISTER FlowAttn;
- /* Unused space. */
- LM_UINT8 Unused3[4];
+ /* Unused space. */
+ LM_UINT8 Unused3[4];
- T3_32BIT_REGISTER NicJumboRcvBdConIdx;
- T3_32BIT_REGISTER NicStdRcvBdConIdx;
- T3_32BIT_REGISTER NicMiniRcvBdConIdx;
+ T3_32BIT_REGISTER NicJumboRcvBdConIdx;
+ T3_32BIT_REGISTER NicStdRcvBdConIdx;
+ T3_32BIT_REGISTER NicMiniRcvBdConIdx;
- /* Unused space. */
- LM_UINT8 Unused4[36];
+ /* Unused space. */
+ LM_UINT8 Unused4[36];
- T3_32BIT_REGISTER NicRetProdIdx[16];
- T3_32BIT_REGISTER NicSndBdConIdx[16];
+ T3_32BIT_REGISTER NicRetProdIdx[16];
+ T3_32BIT_REGISTER NicSndBdConIdx[16];
- /* Unused space. */
- LM_UINT8 Unused5[768];
+ /* Unused space. */
+ LM_UINT8 Unused5[768];
} T3_HOST_COALESCING, *PT3_HOST_COALESCING;
-
/******************************************************************************/
/* Memory arbiter registers. */
/******************************************************************************/
typedef struct {
- T3_32BIT_REGISTER Mode;
+ T3_32BIT_REGISTER Mode;
#define T3_MEM_ARBITER_MODE_RESET BIT_0
#define T3_MEM_ARBITER_MODE_ENABLE BIT_1
- T3_32BIT_REGISTER Status;
+ T3_32BIT_REGISTER Status;
- T3_32BIT_REGISTER ArbTrapAddrLow;
- T3_32BIT_REGISTER ArbTrapAddrHigh;
+ T3_32BIT_REGISTER ArbTrapAddrLow;
+ T3_32BIT_REGISTER ArbTrapAddrHigh;
- /* Unused space. */
- LM_UINT8 Unused[1008];
+ /* Unused space. */
+ LM_UINT8 Unused[1008];
} T3_MEM_ARBITER, *PT3_MEM_ARBITER;
-
/******************************************************************************/
/* Buffer manager control register. */
/******************************************************************************/
typedef struct {
- T3_32BIT_REGISTER Mode;
- #define BUFMGR_MODE_RESET BIT_0
- #define BUFMGR_MODE_ENABLE BIT_1
- #define BUFMGR_MODE_ATTN_ENABLE BIT_2
- #define BUFMGR_MODE_BM_TEST BIT_3
- #define BUFMGR_MODE_MBUF_LOW_ATTN_ENABLE BIT_4
-
- T3_32BIT_REGISTER Status;
- #define BUFMGR_STATUS_ERROR BIT_2
- #define BUFMGR_STATUS_MBUF_LOW BIT_4
-
- T3_32BIT_REGISTER MbufPoolAddr;
- T3_32BIT_REGISTER MbufPoolSize;
- T3_32BIT_REGISTER MbufReadDmaLowWaterMark;
- T3_32BIT_REGISTER MbufMacRxLowWaterMark;
- T3_32BIT_REGISTER MbufHighWaterMark;
-
- T3_32BIT_REGISTER RxCpuMbufAllocReq;
- #define BUFMGR_MBUF_ALLOC_BIT BIT_31
- T3_32BIT_REGISTER RxCpuMbufAllocResp;
- T3_32BIT_REGISTER TxCpuMbufAllocReq;
- T3_32BIT_REGISTER TxCpuMbufAllocResp;
-
- T3_32BIT_REGISTER DmaDescPoolAddr;
- T3_32BIT_REGISTER DmaDescPoolSize;
- T3_32BIT_REGISTER DmaLowWaterMark;
- T3_32BIT_REGISTER DmaHighWaterMark;
-
- T3_32BIT_REGISTER RxCpuDmaAllocReq;
- T3_32BIT_REGISTER RxCpuDmaAllocResp;
- T3_32BIT_REGISTER TxCpuDmaAllocReq;
- T3_32BIT_REGISTER TxCpuDmaAllocResp;
-
- T3_32BIT_REGISTER Hwdiag[3];
-
- /* Unused space. */
- LM_UINT8 Unused[936];
-} T3_BUFFER_MANAGER, *PT3_BUFFER_MANAGER;
+ T3_32BIT_REGISTER Mode;
+#define BUFMGR_MODE_RESET BIT_0
+#define BUFMGR_MODE_ENABLE BIT_1
+#define BUFMGR_MODE_ATTN_ENABLE BIT_2
+#define BUFMGR_MODE_BM_TEST BIT_3
+#define BUFMGR_MODE_MBUF_LOW_ATTN_ENABLE BIT_4
+
+ T3_32BIT_REGISTER Status;
+#define BUFMGR_STATUS_ERROR BIT_2
+#define BUFMGR_STATUS_MBUF_LOW BIT_4
+
+ T3_32BIT_REGISTER MbufPoolAddr;
+ T3_32BIT_REGISTER MbufPoolSize;
+ T3_32BIT_REGISTER MbufReadDmaLowWaterMark;
+ T3_32BIT_REGISTER MbufMacRxLowWaterMark;
+ T3_32BIT_REGISTER MbufHighWaterMark;
+
+ T3_32BIT_REGISTER RxCpuMbufAllocReq;
+#define BUFMGR_MBUF_ALLOC_BIT BIT_31
+ T3_32BIT_REGISTER RxCpuMbufAllocResp;
+ T3_32BIT_REGISTER TxCpuMbufAllocReq;
+ T3_32BIT_REGISTER TxCpuMbufAllocResp;
+
+ T3_32BIT_REGISTER DmaDescPoolAddr;
+ T3_32BIT_REGISTER DmaDescPoolSize;
+ T3_32BIT_REGISTER DmaLowWaterMark;
+ T3_32BIT_REGISTER DmaHighWaterMark;
+
+ T3_32BIT_REGISTER RxCpuDmaAllocReq;
+ T3_32BIT_REGISTER RxCpuDmaAllocResp;
+ T3_32BIT_REGISTER TxCpuDmaAllocReq;
+ T3_32BIT_REGISTER TxCpuDmaAllocResp;
+
+ T3_32BIT_REGISTER Hwdiag[3];
+ /* Unused space. */
+ LM_UINT8 Unused[936];
+} T3_BUFFER_MANAGER, *PT3_BUFFER_MANAGER;
/******************************************************************************/
/* Read DMA control registers. */
/******************************************************************************/
typedef struct {
- T3_32BIT_REGISTER Mode;
- #define DMA_READ_MODE_RESET BIT_0
- #define DMA_READ_MODE_ENABLE BIT_1
- #define DMA_READ_MODE_TARGET_ABORT_ATTN_ENABLE BIT_2
- #define DMA_READ_MODE_MASTER_ABORT_ATTN_ENABLE BIT_3
- #define DMA_READ_MODE_PARITY_ERROR_ATTN_ENABLE BIT_4
- #define DMA_READ_MODE_ADDR_OVERFLOW_ATTN_ENABLE BIT_5
- #define DMA_READ_MODE_FIFO_OVERRUN_ATTN_ENABLE BIT_6
- #define DMA_READ_MODE_FIFO_UNDERRUN_ATTN_ENABLE BIT_7
- #define DMA_READ_MODE_FIFO_OVERREAD_ATTN_ENABLE BIT_8
- #define DMA_READ_MODE_LONG_READ_ATTN_ENABLE BIT_9
- #define DMA_READ_MODE_SPLIT_ENABLE BIT_11
- #define DMA_READ_MODE_SPLIT_RESET BIT_12
-
- T3_32BIT_REGISTER Status;
- #define DMA_READ_STATUS_TARGET_ABORT_ATTN BIT_2
- #define DMA_READ_STATUS_MASTER_ABORT_ATTN BIT_3
- #define DMA_READ_STATUS_PARITY_ERROR_ATTN BIT_4
- #define DMA_READ_STATUS_ADDR_OVERFLOW_ATTN BIT_5
- #define DMA_READ_STATUS_FIFO_OVERRUN_ATTN BIT_6
- #define DMA_READ_STATUS_FIFO_UNDERRUN_ATTN BIT_7
- #define DMA_READ_STATUS_FIFO_OVERREAD_ATTN BIT_8
- #define DMA_READ_STATUS_LONG_READ_ATTN BIT_9
-
- /* Unused space. */
- LM_UINT8 Unused[1016];
+ T3_32BIT_REGISTER Mode;
+#define DMA_READ_MODE_RESET BIT_0
+#define DMA_READ_MODE_ENABLE BIT_1
+#define DMA_READ_MODE_TARGET_ABORT_ATTN_ENABLE BIT_2
+#define DMA_READ_MODE_MASTER_ABORT_ATTN_ENABLE BIT_3
+#define DMA_READ_MODE_PARITY_ERROR_ATTN_ENABLE BIT_4
+#define DMA_READ_MODE_ADDR_OVERFLOW_ATTN_ENABLE BIT_5
+#define DMA_READ_MODE_FIFO_OVERRUN_ATTN_ENABLE BIT_6
+#define DMA_READ_MODE_FIFO_UNDERRUN_ATTN_ENABLE BIT_7
+#define DMA_READ_MODE_FIFO_OVERREAD_ATTN_ENABLE BIT_8
+#define DMA_READ_MODE_LONG_READ_ATTN_ENABLE BIT_9
+#define DMA_READ_MODE_SPLIT_ENABLE BIT_11
+#define DMA_READ_MODE_SPLIT_RESET BIT_12
+
+ T3_32BIT_REGISTER Status;
+#define DMA_READ_STATUS_TARGET_ABORT_ATTN BIT_2
+#define DMA_READ_STATUS_MASTER_ABORT_ATTN BIT_3
+#define DMA_READ_STATUS_PARITY_ERROR_ATTN BIT_4
+#define DMA_READ_STATUS_ADDR_OVERFLOW_ATTN BIT_5
+#define DMA_READ_STATUS_FIFO_OVERRUN_ATTN BIT_6
+#define DMA_READ_STATUS_FIFO_UNDERRUN_ATTN BIT_7
+#define DMA_READ_STATUS_FIFO_OVERREAD_ATTN BIT_8
+#define DMA_READ_STATUS_LONG_READ_ATTN BIT_9
+
+ /* Unused space. */
+ LM_UINT8 Unused[1016];
} T3_DMA_READ, *PT3_DMA_READ;
-typedef union T3_CPU
-{
- struct
- {
- T3_32BIT_REGISTER mode;
- #define CPU_MODE_HALT BIT_10
- #define CPU_MODE_RESET BIT_0
- T3_32BIT_REGISTER state;
- T3_32BIT_REGISTER EventMask;
- T3_32BIT_REGISTER reserved1[4];
- T3_32BIT_REGISTER PC;
- T3_32BIT_REGISTER Instruction;
- T3_32BIT_REGISTER SpadUnderflow;
- T3_32BIT_REGISTER WatchdogClear;
- T3_32BIT_REGISTER WatchdogVector;
- T3_32BIT_REGISTER WatchdogSavedPC;
- T3_32BIT_REGISTER HardwareBp;
- T3_32BIT_REGISTER reserved2[3];
- T3_32BIT_REGISTER WatchdogSavedState;
- T3_32BIT_REGISTER LastBrchAddr;
- T3_32BIT_REGISTER SpadUnderflowSet;
- T3_32BIT_REGISTER reserved3[(0x200-0x50)/4];
- T3_32BIT_REGISTER Regs[32];
- T3_32BIT_REGISTER reserved4[(0x400-0x280)/4];
- }reg;
-}T3_CPU, *PT3_CPU;
+typedef union T3_CPU {
+ struct {
+ T3_32BIT_REGISTER mode;
+#define CPU_MODE_HALT BIT_10
+#define CPU_MODE_RESET BIT_0
+ T3_32BIT_REGISTER state;
+ T3_32BIT_REGISTER EventMask;
+ T3_32BIT_REGISTER reserved1[4];
+ T3_32BIT_REGISTER PC;
+ T3_32BIT_REGISTER Instruction;
+ T3_32BIT_REGISTER SpadUnderflow;
+ T3_32BIT_REGISTER WatchdogClear;
+ T3_32BIT_REGISTER WatchdogVector;
+ T3_32BIT_REGISTER WatchdogSavedPC;
+ T3_32BIT_REGISTER HardwareBp;
+ T3_32BIT_REGISTER reserved2[3];
+ T3_32BIT_REGISTER WatchdogSavedState;
+ T3_32BIT_REGISTER LastBrchAddr;
+ T3_32BIT_REGISTER SpadUnderflowSet;
+ T3_32BIT_REGISTER reserved3[(0x200 - 0x50) / 4];
+ T3_32BIT_REGISTER Regs[32];
+ T3_32BIT_REGISTER reserved4[(0x400 - 0x280) / 4];
+ } reg;
+} T3_CPU, *PT3_CPU;
/******************************************************************************/
/* Write DMA control registers. */
/******************************************************************************/
typedef struct {
- T3_32BIT_REGISTER Mode;
- #define DMA_WRITE_MODE_RESET BIT_0
- #define DMA_WRITE_MODE_ENABLE BIT_1
- #define DMA_WRITE_MODE_TARGET_ABORT_ATTN_ENABLE BIT_2
- #define DMA_WRITE_MODE_MASTER_ABORT_ATTN_ENABLE BIT_3
- #define DMA_WRITE_MODE_PARITY_ERROR_ATTN_ENABLE BIT_4
- #define DMA_WRITE_MODE_ADDR_OVERFLOW_ATTN_ENABLE BIT_5
- #define DMA_WRITE_MODE_FIFO_OVERRUN_ATTN_ENABLE BIT_6
- #define DMA_WRITE_MODE_FIFO_UNDERRUN_ATTN_ENABLE BIT_7
- #define DMA_WRITE_MODE_FIFO_OVERREAD_ATTN_ENABLE BIT_8
- #define DMA_WRITE_MODE_LONG_READ_ATTN_ENABLE BIT_9
-
- T3_32BIT_REGISTER Status;
- #define DMA_WRITE_STATUS_TARGET_ABORT_ATTN BIT_2
- #define DMA_WRITE_STATUS_MASTER_ABORT_ATTN BIT_3
- #define DMA_WRITE_STATUS_PARITY_ERROR_ATTN BIT_4
- #define DMA_WRITE_STATUS_ADDR_OVERFLOW_ATTN BIT_5
- #define DMA_WRITE_STATUS_FIFO_OVERRUN_ATTN BIT_6
- #define DMA_WRITE_STATUS_FIFO_UNDERRUN_ATTN BIT_7
- #define DMA_WRITE_STATUS_FIFO_OVERREAD_ATTN BIT_8
- #define DMA_WRITE_STATUS_LONG_READ_ATTN BIT_9
-
- /* Unused space. */
- LM_UINT8 Unused[1016];
-} T3_DMA_WRITE, *PT3_DMA_WRITE;
+ T3_32BIT_REGISTER Mode;
+#define DMA_WRITE_MODE_RESET BIT_0
+#define DMA_WRITE_MODE_ENABLE BIT_1
+#define DMA_WRITE_MODE_TARGET_ABORT_ATTN_ENABLE BIT_2
+#define DMA_WRITE_MODE_MASTER_ABORT_ATTN_ENABLE BIT_3
+#define DMA_WRITE_MODE_PARITY_ERROR_ATTN_ENABLE BIT_4
+#define DMA_WRITE_MODE_ADDR_OVERFLOW_ATTN_ENABLE BIT_5
+#define DMA_WRITE_MODE_FIFO_OVERRUN_ATTN_ENABLE BIT_6
+#define DMA_WRITE_MODE_FIFO_UNDERRUN_ATTN_ENABLE BIT_7
+#define DMA_WRITE_MODE_FIFO_OVERREAD_ATTN_ENABLE BIT_8
+#define DMA_WRITE_MODE_LONG_READ_ATTN_ENABLE BIT_9
+
+ T3_32BIT_REGISTER Status;
+#define DMA_WRITE_STATUS_TARGET_ABORT_ATTN BIT_2
+#define DMA_WRITE_STATUS_MASTER_ABORT_ATTN BIT_3
+#define DMA_WRITE_STATUS_PARITY_ERROR_ATTN BIT_4
+#define DMA_WRITE_STATUS_ADDR_OVERFLOW_ATTN BIT_5
+#define DMA_WRITE_STATUS_FIFO_OVERRUN_ATTN BIT_6
+#define DMA_WRITE_STATUS_FIFO_UNDERRUN_ATTN BIT_7
+#define DMA_WRITE_STATUS_FIFO_OVERREAD_ATTN BIT_8
+#define DMA_WRITE_STATUS_LONG_READ_ATTN BIT_9
+ /* Unused space. */
+ LM_UINT8 Unused[1016];
+} T3_DMA_WRITE, *PT3_DMA_WRITE;
/******************************************************************************/
/* Mailbox registers. */
/******************************************************************************/
typedef struct {
- /* Interrupt mailbox registers. */
- T3_64BIT_REGISTER Interrupt[4];
+ /* Interrupt mailbox registers. */
+ T3_64BIT_REGISTER Interrupt[4];
- /* General mailbox registers. */
- T3_64BIT_REGISTER General[8];
+ /* General mailbox registers. */
+ T3_64BIT_REGISTER General[8];
- /* Reload statistics mailbox. */
- T3_64BIT_REGISTER ReloadStat;
+ /* Reload statistics mailbox. */
+ T3_64BIT_REGISTER ReloadStat;
- /* Receive BD ring producer index registers. */
- T3_64BIT_REGISTER RcvStdProdIdx;
- T3_64BIT_REGISTER RcvJumboProdIdx;
- T3_64BIT_REGISTER RcvMiniProdIdx;
+ /* Receive BD ring producer index registers. */
+ T3_64BIT_REGISTER RcvStdProdIdx;
+ T3_64BIT_REGISTER RcvJumboProdIdx;
+ T3_64BIT_REGISTER RcvMiniProdIdx;
- /* Receive return ring consumer index registers. */
- T3_64BIT_REGISTER RcvRetConIdx[16];
+ /* Receive return ring consumer index registers. */
+ T3_64BIT_REGISTER RcvRetConIdx[16];
- /* Send BD ring host producer index registers. */
- T3_64BIT_REGISTER SendHostProdIdx[16];
+ /* Send BD ring host producer index registers. */
+ T3_64BIT_REGISTER SendHostProdIdx[16];
- /* Send BD ring nic producer index registers. */
- T3_64BIT_REGISTER SendNicProdIdx[16];
-}T3_MAILBOX, *PT3_MAILBOX;
+ /* Send BD ring nic producer index registers. */
+ T3_64BIT_REGISTER SendNicProdIdx[16];
+} T3_MAILBOX, *PT3_MAILBOX;
typedef struct {
- T3_MAILBOX Mailbox;
+ T3_MAILBOX Mailbox;
- /* Priority mailbox registers. */
- T3_32BIT_REGISTER HighPriorityEventVector;
- T3_32BIT_REGISTER HighPriorityEventMask;
- T3_32BIT_REGISTER LowPriorityEventVector;
- T3_32BIT_REGISTER LowPriorityEventMask;
+ /* Priority mailbox registers. */
+ T3_32BIT_REGISTER HighPriorityEventVector;
+ T3_32BIT_REGISTER HighPriorityEventMask;
+ T3_32BIT_REGISTER LowPriorityEventVector;
+ T3_32BIT_REGISTER LowPriorityEventMask;
- /* Unused space. */
- LM_UINT8 Unused[496];
+ /* Unused space. */
+ LM_UINT8 Unused[496];
} T3_GRC_MAILBOX, *PT3_GRC_MAILBOX;
-
/******************************************************************************/
/* Flow through queues. */
/******************************************************************************/
typedef struct {
- T3_32BIT_REGISTER Reset;
-
- LM_UINT8 Unused[12];
-
- T3_32BIT_REGISTER DmaNormalReadFtqCtrl;
- T3_32BIT_REGISTER DmaNormalReadFtqFullCnt;
- T3_32BIT_REGISTER DmaNormalReadFtqFifoEnqueueDequeue;
- T3_32BIT_REGISTER DmaNormalReadFtqFifoWritePeek;
-
- T3_32BIT_REGISTER DmaHighReadFtqCtrl;
- T3_32BIT_REGISTER DmaHighReadFtqFullCnt;
- T3_32BIT_REGISTER DmaHighReadFtqFifoEnqueueDequeue;
- T3_32BIT_REGISTER DmaHighReadFtqFifoWritePeek;
-
- T3_32BIT_REGISTER DmaCompDiscardFtqCtrl;
- T3_32BIT_REGISTER DmaCompDiscardFtqFullCnt;
- T3_32BIT_REGISTER DmaCompDiscardFtqFifoEnqueueDequeue;
- T3_32BIT_REGISTER DmaCompDiscardFtqFifoWritePeek;
-
- T3_32BIT_REGISTER SendBdCompFtqCtrl;
- T3_32BIT_REGISTER SendBdCompFtqFullCnt;
- T3_32BIT_REGISTER SendBdCompFtqFifoEnqueueDequeue;
- T3_32BIT_REGISTER SendBdCompFtqFifoWritePeek;
-
- T3_32BIT_REGISTER SendDataInitiatorFtqCtrl;
- T3_32BIT_REGISTER SendDataInitiatorFtqFullCnt;
- T3_32BIT_REGISTER SendDataInitiatorFtqFifoEnqueueDequeue;
- T3_32BIT_REGISTER SendDataInitiatorFtqFifoWritePeek;
-
- T3_32BIT_REGISTER DmaNormalWriteFtqCtrl;
- T3_32BIT_REGISTER DmaNormalWriteFtqFullCnt;
- T3_32BIT_REGISTER DmaNormalWriteFtqFifoEnqueueDequeue;
- T3_32BIT_REGISTER DmaNormalWriteFtqFifoWritePeek;
-
- T3_32BIT_REGISTER DmaHighWriteFtqCtrl;
- T3_32BIT_REGISTER DmaHighWriteFtqFullCnt;
- T3_32BIT_REGISTER DmaHighWriteFtqFifoEnqueueDequeue;
- T3_32BIT_REGISTER DmaHighWriteFtqFifoWritePeek;
-
- T3_32BIT_REGISTER SwType1FtqCtrl;
- T3_32BIT_REGISTER SwType1FtqFullCnt;
- T3_32BIT_REGISTER SwType1FtqFifoEnqueueDequeue;
- T3_32BIT_REGISTER SwType1FtqFifoWritePeek;
-
- T3_32BIT_REGISTER SendDataCompFtqCtrl;
- T3_32BIT_REGISTER SendDataCompFtqFullCnt;
- T3_32BIT_REGISTER SendDataCompFtqFifoEnqueueDequeue;
- T3_32BIT_REGISTER SendDataCompFtqFifoWritePeek;
-
- T3_32BIT_REGISTER HostCoalesceFtqCtrl;
- T3_32BIT_REGISTER HostCoalesceFtqFullCnt;
- T3_32BIT_REGISTER HostCoalesceFtqFifoEnqueueDequeue;
- T3_32BIT_REGISTER HostCoalesceFtqFifoWritePeek;
-
- T3_32BIT_REGISTER MacTxFtqCtrl;
- T3_32BIT_REGISTER MacTxFtqFullCnt;
- T3_32BIT_REGISTER MacTxFtqFifoEnqueueDequeue;
- T3_32BIT_REGISTER MacTxFtqFifoWritePeek;
-
- T3_32BIT_REGISTER MbufClustFreeFtqCtrl;
- T3_32BIT_REGISTER MbufClustFreeFtqFullCnt;
- T3_32BIT_REGISTER MbufClustFreeFtqFifoEnqueueDequeue;
- T3_32BIT_REGISTER MbufClustFreeFtqFifoWritePeek;
-
- T3_32BIT_REGISTER RcvBdCompFtqCtrl;
- T3_32BIT_REGISTER RcvBdCompFtqFullCnt;
- T3_32BIT_REGISTER RcvBdCompFtqFifoEnqueueDequeue;
- T3_32BIT_REGISTER RcvBdCompFtqFifoWritePeek;
-
- T3_32BIT_REGISTER RcvListPlmtFtqCtrl;
- T3_32BIT_REGISTER RcvListPlmtFtqFullCnt;
- T3_32BIT_REGISTER RcvListPlmtFtqFifoEnqueueDequeue;
- T3_32BIT_REGISTER RcvListPlmtFtqFifoWritePeek;
-
- T3_32BIT_REGISTER RcvDataBdInitiatorFtqCtrl;
- T3_32BIT_REGISTER RcvDataBdInitiatorFtqFullCnt;
- T3_32BIT_REGISTER RcvDataBdInitiatorFtqFifoEnqueueDequeue;
- T3_32BIT_REGISTER RcvDataBdInitiatorFtqFifoWritePeek;
-
- T3_32BIT_REGISTER RcvDataCompFtqCtrl;
- T3_32BIT_REGISTER RcvDataCompFtqFullCnt;
- T3_32BIT_REGISTER RcvDataCompFtqFifoEnqueueDequeue;
- T3_32BIT_REGISTER RcvDataCompFtqFifoWritePeek;
-
- T3_32BIT_REGISTER SwType2FtqCtrl;
- T3_32BIT_REGISTER SwType2FtqFullCnt;
- T3_32BIT_REGISTER SwType2FtqFifoEnqueueDequeue;
- T3_32BIT_REGISTER SwType2FtqFifoWritePeek;
-
- /* Unused space. */
- LM_UINT8 Unused2[736];
-} T3_FTQ, *PT3_FTQ;
+ T3_32BIT_REGISTER Reset;
+
+ LM_UINT8 Unused[12];
+
+ T3_32BIT_REGISTER DmaNormalReadFtqCtrl;
+ T3_32BIT_REGISTER DmaNormalReadFtqFullCnt;
+ T3_32BIT_REGISTER DmaNormalReadFtqFifoEnqueueDequeue;
+ T3_32BIT_REGISTER DmaNormalReadFtqFifoWritePeek;
+
+ T3_32BIT_REGISTER DmaHighReadFtqCtrl;
+ T3_32BIT_REGISTER DmaHighReadFtqFullCnt;
+ T3_32BIT_REGISTER DmaHighReadFtqFifoEnqueueDequeue;
+ T3_32BIT_REGISTER DmaHighReadFtqFifoWritePeek;
+
+ T3_32BIT_REGISTER DmaCompDiscardFtqCtrl;
+ T3_32BIT_REGISTER DmaCompDiscardFtqFullCnt;
+ T3_32BIT_REGISTER DmaCompDiscardFtqFifoEnqueueDequeue;
+ T3_32BIT_REGISTER DmaCompDiscardFtqFifoWritePeek;
+
+ T3_32BIT_REGISTER SendBdCompFtqCtrl;
+ T3_32BIT_REGISTER SendBdCompFtqFullCnt;
+ T3_32BIT_REGISTER SendBdCompFtqFifoEnqueueDequeue;
+ T3_32BIT_REGISTER SendBdCompFtqFifoWritePeek;
+
+ T3_32BIT_REGISTER SendDataInitiatorFtqCtrl;
+ T3_32BIT_REGISTER SendDataInitiatorFtqFullCnt;
+ T3_32BIT_REGISTER SendDataInitiatorFtqFifoEnqueueDequeue;
+ T3_32BIT_REGISTER SendDataInitiatorFtqFifoWritePeek;
+
+ T3_32BIT_REGISTER DmaNormalWriteFtqCtrl;
+ T3_32BIT_REGISTER DmaNormalWriteFtqFullCnt;
+ T3_32BIT_REGISTER DmaNormalWriteFtqFifoEnqueueDequeue;
+ T3_32BIT_REGISTER DmaNormalWriteFtqFifoWritePeek;
+
+ T3_32BIT_REGISTER DmaHighWriteFtqCtrl;
+ T3_32BIT_REGISTER DmaHighWriteFtqFullCnt;
+ T3_32BIT_REGISTER DmaHighWriteFtqFifoEnqueueDequeue;
+ T3_32BIT_REGISTER DmaHighWriteFtqFifoWritePeek;
+
+ T3_32BIT_REGISTER SwType1FtqCtrl;
+ T3_32BIT_REGISTER SwType1FtqFullCnt;
+ T3_32BIT_REGISTER SwType1FtqFifoEnqueueDequeue;
+ T3_32BIT_REGISTER SwType1FtqFifoWritePeek;
+
+ T3_32BIT_REGISTER SendDataCompFtqCtrl;
+ T3_32BIT_REGISTER SendDataCompFtqFullCnt;
+ T3_32BIT_REGISTER SendDataCompFtqFifoEnqueueDequeue;
+ T3_32BIT_REGISTER SendDataCompFtqFifoWritePeek;
+
+ T3_32BIT_REGISTER HostCoalesceFtqCtrl;
+ T3_32BIT_REGISTER HostCoalesceFtqFullCnt;
+ T3_32BIT_REGISTER HostCoalesceFtqFifoEnqueueDequeue;
+ T3_32BIT_REGISTER HostCoalesceFtqFifoWritePeek;
+
+ T3_32BIT_REGISTER MacTxFtqCtrl;
+ T3_32BIT_REGISTER MacTxFtqFullCnt;
+ T3_32BIT_REGISTER MacTxFtqFifoEnqueueDequeue;
+ T3_32BIT_REGISTER MacTxFtqFifoWritePeek;
+
+ T3_32BIT_REGISTER MbufClustFreeFtqCtrl;
+ T3_32BIT_REGISTER MbufClustFreeFtqFullCnt;
+ T3_32BIT_REGISTER MbufClustFreeFtqFifoEnqueueDequeue;
+ T3_32BIT_REGISTER MbufClustFreeFtqFifoWritePeek;
+
+ T3_32BIT_REGISTER RcvBdCompFtqCtrl;
+ T3_32BIT_REGISTER RcvBdCompFtqFullCnt;
+ T3_32BIT_REGISTER RcvBdCompFtqFifoEnqueueDequeue;
+ T3_32BIT_REGISTER RcvBdCompFtqFifoWritePeek;
+
+ T3_32BIT_REGISTER RcvListPlmtFtqCtrl;
+ T3_32BIT_REGISTER RcvListPlmtFtqFullCnt;
+ T3_32BIT_REGISTER RcvListPlmtFtqFifoEnqueueDequeue;
+ T3_32BIT_REGISTER RcvListPlmtFtqFifoWritePeek;
+
+ T3_32BIT_REGISTER RcvDataBdInitiatorFtqCtrl;
+ T3_32BIT_REGISTER RcvDataBdInitiatorFtqFullCnt;
+ T3_32BIT_REGISTER RcvDataBdInitiatorFtqFifoEnqueueDequeue;
+ T3_32BIT_REGISTER RcvDataBdInitiatorFtqFifoWritePeek;
+
+ T3_32BIT_REGISTER RcvDataCompFtqCtrl;
+ T3_32BIT_REGISTER RcvDataCompFtqFullCnt;
+ T3_32BIT_REGISTER RcvDataCompFtqFifoEnqueueDequeue;
+ T3_32BIT_REGISTER RcvDataCompFtqFifoWritePeek;
+
+ T3_32BIT_REGISTER SwType2FtqCtrl;
+ T3_32BIT_REGISTER SwType2FtqFullCnt;
+ T3_32BIT_REGISTER SwType2FtqFifoEnqueueDequeue;
+ T3_32BIT_REGISTER SwType2FtqFifoWritePeek;
+ /* Unused space. */
+ LM_UINT8 Unused2[736];
+} T3_FTQ, *PT3_FTQ;
/******************************************************************************/
/* Message signaled interrupt registers. */
/******************************************************************************/
typedef struct {
- T3_32BIT_REGISTER Mode;
+ T3_32BIT_REGISTER Mode;
#define MSI_MODE_RESET BIT_0
#define MSI_MODE_ENABLE BIT_1
- T3_32BIT_REGISTER Status;
+ T3_32BIT_REGISTER Status;
- T3_32BIT_REGISTER MsiFifoAccess;
+ T3_32BIT_REGISTER MsiFifoAccess;
- /* Unused space. */
- LM_UINT8 Unused[1012];
+ /* Unused space. */
+ LM_UINT8 Unused[1012];
} T3_MSG_SIGNALED_INT, *PT3_MSG_SIGNALED_INT;
-
/******************************************************************************/
/* DMA Completion registes. */
/******************************************************************************/
typedef struct {
- T3_32BIT_REGISTER Mode;
- #define DMA_COMP_MODE_RESET BIT_0
- #define DMA_COMP_MODE_ENABLE BIT_1
+ T3_32BIT_REGISTER Mode;
+#define DMA_COMP_MODE_RESET BIT_0
+#define DMA_COMP_MODE_ENABLE BIT_1
- /* Unused space. */
- LM_UINT8 Unused[1020];
+ /* Unused space. */
+ LM_UINT8 Unused[1020];
} T3_DMA_COMPLETION, *PT3_DMA_COMPLETION;
-
/******************************************************************************/
/* GRC registers. */
/******************************************************************************/
typedef struct {
- /* Mode control register. */
- T3_32BIT_REGISTER Mode;
- #define GRC_MODE_UPDATE_ON_COALESCING BIT_0
- #define GRC_MODE_BYTE_SWAP_NON_FRAME_DATA BIT_1
- #define GRC_MODE_WORD_SWAP_NON_FRAME_DATA BIT_2
- #define GRC_MODE_BYTE_SWAP_DATA BIT_4
- #define GRC_MODE_WORD_SWAP_DATA BIT_5
- #define GRC_MODE_SPLIT_HEADER_MODE BIT_8
- #define GRC_MODE_NO_FRAME_CRACKING BIT_9
- #define GRC_MODE_INCLUDE_CRC BIT_10
- #define GRC_MODE_ALLOW_BAD_FRAMES BIT_11
- #define GRC_MODE_NO_INTERRUPT_ON_SENDS BIT_13
- #define GRC_MODE_NO_INTERRUPT_ON_RECEIVE BIT_14
- #define GRC_MODE_FORCE_32BIT_PCI_BUS_MODE BIT_15
- #define GRC_MODE_HOST_STACK_UP BIT_16
- #define GRC_MODE_HOST_SEND_BDS BIT_17
- #define GRC_MODE_TX_NO_PSEUDO_HEADER_CHKSUM BIT_20
- #define GRC_MODE_RX_NO_PSEUDO_HEADER_CHKSUM BIT_23
- #define GRC_MODE_INT_ON_TX_CPU_ATTN BIT_24
- #define GRC_MODE_INT_ON_RX_CPU_ATTN BIT_25
- #define GRC_MODE_INT_ON_MAC_ATTN BIT_26
- #define GRC_MODE_INT_ON_DMA_ATTN BIT_27
- #define GRC_MODE_INT_ON_FLOW_ATTN BIT_28
- #define GRC_MODE_4X_NIC_BASED_SEND_RINGS BIT_29
- #define GRC_MODE_MULTICAST_FRAME_ENABLE BIT_30
-
- /* Misc configuration register. */
- T3_32BIT_REGISTER MiscCfg;
- #define GRC_MISC_CFG_CORE_CLOCK_RESET BIT_0
- #define GRC_MISC_PRESCALAR_TIMER_MASK 0xfe
- #define GRC_MISC_BD_ID_MASK 0x0001e000
- #define GRC_MISC_BD_ID_5700 0x0001e000
- #define GRC_MISC_BD_ID_5701 0x00000000
- #define GRC_MISC_BD_ID_5703 0x00000000
- #define GRC_MISC_BD_ID_5703S 0x00002000
- #define GRC_MISC_BD_ID_5702FE 0x00004000
- #define GRC_MISC_BD_ID_5704 0x00000000
- #define GRC_MISC_BD_ID_5704CIOBE 0x00004000
-
- /* Miscellaneous local control register. */
- T3_32BIT_REGISTER LocalCtrl;
- #define GRC_MISC_LOCAL_CTRL_INT_ACTIVE BIT_0
- #define GRC_MISC_LOCAL_CTRL_CLEAR_INT BIT_1
- #define GRC_MISC_LOCAL_CTRL_SET_INT BIT_2
- #define GRC_MISC_LOCAL_CTRL_INT_ON_ATTN BIT_3
- #define GRC_MISC_LOCAL_CTRL_GPIO_INPUT0 BIT_8
- #define GRC_MISC_LOCAL_CTRL_GPIO_INPUT1 BIT_9
- #define GRC_MISC_LOCAL_CTRL_GPIO_INPUT2 BIT_10
- #define GRC_MISC_LOCAL_CTRL_GPIO_OE0 BIT_11
- #define GRC_MISC_LOCAL_CTRL_GPIO_OE1 BIT_12
- #define GRC_MISC_LOCAL_CTRL_GPIO_OE2 BIT_13
- #define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 BIT_14
- #define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 BIT_15
- #define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2 BIT_16
- #define GRC_MISC_LOCAL_CTRL_ENABLE_EXT_MEMORY BIT_17
- #define GRC_MISC_LOCAL_CTRL_BANK_SELECT BIT_21
- #define GRC_MISC_LOCAL_CTRL_SSRAM_TYPE BIT_22
-
- #define GRC_MISC_MEMSIZE_256K 0
- #define GRC_MISC_MEMSIZE_512K (1 << 18)
- #define GRC_MISC_MEMSIZE_1024K (2 << 18)
- #define GRC_MISC_MEMSIZE_2048K (3 << 18)
- #define GRC_MISC_MEMSIZE_4096K (4 << 18)
- #define GRC_MISC_MEMSIZE_8192K (5 << 18)
- #define GRC_MISC_MEMSIZE_16M (6 << 18)
- #define GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM BIT_24
-
-
- T3_32BIT_REGISTER Timer;
-
- T3_32BIT_REGISTER RxCpuEvent;
- T3_32BIT_REGISTER RxTimerRef;
- T3_32BIT_REGISTER RxCpuSemaphore;
- T3_32BIT_REGISTER RemoteRxCpuAttn;
-
- T3_32BIT_REGISTER TxCpuEvent;
- T3_32BIT_REGISTER TxTimerRef;
- T3_32BIT_REGISTER TxCpuSemaphore;
- T3_32BIT_REGISTER RemoteTxCpuAttn;
-
- T3_64BIT_REGISTER MemoryPowerUp;
-
- T3_32BIT_REGISTER EepromAddr;
- #define SEEPROM_ADDR_WRITE 0
- #define SEEPROM_ADDR_READ (1 << 31)
- #define SEEPROM_ADDR_RW_MASK 0x80000000
- #define SEEPROM_ADDR_COMPLETE (1 << 30)
- #define SEEPROM_ADDR_FSM_RESET (1 << 29)
- #define SEEPROM_ADDR_DEV_ID(x) (x << 26)
- #define SEEPROM_ADDR_DEV_ID_MASK 0x1c000000
- #define SEEPROM_ADDR_START (1 << 25)
- #define SEEPROM_ADDR_CLK_PERD(x) (x << 16)
- #define SEEPROM_ADDR_ADDRESS(x) (x & 0xfffc)
- #define SEEPROM_ADDR_ADDRESS_MASK 0x0000ffff
-
- #define SEEPROM_CLOCK_PERIOD 60
- #define SEEPROM_CHIP_SIZE (64 * 1024)
-
- T3_32BIT_REGISTER EepromData;
- T3_32BIT_REGISTER EepromCtrl;
-
- T3_32BIT_REGISTER MdiCtrl;
- T3_32BIT_REGISTER SepromDelay;
-
- /* Unused space. */
- LM_UINT8 Unused[948];
-} T3_GRC, *PT3_GRC;
+ /* Mode control register. */
+ T3_32BIT_REGISTER Mode;
+#define GRC_MODE_UPDATE_ON_COALESCING BIT_0
+#define GRC_MODE_BYTE_SWAP_NON_FRAME_DATA BIT_1
+#define GRC_MODE_WORD_SWAP_NON_FRAME_DATA BIT_2
+#define GRC_MODE_BYTE_SWAP_DATA BIT_4
+#define GRC_MODE_WORD_SWAP_DATA BIT_5
+#define GRC_MODE_SPLIT_HEADER_MODE BIT_8
+#define GRC_MODE_NO_FRAME_CRACKING BIT_9
+#define GRC_MODE_INCLUDE_CRC BIT_10
+#define GRC_MODE_ALLOW_BAD_FRAMES BIT_11
+#define GRC_MODE_NO_INTERRUPT_ON_SENDS BIT_13
+#define GRC_MODE_NO_INTERRUPT_ON_RECEIVE BIT_14
+#define GRC_MODE_FORCE_32BIT_PCI_BUS_MODE BIT_15
+#define GRC_MODE_HOST_STACK_UP BIT_16
+#define GRC_MODE_HOST_SEND_BDS BIT_17
+#define GRC_MODE_TX_NO_PSEUDO_HEADER_CHKSUM BIT_20
+#define GRC_MODE_RX_NO_PSEUDO_HEADER_CHKSUM BIT_23
+#define GRC_MODE_INT_ON_TX_CPU_ATTN BIT_24
+#define GRC_MODE_INT_ON_RX_CPU_ATTN BIT_25
+#define GRC_MODE_INT_ON_MAC_ATTN BIT_26
+#define GRC_MODE_INT_ON_DMA_ATTN BIT_27
+#define GRC_MODE_INT_ON_FLOW_ATTN BIT_28
+#define GRC_MODE_4X_NIC_BASED_SEND_RINGS BIT_29
+#define GRC_MODE_MULTICAST_FRAME_ENABLE BIT_30
+
+ /* Misc configuration register. */
+ T3_32BIT_REGISTER MiscCfg;
+#define GRC_MISC_CFG_CORE_CLOCK_RESET BIT_0
+#define GRC_MISC_PRESCALAR_TIMER_MASK 0xfe
+#define GRC_MISC_BD_ID_MASK 0x0001e000
+#define GRC_MISC_BD_ID_5700 0x0001e000
+#define GRC_MISC_BD_ID_5701 0x00000000
+#define GRC_MISC_BD_ID_5703 0x00000000
+#define GRC_MISC_BD_ID_5703S 0x00002000
+#define GRC_MISC_BD_ID_5702FE 0x00004000
+#define GRC_MISC_BD_ID_5704 0x00000000
+#define GRC_MISC_BD_ID_5704CIOBE 0x00004000
+
+ /* Miscellaneous local control register. */
+ T3_32BIT_REGISTER LocalCtrl;
+#define GRC_MISC_LOCAL_CTRL_INT_ACTIVE BIT_0
+#define GRC_MISC_LOCAL_CTRL_CLEAR_INT BIT_1
+#define GRC_MISC_LOCAL_CTRL_SET_INT BIT_2
+#define GRC_MISC_LOCAL_CTRL_INT_ON_ATTN BIT_3
+#define GRC_MISC_LOCAL_CTRL_GPIO_INPUT0 BIT_8
+#define GRC_MISC_LOCAL_CTRL_GPIO_INPUT1 BIT_9
+#define GRC_MISC_LOCAL_CTRL_GPIO_INPUT2 BIT_10
+#define GRC_MISC_LOCAL_CTRL_GPIO_OE0 BIT_11
+#define GRC_MISC_LOCAL_CTRL_GPIO_OE1 BIT_12
+#define GRC_MISC_LOCAL_CTRL_GPIO_OE2 BIT_13
+#define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 BIT_14
+#define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 BIT_15
+#define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2 BIT_16
+#define GRC_MISC_LOCAL_CTRL_ENABLE_EXT_MEMORY BIT_17
+#define GRC_MISC_LOCAL_CTRL_BANK_SELECT BIT_21
+#define GRC_MISC_LOCAL_CTRL_SSRAM_TYPE BIT_22
+
+#define GRC_MISC_MEMSIZE_256K 0
+#define GRC_MISC_MEMSIZE_512K (1 << 18)
+#define GRC_MISC_MEMSIZE_1024K (2 << 18)
+#define GRC_MISC_MEMSIZE_2048K (3 << 18)
+#define GRC_MISC_MEMSIZE_4096K (4 << 18)
+#define GRC_MISC_MEMSIZE_8192K (5 << 18)
+#define GRC_MISC_MEMSIZE_16M (6 << 18)
+#define GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM BIT_24
+
+ T3_32BIT_REGISTER Timer;
+
+ T3_32BIT_REGISTER RxCpuEvent;
+ T3_32BIT_REGISTER RxTimerRef;
+ T3_32BIT_REGISTER RxCpuSemaphore;
+ T3_32BIT_REGISTER RemoteRxCpuAttn;
+
+ T3_32BIT_REGISTER TxCpuEvent;
+ T3_32BIT_REGISTER TxTimerRef;
+ T3_32BIT_REGISTER TxCpuSemaphore;
+ T3_32BIT_REGISTER RemoteTxCpuAttn;
+
+ T3_64BIT_REGISTER MemoryPowerUp;
+
+ T3_32BIT_REGISTER EepromAddr;
+#define SEEPROM_ADDR_WRITE 0
+#define SEEPROM_ADDR_READ (1 << 31)
+#define SEEPROM_ADDR_RW_MASK 0x80000000
+#define SEEPROM_ADDR_COMPLETE (1 << 30)
+#define SEEPROM_ADDR_FSM_RESET (1 << 29)
+#define SEEPROM_ADDR_DEV_ID(x) (x << 26)
+#define SEEPROM_ADDR_DEV_ID_MASK 0x1c000000
+#define SEEPROM_ADDR_START (1 << 25)
+#define SEEPROM_ADDR_CLK_PERD(x) (x << 16)
+#define SEEPROM_ADDR_ADDRESS(x) (x & 0xfffc)
+#define SEEPROM_ADDR_ADDRESS_MASK 0x0000ffff
+
+#define SEEPROM_CLOCK_PERIOD 60
+#define SEEPROM_CHIP_SIZE (64 * 1024)
+
+ T3_32BIT_REGISTER EepromData;
+ T3_32BIT_REGISTER EepromCtrl;
+
+ T3_32BIT_REGISTER MdiCtrl;
+ T3_32BIT_REGISTER SepromDelay;
+ /* Unused space. */
+ LM_UINT8 Unused[948];
+} T3_GRC, *PT3_GRC;
/******************************************************************************/
/* NVRAM control registers. */
/******************************************************************************/
-typedef struct
-{
- T3_32BIT_REGISTER Cmd;
- #define NVRAM_CMD_RESET BIT_0
- #define NVRAM_CMD_DONE BIT_3
- #define NVRAM_CMD_DO_IT BIT_4
- #define NVRAM_CMD_WR BIT_5
- #define NVRAM_CMD_RD BIT_NONE
- #define NVRAM_CMD_ERASE BIT_6
- #define NVRAM_CMD_FIRST BIT_7
- #define NVRAM_CMD_LAST BIT_8
-
- T3_32BIT_REGISTER Status;
- T3_32BIT_REGISTER WriteData;
-
- T3_32BIT_REGISTER Addr;
- #define NVRAM_ADDRESS_MASK 0xffffff
-
- T3_32BIT_REGISTER ReadData;
-
- /* Flash config 1 register. */
- T3_32BIT_REGISTER Config1;
- #define FLASH_INTERFACE_ENABLE BIT_0
- #define FLASH_SSRAM_BUFFERRED_MODE BIT_1
- #define FLASH_PASS_THRU_MODE BIT_2
- #define FLASH_BIT_BANG_MODE BIT_3
- #define FLASH_COMPAT_BYPASS BIT_31
-
- /* Buffered flash (Atmel: AT45DB011B) specific information */
- #define BUFFERED_FLASH_PAGE_POS 9
- #define BUFFERED_FLASH_BYTE_ADDR_MASK ((1<<BUFFERED_FLASH_PAGE_POS) - 1)
- #define BUFFERED_FLASH_PAGE_SIZE 264
- #define BUFFERED_FLASH_PHY_PAGE_SIZE 512
-
- T3_32BIT_REGISTER Config2;
- T3_32BIT_REGISTER Config3;
- T3_32BIT_REGISTER SwArb;
- #define SW_ARB_REQ_SET0 BIT_0
- #define SW_ARB_REQ_SET1 BIT_1
- #define SW_ARB_REQ_SET2 BIT_2
- #define SW_ARB_REQ_SET3 BIT_3
- #define SW_ARB_REQ_CLR0 BIT_4
- #define SW_ARB_REQ_CLR1 BIT_5
- #define SW_ARB_REQ_CLR2 BIT_6
- #define SW_ARB_REQ_CLR3 BIT_7
- #define SW_ARB_GNT0 BIT_8
- #define SW_ARB_GNT1 BIT_9
- #define SW_ARB_GNT2 BIT_10
- #define SW_ARB_GNT3 BIT_11
- #define SW_ARB_REQ0 BIT_12
- #define SW_ARB_REQ1 BIT_13
- #define SW_ARB_REQ2 BIT_14
- #define SW_ARB_REQ3 BIT_15
-
- /* Unused space. */
- LM_UINT8 Unused[988];
-} T3_NVRAM, *PT3_NVRAM;
+typedef struct {
+ T3_32BIT_REGISTER Cmd;
+#define NVRAM_CMD_RESET BIT_0
+#define NVRAM_CMD_DONE BIT_3
+#define NVRAM_CMD_DO_IT BIT_4
+#define NVRAM_CMD_WR BIT_5
+#define NVRAM_CMD_RD BIT_NONE
+#define NVRAM_CMD_ERASE BIT_6
+#define NVRAM_CMD_FIRST BIT_7
+#define NVRAM_CMD_LAST BIT_8
+
+ T3_32BIT_REGISTER Status;
+ T3_32BIT_REGISTER WriteData;
+
+ T3_32BIT_REGISTER Addr;
+#define NVRAM_ADDRESS_MASK 0xffffff
+
+ T3_32BIT_REGISTER ReadData;
+
+ /* Flash config 1 register. */
+ T3_32BIT_REGISTER Config1;
+#define FLASH_INTERFACE_ENABLE BIT_0
+#define FLASH_SSRAM_BUFFERRED_MODE BIT_1
+#define FLASH_PASS_THRU_MODE BIT_2
+#define FLASH_BIT_BANG_MODE BIT_3
+#define FLASH_COMPAT_BYPASS BIT_31
+
+ /* Buffered flash (Atmel: AT45DB011B) specific information */
+#define BUFFERED_FLASH_PAGE_POS 9
+#define BUFFERED_FLASH_BYTE_ADDR_MASK ((1<<BUFFERED_FLASH_PAGE_POS) - 1)
+#define BUFFERED_FLASH_PAGE_SIZE 264
+#define BUFFERED_FLASH_PHY_PAGE_SIZE 512
+
+ T3_32BIT_REGISTER Config2;
+ T3_32BIT_REGISTER Config3;
+ T3_32BIT_REGISTER SwArb;
+#define SW_ARB_REQ_SET0 BIT_0
+#define SW_ARB_REQ_SET1 BIT_1
+#define SW_ARB_REQ_SET2 BIT_2
+#define SW_ARB_REQ_SET3 BIT_3
+#define SW_ARB_REQ_CLR0 BIT_4
+#define SW_ARB_REQ_CLR1 BIT_5
+#define SW_ARB_REQ_CLR2 BIT_6
+#define SW_ARB_REQ_CLR3 BIT_7
+#define SW_ARB_GNT0 BIT_8
+#define SW_ARB_GNT1 BIT_9
+#define SW_ARB_GNT2 BIT_10
+#define SW_ARB_GNT3 BIT_11
+#define SW_ARB_REQ0 BIT_12
+#define SW_ARB_REQ1 BIT_13
+#define SW_ARB_REQ2 BIT_14
+#define SW_ARB_REQ3 BIT_15
+ /* Unused space. */
+ LM_UINT8 Unused[988];
+} T3_NVRAM, *PT3_NVRAM;
/******************************************************************************/
/* NIC's internal memory. */
/******************************************************************************/
typedef struct {
- /* Page zero for the internal CPUs. */
- LM_UINT8 PageZero[0x100]; /* 0x0000 */
+ /* Page zero for the internal CPUs. */
+ LM_UINT8 PageZero[0x100]; /* 0x0000 */
- /* Send RCBs. */
- T3_RCB SendRcb[16]; /* 0x0100 */
+ /* Send RCBs. */
+ T3_RCB SendRcb[16]; /* 0x0100 */
- /* Receive Return RCBs. */
- T3_RCB RcvRetRcb[16]; /* 0x0200 */
+ /* Receive Return RCBs. */
+ T3_RCB RcvRetRcb[16]; /* 0x0200 */
- /* Statistics block. */
- T3_STATS_BLOCK StatsBlk; /* 0x0300 */
+ /* Statistics block. */
+ T3_STATS_BLOCK StatsBlk; /* 0x0300 */
- /* Status block. */
- T3_STATUS_BLOCK StatusBlk; /* 0x0b00 */
+ /* Status block. */
+ T3_STATUS_BLOCK StatusBlk; /* 0x0b00 */
- /* Reserved for software. */
- LM_UINT8 Reserved[1200]; /* 0x0b50 */
+ /* Reserved for software. */
+ LM_UINT8 Reserved[1200]; /* 0x0b50 */
- /* Unmapped region. */
- LM_UINT8 Unmapped[4096]; /* 0x1000 */
+ /* Unmapped region. */
+ LM_UINT8 Unmapped[4096]; /* 0x1000 */
- /* DMA descriptors. */
- LM_UINT8 DmaDesc[8192]; /* 0x2000 */
+ /* DMA descriptors. */
+ LM_UINT8 DmaDesc[8192]; /* 0x2000 */
- /* Buffer descriptors. */
- LM_UINT8 BufferDesc[16384]; /* 0x4000 */
+ /* Buffer descriptors. */
+ LM_UINT8 BufferDesc[16384]; /* 0x4000 */
} T3_FIRST_32K_SRAM, *PT3_FIRST_32K_SRAM;
-
/******************************************************************************/
/* Memory layout. */
/******************************************************************************/
typedef struct {
- /* PCI configuration registers. */
- T3_PCI_CONFIGURATION PciCfg;
-
- /* Unused. */
- LM_UINT8 Unused1[0x100]; /* 0x0100 */
+ /* PCI configuration registers. */
+ T3_PCI_CONFIGURATION PciCfg;
- /* Mailbox . */
- T3_MAILBOX Mailbox; /* 0x0200 */
+ /* Unused. */
+ LM_UINT8 Unused1[0x100]; /* 0x0100 */
- /* MAC control registers. */
- T3_MAC_CONTROL MacCtrl; /* 0x0400 */
+ /* Mailbox . */
+ T3_MAILBOX Mailbox; /* 0x0200 */
- /* Send data initiator control registers. */
- T3_SEND_DATA_INITIATOR SndDataIn; /* 0x0c00 */
+ /* MAC control registers. */
+ T3_MAC_CONTROL MacCtrl; /* 0x0400 */
- /* Send data completion Control registers. */
- T3_SEND_DATA_COMPLETION SndDataComp; /* 0x1000 */
+ /* Send data initiator control registers. */
+ T3_SEND_DATA_INITIATOR SndDataIn; /* 0x0c00 */
- /* Send BD ring selector. */
- T3_SEND_BD_SELECTOR SndBdSel; /* 0x1400 */
+ /* Send data completion Control registers. */
+ T3_SEND_DATA_COMPLETION SndDataComp; /* 0x1000 */
- /* Send BD initiator control registers. */
- T3_SEND_BD_INITIATOR SndBdIn; /* 0x1800 */
+ /* Send BD ring selector. */
+ T3_SEND_BD_SELECTOR SndBdSel; /* 0x1400 */
- /* Send BD completion control registers. */
- T3_SEND_BD_COMPLETION SndBdComp; /* 0x1c00 */
+ /* Send BD initiator control registers. */
+ T3_SEND_BD_INITIATOR SndBdIn; /* 0x1800 */
- /* Receive list placement control registers. */
- T3_RCV_LIST_PLACEMENT RcvListPlmt; /* 0x2000 */
+ /* Send BD completion control registers. */
+ T3_SEND_BD_COMPLETION SndBdComp; /* 0x1c00 */
- /* Receive Data and Receive BD Initiator Control. */
- T3_RCV_DATA_BD_INITIATOR RcvDataBdIn; /* 0x2400 */
+ /* Receive list placement control registers. */
+ T3_RCV_LIST_PLACEMENT RcvListPlmt; /* 0x2000 */
- /* Receive Data Completion Control */
- T3_RCV_DATA_COMPLETION RcvDataComp; /* 0x2800 */
+ /* Receive Data and Receive BD Initiator Control. */
+ T3_RCV_DATA_BD_INITIATOR RcvDataBdIn; /* 0x2400 */
- /* Receive BD Initiator Control Registers. */
- T3_RCV_BD_INITIATOR RcvBdIn; /* 0x2c00 */
+ /* Receive Data Completion Control */
+ T3_RCV_DATA_COMPLETION RcvDataComp; /* 0x2800 */
- /* Receive BD Completion Control Registers. */
- T3_RCV_BD_COMPLETION RcvBdComp; /* 0x3000 */
+ /* Receive BD Initiator Control Registers. */
+ T3_RCV_BD_INITIATOR RcvBdIn; /* 0x2c00 */
- /* Receive list selector control registers. */
- T3_RCV_LIST_SELECTOR RcvListSel; /* 0x3400 */
+ /* Receive BD Completion Control Registers. */
+ T3_RCV_BD_COMPLETION RcvBdComp; /* 0x3000 */
- /* Mbuf cluster free registers. */
- T3_MBUF_CLUSTER_FREE MbufClusterFree; /* 0x3800 */
+ /* Receive list selector control registers. */
+ T3_RCV_LIST_SELECTOR RcvListSel; /* 0x3400 */
- /* Host coalescing control registers. */
- T3_HOST_COALESCING HostCoalesce; /* 0x3c00 */
+ /* Mbuf cluster free registers. */
+ T3_MBUF_CLUSTER_FREE MbufClusterFree; /* 0x3800 */
- /* Memory arbiter control registers. */
- T3_MEM_ARBITER MemArbiter; /* 0x4000 */
+ /* Host coalescing control registers. */
+ T3_HOST_COALESCING HostCoalesce; /* 0x3c00 */
- /* Buffer manger control registers. */
- T3_BUFFER_MANAGER BufMgr; /* 0x4400 */
+ /* Memory arbiter control registers. */
+ T3_MEM_ARBITER MemArbiter; /* 0x4000 */
- /* Read DMA control registers. */
- T3_DMA_READ DmaRead; /* 0x4800 */
+ /* Buffer manger control registers. */
+ T3_BUFFER_MANAGER BufMgr; /* 0x4400 */
- /* Write DMA control registers. */
- T3_DMA_WRITE DmaWrite; /* 0x4c00 */
+ /* Read DMA control registers. */
+ T3_DMA_READ DmaRead; /* 0x4800 */
- T3_CPU rxCpu; /* 0x5000 */
- T3_CPU txCpu; /* 0x5400 */
+ /* Write DMA control registers. */
+ T3_DMA_WRITE DmaWrite; /* 0x4c00 */
- /* Mailboxes. */
- T3_GRC_MAILBOX GrcMailbox; /* 0x5800 */
+ T3_CPU rxCpu; /* 0x5000 */
+ T3_CPU txCpu; /* 0x5400 */
- /* Flow Through queues. */
- T3_FTQ Ftq; /* 0x5c00 */
+ /* Mailboxes. */
+ T3_GRC_MAILBOX GrcMailbox; /* 0x5800 */
- /* Message signaled interrupt registes. */
- T3_MSG_SIGNALED_INT Msi; /* 0x6000 */
+ /* Flow Through queues. */
+ T3_FTQ Ftq; /* 0x5c00 */
- /* DMA completion registers. */
- T3_DMA_COMPLETION DmaComp; /* 0x6400 */
+ /* Message signaled interrupt registes. */
+ T3_MSG_SIGNALED_INT Msi; /* 0x6000 */
- /* GRC registers. */
- T3_GRC Grc; /* 0x6800 */
+ /* DMA completion registers. */
+ T3_DMA_COMPLETION DmaComp; /* 0x6400 */
- /* Unused space. */
- LM_UINT8 Unused2[1024]; /* 0x6c00 */
+ /* GRC registers. */
+ T3_GRC Grc; /* 0x6800 */
- /* NVRAM registers. */
- T3_NVRAM Nvram; /* 0x7000 */
-
- /* Unused space. */
- LM_UINT8 Unused3[3072]; /* 0x7400 */
+ /* Unused space. */
+ LM_UINT8 Unused2[1024]; /* 0x6c00 */
- /* The 32k memory window into the NIC's */
- /* internal memory. The memory window is */
- /* controlled by the Memory Window Base */
- /* Address register. This register is located */
- /* in the PCI configuration space. */
- union { /* 0x8000 */
- T3_FIRST_32K_SRAM First32k;
+ /* NVRAM registers. */
+ T3_NVRAM Nvram; /* 0x7000 */
- /* Use the memory window base address register to determine the */
- /* MBUF segment. */
- LM_UINT32 Mbuf[32768/4];
- LM_UINT32 MemBlock32K[32768/4];
- } uIntMem;
+ /* Unused space. */
+ LM_UINT8 Unused3[3072]; /* 0x7400 */
+
+ /* The 32k memory window into the NIC's */
+ /* internal memory. The memory window is */
+ /* controlled by the Memory Window Base */
+ /* Address register. This register is located */
+ /* in the PCI configuration space. */
+ union { /* 0x8000 */
+ T3_FIRST_32K_SRAM First32k;
+
+ /* Use the memory window base address register to determine the */
+ /* MBUF segment. */
+ LM_UINT32 Mbuf[32768 / 4];
+ LM_UINT32 MemBlock32K[32768 / 4];
+ } uIntMem;
} T3_STD_MEM_MAP, *PT3_STD_MEM_MAP;
-
/******************************************************************************/
/* Adapter info. */
/******************************************************************************/
-typedef struct
-{
- LM_UINT16 Svid;
- LM_UINT16 Ssid;
- LM_UINT32 PhyId;
- LM_UINT32 Serdes; /* 0 = copper PHY, 1 = Serdes */
+typedef struct {
+ LM_UINT16 Svid;
+ LM_UINT16 Ssid;
+ LM_UINT32 PhyId;
+ LM_UINT32 Serdes; /* 0 = copper PHY, 1 = Serdes */
} LM_ADAPTER_INFO, *PLM_ADAPTER_INFO;
-
/******************************************************************************/
/* Packet queues. */
/******************************************************************************/
-DECLARE_QUEUE_TYPE(LM_RX_PACKET_Q, MAX_RX_PACKET_DESC_COUNT);
-DECLARE_QUEUE_TYPE(LM_TX_PACKET_Q, MAX_TX_PACKET_DESC_COUNT);
-
+DECLARE_QUEUE_TYPE (LM_RX_PACKET_Q, MAX_RX_PACKET_DESC_COUNT);
+DECLARE_QUEUE_TYPE (LM_TX_PACKET_Q, MAX_TX_PACKET_DESC_COUNT);
/******************************************************************************/
/* Tx counters. */
/******************************************************************************/
typedef struct {
- LM_COUNTER TxPacketGoodCnt;
- LM_COUNTER TxBytesGoodCnt;
- LM_COUNTER TxPacketAbortedCnt;
- LM_COUNTER NoSendBdLeftCnt;
- LM_COUNTER NoMapRegisterLeftCnt;
- LM_COUNTER TooManyFragmentsCnt;
- LM_COUNTER NoTxPacketDescCnt;
+ LM_COUNTER TxPacketGoodCnt;
+ LM_COUNTER TxBytesGoodCnt;
+ LM_COUNTER TxPacketAbortedCnt;
+ LM_COUNTER NoSendBdLeftCnt;
+ LM_COUNTER NoMapRegisterLeftCnt;
+ LM_COUNTER TooManyFragmentsCnt;
+ LM_COUNTER NoTxPacketDescCnt;
} LM_TX_COUNTERS, *PLM_TX_COUNTERS;
-
/******************************************************************************/
/* Rx counters. */
/******************************************************************************/
typedef struct {
- LM_COUNTER RxPacketGoodCnt;
- LM_COUNTER RxBytesGoodCnt;
- LM_COUNTER RxPacketErrCnt;
- LM_COUNTER RxErrCrcCnt;
- LM_COUNTER RxErrCollCnt;
- LM_COUNTER RxErrLinkLostCnt;
- LM_COUNTER RxErrPhyDecodeCnt;
- LM_COUNTER RxErrOddNibbleCnt;
- LM_COUNTER RxErrMacAbortCnt;
- LM_COUNTER RxErrShortPacketCnt;
- LM_COUNTER RxErrNoResourceCnt;
- LM_COUNTER RxErrLargePacketCnt;
+ LM_COUNTER RxPacketGoodCnt;
+ LM_COUNTER RxBytesGoodCnt;
+ LM_COUNTER RxPacketErrCnt;
+ LM_COUNTER RxErrCrcCnt;
+ LM_COUNTER RxErrCollCnt;
+ LM_COUNTER RxErrLinkLostCnt;
+ LM_COUNTER RxErrPhyDecodeCnt;
+ LM_COUNTER RxErrOddNibbleCnt;
+ LM_COUNTER RxErrMacAbortCnt;
+ LM_COUNTER RxErrShortPacketCnt;
+ LM_COUNTER RxErrNoResourceCnt;
+ LM_COUNTER RxErrLargePacketCnt;
} LM_RX_COUNTERS, *PLM_RX_COUNTERS;
-
/******************************************************************************/
/* Receive producer rings. */
/******************************************************************************/
typedef enum {
- T3_UNKNOWN_RCV_PROD_RING = 0,
- T3_STD_RCV_PROD_RING = 1,
- T3_MINI_RCV_PROD_RING = 2,
- T3_JUMBO_RCV_PROD_RING = 3
+ T3_UNKNOWN_RCV_PROD_RING = 0,
+ T3_STD_RCV_PROD_RING = 1,
+ T3_MINI_RCV_PROD_RING = 2,
+ T3_JUMBO_RCV_PROD_RING = 3
} T3_RCV_PROD_RING, *PT3_RCV_PROD_RING;
-
/******************************************************************************/
/* Packet descriptor. */
/******************************************************************************/
@@ -2758,331 +2675,328 @@ typedef enum {
#define LM_PACKET_SIGNATURE_RX 0x6b766168
typedef struct _LM_PACKET {
- /* Set in LM. */
- LM_STATUS PacketStatus;
+ /* Set in LM. */
+ LM_STATUS PacketStatus;
- /* Set in LM for Rx, in UM for Tx. */
- LM_UINT32 PacketSize;
+ /* Set in LM for Rx, in UM for Tx. */
+ LM_UINT32 PacketSize;
- LM_UINT16 Flags;
+ LM_UINT16 Flags;
- LM_UINT16 VlanTag;
+ LM_UINT16 VlanTag;
- union {
- /* Send info. */
- struct {
- /* Set up by UM. */
- LM_UINT32 FragCount;
+ union {
+ /* Send info. */
+ struct {
+ /* Set up by UM. */
+ LM_UINT32 FragCount;
- } Tx;
+ } Tx;
- /* Receive info. */
- struct {
- /* This descriptor belongs to either Std, Mini, or Jumbo ring. */
- T3_RCV_PROD_RING RcvProdRing;
+ /* Receive info. */
+ struct {
+ /* This descriptor belongs to either Std, Mini, or Jumbo ring. */
+ T3_RCV_PROD_RING RcvProdRing;
- /* Receive buffer size */
- LM_UINT32 RxBufferSize;
+ /* Receive buffer size */
+ LM_UINT32 RxBufferSize;
- /* Checksum information. */
- LM_UINT16 IpChecksum;
- LM_UINT16 TcpUdpChecksum;
+ /* Checksum information. */
+ LM_UINT16 IpChecksum;
+ LM_UINT16 TcpUdpChecksum;
- } Rx;
- } u;
+ } Rx;
+ } u;
} LM_PACKET;
-
/******************************************************************************/
/* Tigon3 device block. */
/******************************************************************************/
typedef struct _LM_DEVICE_BLOCK {
- int index; /* Device ID */
- /* Memory view. */
- PT3_STD_MEM_MAP pMemView;
+ int index; /* Device ID */
+ /* Memory view. */
+ PT3_STD_MEM_MAP pMemView;
- /* Base address of the block of memory in which the LM_PACKET descriptors */
- /* are allocated from. */
- PLM_VOID pPacketDescBase;
+ /* Base address of the block of memory in which the LM_PACKET descriptors */
+ /* are allocated from. */
+ PLM_VOID pPacketDescBase;
- LM_UINT32 MiscHostCtrl;
- LM_UINT32 GrcLocalCtrl;
- LM_UINT32 DmaReadWriteCtrl;
- LM_UINT32 PciState;
+ LM_UINT32 MiscHostCtrl;
+ LM_UINT32 GrcLocalCtrl;
+ LM_UINT32 DmaReadWriteCtrl;
+ LM_UINT32 PciState;
- /* Rx info */
- LM_UINT32 RxStdDescCnt;
- LM_UINT32 RxStdQueuedCnt;
- LM_UINT32 RxStdProdIdx;
+ /* Rx info */
+ LM_UINT32 RxStdDescCnt;
+ LM_UINT32 RxStdQueuedCnt;
+ LM_UINT32 RxStdProdIdx;
- PT3_RCV_BD pRxStdBdVirt;
- LM_PHYSICAL_ADDRESS RxStdBdPhy;
+ PT3_RCV_BD pRxStdBdVirt;
+ LM_PHYSICAL_ADDRESS RxStdBdPhy;
- LM_UINT32 RxPacketDescCnt;
- LM_RX_PACKET_Q RxPacketFreeQ;
- LM_RX_PACKET_Q RxPacketReceivedQ;
+ LM_UINT32 RxPacketDescCnt;
+ LM_RX_PACKET_Q RxPacketFreeQ;
+ LM_RX_PACKET_Q RxPacketReceivedQ;
- /* Receive info. */
- PT3_RCV_BD pRcvRetBdVirt;
- LM_PHYSICAL_ADDRESS RcvRetBdPhy;
- LM_UINT32 RcvRetConIdx;
+ /* Receive info. */
+ PT3_RCV_BD pRcvRetBdVirt;
+ LM_PHYSICAL_ADDRESS RcvRetBdPhy;
+ LM_UINT32 RcvRetConIdx;
#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
- LM_UINT32 RxJumboDescCnt;
- LM_UINT32 RxJumboBufferSize;
- LM_UINT32 RxJumboQueuedCnt;
+ LM_UINT32 RxJumboDescCnt;
+ LM_UINT32 RxJumboBufferSize;
+ LM_UINT32 RxJumboQueuedCnt;
+
+ LM_UINT32 RxJumboProdIdx;
+
+ PT3_RCV_BD pRxJumboBdVirt;
+ LM_PHYSICAL_ADDRESS RxJumboBdPhy;
+#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
- LM_UINT32 RxJumboProdIdx;
+ /* These values are used by the upper module to inform the protocol */
+ /* of the maximum transmit/receive packet size. */
+ LM_UINT32 TxMtu; /* Does not include CRC. */
+ LM_UINT32 RxMtu; /* Does not include CRC. */
- PT3_RCV_BD pRxJumboBdVirt;
- LM_PHYSICAL_ADDRESS RxJumboBdPhy;
-#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
+ /* We need to shadow the EMAC, Rx, Tx mode registers. With B0 silicon, */
+ /* we may have problems reading any MAC registers in 10mb mode. */
+ LM_UINT32 MacMode;
+ LM_UINT32 RxMode;
+ LM_UINT32 TxMode;
- /* These values are used by the upper module to inform the protocol */
- /* of the maximum transmit/receive packet size. */
- LM_UINT32 TxMtu; /* Does not include CRC. */
- LM_UINT32 RxMtu; /* Does not include CRC. */
+ /* MiMode register. */
+ LM_UINT32 MiMode;
- /* We need to shadow the EMAC, Rx, Tx mode registers. With B0 silicon, */
- /* we may have problems reading any MAC registers in 10mb mode. */
- LM_UINT32 MacMode;
- LM_UINT32 RxMode;
- LM_UINT32 TxMode;
+ /* Host coalesce mode register. */
+ LM_UINT32 CoalesceMode;
- /* MiMode register. */
- LM_UINT32 MiMode;
-
- /* Host coalesce mode register. */
- LM_UINT32 CoalesceMode;
-
- /* Send info. */
- LM_UINT32 TxPacketDescCnt;
-
- /* Tx info. */
- LM_TX_PACKET_Q TxPacketFreeQ;
- LM_TX_PACKET_Q TxPacketActiveQ;
- LM_TX_PACKET_Q TxPacketXmittedQ;
-
- /* Pointers to SendBd. */
- PT3_SND_BD pSendBdVirt;
- LM_PHYSICAL_ADDRESS SendBdPhy; /* Only valid for Host based Send BD. */
-
- /* Send producer and consumer indices. */
- LM_UINT32 SendProdIdx;
- LM_UINT32 SendConIdx;
-
- /* Number of BD left. */
- atomic_t SendBdLeft;
-
- T3_SND_BD ShadowSendBd[T3_SEND_RCB_ENTRY_COUNT];
-
- /* Counters. */
- LM_RX_COUNTERS RxCounters;
- LM_TX_COUNTERS TxCounters;
-
- /* Host coalescing parameters. */
- LM_UINT32 RxCoalescingTicks;
- LM_UINT32 TxCoalescingTicks;
- LM_UINT32 RxMaxCoalescedFrames;
- LM_UINT32 TxMaxCoalescedFrames;
- LM_UINT32 StatsCoalescingTicks;
- LM_UINT32 RxCoalescingTicksDuringInt;
- LM_UINT32 TxCoalescingTicksDuringInt;
- LM_UINT32 RxMaxCoalescedFramesDuringInt;
- LM_UINT32 TxMaxCoalescedFramesDuringInt;
-
- /* DMA water marks. */
- LM_UINT32 DmaMbufLowMark;
- LM_UINT32 RxMacMbufLowMark;
- LM_UINT32 MbufHighMark;
-
- /* Status block. */
- PT3_STATUS_BLOCK pStatusBlkVirt;
- LM_PHYSICAL_ADDRESS StatusBlkPhy;
-
- /* Statistics block. */
- PT3_STATS_BLOCK pStatsBlkVirt;
- LM_PHYSICAL_ADDRESS StatsBlkPhy;
-
- /* Current receive mask. */
- LM_UINT32 ReceiveMask;
-
- /* Task offload capabilities. */
- LM_TASK_OFFLOAD TaskOffloadCap;
-
- /* Task offload selected. */
- LM_TASK_OFFLOAD TaskToOffload;
-
- /* Wake up capability. */
- LM_WAKE_UP_MODE WakeUpModeCap;
-
- /* Wake up capability. */
- LM_WAKE_UP_MODE WakeUpMode;
-
- /* Flow control. */
- LM_FLOW_CONTROL FlowControlCap;
- LM_FLOW_CONTROL FlowControl;
-
- /* Enable or disable PCI MWI. */
- LM_UINT32 EnableMWI;
-
- /* Enable 5701 tagged status mode. */
- LM_UINT32 UseTaggedStatus;
-
- /* NIC will not compute the pseudo header checksum. The driver or OS */
- /* must seed the checksum field with the pseudo checksum. */
- LM_UINT32 NoTxPseudoHdrChksum;
-
- /* The receive checksum in the BD does not include the pseudo checksum. */
- /* The OS or the driver must calculate the pseudo checksum and add it to */
- /* the checksum in the BD. */
- LM_UINT32 NoRxPseudoHdrChksum;
-
- /* Current node address. */
- LM_UINT8 NodeAddress[8];
-
- /* The adapter's node address. */
- LM_UINT8 PermanentNodeAddress[8];
-
- /* Adapter info. */
- LM_UINT16 BusNum;
- LM_UINT8 DevNum;
- LM_UINT8 FunctNum;
- LM_UINT16 PciVendorId;
- LM_UINT16 PciDeviceId;
- LM_UINT32 BondId;
- LM_UINT8 Irq;
- LM_UINT8 IntPin;
- LM_UINT8 CacheLineSize;
- LM_UINT8 PciRevId;
+ /* Send info. */
+ LM_UINT32 TxPacketDescCnt;
+
+ /* Tx info. */
+ LM_TX_PACKET_Q TxPacketFreeQ;
+ LM_TX_PACKET_Q TxPacketActiveQ;
+ LM_TX_PACKET_Q TxPacketXmittedQ;
+
+ /* Pointers to SendBd. */
+ PT3_SND_BD pSendBdVirt;
+ LM_PHYSICAL_ADDRESS SendBdPhy; /* Only valid for Host based Send BD. */
+
+ /* Send producer and consumer indices. */
+ LM_UINT32 SendProdIdx;
+ LM_UINT32 SendConIdx;
+
+ /* Number of BD left. */
+ atomic_t SendBdLeft;
+
+ T3_SND_BD ShadowSendBd[T3_SEND_RCB_ENTRY_COUNT];
+
+ /* Counters. */
+ LM_RX_COUNTERS RxCounters;
+ LM_TX_COUNTERS TxCounters;
+
+ /* Host coalescing parameters. */
+ LM_UINT32 RxCoalescingTicks;
+ LM_UINT32 TxCoalescingTicks;
+ LM_UINT32 RxMaxCoalescedFrames;
+ LM_UINT32 TxMaxCoalescedFrames;
+ LM_UINT32 StatsCoalescingTicks;
+ LM_UINT32 RxCoalescingTicksDuringInt;
+ LM_UINT32 TxCoalescingTicksDuringInt;
+ LM_UINT32 RxMaxCoalescedFramesDuringInt;
+ LM_UINT32 TxMaxCoalescedFramesDuringInt;
+
+ /* DMA water marks. */
+ LM_UINT32 DmaMbufLowMark;
+ LM_UINT32 RxMacMbufLowMark;
+ LM_UINT32 MbufHighMark;
+
+ /* Status block. */
+ PT3_STATUS_BLOCK pStatusBlkVirt;
+ LM_PHYSICAL_ADDRESS StatusBlkPhy;
+
+ /* Statistics block. */
+ PT3_STATS_BLOCK pStatsBlkVirt;
+ LM_PHYSICAL_ADDRESS StatsBlkPhy;
+
+ /* Current receive mask. */
+ LM_UINT32 ReceiveMask;
+
+ /* Task offload capabilities. */
+ LM_TASK_OFFLOAD TaskOffloadCap;
+
+ /* Task offload selected. */
+ LM_TASK_OFFLOAD TaskToOffload;
+
+ /* Wake up capability. */
+ LM_WAKE_UP_MODE WakeUpModeCap;
+
+ /* Wake up capability. */
+ LM_WAKE_UP_MODE WakeUpMode;
+
+ /* Flow control. */
+ LM_FLOW_CONTROL FlowControlCap;
+ LM_FLOW_CONTROL FlowControl;
+
+ /* Enable or disable PCI MWI. */
+ LM_UINT32 EnableMWI;
+
+ /* Enable 5701 tagged status mode. */
+ LM_UINT32 UseTaggedStatus;
+
+ /* NIC will not compute the pseudo header checksum. The driver or OS */
+ /* must seed the checksum field with the pseudo checksum. */
+ LM_UINT32 NoTxPseudoHdrChksum;
+
+ /* The receive checksum in the BD does not include the pseudo checksum. */
+ /* The OS or the driver must calculate the pseudo checksum and add it to */
+ /* the checksum in the BD. */
+ LM_UINT32 NoRxPseudoHdrChksum;
+
+ /* Current node address. */
+ LM_UINT8 NodeAddress[8];
+
+ /* The adapter's node address. */
+ LM_UINT8 PermanentNodeAddress[8];
+
+ /* Adapter info. */
+ LM_UINT16 BusNum;
+ LM_UINT8 DevNum;
+ LM_UINT8 FunctNum;
+ LM_UINT16 PciVendorId;
+ LM_UINT16 PciDeviceId;
+ LM_UINT32 BondId;
+ LM_UINT8 Irq;
+ LM_UINT8 IntPin;
+ LM_UINT8 CacheLineSize;
+ LM_UINT8 PciRevId;
#if PCIX_TARGET_WORKAROUND
LM_UINT32 EnablePciXFix;
#endif
- LM_UINT32 UndiFix; /* new, jimmy */
- LM_UINT32 PciCommandStatusWords;
- LM_UINT32 ChipRevId;
- LM_UINT16 SubsystemVendorId;
- LM_UINT16 SubsystemId;
-#if 0 /* Jimmy, deleted in new driver */
- LM_UINT32 MemBaseLow;
- LM_UINT32 MemBaseHigh;
- LM_UINT32 MemBaseSize;
+ LM_UINT32 UndiFix; /* new, jimmy */
+ LM_UINT32 PciCommandStatusWords;
+ LM_UINT32 ChipRevId;
+ LM_UINT16 SubsystemVendorId;
+ LM_UINT16 SubsystemId;
+#if 0 /* Jimmy, deleted in new driver */
+ LM_UINT32 MemBaseLow;
+ LM_UINT32 MemBaseHigh;
+ LM_UINT32 MemBaseSize;
#endif
- PLM_UINT8 pMappedMemBase;
-
- /* Saved PCI configuration registers for restoring after a reset. */
- LM_UINT32 SavedCacheLineReg;
+ PLM_UINT8 pMappedMemBase;
- /* Phy info. */
- LM_UINT32 PhyAddr;
- LM_UINT32 PhyId;
+ /* Saved PCI configuration registers for restoring after a reset. */
+ LM_UINT32 SavedCacheLineReg;
- /* Requested phy settings. */
- LM_REQUESTED_MEDIA_TYPE RequestedMediaType;
+ /* Phy info. */
+ LM_UINT32 PhyAddr;
+ LM_UINT32 PhyId;
- /* Disable auto-negotiation. */
- LM_UINT32 DisableAutoNeg;
+ /* Requested phy settings. */
+ LM_REQUESTED_MEDIA_TYPE RequestedMediaType;
- /* Ways for the MAC to get link change interrupt. */
- LM_UINT32 PhyIntMode;
- #define T3_PHY_INT_MODE_AUTO 0
- #define T3_PHY_INT_MODE_MI_INTERRUPT 1
- #define T3_PHY_INT_MODE_LINK_READY 2
- #define T3_PHY_INT_MODE_AUTO_POLLING 3
+ /* Disable auto-negotiation. */
+ LM_UINT32 DisableAutoNeg;
- /* Ways to determine link change status. */
- LM_UINT32 LinkChngMode;
- #define T3_LINK_CHNG_MODE_AUTO 0
- #define T3_LINK_CHNG_MODE_USE_STATUS_REG 1
- #define T3_LINK_CHNG_MODE_USE_STATUS_BLOCK 2
+ /* Ways for the MAC to get link change interrupt. */
+ LM_UINT32 PhyIntMode;
+#define T3_PHY_INT_MODE_AUTO 0
+#define T3_PHY_INT_MODE_MI_INTERRUPT 1
+#define T3_PHY_INT_MODE_LINK_READY 2
+#define T3_PHY_INT_MODE_AUTO_POLLING 3
+ /* Ways to determine link change status. */
+ LM_UINT32 LinkChngMode;
+#define T3_LINK_CHNG_MODE_AUTO 0
+#define T3_LINK_CHNG_MODE_USE_STATUS_REG 1
+#define T3_LINK_CHNG_MODE_USE_STATUS_BLOCK 2
- /* LED mode. */
- LM_UINT32 LedMode;
+ /* LED mode. */
+ LM_UINT32 LedMode;
- #define LED_MODE_AUTO 0
+#define LED_MODE_AUTO 0
- /* 5700/01 LED mode. */
- #define LED_MODE_THREE_LINK 1
- #define LED_MODE_LINK10 2
+ /* 5700/01 LED mode. */
+#define LED_MODE_THREE_LINK 1
+#define LED_MODE_LINK10 2
- /* 5703/02/04 LED mode. */
- #define LED_MODE_OPEN_DRAIN 1
- #define LED_MODE_OUTPUT 2
+ /* 5703/02/04 LED mode. */
+#define LED_MODE_OPEN_DRAIN 1
+#define LED_MODE_OUTPUT 2
- /* WOL Speed */
- LM_UINT32 WolSpeed;
- #define WOL_SPEED_10MB 1
- #define WOL_SPEED_100MB 2
+ /* WOL Speed */
+ LM_UINT32 WolSpeed;
+#define WOL_SPEED_10MB 1
+#define WOL_SPEED_100MB 2
- /* Reset the PHY on initialization. */
- LM_UINT32 ResetPhyOnInit;
+ /* Reset the PHY on initialization. */
+ LM_UINT32 ResetPhyOnInit;
- LM_UINT32 RestoreOnWakeUp;
- LM_REQUESTED_MEDIA_TYPE WakeUpRequestedMediaType;
- LM_UINT32 WakeUpDisableAutoNeg;
+ LM_UINT32 RestoreOnWakeUp;
+ LM_REQUESTED_MEDIA_TYPE WakeUpRequestedMediaType;
+ LM_UINT32 WakeUpDisableAutoNeg;
- /* Current phy settings. */
- LM_MEDIA_TYPE MediaType;
- LM_LINE_SPEED LineSpeed;
- LM_LINE_SPEED OldLineSpeed;
- LM_DUPLEX_MODE DuplexMode;
- LM_STATUS LinkStatus;
- LM_UINT32 advertising; /* Jimmy, new! */
- LM_UINT32 advertising1000; /* Jimmy, new! */
+ /* Current phy settings. */
+ LM_MEDIA_TYPE MediaType;
+ LM_LINE_SPEED LineSpeed;
+ LM_LINE_SPEED OldLineSpeed;
+ LM_DUPLEX_MODE DuplexMode;
+ LM_STATUS LinkStatus;
+ LM_UINT32 advertising; /* Jimmy, new! */
+ LM_UINT32 advertising1000; /* Jimmy, new! */
- /* Multicast address list. */
- LM_UINT32 McEntryCount;
- LM_UINT8 McTable[LM_MAX_MC_TABLE_SIZE][LM_MC_ENTRY_SIZE];
+ /* Multicast address list. */
+ LM_UINT32 McEntryCount;
+ LM_UINT8 McTable[LM_MAX_MC_TABLE_SIZE][LM_MC_ENTRY_SIZE];
- /* Use NIC or Host based send BD. */
- LM_UINT32 NicSendBd;
+ /* Use NIC or Host based send BD. */
+ LM_UINT32 NicSendBd;
- /* Athlon fix. */
- LM_UINT32 DelayPciGrant;
+ /* Athlon fix. */
+ LM_UINT32 DelayPciGrant;
- /* Enable OneDmaAtOnce */
- LM_UINT32 OneDmaAtOnce;
+ /* Enable OneDmaAtOnce */
+ LM_UINT32 OneDmaAtOnce;
- /* Split Mode flags, Jimmy new */
- LM_UINT32 SplitModeEnable;
- LM_UINT32 SplitModeMaxReq;
+ /* Split Mode flags, Jimmy new */
+ LM_UINT32 SplitModeEnable;
+ LM_UINT32 SplitModeMaxReq;
- /* Init flag. */
- LM_BOOL InitDone;
+ /* Init flag. */
+ LM_BOOL InitDone;
- /* Shutdown flag. Set by the upper module. */
- LM_BOOL ShuttingDown;
+ /* Shutdown flag. Set by the upper module. */
+ LM_BOOL ShuttingDown;
- /* Flag to determine whether to call LM_QueueRxPackets or not in */
- /* LM_ResetAdapter routine. */
- LM_BOOL QueueRxPackets;
+ /* Flag to determine whether to call LM_QueueRxPackets or not in */
+ /* LM_ResetAdapter routine. */
+ LM_BOOL QueueRxPackets;
- LM_UINT32 MbufBase;
- LM_UINT32 MbufSize;
+ LM_UINT32 MbufBase;
+ LM_UINT32 MbufSize;
- /* TRUE if we have a SERDES PHY. */
- LM_UINT32 EnableTbi;
+ /* TRUE if we have a SERDES PHY. */
+ LM_UINT32 EnableTbi;
- /* Ethernet@WireSpeed. */
- LM_UINT32 EnableWireSpeed;
+ /* Ethernet@WireSpeed. */
+ LM_UINT32 EnableWireSpeed;
- LM_UINT32 EepromWp;
+ LM_UINT32 EepromWp;
#if INCLUDE_TBI_SUPPORT
- /* Autoneg state info. */
- AN_STATE_INFO AnInfo;
- LM_UINT32 PollTbiLink;
- LM_UINT32 IgnoreTbiLinkChange;
+ /* Autoneg state info. */
+ AN_STATE_INFO AnInfo;
+ LM_UINT32 PollTbiLink;
+ LM_UINT32 IgnoreTbiLinkChange;
#endif
- char PartNo[24];
- char BootCodeVer[16];
- char BusSpeedStr[24]; /* Jimmy, new! */
- LM_UINT32 PhyCrcCount;
+ char PartNo[24];
+ char BootCodeVer[16];
+ char BusSpeedStr[24]; /* Jimmy, new! */
+ LM_UINT32 PhyCrcCount;
} LM_DEVICE_BLOCK;
-
#define T3_REG_CPU_VIEW 0xc0000000
#define T3_BLOCK_DMA_RD (1 << 0)
@@ -3216,7 +3130,6 @@ typedef struct _LM_DEVICE_BLOCK {
#define TX_CPU_EVT_SW12 30
#define TX_CPU_EVT_SW13 31
-
/* TX-CPU event */
#define TX_CPU_EVENT_SW_EVENT0 (1 << TX_CPU_EVT_SW0)
#define TX_CPU_EVENT_SW_EVENT1 (1 << TX_CPU_EVT_SW1)
@@ -3251,12 +3164,10 @@ typedef struct _LM_DEVICE_BLOCK {
#define TX_CPU_EVENT_SW_EVENT12 (1 << TX_CPU_EVT_SW12)
#define TX_CPU_EVENT_SW_EVENT13 (1 << TX_CPU_EVT_SW13)
-
#define TX_CPU_MASK (TX_CPU_EVENT_SW_EVENT0 | \
TX_CPU_EVENT_SDI | \
TX_CPU_EVENT_SDC)
-
#define T3_FTQ_TYPE1_UNDERFLOW_BIT (1 << 29)
#define T3_FTQ_TYPE1_PASS_BIT (1 << 30)
#define T3_FTQ_TYPE1_SKIP_BIT (1 << 31)
@@ -3283,25 +3194,24 @@ typedef struct _LM_DEVICE_BLOCK {
#define T3_QID_RX_DATA_COMP 16
#define T3_QID_SW_TYPE2 17
-LM_STATUS LM_LoadFirmware(PLM_DEVICE_BLOCK pDevice,
- PT3_FWIMG_INFO pFwImg,
- LM_UINT32 LoadCpu,
- LM_UINT32 StartCpu);
+LM_STATUS LM_LoadFirmware (PLM_DEVICE_BLOCK pDevice,
+ PT3_FWIMG_INFO pFwImg,
+ LM_UINT32 LoadCpu, LM_UINT32 StartCpu);
/******************************************************************************/
/* NIC register read/write macros. */
/******************************************************************************/
-#if 0 /* Jimmy */
+#if 0 /* Jimmy */
/* MAC register access. */
-LM_UINT32 LM_RegRdInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register);
-LM_VOID LM_RegWrInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register,
- LM_UINT32 Value32);
+LM_UINT32 LM_RegRdInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register);
+LM_VOID LM_RegWrInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register,
+ LM_UINT32 Value32);
/* MAC memory access. */
-LM_UINT32 LM_MemRdInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr);
-LM_VOID LM_MemWrInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr,
- LM_UINT32 Value32);
+LM_UINT32 LM_MemRdInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr);
+LM_VOID LM_MemWrInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr,
+ LM_UINT32 Value32);
#if PCIX_TARGET_WORKAROUND
@@ -3342,7 +3252,7 @@ LM_VOID LM_MemWrInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr,
#define MEM_WR_OFFSET(pDevice, Offset, Value32) \
LM_MemWrInd(pDevice, Offset, Value32)
-#else /* normal target access path below */
+#else /* normal target access path below */
/* Register access. */
#define REG_RD(pDevice, OffsetName) \
@@ -3355,7 +3265,6 @@ LM_VOID LM_MemWrInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr,
#define REG_WR_OFFSET(pDevice, Offset, Value32) \
writel(Value32, ((LM_UINT8 *) (pDevice)->pMemView + Offset))
-
/* There could be problem access the memory window directly. For now, */
/* we have to go through the PCI configuration register. */
#define MEM_RD(pDevice, AddrName) \
@@ -3368,9 +3277,9 @@ LM_VOID LM_MemWrInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr,
#define MEM_WR_OFFSET(pDevice, Offset, Value32) \
LM_MemWrInd(pDevice, Offset, Value32)
-#endif /* PCIX_TARGET_WORKAROUND */
+#endif /* PCIX_TARGET_WORKAROUND */
-#endif /* Jimmy, merging */
+#endif /* Jimmy, merging */
/* Jimmy...rest of file is new stuff! */
/******************************************************************************/
@@ -3378,14 +3287,14 @@ LM_VOID LM_MemWrInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr,
/******************************************************************************/
/* MAC register access. */
-LM_UINT32 LM_RegRdInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register);
-LM_VOID LM_RegWrInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register,
- LM_UINT32 Value32);
+LM_UINT32 LM_RegRdInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register);
+LM_VOID LM_RegWrInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register,
+ LM_UINT32 Value32);
/* MAC memory access. */
-LM_UINT32 LM_MemRdInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr);
-LM_VOID LM_MemWrInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr,
- LM_UINT32 Value32);
+LM_UINT32 LM_MemRdInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr);
+LM_VOID LM_MemWrInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr,
+ LM_UINT32 Value32);
#define MB_REG_WR(pDevice, OffsetName, Value32) \
((pDevice)->UndiFix) ? \
@@ -3427,4 +3336,4 @@ LM_VOID LM_MemWrInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr,
#define MEM_WR_OFFSET(pDevice, Offset, Value32) \
LM_MemWrInd(pDevice, Offset, Value32)
-#endif /* TIGON3_H */
+#endif /* TIGON3_H */
diff --git a/drivers/tsec.c b/drivers/tsec.c
index 60bef9a..fd21ed4 100644
--- a/drivers/tsec.c
+++ b/drivers/tsec.c
@@ -71,6 +71,7 @@ static struct tsec_info_struct tsec_info[] = {
#else
{TSEC1_PHY_ADDR, TSEC_GIGABIT, TSEC1_PHYIDX},
#endif
+#else
{0, 0, 0},
#endif
#if defined(CONFIG_TSEC2)
@@ -79,6 +80,7 @@ static struct tsec_info_struct tsec_info[] = {
#else
{TSEC2_PHY_ADDR, TSEC_GIGABIT, TSEC2_PHYIDX},
#endif
+#else
{0, 0, 0},
#endif
#ifdef CONFIG_MPC85XX_FEC
@@ -127,6 +129,9 @@ static int tsec_miiphy_write(char *devname, unsigned char addr,
unsigned char reg, unsigned short value);
static int tsec_miiphy_read(char *devname, unsigned char addr,
unsigned char reg, unsigned short *value);
+#ifdef CONFIG_MCAST_TFTP
+static int tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set);
+#endif
/* Initialize device structure. Returns success if PHY
* initialization succeeded (i.e. if it recognizes the PHY)
@@ -165,6 +170,9 @@ int tsec_initialize(bd_t * bis, int index, char *devname)
dev->halt = tsec_halt;
dev->send = tsec_send;
dev->recv = tsec_recv;
+#ifdef CONFIG_MCAST_TFTP
+ dev->mcast = tsec_mcast_addr;
+#endif
/* Tell u-boot to get the addr from the env */
for (i = 0; i < 6; i++)
@@ -296,9 +304,9 @@ static int init_phy(struct eth_device *dev)
volatile tsec_t *regs = (volatile tsec_t *)(TSEC_BASE_ADDR);
/* Assign a Physical address to the TBI */
- regs->tbipa = TBIPA_VALUE;
+ regs->tbipa = CFG_TBIPA_VALUE;
regs = (volatile tsec_t *)(TSEC_BASE_ADDR + TSEC_SIZE);
- regs->tbipa = TBIPA_VALUE;
+ regs->tbipa = CFG_TBIPA_VALUE;
asm("sync");
/* Reset MII (due to new addresses) */
@@ -1537,4 +1545,46 @@ static int tsec_miiphy_write(char *devname, unsigned char addr,
#endif
+#ifdef CONFIG_MCAST_TFTP
+
+/* CREDITS: linux gianfar driver, slightly adjusted... thanx. */
+
+/* Set the appropriate hash bit for the given addr */
+
+/* The algorithm works like so:
+ * 1) Take the Destination Address (ie the multicast address), and
+ * do a CRC on it (little endian), and reverse the bits of the
+ * result.
+ * 2) Use the 8 most significant bits as a hash into a 256-entry
+ * table. The table is controlled through 8 32-bit registers:
+ * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
+ * gaddr7. This means that the 3 most significant bits in the
+ * hash index which gaddr register to use, and the 5 other bits
+ * indicate which bit (assuming an IBM numbering scheme, which
+ * for PowerPC (tm) is usually the case) in the tregister holds
+ * the entry. */
+static int
+tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set)
+{
+ struct tsec_private *priv = privlist[1];
+ volatile tsec_t *regs = priv->regs;
+ volatile u32 *reg_array, value;
+ u8 result, whichbit, whichreg;
+
+ result = (u8)((ether_crc(MAC_ADDR_LEN,mcast_mac) >> 24) & 0xff);
+ whichbit = result & 0x1f; /* the 5 LSB = which bit to set */
+ whichreg = result >> 5; /* the 3 MSB = which reg to set it in */
+ value = (1 << (31-whichbit));
+
+ reg_array = &(regs->hash.gaddr0);
+
+ if (set) {
+ reg_array[whichreg] |= value;
+ } else {
+ reg_array[whichreg] &= ~value;
+ }
+ return 0;
+}
+#endif /* Multicast TFTP ? */
+
#endif /* CONFIG_TSEC_ENET */
diff --git a/drivers/tsec.h b/drivers/tsec.h
index 7bf3dee..2f0092a 100644
--- a/drivers/tsec.h
+++ b/drivers/tsec.h
@@ -70,7 +70,9 @@
#define miim_end -2
#define miim_read -1
-#define TBIPA_VALUE 0x1f
+#ifndef CFG_TBIPA_VALUE
+ #define CFG_TBIPA_VALUE 0x1f
+#endif
#define MIIMCFG_INIT_VALUE 0x00000003
#define MIIMCFG_RESET 0x80000000
diff --git a/drivers/usb_ohci.c b/drivers/usb_ohci.c
new file mode 100644
index 0000000..f0a37b2
--- /dev/null
+++ b/drivers/usb_ohci.c
@@ -0,0 +1,1918 @@
+/*
+ * URB OHCI HCD (Host Controller Driver) for USB on the AT91RM9200 and PCI bus.
+ *
+ * Interrupt support is added. Now, it has been tested
+ * on ULI1575 chip and works well with USB keyboard.
+ *
+ * (C) Copyright 2007
+ * Zhang Wei, Freescale Semiconductor, Inc. <wei.zhang@freescale.com>
+ *
+ * (C) Copyright 2003
+ * Gary Jennejohn, DENX Software Engineering <gj@denx.de>
+ *
+ * Note: Much of this code has been derived from Linux 2.4
+ * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
+ * (C) Copyright 2000-2002 David Brownell
+ *
+ * Modified for the MP2USB by (C) Copyright 2005 Eric Benard
+ * ebenard@eukrea.com - based on s3c24x0's driver
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+/*
+ * IMPORTANT NOTES
+ * 1 - Read doc/README.generic_usb_ohci
+ * 2 - this driver is intended for use with USB Mass Storage Devices
+ * (BBB) and USB keyboard. There is NO support for Isochronous pipes!
+ * 2 - when running on a PQFP208 AT91RM9200, define CONFIG_AT91C_PQFP_UHPBUG
+ * to activate workaround for bug #41 or this driver will NOT work!
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_USB_OHCI_NEW
+
+#include <asm/byteorder.h>
+
+#if defined(CONFIG_PCI_OHCI)
+# include <pci.h>
+#endif
+
+#include <malloc.h>
+#include <usb.h>
+#include "usb_ohci.h"
+
+#if defined(CONFIG_ARM920T) || \
+ defined(CONFIG_S3C2400) || \
+ defined(CONFIG_S3C2410) || \
+ defined(CONFIG_440EP) || \
+ defined(CONFIG_PCI_OHCI) || \
+ defined(CONFIG_MPC5200)
+# define OHCI_USE_NPS /* force NoPowerSwitching mode */
+#endif
+
+#undef OHCI_VERBOSE_DEBUG /* not always helpful */
+#undef DEBUG
+#undef SHOW_INFO
+#undef OHCI_FILL_TRACE
+
+/* For initializing controller (mask in an HCFS mode too) */
+#define OHCI_CONTROL_INIT \
+ (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
+
+/*
+ * e.g. PCI controllers need this
+ */
+#ifdef CFG_OHCI_SWAP_REG_ACCESS
+# define readl(a) __swap_32(*((vu_long *)(a)))
+# define writel(a, b) (*((vu_long *)(b)) = __swap_32((vu_long)a))
+#else
+# define readl(a) (*((vu_long *)(a)))
+# define writel(a, b) (*((vu_long *)(b)) = ((vu_long)a))
+#endif /* CFG_OHCI_SWAP_REG_ACCESS */
+
+#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
+
+#ifdef CONFIG_PCI_OHCI
+static struct pci_device_id ohci_pci_ids[] = {
+ {0x10b9, 0x5237}, /* ULI1575 PCI OHCI module ids */
+ /* Please add supported PCI OHCI controller ids here */
+ {0, 0}
+};
+#endif
+
+#ifdef DEBUG
+#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
+#else
+#define dbg(format, arg...) do {} while(0)
+#endif /* DEBUG */
+#define err(format, arg...) printf("ERROR: " format "\n", ## arg)
+#undef SHOW_INFO
+#ifdef SHOW_INFO
+#define info(format, arg...) printf("INFO: " format "\n", ## arg)
+#else
+#define info(format, arg...) do {} while(0)
+#endif
+
+#ifdef CFG_OHCI_BE_CONTROLLER
+# define m16_swap(x) cpu_to_be16(x)
+# define m32_swap(x) cpu_to_be32(x)
+#else
+# define m16_swap(x) cpu_to_le16(x)
+# define m32_swap(x) cpu_to_le32(x)
+#endif /* CFG_OHCI_BE_CONTROLLER */
+
+/* global ohci_t */
+static ohci_t gohci;
+/* this must be aligned to a 256 byte boundary */
+struct ohci_hcca ghcca[1];
+/* a pointer to the aligned storage */
+struct ohci_hcca *phcca;
+/* this allocates EDs for all possible endpoints */
+struct ohci_device ohci_dev;
+/* RHSC flag */
+int got_rhsc;
+/* device which was disconnected */
+struct usb_device *devgone;
+
+/*-------------------------------------------------------------------------*/
+
+/* AMD-756 (D2 rev) reports corrupt register contents in some cases.
+ * The erratum (#4) description is incorrect. AMD's workaround waits
+ * till some bits (mostly reserved) are clear; ok for all revs.
+ */
+#define OHCI_QUIRK_AMD756 0xabcd
+#define read_roothub(hc, register, mask) ({ \
+ u32 temp = readl (&hc->regs->roothub.register); \
+ if (hc->flags & OHCI_QUIRK_AMD756) \
+ while (temp & mask) \
+ temp = readl (&hc->regs->roothub.register); \
+ temp; })
+
+static u32 roothub_a (struct ohci *hc)
+ { return read_roothub (hc, a, 0xfc0fe000); }
+static inline u32 roothub_b (struct ohci *hc)
+ { return readl (&hc->regs->roothub.b); }
+static inline u32 roothub_status (struct ohci *hc)
+ { return readl (&hc->regs->roothub.status); }
+static u32 roothub_portstatus (struct ohci *hc, int i)
+ { return read_roothub (hc, portstatus [i], 0xffe0fce0); }
+
+/* forward declaration */
+static int hc_interrupt (void);
+static void
+td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer,
+ int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval);
+
+/*-------------------------------------------------------------------------*
+ * URB support functions
+ *-------------------------------------------------------------------------*/
+
+/* free HCD-private data associated with this URB */
+
+static void urb_free_priv (urb_priv_t * urb)
+{
+ int i;
+ int last;
+ struct td * td;
+
+ last = urb->length - 1;
+ if (last >= 0) {
+ for (i = 0; i <= last; i++) {
+ td = urb->td[i];
+ if (td) {
+ td->usb_dev = NULL;
+ urb->td[i] = NULL;
+ }
+ }
+ }
+ free(urb);
+}
+
+/*-------------------------------------------------------------------------*/
+
+#ifdef DEBUG
+static int sohci_get_current_frame_number (struct usb_device * dev);
+
+/* debug| print the main components of an URB
+ * small: 0) header + data packets 1) just header */
+
+static void pkt_print (urb_priv_t *purb, struct usb_device * dev,
+ unsigned long pipe, void * buffer,
+ int transfer_len, struct devrequest * setup, char * str, int small)
+{
+ dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",
+ str,
+ sohci_get_current_frame_number (dev),
+ usb_pipedevice (pipe),
+ usb_pipeendpoint (pipe),
+ usb_pipeout (pipe)? 'O': 'I',
+ usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"):
+ (usb_pipecontrol (pipe)? "CTRL": "BULK"),
+ (purb ? purb->actual_length : 0),
+ transfer_len, dev->status);
+#ifdef OHCI_VERBOSE_DEBUG
+ if (!small) {
+ int i, len;
+
+ if (usb_pipecontrol (pipe)) {
+ printf (__FILE__ ": cmd(8):");
+ for (i = 0; i < 8 ; i++)
+ printf (" %02x", ((__u8 *) setup) [i]);
+ printf ("\n");
+ }
+ if (transfer_len > 0 && buffer) {
+ printf (__FILE__ ": data(%d/%d):",
+ (purb ? purb->actual_length : 0),
+ transfer_len);
+ len = usb_pipeout (pipe)?
+ transfer_len:
+ (purb ? purb->actual_length : 0);
+ for (i = 0; i < 16 && i < len; i++)
+ printf (" %02x", ((__u8 *) buffer) [i]);
+ printf ("%s\n", i < len? "...": "");
+ }
+ }
+#endif
+}
+
+/* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/
+void ep_print_int_eds (ohci_t *ohci, char * str) {
+ int i, j;
+ __u32 * ed_p;
+ for (i= 0; i < 32; i++) {
+ j = 5;
+ ed_p = &(ohci->hcca->int_table [i]);
+ if (*ed_p == 0)
+ continue;
+ printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i);
+ while (*ed_p != 0 && j--) {
+ ed_t *ed = (ed_t *)m32_swap(ed_p);
+ printf (" ed: %4x;", ed->hwINFO);
+ ed_p = &ed->hwNextED;
+ }
+ printf ("\n");
+ }
+}
+
+static void ohci_dump_intr_mask (char *label, __u32 mask)
+{
+ dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
+ label,
+ mask,
+ (mask & OHCI_INTR_MIE) ? " MIE" : "",
+ (mask & OHCI_INTR_OC) ? " OC" : "",
+ (mask & OHCI_INTR_RHSC) ? " RHSC" : "",
+ (mask & OHCI_INTR_FNO) ? " FNO" : "",
+ (mask & OHCI_INTR_UE) ? " UE" : "",
+ (mask & OHCI_INTR_RD) ? " RD" : "",
+ (mask & OHCI_INTR_SF) ? " SF" : "",
+ (mask & OHCI_INTR_WDH) ? " WDH" : "",
+ (mask & OHCI_INTR_SO) ? " SO" : ""
+ );
+}
+
+static void maybe_print_eds (char *label, __u32 value)
+{
+ ed_t *edp = (ed_t *)value;
+
+ if (value) {
+ dbg ("%s %08x", label, value);
+ dbg ("%08x", edp->hwINFO);
+ dbg ("%08x", edp->hwTailP);
+ dbg ("%08x", edp->hwHeadP);
+ dbg ("%08x", edp->hwNextED);
+ }
+}
+
+static char * hcfs2string (int state)
+{
+ switch (state) {
+ case OHCI_USB_RESET: return "reset";
+ case OHCI_USB_RESUME: return "resume";
+ case OHCI_USB_OPER: return "operational";
+ case OHCI_USB_SUSPEND: return "suspend";
+ }
+ return "?";
+}
+
+/* dump control and status registers */
+static void ohci_dump_status (ohci_t *controller)
+{
+ struct ohci_regs *regs = controller->regs;
+ __u32 temp;
+
+ temp = readl (&regs->revision) & 0xff;
+ if (temp != 0x10)
+ dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f));
+
+ temp = readl (&regs->control);
+ dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
+ (temp & OHCI_CTRL_RWE) ? " RWE" : "",
+ (temp & OHCI_CTRL_RWC) ? " RWC" : "",
+ (temp & OHCI_CTRL_IR) ? " IR" : "",
+ hcfs2string (temp & OHCI_CTRL_HCFS),
+ (temp & OHCI_CTRL_BLE) ? " BLE" : "",
+ (temp & OHCI_CTRL_CLE) ? " CLE" : "",
+ (temp & OHCI_CTRL_IE) ? " IE" : "",
+ (temp & OHCI_CTRL_PLE) ? " PLE" : "",
+ temp & OHCI_CTRL_CBSR
+ );
+
+ temp = readl (&regs->cmdstatus);
+ dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
+ (temp & OHCI_SOC) >> 16,
+ (temp & OHCI_OCR) ? " OCR" : "",
+ (temp & OHCI_BLF) ? " BLF" : "",
+ (temp & OHCI_CLF) ? " CLF" : "",
+ (temp & OHCI_HCR) ? " HCR" : ""
+ );
+
+ ohci_dump_intr_mask ("intrstatus", readl (&regs->intrstatus));
+ ohci_dump_intr_mask ("intrenable", readl (&regs->intrenable));
+
+ maybe_print_eds ("ed_periodcurrent", readl (&regs->ed_periodcurrent));
+
+ maybe_print_eds ("ed_controlhead", readl (&regs->ed_controlhead));
+ maybe_print_eds ("ed_controlcurrent", readl (&regs->ed_controlcurrent));
+
+ maybe_print_eds ("ed_bulkhead", readl (&regs->ed_bulkhead));
+ maybe_print_eds ("ed_bulkcurrent", readl (&regs->ed_bulkcurrent));
+
+ maybe_print_eds ("donehead", readl (&regs->donehead));
+}
+
+static void ohci_dump_roothub (ohci_t *controller, int verbose)
+{
+ __u32 temp, ndp, i;
+
+ temp = roothub_a (controller);
+ ndp = (temp & RH_A_NDP);
+#ifdef CONFIG_AT91C_PQFP_UHPBUG
+ ndp = (ndp == 2) ? 1:0;
+#endif
+ if (verbose) {
+ dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
+ ((temp & RH_A_POTPGT) >> 24) & 0xff,
+ (temp & RH_A_NOCP) ? " NOCP" : "",
+ (temp & RH_A_OCPM) ? " OCPM" : "",
+ (temp & RH_A_DT) ? " DT" : "",
+ (temp & RH_A_NPS) ? " NPS" : "",
+ (temp & RH_A_PSM) ? " PSM" : "",
+ ndp
+ );
+ temp = roothub_b (controller);
+ dbg ("roothub.b: %08x PPCM=%04x DR=%04x",
+ temp,
+ (temp & RH_B_PPCM) >> 16,
+ (temp & RH_B_DR)
+ );
+ temp = roothub_status (controller);
+ dbg ("roothub.status: %08x%s%s%s%s%s%s",
+ temp,
+ (temp & RH_HS_CRWE) ? " CRWE" : "",
+ (temp & RH_HS_OCIC) ? " OCIC" : "",
+ (temp & RH_HS_LPSC) ? " LPSC" : "",
+ (temp & RH_HS_DRWE) ? " DRWE" : "",
+ (temp & RH_HS_OCI) ? " OCI" : "",
+ (temp & RH_HS_LPS) ? " LPS" : ""
+ );
+ }
+
+ for (i = 0; i < ndp; i++) {
+ temp = roothub_portstatus (controller, i);
+ dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
+ i,
+ temp,
+ (temp & RH_PS_PRSC) ? " PRSC" : "",
+ (temp & RH_PS_OCIC) ? " OCIC" : "",
+ (temp & RH_PS_PSSC) ? " PSSC" : "",
+ (temp & RH_PS_PESC) ? " PESC" : "",
+ (temp & RH_PS_CSC) ? " CSC" : "",
+
+ (temp & RH_PS_LSDA) ? " LSDA" : "",
+ (temp & RH_PS_PPS) ? " PPS" : "",
+ (temp & RH_PS_PRS) ? " PRS" : "",
+ (temp & RH_PS_POCI) ? " POCI" : "",
+ (temp & RH_PS_PSS) ? " PSS" : "",
+
+ (temp & RH_PS_PES) ? " PES" : "",
+ (temp & RH_PS_CCS) ? " CCS" : ""
+ );
+ }
+}
+
+static void ohci_dump (ohci_t *controller, int verbose)
+{
+ dbg ("OHCI controller usb-%s state", controller->slot_name);
+
+ /* dumps some of the state we know about */
+ ohci_dump_status (controller);
+ if (verbose)
+ ep_print_int_eds (controller, "hcca");
+ dbg ("hcca frame #%04x", controller->hcca->frame_no);
+ ohci_dump_roothub (controller, 1);
+
+#endif /* DEBUG */
+
+/*-------------------------------------------------------------------------*
+ * Interface functions (URB)
+ *-------------------------------------------------------------------------*/
+
+/* get a transfer request */
+
+int sohci_submit_job(urb_priv_t *urb, struct devrequest *setup)
+{
+ ohci_t *ohci;
+ ed_t * ed;
+ urb_priv_t *purb_priv = urb;
+ int i, size = 0;
+ struct usb_device *dev = urb->dev;
+ unsigned long pipe = urb->pipe;
+ void *buffer = urb->transfer_buffer;
+ int transfer_len = urb->transfer_buffer_length;
+ int interval = urb->interval;
+
+ ohci = &gohci;
+
+ /* when controller's hung, permit only roothub cleanup attempts
+ * such as powering down ports */
+ if (ohci->disabled) {
+ err("sohci_submit_job: EPIPE");
+ return -1;
+ }
+
+ /* we're about to begin a new transaction here so mark the URB unfinished */
+ urb->finished = 0;
+
+ /* every endpoint has a ed, locate and fill it */
+ if (!(ed = ep_add_ed (dev, pipe, interval, 1))) {
+ err("sohci_submit_job: ENOMEM");
+ return -1;
+ }
+
+ /* for the private part of the URB we need the number of TDs (size) */
+ switch (usb_pipetype (pipe)) {
+ case PIPE_BULK: /* one TD for every 4096 Byte */
+ size = (transfer_len - 1) / 4096 + 1;
+ break;
+ case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
+ size = (transfer_len == 0)? 2:
+ (transfer_len - 1) / 4096 + 3;
+ break;
+ case PIPE_INTERRUPT: /* 1 TD */
+ size = 1;
+ break;
+ }
+
+ ed->purb = urb;
+
+ if (size >= (N_URB_TD - 1)) {
+ err("need %d TDs, only have %d", size, N_URB_TD);
+ return -1;
+ }
+ purb_priv->pipe = pipe;
+
+ /* fill the private part of the URB */
+ purb_priv->length = size;
+ purb_priv->ed = ed;
+ purb_priv->actual_length = 0;
+
+ /* allocate the TDs */
+ /* note that td[0] was allocated in ep_add_ed */
+ for (i = 0; i < size; i++) {
+ purb_priv->td[i] = td_alloc (dev);
+ if (!purb_priv->td[i]) {
+ purb_priv->length = i;
+ urb_free_priv (purb_priv);
+ err("sohci_submit_job: ENOMEM");
+ return -1;
+ }
+ }
+
+ if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
+ urb_free_priv (purb_priv);
+ err("sohci_submit_job: EINVAL");
+ return -1;
+ }
+
+ /* link the ed into a chain if is not already */
+ if (ed->state != ED_OPER)
+ ep_link (ohci, ed);
+
+ /* fill the TDs and link it to the ed */
+ td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval);
+
+ return 0;
+}
+
+static inline int sohci_return_job(struct ohci *hc, urb_priv_t *urb)
+{
+ struct ohci_regs *regs = hc->regs;
+
+ switch (usb_pipetype (urb->pipe)) {
+ case PIPE_INTERRUPT:
+ /* implicitly requeued */
+ if (urb->dev->irq_handle &&
+ (urb->dev->irq_act_len = urb->actual_length)) {
+ writel (OHCI_INTR_WDH, &regs->intrenable);
+ readl (&regs->intrenable); /* PCI posting flush */
+ urb->dev->irq_handle(urb->dev);
+ writel (OHCI_INTR_WDH, &regs->intrdisable);
+ readl (&regs->intrdisable); /* PCI posting flush */
+ }
+ urb->actual_length = 0;
+ td_submit_job (
+ urb->dev,
+ urb->pipe,
+ urb->transfer_buffer,
+ urb->transfer_buffer_length,
+ NULL,
+ urb,
+ urb->interval);
+ break;
+ case PIPE_CONTROL:
+ case PIPE_BULK:
+ break;
+ default:
+ return 0;
+ }
+ return 1;
+}
+
+/*-------------------------------------------------------------------------*/
+
+#ifdef DEBUG
+/* tell us the current USB frame number */
+
+static int sohci_get_current_frame_number (struct usb_device *usb_dev)
+{
+ ohci_t *ohci = &gohci;
+
+ return m16_swap (ohci->hcca->frame_no);
+}
+#endif
+
+/*-------------------------------------------------------------------------*
+ * ED handling functions
+ *-------------------------------------------------------------------------*/
+
+/* search for the right branch to insert an interrupt ed into the int tree
+ * do some load ballancing;
+ * returns the branch and
+ * sets the interval to interval = 2^integer (ld (interval)) */
+
+static int ep_int_ballance (ohci_t * ohci, int interval, int load)
+{
+ int i, branch = 0;
+
+ /* search for the least loaded interrupt endpoint
+ * branch of all 32 branches
+ */
+ for (i = 0; i < 32; i++)
+ if (ohci->ohci_int_load [branch] > ohci->ohci_int_load [i])
+ branch = i;
+
+ branch = branch % interval;
+ for (i = branch; i < 32; i += interval)
+ ohci->ohci_int_load [i] += load;
+
+ return branch;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* 2^int( ld (inter)) */
+
+static int ep_2_n_interval (int inter)
+{
+ int i;
+ for (i = 0; ((inter >> i) > 1 ) && (i < 5); i++);
+ return 1 << i;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* the int tree is a binary tree
+ * in order to process it sequentially the indexes of the branches have to be mapped
+ * the mapping reverses the bits of a word of num_bits length */
+
+static int ep_rev (int num_bits, int word)
+{
+ int i, wout = 0;
+
+ for (i = 0; i < num_bits; i++)
+ wout |= (((word >> i) & 1) << (num_bits - i - 1));
+ return wout;
+}
+
+/*-------------------------------------------------------------------------*
+ * ED handling functions
+ *-------------------------------------------------------------------------*/
+
+/* link an ed into one of the HC chains */
+
+static int ep_link (ohci_t *ohci, ed_t *edi)
+{
+ volatile ed_t *ed = edi;
+ int int_branch;
+ int i;
+ int inter;
+ int interval;
+ int load;
+ __u32 * ed_p;
+
+ ed->state = ED_OPER;
+ ed->int_interval = 0;
+
+ switch (ed->type) {
+ case PIPE_CONTROL:
+ ed->hwNextED = 0;
+ if (ohci->ed_controltail == NULL) {
+ writel (ed, &ohci->regs->ed_controlhead);
+ } else {
+ ohci->ed_controltail->hwNextED = m32_swap ((unsigned long)ed);
+ }
+ ed->ed_prev = ohci->ed_controltail;
+ if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
+ !ohci->ed_rm_list[1] && !ohci->sleeping) {
+ ohci->hc_control |= OHCI_CTRL_CLE;
+ writel (ohci->hc_control, &ohci->regs->control);
+ }
+ ohci->ed_controltail = edi;
+ break;
+
+ case PIPE_BULK:
+ ed->hwNextED = 0;
+ if (ohci->ed_bulktail == NULL) {
+ writel (ed, &ohci->regs->ed_bulkhead);
+ } else {
+ ohci->ed_bulktail->hwNextED = m32_swap ((unsigned long)ed);
+ }
+ ed->ed_prev = ohci->ed_bulktail;
+ if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
+ !ohci->ed_rm_list[1] && !ohci->sleeping) {
+ ohci->hc_control |= OHCI_CTRL_BLE;
+ writel (ohci->hc_control, &ohci->regs->control);
+ }
+ ohci->ed_bulktail = edi;
+ break;
+
+ case PIPE_INTERRUPT:
+ load = ed->int_load;
+ interval = ep_2_n_interval (ed->int_period);
+ ed->int_interval = interval;
+ int_branch = ep_int_ballance (ohci, interval, load);
+ ed->int_branch = int_branch;
+
+ for (i = 0; i < ep_rev (6, interval); i += inter) {
+ inter = 1;
+ for (ed_p = &(ohci->hcca->int_table[ep_rev (5, i) + int_branch]);
+ (*ed_p != 0) && (((ed_t *)ed_p)->int_interval >= interval);
+ ed_p = &(((ed_t *)ed_p)->hwNextED))
+ inter = ep_rev (6, ((ed_t *)ed_p)->int_interval);
+ ed->hwNextED = *ed_p;
+ *ed_p = m32_swap(ed);
+ }
+ break;
+ }
+ return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* scan the periodic table to find and unlink this ED */
+static void periodic_unlink ( struct ohci *ohci, volatile struct ed *ed,
+ unsigned index, unsigned period)
+{
+ for (; index < NUM_INTS; index += period) {
+ __u32 *ed_p = &ohci->hcca->int_table [index];
+
+ /* ED might have been unlinked through another path */
+ while (*ed_p != 0) {
+ if (((struct ed *)m32_swap (ed_p)) == ed) {
+ *ed_p = ed->hwNextED;
+ break;
+ }
+ ed_p = & (((struct ed *)m32_swap (ed_p))->hwNextED);
+ }
+ }
+}
+
+/* unlink an ed from one of the HC chains.
+ * just the link to the ed is unlinked.
+ * the link from the ed still points to another operational ed or 0
+ * so the HC can eventually finish the processing of the unlinked ed */
+
+static int ep_unlink (ohci_t *ohci, ed_t *edi)
+{
+ volatile ed_t *ed = edi;
+ int i;
+
+ ed->hwINFO |= m32_swap (OHCI_ED_SKIP);
+
+ switch (ed->type) {
+ case PIPE_CONTROL:
+ if (ed->ed_prev == NULL) {
+ if (!ed->hwNextED) {
+ ohci->hc_control &= ~OHCI_CTRL_CLE;
+ writel (ohci->hc_control, &ohci->regs->control);
+ }
+ writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead);
+ } else {
+ ed->ed_prev->hwNextED = ed->hwNextED;
+ }
+ if (ohci->ed_controltail == ed) {
+ ohci->ed_controltail = ed->ed_prev;
+ } else {
+ ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
+ }
+ break;
+
+ case PIPE_BULK:
+ if (ed->ed_prev == NULL) {
+ if (!ed->hwNextED) {
+ ohci->hc_control &= ~OHCI_CTRL_BLE;
+ writel (ohci->hc_control, &ohci->regs->control);
+ }
+ writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead);
+ } else {
+ ed->ed_prev->hwNextED = ed->hwNextED;
+ }
+ if (ohci->ed_bulktail == ed) {
+ ohci->ed_bulktail = ed->ed_prev;
+ } else {
+ ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
+ }
+ break;
+
+ case PIPE_INTERRUPT:
+ periodic_unlink (ohci, ed, 0, 1);
+ for (i = ed->int_branch; i < 32; i += ed->int_interval)
+ ohci->ohci_int_load[i] -= ed->int_load;
+ break;
+ }
+ ed->state = ED_UNLINK;
+ return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* add/reinit an endpoint; this should be done once at the
+ * usb_set_configuration command, but the USB stack is a little bit
+ * stateless so we do it at every transaction if the state of the ed
+ * is ED_NEW then a dummy td is added and the state is changed to
+ * ED_UNLINK in all other cases the state is left unchanged the ed
+ * info fields are setted anyway even though most of them should not
+ * change
+ */
+static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe,
+ int interval, int load)
+{
+ td_t *td;
+ ed_t *ed_ret;
+ volatile ed_t *ed;
+
+ ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) |
+ (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))];
+
+ if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
+ err("ep_add_ed: pending delete");
+ /* pending delete request */
+ return NULL;
+ }
+
+ if (ed->state == ED_NEW) {
+ ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */
+ /* dummy td; end of td list for ed */
+ td = td_alloc (usb_dev);
+ ed->hwTailP = m32_swap ((unsigned long)td);
+ ed->hwHeadP = ed->hwTailP;
+ ed->state = ED_UNLINK;
+ ed->type = usb_pipetype (pipe);
+ ohci_dev.ed_cnt++;
+ }
+
+ ed->hwINFO = m32_swap (usb_pipedevice (pipe)
+ | usb_pipeendpoint (pipe) << 7
+ | (usb_pipeisoc (pipe)? 0x8000: 0)
+ | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000))
+ | usb_pipeslow (pipe) << 13
+ | usb_maxpacket (usb_dev, pipe) << 16);
+
+ if (ed->type == PIPE_INTERRUPT && ed->state == ED_UNLINK) {
+ ed->int_period = interval;
+ ed->int_load = load;
+ }
+
+ return ed_ret;
+}
+
+/*-------------------------------------------------------------------------*
+ * TD handling functions
+ *-------------------------------------------------------------------------*/
+
+/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
+
+static void td_fill (ohci_t *ohci, unsigned int info,
+ void *data, int len,
+ struct usb_device *dev, int index, urb_priv_t *urb_priv)
+{
+ volatile td_t *td, *td_pt;
+#ifdef OHCI_FILL_TRACE
+ int i;
+#endif
+
+ if (index > urb_priv->length) {
+ err("index > length");
+ return;
+ }
+ /* use this td as the next dummy */
+ td_pt = urb_priv->td [index];
+ td_pt->hwNextTD = 0;
+
+ /* fill the old dummy TD */
+ td = urb_priv->td [index] = (td_t *)(m32_swap (urb_priv->ed->hwTailP) & ~0xf);
+
+ td->ed = urb_priv->ed;
+ td->next_dl_td = NULL;
+ td->index = index;
+ td->data = (__u32)data;
+#ifdef OHCI_FILL_TRACE
+ if ((usb_pipetype(urb_priv->pipe) == PIPE_BULK) && usb_pipeout(urb_priv->pipe)) {
+ for (i = 0; i < len; i++)
+ printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]);
+ printf("\n");
+ }
+#endif
+ if (!len)
+ data = 0;
+
+ td->hwINFO = m32_swap (info);
+ td->hwCBP = m32_swap ((unsigned long)data);
+ if (data)
+ td->hwBE = m32_swap ((unsigned long)(data + len - 1));
+ else
+ td->hwBE = 0;
+ td->hwNextTD = m32_swap ((unsigned long)td_pt);
+
+ /* append to queue */
+ td->ed->hwTailP = td->hwNextTD;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* prepare all TDs of a transfer */
+
+static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer,
+ int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval)
+{
+ ohci_t *ohci = &gohci;
+ int data_len = transfer_len;
+ void *data;
+ int cnt = 0;
+ __u32 info = 0;
+ unsigned int toggle = 0;
+
+ /* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */
+ if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
+ toggle = TD_T_TOGGLE;
+ } else {
+ toggle = TD_T_DATA0;
+ usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1);
+ }
+ urb->td_cnt = 0;
+ if (data_len)
+ data = buffer;
+ else
+ data = 0;
+
+ switch (usb_pipetype (pipe)) {
+ case PIPE_BULK:
+ info = usb_pipeout (pipe)?
+ TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ;
+ while(data_len > 4096) {
+ td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb);
+ data += 4096; data_len -= 4096; cnt++;
+ }
+ info = usb_pipeout (pipe)?
+ TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ;
+ td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb);
+ cnt++;
+
+ if (!ohci->sleeping)
+ writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */
+ break;
+
+ case PIPE_CONTROL:
+ info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
+ td_fill (ohci, info, setup, 8, dev, cnt++, urb);
+ if (data_len > 0) {
+ info = usb_pipeout (pipe)?
+ TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
+ /* NOTE: mishandles transfers >8K, some >4K */
+ td_fill (ohci, info, data, data_len, dev, cnt++, urb);
+ }
+ info = usb_pipeout (pipe)?
+ TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1;
+ td_fill (ohci, info, data, 0, dev, cnt++, urb);
+ if (!ohci->sleeping)
+ writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */
+ break;
+
+ case PIPE_INTERRUPT:
+ info = usb_pipeout (urb->pipe)?
+ TD_CC | TD_DP_OUT | toggle:
+ TD_CC | TD_R | TD_DP_IN | toggle;
+ td_fill (ohci, info, data, data_len, dev, cnt++, urb);
+ break;
+ }
+ if (urb->length != cnt)
+ dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
+}
+
+/*-------------------------------------------------------------------------*
+ * Done List handling functions
+ *-------------------------------------------------------------------------*/
+
+/* calculate the transfer length and update the urb */
+
+static void dl_transfer_length(td_t * td)
+{
+ __u32 tdINFO, tdBE, tdCBP;
+ urb_priv_t *lurb_priv = td->ed->purb;
+
+ tdINFO = m32_swap (td->hwINFO);
+ tdBE = m32_swap (td->hwBE);
+ tdCBP = m32_swap (td->hwCBP);
+
+ if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL &&
+ ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
+ if (tdBE != 0) {
+ if (td->hwCBP == 0)
+ lurb_priv->actual_length += tdBE - td->data + 1;
+ else
+ lurb_priv->actual_length += tdCBP - td->data;
+ }
+ }
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* replies to the request have to be on a FIFO basis so
+ * we reverse the reversed done-list */
+
+static td_t * dl_reverse_done_list (ohci_t *ohci)
+{
+ __u32 td_list_hc;
+ td_t *td_rev = NULL;
+ td_t *td_list = NULL;
+ urb_priv_t *lurb_priv = NULL;
+
+ td_list_hc = m32_swap (ohci->hcca->done_head) & 0xfffffff0;
+ ohci->hcca->done_head = 0;
+
+ while (td_list_hc) {
+ td_list = (td_t *)td_list_hc;
+
+ if (TD_CC_GET (m32_swap (td_list->hwINFO))) {
+ lurb_priv = td_list->ed->purb;
+ dbg(" USB-error/status: %x : %p",
+ TD_CC_GET (m32_swap (td_list->hwINFO)), td_list);
+ if (td_list->ed->hwHeadP & m32_swap (0x1)) {
+ if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) {
+ td_list->ed->hwHeadP =
+ (lurb_priv->td[lurb_priv->length - 1]->hwNextTD & m32_swap (0xfffffff0)) |
+ (td_list->ed->hwHeadP & m32_swap (0x2));
+ lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1;
+ } else
+ td_list->ed->hwHeadP &= m32_swap (0xfffffff2);
+ }
+#ifdef CONFIG_MPC5200
+ td_list->hwNextTD = 0;
+#endif
+ }
+
+ td_list->next_dl_td = td_rev;
+ td_rev = td_list;
+ td_list_hc = m32_swap (td_list->hwNextTD) & 0xfffffff0;
+ }
+ return td_list;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* td done list */
+static int dl_done_list (ohci_t *ohci, td_t *td_list)
+{
+ td_t *td_list_next = NULL;
+ ed_t *ed;
+ int cc = 0;
+ int stat = 0;
+ /* urb_t *urb; */
+ urb_priv_t *lurb_priv;
+ __u32 tdINFO, edHeadP, edTailP;
+
+ while (td_list) {
+ td_list_next = td_list->next_dl_td;
+
+ tdINFO = m32_swap (td_list->hwINFO);
+
+ ed = td_list->ed;
+ lurb_priv = ed->purb;
+
+ dl_transfer_length(td_list);
+
+ /* error code of transfer */
+ cc = TD_CC_GET (tdINFO);
+ if (cc != 0) {
+ dbg("ConditionCode %#x", cc);
+ stat = cc_to_error[cc];
+ }
+
+ /* see if this done list makes for all TD's of current URB,
+ * and mark the URB finished if so */
+ if (++(lurb_priv->td_cnt) == lurb_priv->length) {
+#if 1
+ if ((ed->state & (ED_OPER | ED_UNLINK)) &&
+ (lurb_priv->state != URB_DEL))
+#else
+ if ((ed->state & (ED_OPER | ED_UNLINK)))
+#endif
+ lurb_priv->finished = sohci_return_job(ohci,
+ lurb_priv);
+ else
+ dbg("dl_done_list: strange.., ED state %x, ed->state\n");
+ } else
+ dbg("dl_done_list: processing TD %x, len %x\n", lurb_priv->td_cnt,
+ lurb_priv->length);
+ if (ed->state != ED_NEW &&
+ (usb_pipetype (lurb_priv->pipe) != PIPE_INTERRUPT)) {
+ edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0;
+ edTailP = m32_swap (ed->hwTailP);
+
+ /* unlink eds if they are not busy */
+ if ((edHeadP == edTailP) && (ed->state == ED_OPER))
+ ep_unlink (ohci, ed);
+ }
+
+ td_list = td_list_next;
+ }
+ return stat;
+}
+
+/*-------------------------------------------------------------------------*
+ * Virtual Root Hub
+ *-------------------------------------------------------------------------*/
+
+/* Device descriptor */
+static __u8 root_hub_dev_des[] =
+{
+ 0x12, /* __u8 bLength; */
+ 0x01, /* __u8 bDescriptorType; Device */
+ 0x10, /* __u16 bcdUSB; v1.1 */
+ 0x01,
+ 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
+ 0x00, /* __u8 bDeviceSubClass; */
+ 0x00, /* __u8 bDeviceProtocol; */
+ 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
+ 0x00, /* __u16 idVendor; */
+ 0x00,
+ 0x00, /* __u16 idProduct; */
+ 0x00,
+ 0x00, /* __u16 bcdDevice; */
+ 0x00,
+ 0x00, /* __u8 iManufacturer; */
+ 0x01, /* __u8 iProduct; */
+ 0x00, /* __u8 iSerialNumber; */
+ 0x01 /* __u8 bNumConfigurations; */
+};
+
+/* Configuration descriptor */
+static __u8 root_hub_config_des[] =
+{
+ 0x09, /* __u8 bLength; */
+ 0x02, /* __u8 bDescriptorType; Configuration */
+ 0x19, /* __u16 wTotalLength; */
+ 0x00,
+ 0x01, /* __u8 bNumInterfaces; */
+ 0x01, /* __u8 bConfigurationValue; */
+ 0x00, /* __u8 iConfiguration; */
+ 0x40, /* __u8 bmAttributes;
+ Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
+ 0x00, /* __u8 MaxPower; */
+
+ /* interface */
+ 0x09, /* __u8 if_bLength; */
+ 0x04, /* __u8 if_bDescriptorType; Interface */
+ 0x00, /* __u8 if_bInterfaceNumber; */
+ 0x00, /* __u8 if_bAlternateSetting; */
+ 0x01, /* __u8 if_bNumEndpoints; */
+ 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
+ 0x00, /* __u8 if_bInterfaceSubClass; */
+ 0x00, /* __u8 if_bInterfaceProtocol; */
+ 0x00, /* __u8 if_iInterface; */
+
+ /* endpoint */
+ 0x07, /* __u8 ep_bLength; */
+ 0x05, /* __u8 ep_bDescriptorType; Endpoint */
+ 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
+ 0x03, /* __u8 ep_bmAttributes; Interrupt */
+ 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
+ 0x00,
+ 0xff /* __u8 ep_bInterval; 255 ms */
+};
+
+static unsigned char root_hub_str_index0[] =
+{
+ 0x04, /* __u8 bLength; */
+ 0x03, /* __u8 bDescriptorType; String-descriptor */
+ 0x09, /* __u8 lang ID */
+ 0x04, /* __u8 lang ID */
+};
+
+static unsigned char root_hub_str_index1[] =
+{
+ 28, /* __u8 bLength; */
+ 0x03, /* __u8 bDescriptorType; String-descriptor */
+ 'O', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'H', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'C', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'I', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ ' ', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'R', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'o', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'o', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 't', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ ' ', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'H', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'u', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'b', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+};
+
+/* Hub class-specific descriptor is constructed dynamically */
+
+/*-------------------------------------------------------------------------*/
+
+#define OK(x) len = (x); break
+#ifdef DEBUG
+#define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);}
+#define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);}
+#else
+#define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status)
+#define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1])
+#endif
+#define RD_RH_STAT roothub_status(&gohci)
+#define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1)
+
+/* request to virtual root hub */
+
+int rh_check_port_status(ohci_t *controller)
+{
+ __u32 temp, ndp, i;
+ int res;
+
+ res = -1;
+ temp = roothub_a (controller);
+ ndp = (temp & RH_A_NDP);
+#ifdef CONFIG_AT91C_PQFP_UHPBUG
+ ndp = (ndp == 2) ? 1:0;
+#endif
+ for (i = 0; i < ndp; i++) {
+ temp = roothub_portstatus (controller, i);
+ /* check for a device disconnect */
+ if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
+ (RH_PS_PESC | RH_PS_CSC)) &&
+ ((temp & RH_PS_CCS) == 0)) {
+ res = i;
+ break;
+ }
+ }
+ return res;
+}
+
+static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
+ void *buffer, int transfer_len, struct devrequest *cmd)
+{
+ void * data = buffer;
+ int leni = transfer_len;
+ int len = 0;
+ int stat = 0;
+ __u32 datab[4];
+ __u8 *data_buf = (__u8 *)datab;
+ __u16 bmRType_bReq;
+ __u16 wValue;
+ __u16 wIndex;
+ __u16 wLength;
+
+#ifdef DEBUG
+pkt_print(NULL, dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
+#else
+ wait_ms(1);
+#endif
+ if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {
+ info("Root-Hub submit IRQ: NOT implemented");
+ return 0;
+ }
+
+ bmRType_bReq = cmd->requesttype | (cmd->request << 8);
+ wValue = cpu_to_le16 (cmd->value);
+ wIndex = cpu_to_le16 (cmd->index);
+ wLength = cpu_to_le16 (cmd->length);
+
+ info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
+ dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
+
+ switch (bmRType_bReq) {
+ /* Request Destination:
+ without flags: Device,
+ RH_INTERFACE: interface,
+ RH_ENDPOINT: endpoint,
+ RH_CLASS means HUB here,
+ RH_OTHER | RH_CLASS almost ever means HUB_PORT here
+ */
+
+ case RH_GET_STATUS:
+ *(__u16 *) data_buf = cpu_to_le16 (1); OK (2);
+ case RH_GET_STATUS | RH_INTERFACE:
+ *(__u16 *) data_buf = cpu_to_le16 (0); OK (2);
+ case RH_GET_STATUS | RH_ENDPOINT:
+ *(__u16 *) data_buf = cpu_to_le16 (0); OK (2);
+ case RH_GET_STATUS | RH_CLASS:
+ *(__u32 *) data_buf = cpu_to_le32 (
+ RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
+ OK (4);
+ case RH_GET_STATUS | RH_OTHER | RH_CLASS:
+ *(__u32 *) data_buf = cpu_to_le32 (RD_RH_PORTSTAT); OK (4);
+
+ case RH_CLEAR_FEATURE | RH_ENDPOINT:
+ switch (wValue) {
+ case (RH_ENDPOINT_STALL): OK (0);
+ }
+ break;
+
+ case RH_CLEAR_FEATURE | RH_CLASS:
+ switch (wValue) {
+ case RH_C_HUB_LOCAL_POWER:
+ OK(0);
+ case (RH_C_HUB_OVER_CURRENT):
+ WR_RH_STAT(RH_HS_OCIC); OK (0);
+ }
+ break;
+
+ case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
+ switch (wValue) {
+ case (RH_PORT_ENABLE):
+ WR_RH_PORTSTAT (RH_PS_CCS ); OK (0);
+ case (RH_PORT_SUSPEND):
+ WR_RH_PORTSTAT (RH_PS_POCI); OK (0);
+ case (RH_PORT_POWER):
+ WR_RH_PORTSTAT (RH_PS_LSDA); OK (0);
+ case (RH_C_PORT_CONNECTION):
+ WR_RH_PORTSTAT (RH_PS_CSC ); OK (0);
+ case (RH_C_PORT_ENABLE):
+ WR_RH_PORTSTAT (RH_PS_PESC); OK (0);
+ case (RH_C_PORT_SUSPEND):
+ WR_RH_PORTSTAT (RH_PS_PSSC); OK (0);
+ case (RH_C_PORT_OVER_CURRENT):
+ WR_RH_PORTSTAT (RH_PS_OCIC); OK (0);
+ case (RH_C_PORT_RESET):
+ WR_RH_PORTSTAT (RH_PS_PRSC); OK (0);
+ }
+ break;
+
+ case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
+ switch (wValue) {
+ case (RH_PORT_SUSPEND):
+ WR_RH_PORTSTAT (RH_PS_PSS ); OK (0);
+ case (RH_PORT_RESET): /* BUG IN HUP CODE *********/
+ if (RD_RH_PORTSTAT & RH_PS_CCS)
+ WR_RH_PORTSTAT (RH_PS_PRS);
+ OK (0);
+ case (RH_PORT_POWER):
+ WR_RH_PORTSTAT (RH_PS_PPS );
+ wait_ms(100);
+ OK (0);
+ case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/
+ if (RD_RH_PORTSTAT & RH_PS_CCS)
+ WR_RH_PORTSTAT (RH_PS_PES );
+ OK (0);
+ }
+ break;
+
+ case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0);
+
+ case RH_GET_DESCRIPTOR:
+ switch ((wValue & 0xff00) >> 8) {
+ case (0x01): /* device descriptor */
+ len = min_t(unsigned int,
+ leni,
+ min_t(unsigned int,
+ sizeof (root_hub_dev_des),
+ wLength));
+ data_buf = root_hub_dev_des; OK(len);
+ case (0x02): /* configuration descriptor */
+ len = min_t(unsigned int,
+ leni,
+ min_t(unsigned int,
+ sizeof (root_hub_config_des),
+ wLength));
+ data_buf = root_hub_config_des; OK(len);
+ case (0x03): /* string descriptors */
+ if(wValue==0x0300) {
+ len = min_t(unsigned int,
+ leni,
+ min_t(unsigned int,
+ sizeof (root_hub_str_index0),
+ wLength));
+ data_buf = root_hub_str_index0;
+ OK(len);
+ }
+ if(wValue==0x0301) {
+ len = min_t(unsigned int,
+ leni,
+ min_t(unsigned int,
+ sizeof (root_hub_str_index1),
+ wLength));
+ data_buf = root_hub_str_index1;
+ OK(len);
+ }
+ default:
+ stat = USB_ST_STALLED;
+ }
+ break;
+
+ case RH_GET_DESCRIPTOR | RH_CLASS:
+ {
+ __u32 temp = roothub_a (&gohci);
+
+ data_buf [0] = 9; /* min length; */
+ data_buf [1] = 0x29;
+ data_buf [2] = temp & RH_A_NDP;
+#ifdef CONFIG_AT91C_PQFP_UHPBUG
+ data_buf [2] = (data_buf [2] == 2) ? 1:0;
+#endif
+ data_buf [3] = 0;
+ if (temp & RH_A_PSM) /* per-port power switching? */
+ data_buf [3] |= 0x1;
+ if (temp & RH_A_NOCP) /* no overcurrent reporting? */
+ data_buf [3] |= 0x10;
+ else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */
+ data_buf [3] |= 0x8;
+
+ /* corresponds to data_buf[4-7] */
+ datab [1] = 0;
+ data_buf [5] = (temp & RH_A_POTPGT) >> 24;
+ temp = roothub_b (&gohci);
+ data_buf [7] = temp & RH_B_DR;
+ if (data_buf [2] < 7) {
+ data_buf [8] = 0xff;
+ } else {
+ data_buf [0] += 2;
+ data_buf [8] = (temp & RH_B_DR) >> 8;
+ data_buf [10] = data_buf [9] = 0xff;
+ }
+
+ len = min_t(unsigned int, leni,
+ min_t(unsigned int, data_buf [0], wLength));
+ OK (len);
+ }
+
+ case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1);
+
+ case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0);
+
+ default:
+ dbg ("unsupported root hub command");
+ stat = USB_ST_STALLED;
+ }
+
+#ifdef DEBUG
+ ohci_dump_roothub (&gohci, 1);
+#else
+ wait_ms(1);
+#endif
+
+ len = min_t(int, len, leni);
+ if (data != data_buf)
+ memcpy (data, data_buf, len);
+ dev->act_len = len;
+ dev->status = stat;
+
+#ifdef DEBUG
+ pkt_print(NULL, dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/);
+#else
+ wait_ms(1);
+#endif
+
+ return stat;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* common code for handling submit messages - used for all but root hub */
+/* accesses. */
+int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+ int transfer_len, struct devrequest *setup, int interval)
+{
+ int stat = 0;
+ int maxsize = usb_maxpacket(dev, pipe);
+ int timeout;
+ urb_priv_t *urb;
+
+ urb = malloc(sizeof(urb_priv_t));
+ memset(urb, 0, sizeof(urb_priv_t));
+
+ urb->dev = dev;
+ urb->pipe = pipe;
+ urb->transfer_buffer = buffer;
+ urb->transfer_buffer_length = transfer_len;
+ urb->interval = interval;
+
+ /* device pulled? Shortcut the action. */
+ if (devgone == dev) {
+ dev->status = USB_ST_CRC_ERR;
+ return 0;
+ }
+
+#ifdef DEBUG
+ urb->actual_length = 0;
+ pkt_print(urb, dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
+#else
+ wait_ms(1);
+#endif
+ if (!maxsize) {
+ err("submit_common_message: pipesize for pipe %lx is zero",
+ pipe);
+ return -1;
+ }
+
+ if (sohci_submit_job(urb, setup) < 0) {
+ err("sohci_submit_job failed");
+ return -1;
+ }
+
+#if 0
+ wait_ms(10);
+ /* ohci_dump_status(&gohci); */
+#endif
+
+ /* allow more time for a BULK device to react - some are slow */
+#define BULK_TO 5000 /* timeout in milliseconds */
+ if (usb_pipetype (pipe) == PIPE_BULK)
+ timeout = BULK_TO;
+ else
+ timeout = 100;
+
+ /* wait for it to complete */
+ for (;;) {
+ /* check whether the controller is done */
+ stat = hc_interrupt();
+ if (stat < 0) {
+ stat = USB_ST_CRC_ERR;
+ break;
+ }
+
+ /* NOTE: since we are not interrupt driven in U-Boot and always
+ * handle only one URB at a time, we cannot assume the
+ * transaction finished on the first successful return from
+ * hc_interrupt().. unless the flag for current URB is set,
+ * meaning that all TD's to/from device got actually
+ * transferred and processed. If the current URB is not
+ * finished we need to re-iterate this loop so as
+ * hc_interrupt() gets called again as there needs to be some
+ * more TD's to process still */
+ if ((stat >= 0) && (stat != 0xff) && (urb->finished)) {
+ /* 0xff is returned for an SF-interrupt */
+ break;
+ }
+
+ if (--timeout) {
+ wait_ms(1);
+ if (!urb->finished)
+ dbg("\%");
+
+ } else {
+ err("CTL:TIMEOUT ");
+ dbg("submit_common_msg: TO status %x\n", stat);
+ urb->finished = 1;
+ stat = USB_ST_CRC_ERR;
+ break;
+ }
+ }
+
+ dev->status = stat;
+ dev->act_len = transfer_len;
+
+#ifdef DEBUG
+ pkt_print(urb, dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe));
+#else
+ wait_ms(1);
+#endif
+
+ /* free TDs in urb_priv */
+ if (usb_pipetype (pipe) != PIPE_INTERRUPT)
+ urb_free_priv (urb);
+ return 0;
+}
+
+/* submit routines called from usb.c */
+int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+ int transfer_len)
+{
+ info("submit_bulk_msg");
+ return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);
+}
+
+int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+ int transfer_len, struct devrequest *setup)
+{
+ int maxsize = usb_maxpacket(dev, pipe);
+
+ info("submit_control_msg");
+#ifdef DEBUG
+ pkt_print(NULL, dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
+#else
+ wait_ms(1);
+#endif
+ if (!maxsize) {
+ err("submit_control_message: pipesize for pipe %lx is zero",
+ pipe);
+ return -1;
+ }
+ if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {
+ gohci.rh.dev = dev;
+ /* root hub - redirect */
+ return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,
+ setup);
+ }
+
+ return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);
+}
+
+int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+ int transfer_len, int interval)
+{
+ info("submit_int_msg");
+ return submit_common_msg(dev, pipe, buffer, transfer_len, NULL,
+ interval);
+}
+
+/*-------------------------------------------------------------------------*
+ * HC functions
+ *-------------------------------------------------------------------------*/
+
+/* reset the HC and BUS */
+
+static int hc_reset (ohci_t *ohci)
+{
+ int timeout = 30;
+ int smm_timeout = 50; /* 0,5 sec */
+
+ dbg("%s\n", __FUNCTION__);
+
+ if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */
+ writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */
+ info("USB HC TakeOver from SMM");
+ while (readl (&ohci->regs->control) & OHCI_CTRL_IR) {
+ wait_ms (10);
+ if (--smm_timeout == 0) {
+ err("USB HC TakeOver failed!");
+ return -1;
+ }
+ }
+ }
+
+ /* Disable HC interrupts */
+ writel (OHCI_INTR_MIE, &ohci->regs->intrdisable);
+
+ dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;\n",
+ ohci->slot_name,
+ readl(&ohci->regs->control));
+
+ /* Reset USB (needed by some controllers) */
+ ohci->hc_control = 0;
+ writel (ohci->hc_control, &ohci->regs->control);
+
+ /* HC Reset requires max 10 us delay */
+ writel (OHCI_HCR, &ohci->regs->cmdstatus);
+ while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
+ if (--timeout == 0) {
+ err("USB HC reset timed out!");
+ return -1;
+ }
+ udelay (1);
+ }
+ return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* Start an OHCI controller, set the BUS operational
+ * enable interrupts
+ * connect the virtual root hub */
+
+static int hc_start (ohci_t * ohci)
+{
+ __u32 mask;
+ unsigned int fminterval;
+
+ ohci->disabled = 1;
+
+ /* Tell the controller where the control and bulk lists are
+ * The lists are empty now. */
+
+ writel (0, &ohci->regs->ed_controlhead);
+ writel (0, &ohci->regs->ed_bulkhead);
+
+ writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */
+
+ fminterval = 0x2edf;
+ writel ((fminterval * 9) / 10, &ohci->regs->periodicstart);
+ fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
+ writel (fminterval, &ohci->regs->fminterval);
+ writel (0x628, &ohci->regs->lsthresh);
+
+ /* start controller operations */
+ ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
+ ohci->disabled = 0;
+ writel (ohci->hc_control, &ohci->regs->control);
+
+ /* disable all interrupts */
+ mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
+ OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
+ OHCI_INTR_OC | OHCI_INTR_MIE);
+ writel (mask, &ohci->regs->intrdisable);
+ /* clear all interrupts */
+ mask &= ~OHCI_INTR_MIE;
+ writel (mask, &ohci->regs->intrstatus);
+ /* Choose the interrupts we care about now - but w/o MIE */
+ mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
+ writel (mask, &ohci->regs->intrenable);
+
+#ifdef OHCI_USE_NPS
+ /* required for AMD-756 and some Mac platforms */
+ writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM,
+ &ohci->regs->roothub.a);
+ writel (RH_HS_LPSC, &ohci->regs->roothub.status);
+#endif /* OHCI_USE_NPS */
+
+#define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);})
+ /* POTPGT delay is bits 24-31, in 2 ms units. */
+ mdelay ((roothub_a (ohci) >> 23) & 0x1fe);
+
+ /* connect the virtual root hub */
+ ohci->rh.devnum = 0;
+
+ return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* Poll USB interrupt. */
+void usb_event_poll(void)
+{
+ hc_interrupt();
+}
+
+/* an interrupt happens */
+
+static int hc_interrupt (void)
+{
+ ohci_t *ohci = &gohci;
+ struct ohci_regs *regs = ohci->regs;
+ int ints;
+ int stat = -1;
+
+ if ((ohci->hcca->done_head != 0) &&
+ !(m32_swap (ohci->hcca->done_head) & 0x01)) {
+ ints = OHCI_INTR_WDH;
+ } else if ((ints = readl (&regs->intrstatus)) == ~(u32)0) {
+ ohci->disabled++;
+ err ("%s device removed!", ohci->slot_name);
+ return -1;
+ } else if ((ints &= readl (&regs->intrenable)) == 0) {
+ dbg("hc_interrupt: returning..\n");
+ return 0xff;
+ }
+
+ /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */
+
+ if (ints & OHCI_INTR_RHSC) {
+ got_rhsc = 1;
+ stat = 0xff;
+ }
+
+ if (ints & OHCI_INTR_UE) {
+ ohci->disabled++;
+ err ("OHCI Unrecoverable Error, controller usb-%s disabled",
+ ohci->slot_name);
+ /* e.g. due to PCI Master/Target Abort */
+
+#ifdef DEBUG
+ ohci_dump (ohci, 1);
+#else
+ wait_ms(1);
+#endif
+ /* FIXME: be optimistic, hope that bug won't repeat often. */
+ /* Make some non-interrupt context restart the controller. */
+ /* Count and limit the retries though; either hardware or */
+ /* software errors can go forever... */
+ hc_reset (ohci);
+ return -1;
+ }
+
+ if (ints & OHCI_INTR_WDH) {
+ wait_ms(1);
+ writel (OHCI_INTR_WDH, &regs->intrdisable);
+ (void)readl (&regs->intrdisable); /* flush */
+ stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci));
+ writel (OHCI_INTR_WDH, &regs->intrenable);
+ (void)readl (&regs->intrdisable); /* flush */
+ }
+
+ if (ints & OHCI_INTR_SO) {
+ dbg("USB Schedule overrun\n");
+ writel (OHCI_INTR_SO, &regs->intrenable);
+ stat = -1;
+ }
+
+ /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */
+ if (ints & OHCI_INTR_SF) {
+ unsigned int frame = m16_swap (ohci->hcca->frame_no) & 1;
+ wait_ms(1);
+ writel (OHCI_INTR_SF, &regs->intrdisable);
+ if (ohci->ed_rm_list[frame] != NULL)
+ writel (OHCI_INTR_SF, &regs->intrenable);
+ stat = 0xff;
+ }
+
+ writel (ints, &regs->intrstatus);
+ return stat;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/*-------------------------------------------------------------------------*/
+
+/* De-allocate all resources.. */
+
+static void hc_release_ohci (ohci_t *ohci)
+{
+ dbg ("USB HC release ohci usb-%s", ohci->slot_name);
+
+ if (!ohci->disabled)
+ hc_reset (ohci);
+}
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * low level initalisation routine, called from usb.c
+ */
+static char ohci_inited = 0;
+
+int usb_lowlevel_init(void)
+{
+#ifdef CONFIG_PCI_OHCI
+ pci_dev_t pdev;
+#endif
+
+#ifdef CFG_USB_OHCI_CPU_INIT
+ /* cpu dependant init */
+ if(usb_cpu_init())
+ return -1;
+#endif
+
+#ifdef CFG_USB_OHCI_BOARD_INIT
+ /* board dependant init */
+ if(usb_board_init())
+ return -1;
+#endif
+ memset (&gohci, 0, sizeof (ohci_t));
+
+ /* align the storage */
+ if ((__u32)&ghcca[0] & 0xff) {
+ err("HCCA not aligned!!");
+ return -1;
+ }
+ phcca = &ghcca[0];
+ info("aligned ghcca %p", phcca);
+ memset(&ohci_dev, 0, sizeof(struct ohci_device));
+ if ((__u32)&ohci_dev.ed[0] & 0x7) {
+ err("EDs not aligned!!");
+ return -1;
+ }
+ memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1));
+ if ((__u32)gtd & 0x7) {
+ err("TDs not aligned!!");
+ return -1;
+ }
+ ptd = gtd;
+ gohci.hcca = phcca;
+ memset (phcca, 0, sizeof (struct ohci_hcca));
+
+ gohci.disabled = 1;
+ gohci.sleeping = 0;
+ gohci.irq = -1;
+#ifdef CONFIG_PCI_OHCI
+ pdev = pci_find_devices(ohci_pci_ids, 0);
+
+ if (pdev != -1) {
+ u16 vid, did;
+ u32 base;
+ pci_read_config_word(pdev, PCI_VENDOR_ID, &vid);
+ pci_read_config_word(pdev, PCI_DEVICE_ID, &did);
+ printf("OHCI pci controller (%04x, %04x) found @(%d:%d:%d)\n",
+ vid, did, (pdev >> 16) & 0xff,
+ (pdev >> 11) & 0x1f, (pdev >> 8) & 0x7);
+ pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base);
+ printf("OHCI regs address 0x%08x\n", base);
+ gohci.regs = (struct ohci_regs *)base;
+ } else
+ return -1;
+#else
+ gohci.regs = (struct ohci_regs *)CFG_USB_OHCI_REGS_BASE;
+#endif
+
+ gohci.flags = 0;
+ gohci.slot_name = CFG_USB_OHCI_SLOT_NAME;
+
+ if (hc_reset (&gohci) < 0) {
+ hc_release_ohci (&gohci);
+ err ("can't reset usb-%s", gohci.slot_name);
+#ifdef CFG_USB_OHCI_BOARD_INIT
+ /* board dependant cleanup */
+ usb_board_init_fail();
+#endif
+
+#ifdef CFG_USB_OHCI_CPU_INIT
+ /* cpu dependant cleanup */
+ usb_cpu_init_fail();
+#endif
+ return -1;
+ }
+
+ /* FIXME this is a second HC reset; why?? */
+ /* writel(gohci.hc_control = OHCI_USB_RESET, &gohci.regs->control);
+ wait_ms(10); */
+ if (hc_start (&gohci) < 0) {
+ err ("can't start usb-%s", gohci.slot_name);
+ hc_release_ohci (&gohci);
+ /* Initialization failed */
+#ifdef CFG_USB_OHCI_BOARD_INIT
+ /* board dependant cleanup */
+ usb_board_stop();
+#endif
+
+#ifdef CFG_USB_OHCI_CPU_INIT
+ /* cpu dependant cleanup */
+ usb_cpu_stop();
+#endif
+ return -1;
+ }
+
+#ifdef DEBUG
+ ohci_dump (&gohci, 1);
+#else
+ wait_ms(1);
+#endif
+ ohci_inited = 1;
+ return 0;
+}
+
+int usb_lowlevel_stop(void)
+{
+ /* this gets called really early - before the controller has */
+ /* even been initialized! */
+ if (!ohci_inited)
+ return 0;
+ /* TODO release any interrupts, etc. */
+ /* call hc_release_ohci() here ? */
+ hc_reset (&gohci);
+
+#ifdef CFG_USB_OHCI_BOARD_INIT
+ /* board dependant cleanup */
+ if(usb_board_stop())
+ return -1;
+#endif
+
+#ifdef CFG_USB_OHCI_CPU_INIT
+ /* cpu dependant cleanup */
+ if(usb_cpu_stop())
+ return -1;
+#endif
+
+ return 0;
+}
+#endif /* CONFIG_USB_OHCI_NEW */
diff --git a/drivers/usb_ohci.h b/drivers/usb_ohci.h
new file mode 100644
index 0000000..380cb4c
--- /dev/null
+++ b/drivers/usb_ohci.h
@@ -0,0 +1,445 @@
+/*
+ * URB OHCI HCD (Host Controller Driver) for USB.
+ *
+ * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
+ * (C) Copyright 2000-2001 David Brownell <dbrownell@users.sourceforge.net>
+ *
+ * usb-ohci.h
+ */
+
+/* functions for doing board or CPU specific setup/cleanup */
+extern int usb_board_init(void);
+extern int usb_board_stop(void);
+extern int usb_board_init_fail(void);
+
+extern int usb_cpu_init(void);
+extern int usb_cpu_stop(void);
+extern int usb_cpu_init_fail(void);
+
+
+static int cc_to_error[16] = {
+
+/* mapping of the OHCI CC status to error codes */
+ /* No Error */ 0,
+ /* CRC Error */ USB_ST_CRC_ERR,
+ /* Bit Stuff */ USB_ST_BIT_ERR,
+ /* Data Togg */ USB_ST_CRC_ERR,
+ /* Stall */ USB_ST_STALLED,
+ /* DevNotResp */ -1,
+ /* PIDCheck */ USB_ST_BIT_ERR,
+ /* UnExpPID */ USB_ST_BIT_ERR,
+ /* DataOver */ USB_ST_BUF_ERR,
+ /* DataUnder */ USB_ST_BUF_ERR,
+ /* reservd */ -1,
+ /* reservd */ -1,
+ /* BufferOver */ USB_ST_BUF_ERR,
+ /* BuffUnder */ USB_ST_BUF_ERR,
+ /* Not Access */ -1,
+ /* Not Access */ -1
+};
+
+/* ED States */
+
+#define ED_NEW 0x00
+#define ED_UNLINK 0x01
+#define ED_OPER 0x02
+#define ED_DEL 0x04
+#define ED_URB_DEL 0x08
+
+/* usb_ohci_ed */
+struct ed {
+ __u32 hwINFO;
+ __u32 hwTailP;
+ __u32 hwHeadP;
+ __u32 hwNextED;
+
+ struct ed *ed_prev;
+ __u8 int_period;
+ __u8 int_branch;
+ __u8 int_load;
+ __u8 int_interval;
+ __u8 state;
+ __u8 type;
+ __u16 last_iso;
+ struct ed *ed_rm_list;
+
+ struct usb_device *usb_dev;
+ void *purb;
+ __u32 unused[2];
+} __attribute((aligned(16)));
+typedef struct ed ed_t;
+
+
+/* TD info field */
+#define TD_CC 0xf0000000
+#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f)
+#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)
+#define TD_EC 0x0C000000
+#define TD_T 0x03000000
+#define TD_T_DATA0 0x02000000
+#define TD_T_DATA1 0x03000000
+#define TD_T_TOGGLE 0x00000000
+#define TD_R 0x00040000
+#define TD_DI 0x00E00000
+#define TD_DI_SET(X) (((X) & 0x07)<< 21)
+#define TD_DP 0x00180000
+#define TD_DP_SETUP 0x00000000
+#define TD_DP_IN 0x00100000
+#define TD_DP_OUT 0x00080000
+
+#define TD_ISO 0x00010000
+#define TD_DEL 0x00020000
+
+/* CC Codes */
+#define TD_CC_NOERROR 0x00
+#define TD_CC_CRC 0x01
+#define TD_CC_BITSTUFFING 0x02
+#define TD_CC_DATATOGGLEM 0x03
+#define TD_CC_STALL 0x04
+#define TD_DEVNOTRESP 0x05
+#define TD_PIDCHECKFAIL 0x06
+#define TD_UNEXPECTEDPID 0x07
+#define TD_DATAOVERRUN 0x08
+#define TD_DATAUNDERRUN 0x09
+#define TD_BUFFEROVERRUN 0x0C
+#define TD_BUFFERUNDERRUN 0x0D
+#define TD_NOTACCESSED 0x0F
+
+
+#define MAXPSW 1
+
+struct td {
+ __u32 hwINFO;
+ __u32 hwCBP; /* Current Buffer Pointer */
+ __u32 hwNextTD; /* Next TD Pointer */
+ __u32 hwBE; /* Memory Buffer End Pointer */
+
+/* #ifndef CONFIG_MPC5200 /\* this seems wrong *\/ */
+ __u16 hwPSW[MAXPSW];
+/* #endif */
+ __u8 unused;
+ __u8 index;
+ struct ed *ed;
+ struct td *next_dl_td;
+ struct usb_device *usb_dev;
+ int transfer_len;
+ __u32 data;
+
+ __u32 unused2[2];
+} __attribute((aligned(32)));
+typedef struct td td_t;
+
+#define OHCI_ED_SKIP (1 << 14)
+
+/*
+ * The HCCA (Host Controller Communications Area) is a 256 byte
+ * structure defined in the OHCI spec. that the host controller is
+ * told the base address of. It must be 256-byte aligned.
+ */
+
+#define NUM_INTS 32 /* part of the OHCI standard */
+struct ohci_hcca {
+ __u32 int_table[NUM_INTS]; /* Interrupt ED table */
+#if defined(CONFIG_MPC5200)
+ __u16 pad1; /* set to 0 on each frame_no change */
+ __u16 frame_no; /* current frame number */
+#else
+ __u16 frame_no; /* current frame number */
+ __u16 pad1; /* set to 0 on each frame_no change */
+#endif
+ __u32 done_head; /* info returned for an interrupt */
+ u8 reserved_for_hc[116];
+} __attribute((aligned(256)));
+
+
+/*
+ * Maximum number of root hub ports.
+ */
+#ifndef CFG_USB_OHCI_MAX_ROOT_PORTS
+# error "CFG_USB_OHCI_MAX_ROOT_PORTS undefined!"
+#endif
+
+/*
+ * This is the structure of the OHCI controller's memory mapped I/O
+ * region. This is Memory Mapped I/O. You must use the readl() and
+ * writel() macros defined in asm/io.h to access these!!
+ */
+struct ohci_regs {
+ /* control and status registers */
+ __u32 revision;
+ __u32 control;
+ __u32 cmdstatus;
+ __u32 intrstatus;
+ __u32 intrenable;
+ __u32 intrdisable;
+ /* memory pointers */
+ __u32 hcca;
+ __u32 ed_periodcurrent;
+ __u32 ed_controlhead;
+ __u32 ed_controlcurrent;
+ __u32 ed_bulkhead;
+ __u32 ed_bulkcurrent;
+ __u32 donehead;
+ /* frame counters */
+ __u32 fminterval;
+ __u32 fmremaining;
+ __u32 fmnumber;
+ __u32 periodicstart;
+ __u32 lsthresh;
+ /* Root hub ports */
+ struct ohci_roothub_regs {
+ __u32 a;
+ __u32 b;
+ __u32 status;
+ __u32 portstatus[CFG_USB_OHCI_MAX_ROOT_PORTS];
+ } roothub;
+} __attribute((aligned(32)));
+
+
+/* OHCI CONTROL AND STATUS REGISTER MASKS */
+
+/*
+ * HcControl (control) register masks
+ */
+#define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */
+#define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */
+#define OHCI_CTRL_IE (1 << 3) /* isochronous enable */
+#define OHCI_CTRL_CLE (1 << 4) /* control list enable */
+#define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */
+#define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */
+#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */
+#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */
+#define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */
+
+/* pre-shifted values for HCFS */
+# define OHCI_USB_RESET (0 << 6)
+# define OHCI_USB_RESUME (1 << 6)
+# define OHCI_USB_OPER (2 << 6)
+# define OHCI_USB_SUSPEND (3 << 6)
+
+/*
+ * HcCommandStatus (cmdstatus) register masks
+ */
+#define OHCI_HCR (1 << 0) /* host controller reset */
+#define OHCI_CLF (1 << 1) /* control list filled */
+#define OHCI_BLF (1 << 2) /* bulk list filled */
+#define OHCI_OCR (1 << 3) /* ownership change request */
+#define OHCI_SOC (3 << 16) /* scheduling overrun count */
+
+/*
+ * masks used with interrupt registers:
+ * HcInterruptStatus (intrstatus)
+ * HcInterruptEnable (intrenable)
+ * HcInterruptDisable (intrdisable)
+ */
+#define OHCI_INTR_SO (1 << 0) /* scheduling overrun */
+#define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */
+#define OHCI_INTR_SF (1 << 2) /* start frame */
+#define OHCI_INTR_RD (1 << 3) /* resume detect */
+#define OHCI_INTR_UE (1 << 4) /* unrecoverable error */
+#define OHCI_INTR_FNO (1 << 5) /* frame number overflow */
+#define OHCI_INTR_RHSC (1 << 6) /* root hub status change */
+#define OHCI_INTR_OC (1 << 30) /* ownership change */
+#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */
+
+
+/* Virtual Root HUB */
+struct virt_root_hub {
+ int devnum; /* Address of Root Hub endpoint */
+ void *dev; /* was urb */
+ void *int_addr;
+ int send;
+ int interval;
+};
+
+/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */
+
+/* destination of request */
+#define RH_INTERFACE 0x01
+#define RH_ENDPOINT 0x02
+#define RH_OTHER 0x03
+
+#define RH_CLASS 0x20
+#define RH_VENDOR 0x40
+
+/* Requests: bRequest << 8 | bmRequestType */
+#define RH_GET_STATUS 0x0080
+#define RH_CLEAR_FEATURE 0x0100
+#define RH_SET_FEATURE 0x0300
+#define RH_SET_ADDRESS 0x0500
+#define RH_GET_DESCRIPTOR 0x0680
+#define RH_SET_DESCRIPTOR 0x0700
+#define RH_GET_CONFIGURATION 0x0880
+#define RH_SET_CONFIGURATION 0x0900
+#define RH_GET_STATE 0x0280
+#define RH_GET_INTERFACE 0x0A80
+#define RH_SET_INTERFACE 0x0B00
+#define RH_SYNC_FRAME 0x0C80
+/* Our Vendor Specific Request */
+#define RH_SET_EP 0x2000
+
+
+/* Hub port features */
+#define RH_PORT_CONNECTION 0x00
+#define RH_PORT_ENABLE 0x01
+#define RH_PORT_SUSPEND 0x02
+#define RH_PORT_OVER_CURRENT 0x03
+#define RH_PORT_RESET 0x04
+#define RH_PORT_POWER 0x08
+#define RH_PORT_LOW_SPEED 0x09
+
+#define RH_C_PORT_CONNECTION 0x10
+#define RH_C_PORT_ENABLE 0x11
+#define RH_C_PORT_SUSPEND 0x12
+#define RH_C_PORT_OVER_CURRENT 0x13
+#define RH_C_PORT_RESET 0x14
+
+/* Hub features */
+#define RH_C_HUB_LOCAL_POWER 0x00
+#define RH_C_HUB_OVER_CURRENT 0x01
+
+#define RH_DEVICE_REMOTE_WAKEUP 0x00
+#define RH_ENDPOINT_STALL 0x01
+
+#define RH_ACK 0x01
+#define RH_REQ_ERR -1
+#define RH_NACK 0x00
+
+
+/* OHCI ROOT HUB REGISTER MASKS */
+
+/* roothub.portstatus [i] bits */
+#define RH_PS_CCS 0x00000001 /* current connect status */
+#define RH_PS_PES 0x00000002 /* port enable status*/
+#define RH_PS_PSS 0x00000004 /* port suspend status */
+#define RH_PS_POCI 0x00000008 /* port over current indicator */
+#define RH_PS_PRS 0x00000010 /* port reset status */
+#define RH_PS_PPS 0x00000100 /* port power status */
+#define RH_PS_LSDA 0x00000200 /* low speed device attached */
+#define RH_PS_CSC 0x00010000 /* connect status change */
+#define RH_PS_PESC 0x00020000 /* port enable status change */
+#define RH_PS_PSSC 0x00040000 /* port suspend status change */
+#define RH_PS_OCIC 0x00080000 /* over current indicator change */
+#define RH_PS_PRSC 0x00100000 /* port reset status change */
+
+/* roothub.status bits */
+#define RH_HS_LPS 0x00000001 /* local power status */
+#define RH_HS_OCI 0x00000002 /* over current indicator */
+#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */
+#define RH_HS_LPSC 0x00010000 /* local power status change */
+#define RH_HS_OCIC 0x00020000 /* over current indicator change */
+#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */
+
+/* roothub.b masks */
+#define RH_B_DR 0x0000ffff /* device removable flags */
+#define RH_B_PPCM 0xffff0000 /* port power control mask */
+
+/* roothub.a masks */
+#define RH_A_NDP (0xff << 0) /* number of downstream ports */
+#define RH_A_PSM (1 << 8) /* power switching mode */
+#define RH_A_NPS (1 << 9) /* no power switching */
+#define RH_A_DT (1 << 10) /* device type (mbz) */
+#define RH_A_OCPM (1 << 11) /* over current protection mode */
+#define RH_A_NOCP (1 << 12) /* no over current protection */
+#define RH_A_POTPGT (0xff << 24) /* power on to power good time */
+
+/* urb */
+#define N_URB_TD 48
+typedef struct
+{
+ ed_t *ed;
+ __u16 length; /* number of tds associated with this request */
+ __u16 td_cnt; /* number of tds already serviced */
+ struct usb_device *dev;
+ int state;
+ unsigned long pipe;
+ void *transfer_buffer;
+ int transfer_buffer_length;
+ int interval;
+ int actual_length;
+ int finished;
+ td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */
+} urb_priv_t;
+#define URB_DEL 1
+
+/*
+ * This is the full ohci controller description
+ *
+ * Note how the "proper" USB information is just
+ * a subset of what the full implementation needs. (Linus)
+ */
+
+
+typedef struct ohci {
+ struct ohci_hcca *hcca; /* hcca */
+ /*dma_addr_t hcca_dma;*/
+
+ int irq;
+ int disabled; /* e.g. got a UE, we're hung */
+ int sleeping;
+ unsigned long flags; /* for HC bugs */
+
+ struct ohci_regs *regs; /* OHCI controller's memory */
+
+ int ohci_int_load[32]; /* load of the 32 Interrupt Chains (for load balancing)*/
+ ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */
+ ed_t *ed_bulktail; /* last endpoint of bulk list */
+ ed_t *ed_controltail; /* last endpoint of control list */
+ int intrstatus;
+ __u32 hc_control; /* copy of the hc control reg */
+ struct usb_device *dev[32];
+ struct virt_root_hub rh;
+
+ const char *slot_name;
+} ohci_t;
+
+#define NUM_EDS 8 /* num of preallocated endpoint descriptors */
+
+struct ohci_device {
+ ed_t ed[NUM_EDS];
+ int ed_cnt;
+};
+
+/* hcd */
+/* endpoint */
+static int ep_link(ohci_t * ohci, ed_t * ed);
+static int ep_unlink(ohci_t * ohci, ed_t * ed);
+static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned long pipe,
+ int interval, int load);
+
+/*-------------------------------------------------------------------------*/
+
+/* we need more TDs than EDs */
+#define NUM_TD 64
+
+/* +1 so we can align the storage */
+td_t gtd[NUM_TD+1];
+/* pointers to aligned storage */
+td_t *ptd;
+
+/* TDs ... */
+static inline struct td *
+td_alloc (struct usb_device *usb_dev)
+{
+ int i;
+ struct td *td;
+
+ td = NULL;
+ for (i = 0; i < NUM_TD; i++)
+ {
+ if (ptd[i].usb_dev == NULL)
+ {
+ td = &ptd[i];
+ td->usb_dev = usb_dev;
+ break;
+ }
+ }
+
+ return td;
+}
+
+static inline void
+ed_free (struct ed *ed)
+{
+ ed->usb_dev = NULL;
+}
diff --git a/drivers/usbdcore_ep0.c b/drivers/usbdcore_ep0.c
index 260befe..1e44f32 100644
--- a/drivers/usbdcore_ep0.c
+++ b/drivers/usbdcore_ep0.c
@@ -2,6 +2,9 @@
* (C) Copyright 2003
* Gerry Hamel, geh@ti.com, Texas Instruments
*
+ * (C) Copyright 2006
+ * Bryan O'Donoghue, deckard@CodeHermit.ie
+ *
* Based on
* linux/drivers/usbd/ep0.c
*
@@ -39,11 +42,17 @@
* function driver. This may need to change.
*
* XXX
+ *
+ * As alluded to above, a simple callback cdc_recv_setup has been implemented
+ * in the usb_device data structure to facilicate passing
+ * Common Device Class packets to a function driver.
+ *
+ * XXX
*/
#include <common.h>
-#if defined(CONFIG_OMAP1510) && defined(CONFIG_USB_DEVICE)
+#if defined(CONFIG_USB_DEVICE)
#include "usbdcore.h"
#if 0
@@ -69,7 +78,7 @@ static int ep0_get_status (struct usb_device_instance *device,
char *cp;
urb->actual_length = 2;
- cp = urb->buffer;
+ cp = (char*)urb->buffer;
cp[0] = cp[1] = 0;
switch (requesttype) {
@@ -115,7 +124,7 @@ static int ep0_get_one (struct usb_device_instance *device, struct urb *urb,
*
* Copy configuration data to urb transfer buffer if there is room for it.
*/
-static void copy_config (struct urb *urb, void *data, int max_length,
+void copy_config (struct urb *urb, void *data, int max_length,
int max_buf)
{
int available;
@@ -128,10 +137,7 @@ static void copy_config (struct urb *urb, void *data, int max_length,
dbg_ep0 (1, "data is NULL");
return;
}
- if (!(length = *(unsigned char *) data)) {
- dbg_ep0 (1, "length is zero");
- return;
- }
+ length = max_length;
if (length > max_length) {
dbg_ep0 (1, "length: %d >= max_length: %d", length,
@@ -192,7 +198,7 @@ static int ep0_get_descriptor (struct usb_device_instance *device,
/* setup tx urb */
urb->actual_length = 0;
- cp = urb->buffer;
+ cp = (char*)urb->buffer;
dbg_ep0 (2, "%s", USBD_DEVICE_DESCRIPTORS (descriptor_type));
@@ -200,7 +206,6 @@ static int ep0_get_descriptor (struct usb_device_instance *device,
case USB_DESCRIPTOR_TYPE_DEVICE:
{
struct usb_device_descriptor *device_descriptor;
-
if (!
(device_descriptor =
usbd_device_device_descriptor (device, port))) {
@@ -214,20 +219,16 @@ static int ep0_get_descriptor (struct usb_device_instance *device,
/* correct the correct control endpoint 0 max packet size into the descriptor */
device_descriptor =
(struct usb_device_descriptor *) urb->buffer;
- device_descriptor->bMaxPacketSize0 =
- urb->device->bus->maxpacketsize;
}
- /*dbg_ep0(3, "copied device configuration, actual_length: %x", urb->actual_length); */
+ dbg_ep0(3, "copied device configuration, actual_length: 0x%x", urb->actual_length);
break;
case USB_DESCRIPTOR_TYPE_CONFIGURATION:
{
- int bNumInterface;
struct usb_configuration_descriptor
*configuration_descriptor;
struct usb_device_descriptor *device_descriptor;
-
if (!
(device_descriptor =
usbd_device_device_descriptor (device, port))) {
@@ -251,130 +252,35 @@ static int ep0_get_descriptor (struct usb_device_instance *device,
index);
return -1;
}
+ dbg_ep0(0, "attempt to copy %d bytes to urb\n",cpu_to_le16(configuration_descriptor->wTotalLength));
copy_config (urb, configuration_descriptor,
- sizeof (struct
- usb_configuration_descriptor),
- max);
-
-
- /* iterate across interfaces for specified configuration */
- dbg_ep0 (0, "bNumInterfaces: %d",
- configuration_descriptor->bNumInterfaces);
- for (bNumInterface = 0;
- bNumInterface <
- configuration_descriptor->bNumInterfaces;
- bNumInterface++) {
- int bAlternateSetting;
- struct usb_interface_instance
- *interface_instance;
-
- dbg_ep0 (3, "[%d] bNumInterfaces: %d",
- bNumInterface,
- configuration_descriptor->bNumInterfaces);
-
- if (! (interface_instance = usbd_device_interface_instance (device,
- port, index, bNumInterface)))
- {
- dbg_ep0 (3, "[%d] interface_instance NULL",
- bNumInterface);
- return -1;
- }
- /* iterate across interface alternates */
- for (bAlternateSetting = 0;
- bAlternateSetting < interface_instance->alternates;
- bAlternateSetting++) {
- /*int class; */
- int bNumEndpoint;
- struct usb_interface_descriptor *interface_descriptor;
-
- struct usb_alternate_instance *alternate_instance;
-
- dbg_ep0 (3, "[%d:%d] alternates: %d",
- bNumInterface,
- bAlternateSetting,
- interface_instance->alternates);
-
- if (! (alternate_instance = usbd_device_alternate_instance (device, port, index, bNumInterface, bAlternateSetting))) {
- dbg_ep0 (3, "[%d] alternate_instance NULL",
- bNumInterface);
- return -1;
- }
- /* copy descriptor for this interface */
- copy_config (urb, alternate_instance->interface_descriptor,
- sizeof (struct usb_interface_descriptor),
- max);
-
- /*dbg_ep0(3, "[%d:%d] classes: %d endpoints: %d", bNumInterface, bAlternateSetting, */
- /* alternate_instance->classes, alternate_instance->endpoints); */
-
- /* iterate across classes for this alternate interface */
-#if 0
- for (class = 0;
- class < alternate_instance->classes;
- class++) {
- struct usb_class_descriptor *class_descriptor;
- /*dbg_ep0(3, "[%d:%d:%d] classes: %d", bNumInterface, bAlternateSetting, */
- /* class, alternate_instance->classes); */
- if (!(class_descriptor = usbd_device_class_descriptor_index (device, port, index, bNumInterface, bAlternateSetting, class))) {
- dbg_ep0 (3, "[%d] class NULL",
- class);
- return -1;
- }
- /* copy descriptor for this class */
- copy_config (urb, class_descriptor,
- sizeof (struct usb_class_descriptor),
- max);
- }
-#endif
-
- /* iterate across endpoints for this alternate interface */
- interface_descriptor = alternate_instance->interface_descriptor;
- for (bNumEndpoint = 0;
- bNumEndpoint < alternate_instance->endpoints;
- bNumEndpoint++) {
- struct usb_endpoint_descriptor *endpoint_descriptor;
- dbg_ep0 (3, "[%d:%d:%d] endpoint: %d",
- bNumInterface,
- bAlternateSetting,
- bNumEndpoint,
- interface_descriptor->
- bNumEndpoints);
- if (!(endpoint_descriptor = usbd_device_endpoint_descriptor_index (device, port, index, bNumInterface, bAlternateSetting, bNumEndpoint))) {
- dbg_ep0 (3, "[%d] endpoint NULL",
- bNumEndpoint);
- return -1;
- }
- /* copy descriptor for this endpoint */
- copy_config (urb, endpoint_descriptor,
- sizeof (struct usb_endpoint_descriptor),
- max);
- }
- }
- }
- dbg_ep0 (3, "lengths: %d %d",
- le16_to_cpu (configuration_descriptor->wTotalLength),
- urb->actual_length);
+ cpu_to_le16(configuration_descriptor->wTotalLength),
+ max);
}
+
break;
case USB_DESCRIPTOR_TYPE_STRING:
{
struct usb_string_descriptor *string_descriptor;
-
if (!(string_descriptor = usbd_get_string (index))) {
+ serial_printf("Invalid string index %d\n", index);
return -1;
}
- /*dbg_ep0(3, "string_descriptor: %p", string_descriptor); */
+ dbg_ep0(3, "string_descriptor: %p length %d", string_descriptor, string_descriptor->bLength);
copy_config (urb, string_descriptor, string_descriptor->bLength, max);
}
break;
case USB_DESCRIPTOR_TYPE_INTERFACE:
+ serial_printf("USB_DESCRIPTOR_TYPE_INTERFACE - error not implemented\n");
return -1;
case USB_DESCRIPTOR_TYPE_ENDPOINT:
+ serial_printf("USB_DESCRIPTOR_TYPE_ENDPOINT - error not implemented\n");
return -1;
case USB_DESCRIPTOR_TYPE_HID:
{
+ serial_printf("USB_DESCRIPTOR_TYPE_HID - error not implemented\n");
return -1; /* unsupported at this time */
#if 0
int bNumInterface =
@@ -403,6 +309,7 @@ static int ep0_get_descriptor (struct usb_device_instance *device,
break;
case USB_DESCRIPTOR_TYPE_REPORT:
{
+ serial_printf("USB_DESCRIPTOR_TYPE_REPORT - error not implemented\n");
return -1; /* unsupported at this time */
#if 0
int bNumInterface =
@@ -434,12 +341,19 @@ static int ep0_get_descriptor (struct usb_device_instance *device,
#endif
}
break;
+ case USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER:
+ {
+ /* If a USB device supports both a full speed and low speed operation
+ * we must send a Device_Qualifier descriptor here
+ */
+ return -1;
+ }
default:
return -1;
}
- dbg_ep0 (1, "urb: buffer: %p buffer_length: %2d actual_length: %2d packet size: %2d",
+ dbg_ep0 (1, "urb: buffer: %p buffer_length: %2d actual_length: %2d tx_packetSize: %2d",
urb->buffer, urb->buffer_length, urb->actual_length,
device->bus->endpoint_array[0].tx_packetSize);
/*
@@ -495,6 +409,12 @@ int ep0_recv_setup (struct urb *urb)
/* handle USB Standard Request (c.f. USB Spec table 9-2) */
if ((request->bmRequestType & USB_REQ_TYPE_MASK) != 0) {
+ if(device->device_state <= STATE_CONFIGURED){
+ /* Attempt to handle a CDC specific request if we are
+ * in the configured state.
+ */
+ return device->cdc_recv_setup(request,urb);
+ }
dbg_ep0 (1, "non standard request: %x",
request->bmRequestType & USB_REQ_TYPE_MASK);
return -1; /* Stall here */
@@ -567,6 +487,7 @@ int ep0_recv_setup (struct urb *urb)
le16_to_cpu (request->wValue) & 0xff);
case USB_REQ_GET_CONFIGURATION:
+ serial_printf("get config %d\n", device->configuration);
return ep0_get_one (device, urb,
device->configuration);
@@ -642,7 +563,6 @@ int ep0_recv_setup (struct urb *urb)
/*dbg_ep0(2, "address: %d %d %d", */
/* request->wValue, le16_to_cpu(request->wValue), device->address); */
- serial_printf ("DEVICE_ADDRESS_ASSIGNED.. event?\n");
return 0;
case USB_REQ_SET_DESCRIPTOR: /* XXX should we support this? */
@@ -653,9 +573,10 @@ int ep0_recv_setup (struct urb *urb)
/* c.f. 9.4.7 - the top half of wValue is reserved */
/* */
if ((device->configuration =
- le16_to_cpu (request->wValue) & 0x7f) != 0) {
+ le16_to_cpu (request->wValue) & 0xFF80) != 0) {
/* c.f. 9.4.7 - zero is the default or addressed state, in our case this */
/* is the same is configuration zero */
+ serial_printf("error setting dev->config to zero!\n");
device->configuration = 0; /* TBR - ?????? */
}
/* reset interface and alternate settings */
diff --git a/drivers/usbdcore_mpc8xx.c b/drivers/usbdcore_mpc8xx.c
new file mode 100644
index 0000000..e87284b
--- /dev/null
+++ b/drivers/usbdcore_mpc8xx.c
@@ -0,0 +1,1400 @@
+/*
+ * Copyright (C) 2006 by Bryan O'Donoghue, CodeHermit
+ * bodonoghue@CodeHermit.ie
+ *
+ * References
+ * DasUBoot/drivers/usbdcore_omap1510.c, for design and implementation ideas.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the
+ * Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ */
+
+/*
+ * Notes :
+ * 1. #define __SIMULATE_ERROR__ to inject a CRC error into every 2nd TX
+ * packet to force the USB re-transmit protocol.
+ *
+ * 2. #define __DEBUG_UDC__ to switch on debug tracing to serial console
+ * be careful that tracing doesn't create Hiesen-bugs with respect to
+ * response timeouts to control requests.
+ *
+ * 3. This driver should be able to support any higher level driver that
+ * that wants to do either of the two standard UDC implementations
+ * Control-Bulk-Interrupt or Bulk-IN/Bulk-Out standards. Hence
+ * gserial and cdc_acm should work with this code.
+ *
+ * 4. NAK events never actually get raised at all, the documentation
+ * is just wrong !
+ *
+ * 5. For some reason, cbd_datlen is *always* +2 the value it should be.
+ * this means that having an RX cbd of 16 bytes is not possible, since
+ * the same size is reported for 14 bytes received as 16 bytes received
+ * until we can find out why this happens, RX cbds must be limited to 8
+ * bytes. TODO: check errata for this behaviour.
+ *
+ * 6. Right now this code doesn't support properly powering up with the USB
+ * cable attached to the USB host my development board the Adder87x doesn't
+ * have a pull-up fitted to allow this, so it is necessary to power the
+ * board and *then* attached the USB cable to the host. However somebody
+ * with a different design in their board may be able to keep the cable
+ * constantly connected and simply enable/disable a pull-up re
+ * figure 31.1 in MPC885RM.pdf instead of having to power up the board and
+ * then attach the cable !
+ *
+ */
+#include <common.h>
+#include <config.h>
+
+#if defined(CONFIG_MPC885_FAMILY) && defined(CONFIG_USB_DEVICE)
+#include <commproc.h>
+#include "usbdcore.h"
+#include "usbdcore_mpc8xx.h"
+#include "usbdcore_ep0.h"
+
+#define ERR(fmt, args...)\
+ serial_printf("ERROR : [%s] %s:%d: "fmt,\
+ __FILE__,__FUNCTION__,__LINE__, ##args)
+#ifdef __DEBUG_UDC__
+#define DBG(fmt,args...)\
+ serial_printf("[%s] %s:%d: "fmt,\
+ __FILE__,__FUNCTION__,__LINE__, ##args)
+#else
+#define DBG(fmt,args...)
+#endif
+
+/* Static Data */
+#ifdef __SIMULATE_ERROR__
+static char err_poison_test = 0;
+#endif
+static struct mpc8xx_ep ep_ref[MAX_ENDPOINTS];
+static u32 address_base = STATE_NOT_READY;
+static mpc8xx_udc_state_t udc_state = 0;
+static struct usb_device_instance *udc_device = 0;
+static volatile usb_epb_t *endpoints[MAX_ENDPOINTS];
+static volatile cbd_t *tx_cbd[TX_RING_SIZE];
+static volatile cbd_t *rx_cbd[RX_RING_SIZE];
+static volatile immap_t *immr = 0;
+static volatile cpm8xx_t *cp = 0;
+static volatile usb_pram_t *usb_paramp = 0;
+static volatile usb_t *usbp = 0;
+static int rx_ct = 0;
+static int tx_ct = 0;
+
+/* Static Function Declarations */
+static void mpc8xx_udc_state_transition_up (usb_device_state_t initial,
+ usb_device_state_t final);
+static void mpc8xx_udc_state_transition_down (usb_device_state_t initial,
+ usb_device_state_t final);
+static void mpc8xx_udc_stall (unsigned int ep);
+static void mpc8xx_udc_flush_tx_fifo (int epid);
+static void mpc8xx_udc_flush_rx_fifo (void);
+static void mpc8xx_udc_clear_rxbd (volatile cbd_t * rx_cbdp);
+static void mpc8xx_udc_init_tx (struct usb_endpoint_instance *epi,
+ struct urb *tx_urb);
+static void mpc8xx_udc_dump_request (struct usb_device_request *request);
+static void mpc8xx_udc_clock_init (volatile immap_t * immr,
+ volatile cpm8xx_t * cp);
+static int mpc8xx_udc_ep_tx (struct usb_endpoint_instance *epi);
+static int mpc8xx_udc_epn_rx (unsigned int epid, volatile cbd_t * rx_cbdp);
+static void mpc8xx_udc_ep0_rx (volatile cbd_t * rx_cbdp);
+static void mpc8xx_udc_cbd_init (void);
+static void mpc8xx_udc_endpoint_init (void);
+static void mpc8xx_udc_cbd_attach (int ep, uchar tx_size, uchar rx_size);
+static u32 mpc8xx_udc_alloc (u32 data_size, u32 alignment);
+static int mpc8xx_udc_ep0_rx_setup (volatile cbd_t * rx_cbdp);
+static void mpc8xx_udc_set_nak (unsigned int ep);
+static short mpc8xx_udc_handle_txerr (void);
+static void mpc8xx_udc_advance_rx (volatile cbd_t ** rx_cbdp, int epid);
+
+/******************************************************************************
+ Global Linkage
+ *****************************************************************************/
+
+/* udc_init
+ *
+ * Do initial bus gluing
+ */
+int udc_init (void)
+{
+ /* Init various pointers */
+ immr = (immap_t *) CFG_IMMR;
+ cp = (cpm8xx_t *) & (immr->im_cpm);
+ usb_paramp = (usb_pram_t *) & (cp->cp_dparam[PROFF_USB]);
+ usbp = (usb_t *) & (cp->cp_scc[0]);
+
+ memset (ep_ref, 0x00, (sizeof (struct mpc8xx_ep) * MAX_ENDPOINTS));
+
+ udc_device = 0;
+ udc_state = STATE_NOT_READY;
+
+ usbp->usmod = 0x00;
+ usbp->uscom = 0;
+
+ /* Set USB Frame #0, Respond at Address & Get a clock source */
+ usbp->usaddr = 0x00;
+ mpc8xx_udc_clock_init (immr, cp);
+
+ /* PA15, PA14 as perhiperal USBRXD and USBOE */
+ immr->im_ioport.iop_padir &= ~0x0003;
+ immr->im_ioport.iop_papar |= 0x0003;
+
+ /* PC11/PC10 as peripheral USBRXP USBRXN */
+ immr->im_ioport.iop_pcso |= 0x0030;
+
+ /* PC7/PC6 as perhiperal USBTXP and USBTXN */
+ immr->im_ioport.iop_pcdir |= 0x0300;
+ immr->im_ioport.iop_pcpar |= 0x0300;
+
+ /* Set the base address */
+ address_base = (u32) (cp->cp_dpmem + CPM_USB_BASE);
+
+ /* Initialise endpoints and circular buffers */
+ mpc8xx_udc_endpoint_init ();
+ mpc8xx_udc_cbd_init ();
+
+ /* Assign allocated Dual Port Endpoint descriptors */
+ usb_paramp->ep0ptr = (u32) endpoints[0];
+ usb_paramp->ep1ptr = (u32) endpoints[1];
+ usb_paramp->ep2ptr = (u32) endpoints[2];
+ usb_paramp->ep3ptr = (u32) endpoints[3];
+ usb_paramp->frame_n = 0;
+
+ DBG ("ep0ptr=0x%08x ep1ptr=0x%08x ep2ptr=0x%08x ep3ptr=0x%08x\n",
+ usb_paramp->ep0ptr, usb_paramp->ep1ptr, usb_paramp->ep2ptr,
+ usb_paramp->ep3ptr);
+
+ return 0;
+}
+
+/* udc_irq
+ *
+ * Poll for whatever events may have occured
+ */
+void udc_irq (void)
+{
+ int epid = 0;
+ volatile cbd_t *rx_cbdp = 0;
+ volatile cbd_t *rx_cbdp_base = 0;
+
+ if (udc_state != STATE_READY) {
+ return;
+ }
+
+ if (usbp->usber & USB_E_BSY) {
+ /* This shouldn't happen. If it does then it's a bug ! */
+ usbp->usber |= USB_E_BSY;
+ mpc8xx_udc_flush_rx_fifo ();
+ }
+
+ /* Scan all RX/Bidirectional Endpoints for RX data. */
+ for (epid = 0; epid < MAX_ENDPOINTS; epid++) {
+ if (!ep_ref[epid].prx) {
+ continue;
+ }
+ rx_cbdp = rx_cbdp_base = ep_ref[epid].prx;
+
+ do {
+ if (!(rx_cbdp->cbd_sc & RX_BD_E)) {
+
+ if (rx_cbdp->cbd_sc & 0x1F) {
+ /* Corrupt data discard it.
+ * Controller has NAK'd this packet.
+ */
+ mpc8xx_udc_clear_rxbd (rx_cbdp);
+
+ } else {
+ if (!epid) {
+ mpc8xx_udc_ep0_rx (rx_cbdp);
+
+ } else {
+ /* Process data */
+ mpc8xx_udc_set_nak (epid);
+ mpc8xx_udc_epn_rx (epid, rx_cbdp);
+ mpc8xx_udc_clear_rxbd (rx_cbdp);
+ }
+ }
+
+ /* Advance RX CBD pointer */
+ mpc8xx_udc_advance_rx (&rx_cbdp, epid);
+ ep_ref[epid].prx = rx_cbdp;
+ } else {
+ /* Advance RX CBD pointer */
+ mpc8xx_udc_advance_rx (&rx_cbdp, epid);
+ }
+
+ } while (rx_cbdp != rx_cbdp_base);
+ }
+
+ /* Handle TX events as appropiate, the correct place to do this is
+ * in a tx routine. Perhaps TX on epn was pre-empted by ep0
+ */
+
+ if (usbp->usber & USB_E_TXB) {
+ usbp->usber |= USB_E_TXB;
+ }
+
+ if (usbp->usber & (USB_TX_ERRMASK)) {
+ mpc8xx_udc_handle_txerr ();
+ }
+
+ /* Switch to the default state, respond at the default address */
+ if (usbp->usber & USB_E_RESET) {
+ usbp->usber |= USB_E_RESET;
+ usbp->usaddr = 0x00;
+ udc_device->device_state = STATE_DEFAULT;
+ }
+
+ /* if(usbp->usber&USB_E_IDLE){
+ We could suspend here !
+ usbp->usber|=USB_E_IDLE;
+ DBG("idle state change\n");
+ }
+ if(usbp->usbs){
+ We could resume here when IDLE is deasserted !
+ Not worth doing, so long as we are self powered though.
+ }
+ */
+
+ return;
+}
+
+/* udc_endpoint_write
+ *
+ * Write some data to an endpoint
+ */
+int udc_endpoint_write (struct usb_endpoint_instance *epi)
+{
+ int ep = 0;
+ short epid = 1, unnak = 0, ret = 0;
+
+ if (udc_state != STATE_READY) {
+ ERR ("invalid udc_state != STATE_READY!\n");
+ return -1;
+ }
+
+ if (!udc_device || !epi) {
+ return -1;
+ }
+
+ if (udc_device->device_state != STATE_CONFIGURED) {
+ return -1;
+ }
+
+ ep = epi->endpoint_address & 0x03;
+ if (ep >= MAX_ENDPOINTS) {
+ return -1;
+ }
+
+ /* Set NAK for all RX endpoints during TX */
+ for (epid = 1; epid < MAX_ENDPOINTS; epid++) {
+
+ /* Don't set NAK on DATA IN/CONTROL endpoints */
+ if (ep_ref[epid].sc & USB_DIR_IN) {
+ continue;
+ }
+
+ if (!(usbp->usep[epid] & (USEP_THS_NAK | USEP_RHS_NAK))) {
+ unnak |= 1 << epid;
+ }
+
+ mpc8xx_udc_set_nak (epid);
+ }
+
+ mpc8xx_udc_init_tx (&udc_device->bus->endpoint_array[ep],
+ epi->tx_urb);
+ ret = mpc8xx_udc_ep_tx (&udc_device->bus->endpoint_array[ep]);
+
+ /* Remove temporary NAK */
+ for (epid = 1; epid < MAX_ENDPOINTS; epid++) {
+ if (unnak & (1 << epid)) {
+ udc_unset_nak (epid);
+ }
+ }
+
+ return ret;
+}
+
+/* mpc8xx_udc_assign_urb
+ *
+ * Associate a given urb to an endpoint TX or RX transmit/receive buffers
+ */
+static int mpc8xx_udc_assign_urb (int ep, char direction)
+{
+ struct usb_endpoint_instance *epi = 0;
+
+ if (ep >= MAX_ENDPOINTS) {
+ goto err;
+ }
+ epi = &udc_device->bus->endpoint_array[ep];
+ if (!epi) {
+ goto err;
+ }
+
+ if (!ep_ref[ep].urb) {
+ ep_ref[ep].urb = usbd_alloc_urb (udc_device, udc_device->bus->endpoint_array);
+ if (!ep_ref[ep].urb) {
+ goto err;
+ }
+ } else {
+ ep_ref[ep].urb->actual_length = 0;
+ }
+
+ switch (direction) {
+ case USB_DIR_IN:
+ epi->tx_urb = ep_ref[ep].urb;
+ break;
+ case USB_DIR_OUT:
+ epi->rcv_urb = ep_ref[ep].urb;
+ break;
+ default:
+ goto err;
+ }
+ return 0;
+
+ err:
+ udc_state = STATE_ERROR;
+ return -1;
+}
+
+/* udc_setup_ep
+ *
+ * Associate U-Boot software endpoints to mpc8xx endpoint parameter ram
+ * Isochronous endpoints aren't yet supported!
+ */
+void udc_setup_ep (struct usb_device_instance *device, unsigned int ep,
+ struct usb_endpoint_instance *epi)
+{
+ uchar direction = 0;
+ int ep_attrib = 0;
+
+ if (epi && (ep < MAX_ENDPOINTS)) {
+
+ if (ep == 0) {
+ if (epi->rcv_attributes != USB_ENDPOINT_XFER_CONTROL
+ || epi->tx_attributes !=
+ USB_ENDPOINT_XFER_CONTROL) {
+
+ /* ep0 must be a control endpoint */
+ udc_state = STATE_ERROR;
+ return;
+
+ }
+ if (!(ep_ref[ep].sc & EP_ATTACHED)) {
+ mpc8xx_udc_cbd_attach (ep, epi->tx_packetSize,
+ epi->rcv_packetSize);
+ }
+ usbp->usep[ep] = 0x0000;
+ return;
+ }
+
+ if ((epi->endpoint_address & USB_ENDPOINT_DIR_MASK)
+ == USB_DIR_IN) {
+
+ direction = 1;
+ ep_attrib = epi->tx_attributes;
+ epi->rcv_packetSize = 0;
+ ep_ref[ep].sc |= USB_DIR_IN;
+ } else {
+
+ direction = 0;
+ ep_attrib = epi->rcv_attributes;
+ epi->tx_packetSize = 0;
+ ep_ref[ep].sc &= ~USB_DIR_IN;
+ }
+
+ if (mpc8xx_udc_assign_urb (ep, epi->endpoint_address
+ & USB_ENDPOINT_DIR_MASK)) {
+ return;
+ }
+
+ switch (ep_attrib) {
+ case USB_ENDPOINT_XFER_CONTROL:
+ if (!(ep_ref[ep].sc & EP_ATTACHED)) {
+ mpc8xx_udc_cbd_attach (ep,
+ epi->tx_packetSize,
+ epi->rcv_packetSize);
+ }
+ usbp->usep[ep] = ep << 12;
+ epi->rcv_urb = epi->tx_urb = ep_ref[ep].urb;
+
+ break;
+ case USB_ENDPOINT_XFER_BULK:
+ case USB_ENDPOINT_XFER_INT:
+ if (!(ep_ref[ep].sc & EP_ATTACHED)) {
+ if (direction) {
+ mpc8xx_udc_cbd_attach (ep,
+ epi->tx_packetSize,
+ 0);
+ } else {
+ mpc8xx_udc_cbd_attach (ep,
+ 0,
+ epi->rcv_packetSize);
+ }
+ }
+ usbp->usep[ep] = (ep << 12) | ((ep_attrib) << 8);
+
+ break;
+ case USB_ENDPOINT_XFER_ISOC:
+ default:
+ serial_printf ("Error endpoint attrib %d>3\n", ep_attrib);
+ udc_state = STATE_ERROR;
+ break;
+ }
+ }
+
+}
+
+/* udc_connect
+ *
+ * Move state, switch on the USB
+ */
+void udc_connect (void)
+{
+ /* Enable pull-up resistor on D+
+ * TODO: fit a pull-up resistor to drive SE0 for > 2.5us
+ */
+
+ if (udc_state != STATE_ERROR) {
+ udc_state = STATE_READY;
+ usbp->usmod |= USMOD_EN;
+ }
+}
+
+/* udc_disconnect
+ *
+ * Disconnect is not used but, is included for completeness
+ */
+void udc_disconnect (void)
+{
+ /* Disable pull-up resistor on D-
+ * TODO: fix a pullup resistor to control this
+ */
+
+ if (udc_state != STATE_ERROR) {
+ udc_state = STATE_NOT_READY;
+ }
+ usbp->usmod &= ~USMOD_EN;
+}
+
+/* udc_enable
+ *
+ * Grab an EP0 URB, register interest in a subset of USB events
+ */
+void udc_enable (struct usb_device_instance *device)
+{
+ if (udc_state == STATE_ERROR) {
+ return;
+ }
+
+ udc_device = device;
+
+ if (!ep_ref[0].urb) {
+ ep_ref[0].urb = usbd_alloc_urb (device, device->bus->endpoint_array);
+ }
+
+ /* Register interest in all events except SOF, enable transceiver */
+ usbp->usber = 0x03FF;
+ usbp->usbmr = 0x02F7;
+
+ return;
+}
+
+/* udc_disable
+ *
+ * disable the currently hooked device
+ */
+void udc_disable (void)
+{
+ int i = 0;
+
+ if (udc_state == STATE_ERROR) {
+ DBG ("Won't disable UDC. udc_state==STATE_ERROR !\n");
+ return;
+ }
+
+ udc_device = 0;
+
+ for (; i < MAX_ENDPOINTS; i++) {
+ if (ep_ref[i].urb) {
+ usbd_dealloc_urb (ep_ref[i].urb);
+ ep_ref[i].urb = 0;
+ }
+ }
+
+ usbp->usbmr = 0x00;
+ usbp->usmod = ~USMOD_EN;
+ udc_state = STATE_NOT_READY;
+}
+
+/* udc_startup_events
+ *
+ * Enable the specified device
+ */
+void udc_startup_events (struct usb_device_instance *device)
+{
+ udc_enable (device);
+ if (udc_state == STATE_READY) {
+ usbd_device_event_irq (device, DEVICE_CREATE, 0);
+ }
+}
+
+/* udc_set_nak
+ *
+ * Allow upper layers to signal lower layers should not accept more RX data
+ *
+ */
+void udc_set_nak (int epid)
+{
+ if (epid) {
+ mpc8xx_udc_set_nak (epid);
+ }
+}
+
+/* udc_unset_nak
+ *
+ * Suspend sending of NAK tokens for DATA OUT tokens on a given endpoint.
+ * Switch off NAKing on this endpoint to accept more data output from host.
+ *
+ */
+void udc_unset_nak (int epid)
+{
+ if (epid > MAX_ENDPOINTS) {
+ return;
+ }
+
+ if (usbp->usep[epid] & (USEP_THS_NAK | USEP_RHS_NAK)) {
+ usbp->usep[epid] &= ~(USEP_THS_NAK | USEP_RHS_NAK);
+ __asm__ ("eieio");
+ }
+}
+
+/******************************************************************************
+ Static Linkage
+******************************************************************************/
+
+/* udc_state_transition_up
+ * udc_state_transition_down
+ *
+ * Helper functions to implement device state changes. The device states and
+ * the events that transition between them are:
+ *
+ * STATE_ATTACHED
+ * || /\
+ * \/ ||
+ * DEVICE_HUB_CONFIGURED DEVICE_HUB_RESET
+ * || /\
+ * \/ ||
+ * STATE_POWERED
+ * || /\
+ * \/ ||
+ * DEVICE_RESET DEVICE_POWER_INTERRUPTION
+ * || /\
+ * \/ ||
+ * STATE_DEFAULT
+ * || /\
+ * \/ ||
+ * DEVICE_ADDRESS_ASSIGNED DEVICE_RESET
+ * || /\
+ * \/ ||
+ * STATE_ADDRESSED
+ * || /\
+ * \/ ||
+ * DEVICE_CONFIGURED DEVICE_DE_CONFIGURED
+ * || /\
+ * \/ ||
+ * STATE_CONFIGURED
+ *
+ * udc_state_transition_up transitions up (in the direction from STATE_ATTACHED
+ * to STATE_CONFIGURED) from the specified initial state to the specified final
+ * state, passing through each intermediate state on the way. If the initial
+ * state is at or above (i.e. nearer to STATE_CONFIGURED) the final state, then
+ * no state transitions will take place.
+ *
+ * udc_state_transition_down transitions down (in the direction from
+ * STATE_CONFIGURED to STATE_ATTACHED) from the specified initial state to the
+ * specified final state, passing through each intermediate state on the way.
+ * If the initial state is at or below (i.e. nearer to STATE_ATTACHED) the final
+ * state, then no state transitions will take place.
+ *
+ */
+
+static void mpc8xx_udc_state_transition_up (usb_device_state_t initial,
+ usb_device_state_t final)
+{
+ if (initial < final) {
+ switch (initial) {
+ case STATE_ATTACHED:
+ usbd_device_event_irq (udc_device,
+ DEVICE_HUB_CONFIGURED, 0);
+ if (final == STATE_POWERED)
+ break;
+ case STATE_POWERED:
+ usbd_device_event_irq (udc_device, DEVICE_RESET, 0);
+ if (final == STATE_DEFAULT)
+ break;
+ case STATE_DEFAULT:
+ usbd_device_event_irq (udc_device,
+ DEVICE_ADDRESS_ASSIGNED, 0);
+ if (final == STATE_ADDRESSED)
+ break;
+ case STATE_ADDRESSED:
+ usbd_device_event_irq (udc_device, DEVICE_CONFIGURED,
+ 0);
+ case STATE_CONFIGURED:
+ break;
+ default:
+ break;
+ }
+ }
+}
+
+static void mpc8xx_udc_state_transition_down (usb_device_state_t initial,
+ usb_device_state_t final)
+{
+ if (initial > final) {
+ switch (initial) {
+ case STATE_CONFIGURED:
+ usbd_device_event_irq (udc_device,
+ DEVICE_DE_CONFIGURED, 0);
+ if (final == STATE_ADDRESSED)
+ break;
+ case STATE_ADDRESSED:
+ usbd_device_event_irq (udc_device, DEVICE_RESET, 0);
+ if (final == STATE_DEFAULT)
+ break;
+ case STATE_DEFAULT:
+ usbd_device_event_irq (udc_device,
+ DEVICE_POWER_INTERRUPTION, 0);
+ if (final == STATE_POWERED)
+ break;
+ case STATE_POWERED:
+ usbd_device_event_irq (udc_device, DEVICE_HUB_RESET,
+ 0);
+ case STATE_ATTACHED:
+ break;
+ default:
+ break;
+ }
+ }
+}
+
+/* mpc8xx_udc_stall
+ *
+ * Force returning of STALL tokens on the given endpoint. Protocol or function
+ * STALL conditions are permissable here
+ */
+static void mpc8xx_udc_stall (unsigned int ep)
+{
+ usbp->usep[ep] |= STALL_BITMASK;
+}
+
+/* mpc8xx_udc_set_nak
+ *
+ * Force returning of NAK responses for the given endpoint as a kind of very
+ * simple flow control
+ */
+static void mpc8xx_udc_set_nak (unsigned int ep)
+{
+ usbp->usep[ep] |= NAK_BITMASK;
+ __asm__ ("eieio");
+}
+
+/* mpc8xx_udc_handle_txerr
+ *
+ * Handle errors relevant to TX. Return a status code to allow calling
+ * indicative of what if anything happened
+ */
+static short mpc8xx_udc_handle_txerr ()
+{
+ short ep = 0, ret = 0;
+
+ for (; ep < TX_RING_SIZE; ep++) {
+ if (usbp->usber & (0x10 << ep)) {
+
+ /* Timeout or underrun */
+ if (tx_cbd[ep]->cbd_sc & 0x06) {
+ ret = 1;
+ mpc8xx_udc_flush_tx_fifo (ep);
+
+ } else {
+ if (usbp->usep[ep] & STALL_BITMASK) {
+ if (!ep) {
+ usbp->usep[ep] &= ~STALL_BITMASK;
+ }
+ } /* else NAK */
+ }
+ usbp->usber |= (0x10 << ep);
+ }
+ }
+ return ret;
+}
+
+/* mpc8xx_udc_advance_rx
+ *
+ * Advance cbd rx
+ */
+static void mpc8xx_udc_advance_rx (volatile cbd_t ** rx_cbdp, int epid)
+{
+ if ((*rx_cbdp)->cbd_sc & RX_BD_W) {
+ *rx_cbdp = (volatile cbd_t *) (endpoints[epid]->rbase + CFG_IMMR);
+
+ } else {
+ (*rx_cbdp)++;
+ }
+}
+
+
+/* mpc8xx_udc_flush_tx_fifo
+ *
+ * Flush a given TX fifo. Assumes one tx cbd per endpoint
+ */
+static void mpc8xx_udc_flush_tx_fifo (int epid)
+{
+ volatile cbd_t *tx_cbdp = 0;
+
+ if (epid > MAX_ENDPOINTS) {
+ return;
+ }
+
+ /* TX stop */
+ immr->im_cpm.cp_cpcr = ((epid << 2) | 0x1D01);
+ __asm__ ("eieio");
+ while (immr->im_cpm.cp_cpcr & 0x01);
+
+ usbp->uscom = 0x40 | 0;
+
+ /* reset ring */
+ tx_cbdp = (cbd_t *) (endpoints[epid]->tbptr + CFG_IMMR);
+ tx_cbdp->cbd_sc = (TX_BD_I | TX_BD_W);
+
+
+ endpoints[epid]->tptr = endpoints[epid]->tbase;
+ endpoints[epid]->tstate = 0x00;
+ endpoints[epid]->tbcnt = 0x00;
+
+ /* TX start */
+ immr->im_cpm.cp_cpcr = ((epid << 2) | 0x2D01);
+ __asm__ ("eieio");
+ while (immr->im_cpm.cp_cpcr & 0x01);
+
+ return;
+}
+
+/* mpc8xx_udc_flush_rx_fifo
+ *
+ * For the sake of completeness of the namespace, it seems like
+ * a good-design-decision (tm) to include mpc8xx_udc_flush_rx_fifo();
+ * If RX_BD_E is true => a driver bug either here or in an upper layer
+ * not polling frequently enough. If RX_BD_E is true we have told the host
+ * we have accepted data but, the CPM found it had no-where to put that data
+ * which needless to say would be a bad thing.
+ */
+static void mpc8xx_udc_flush_rx_fifo ()
+{
+ int i = 0;
+
+ for (i = 0; i < RX_RING_SIZE; i++) {
+ if (!(rx_cbd[i]->cbd_sc & RX_BD_E)) {
+ ERR ("buf %p used rx data len = 0x%x sc=0x%x!\n",
+ rx_cbd[i], rx_cbd[i]->cbd_datlen,
+ rx_cbd[i]->cbd_sc);
+
+ }
+ }
+ ERR ("BUG : Input over-run\n");
+}
+
+/* mpc8xx_udc_clear_rxbd
+ *
+ * Release control of RX CBD to CP.
+ */
+static void mpc8xx_udc_clear_rxbd (volatile cbd_t * rx_cbdp)
+{
+ rx_cbdp->cbd_datlen = 0x0000;
+ rx_cbdp->cbd_sc = ((rx_cbdp->cbd_sc & RX_BD_W) | (RX_BD_E | RX_BD_I));
+ __asm__ ("eieio");
+}
+
+/* mpc8xx_udc_tx_irq
+ *
+ * Parse for tx timeout, control RX or USB reset/busy conditions
+ * Return -1 on timeout, -2 on fatal error, else return zero
+ */
+static int mpc8xx_udc_tx_irq (int ep)
+{
+ int i = 0;
+
+ if (usbp->usber & (USB_TX_ERRMASK)) {
+ if (mpc8xx_udc_handle_txerr ()) {
+ /* Timeout, controlling function must retry send */
+ return -1;
+ }
+ }
+
+ if (usbp->usber & (USB_E_RESET | USB_E_BSY)) {
+ /* Fatal, abandon TX transaction */
+ return -2;
+ }
+
+ if (usbp->usber & USB_E_RXB) {
+ for (i = 0; i < RX_RING_SIZE; i++) {
+ if (!(rx_cbd[i]->cbd_sc & RX_BD_E)) {
+ if ((rx_cbd[i] == ep_ref[0].prx) || ep) {
+ return -2;
+ }
+ }
+ }
+ }
+
+ return 0;
+}
+
+/* mpc8xx_udc_ep_tx
+ *
+ * Transmit in a re-entrant fashion outbound USB packets.
+ * Implement retry/timeout mechanism described in USB specification
+ * Toggle DATA0/DATA1 pids as necessary
+ * Introduces non-standard tx_retry. The USB standard has no scope for slave
+ * devices to give up TX, however tx_retry stops us getting stuck in an endless
+ * TX loop.
+ */
+static int mpc8xx_udc_ep_tx (struct usb_endpoint_instance *epi)
+{
+ struct urb *urb = epi->tx_urb;
+ volatile cbd_t *tx_cbdp = 0;
+ unsigned int ep = 0, pkt_len = 0, x = 0, tx_retry = 0;
+ int ret = 0;
+
+ if (!epi || (epi->endpoint_address & 0x03) >= MAX_ENDPOINTS || !urb) {
+ return -1;
+ }
+
+ ep = epi->endpoint_address & 0x03;
+ tx_cbdp = (cbd_t *) (endpoints[ep]->tbptr + CFG_IMMR);
+
+ if (tx_cbdp->cbd_sc & TX_BD_R || usbp->usber & USB_E_TXB) {
+ mpc8xx_udc_flush_tx_fifo (ep);
+ usbp->usber |= USB_E_TXB;
+ };
+
+ while (tx_retry++ < 100) {
+ ret = mpc8xx_udc_tx_irq (ep);
+ if (ret == -1) {
+ /* ignore timeout here */
+ } else if (ret == -2) {
+ /* Abandon TX */
+ mpc8xx_udc_flush_tx_fifo (ep);
+ return -1;
+ }
+
+ tx_cbdp = (cbd_t *) (endpoints[ep]->tbptr + CFG_IMMR);
+ while (tx_cbdp->cbd_sc & TX_BD_R) {
+ };
+ tx_cbdp->cbd_sc = (tx_cbdp->cbd_sc & TX_BD_W);
+
+ pkt_len = urb->actual_length - epi->sent;
+
+ if (pkt_len > epi->tx_packetSize || pkt_len > EP_MAX_PKT) {
+ pkt_len = MIN (epi->tx_packetSize, EP_MAX_PKT);
+ }
+
+ for (x = 0; x < pkt_len; x++) {
+ *((unsigned char *) (tx_cbdp->cbd_bufaddr + x)) =
+ urb->buffer[epi->sent + x];
+ }
+ tx_cbdp->cbd_datlen = pkt_len;
+ tx_cbdp->cbd_sc |= (CBD_TX_BITMASK | ep_ref[ep].pid);
+ __asm__ ("eieio");
+
+#ifdef __SIMULATE_ERROR__
+ if (++err_poison_test == 2) {
+ err_poison_test = 0;
+ tx_cbdp->cbd_sc &= ~TX_BD_TC;
+ }
+#endif
+
+ usbp->uscom = (USCOM_STR | ep);
+
+ while (!(usbp->usber & USB_E_TXB)) {
+ ret = mpc8xx_udc_tx_irq (ep);
+ if (ret == -1) {
+ /* TX timeout */
+ break;
+ } else if (ret == -2) {
+ if (usbp->usber & USB_E_TXB) {
+ usbp->usber |= USB_E_TXB;
+ }
+ mpc8xx_udc_flush_tx_fifo (ep);
+ return -1;
+ }
+ };
+
+ if (usbp->usber & USB_E_TXB) {
+ usbp->usber |= USB_E_TXB;
+ }
+
+ /* ACK must be present <= 18bit times from TX */
+ if (ret == -1) {
+ continue;
+ }
+
+ /* TX ACK : USB 2.0 8.7.2, Toggle PID, Advance TX */
+ epi->sent += pkt_len;
+ epi->last = MIN (urb->actual_length - epi->sent, epi->tx_packetSize);
+ TOGGLE_TX_PID (ep_ref[ep].pid);
+
+ if (epi->sent >= epi->tx_urb->actual_length) {
+
+ epi->tx_urb->actual_length = 0;
+ epi->sent = 0;
+
+ if (ep_ref[ep].sc & EP_SEND_ZLP) {
+ ep_ref[ep].sc &= ~EP_SEND_ZLP;
+ } else {
+ return 0;
+ }
+ }
+ }
+
+ ERR ("TX fail, endpoint 0x%x tx bytes 0x%x/0x%x\n", ep, epi->sent,
+ epi->tx_urb->actual_length);
+
+ return -1;
+}
+
+/* mpc8xx_udc_dump_request
+ *
+ * Dump a control request to console
+ */
+static void mpc8xx_udc_dump_request (struct usb_device_request *request)
+{
+ DBG ("bmRequestType:%02x bRequest:%02x wValue:%04x "
+ "wIndex:%04x wLength:%04x ?\n",
+ request->bmRequestType,
+ request->bRequest,
+ request->wValue, request->wIndex, request->wLength);
+
+ return;
+}
+
+/* mpc8xx_udc_ep0_rx_setup
+ *
+ * Decode received ep0 SETUP packet. return non-zero on error
+ */
+static int mpc8xx_udc_ep0_rx_setup (volatile cbd_t * rx_cbdp)
+{
+ unsigned int x = 0;
+ struct urb *purb = ep_ref[0].urb;
+ struct usb_endpoint_instance *epi =
+ &udc_device->bus->endpoint_array[0];
+
+ for (; x < rx_cbdp->cbd_datlen; x++) {
+ *(((unsigned char *) &ep_ref[0].urb->device_request) + x) =
+ *((unsigned char *) (rx_cbdp->cbd_bufaddr + x));
+ }
+
+ mpc8xx_udc_clear_rxbd (rx_cbdp);
+
+ if (ep0_recv_setup (purb)) {
+ mpc8xx_udc_dump_request (&purb->device_request);
+ return -1;
+ }
+
+ if ((purb->device_request.bmRequestType & USB_REQ_DIRECTION_MASK)
+ == USB_REQ_HOST2DEVICE) {
+
+ switch (purb->device_request.bRequest) {
+ case USB_REQ_SET_ADDRESS:
+ /* Send the Status OUT ZLP */
+ ep_ref[0].pid = TX_BD_PID_DATA1;
+ purb->actual_length = 0;
+ mpc8xx_udc_init_tx (epi, purb);
+ mpc8xx_udc_ep_tx (epi);
+
+ /* Move to the addressed state */
+ usbp->usaddr = udc_device->address;
+ mpc8xx_udc_state_transition_up (udc_device->device_state,
+ STATE_ADDRESSED);
+ return 0;
+
+ case USB_REQ_SET_CONFIGURATION:
+ if (!purb->device_request.wValue) {
+ /* Respond at default address */
+ usbp->usaddr = 0x00;
+ mpc8xx_udc_state_transition_down (udc_device->device_state,
+ STATE_ADDRESSED);
+ } else {
+ /* TODO: Support multiple configurations */
+ mpc8xx_udc_state_transition_up (udc_device->device_state,
+ STATE_CONFIGURED);
+ for (x = 1; x < MAX_ENDPOINTS; x++) {
+ if ((udc_device->bus->endpoint_array[x].endpoint_address & USB_ENDPOINT_DIR_MASK)
+ == USB_DIR_IN) {
+ ep_ref[x].pid = TX_BD_PID_DATA0;
+ } else {
+ ep_ref[x].pid = RX_BD_PID_DATA0;
+ }
+ /* Set configuration must unstall endpoints */
+ usbp->usep[x] &= ~STALL_BITMASK;
+ }
+ }
+ break;
+ default:
+ /* CDC/Vendor specific */
+ break;
+ }
+
+ /* Send ZLP as ACK in Status OUT phase */
+ ep_ref[0].pid = TX_BD_PID_DATA1;
+ purb->actual_length = 0;
+ mpc8xx_udc_init_tx (epi, purb);
+ mpc8xx_udc_ep_tx (epi);
+
+ } else {
+
+ if (purb->actual_length) {
+ ep_ref[0].pid = TX_BD_PID_DATA1;
+ mpc8xx_udc_init_tx (epi, purb);
+
+ if (!(purb->actual_length % EP0_MAX_PACKET_SIZE)) {
+ ep_ref[0].sc |= EP_SEND_ZLP;
+ }
+
+ if (purb->device_request.wValue ==
+ USB_DESCRIPTOR_TYPE_DEVICE) {
+ if (le16_to_cpu (purb->device_request.wLength)
+ > purb->actual_length) {
+ /* Send EP0_MAX_PACKET_SIZE bytes
+ * unless correct size requested.
+ */
+ if (purb->actual_length > epi->tx_packetSize) {
+ purb->actual_length = epi->tx_packetSize;
+ }
+ }
+ }
+ mpc8xx_udc_ep_tx (epi);
+
+ } else {
+ /* Corrupt SETUP packet? */
+ ERR ("Zero length data or SETUP with DATA-IN phase ?\n");
+ return 1;
+ }
+ }
+ return 0;
+}
+
+/* mpc8xx_udc_init_tx
+ *
+ * Setup some basic parameters for a TX transaction
+ */
+static void mpc8xx_udc_init_tx (struct usb_endpoint_instance *epi,
+ struct urb *tx_urb)
+{
+ epi->sent = 0;
+ epi->last = 0;
+ epi->tx_urb = tx_urb;
+}
+
+/* mpc8xx_udc_ep0_rx
+ *
+ * Receive ep0/control USB data. Parse and possibly send a response.
+ */
+static void mpc8xx_udc_ep0_rx (volatile cbd_t * rx_cbdp)
+{
+ if (rx_cbdp->cbd_sc & RX_BD_PID_SETUP) {
+
+ /* Unconditionally accept SETUP packets */
+ if (mpc8xx_udc_ep0_rx_setup (rx_cbdp)) {
+ mpc8xx_udc_stall (0);
+ }
+
+ } else {
+
+ mpc8xx_udc_clear_rxbd (rx_cbdp);
+
+ if ((rx_cbdp->cbd_datlen - 2)) {
+ /* SETUP with a DATA phase
+ * outside of SETUP packet.
+ * Reply with STALL.
+ */
+ mpc8xx_udc_stall (0);
+ }
+ }
+}
+
+/* mpc8xx_udc_epn_rx
+ *
+ * Receive some data from cbd into USB system urb data abstraction
+ * Upper layers should NAK if there is insufficient RX data space
+ */
+static int mpc8xx_udc_epn_rx (unsigned int epid, volatile cbd_t * rx_cbdp)
+{
+ struct usb_endpoint_instance *epi = 0;
+ struct urb *urb = 0;
+ unsigned int x = 0;
+
+ if (epid >= MAX_ENDPOINTS || !rx_cbdp->cbd_datlen) {
+ return 0;
+ }
+
+ /* USB 2.0 PDF section 8.6.4
+ * Discard data with invalid PID it is a resend.
+ */
+ if (ep_ref[epid].pid != (rx_cbdp->cbd_sc & 0xC0)) {
+ return 1;
+ }
+ TOGGLE_RX_PID (ep_ref[epid].pid);
+
+ epi = &udc_device->bus->endpoint_array[epid];
+ urb = epi->rcv_urb;
+
+ for (; x < (rx_cbdp->cbd_datlen - 2); x++) {
+ *((unsigned char *) (urb->buffer + urb->actual_length + x)) =
+ *((unsigned char *) (rx_cbdp->cbd_bufaddr + x));
+ }
+
+ if (x) {
+ usbd_rcv_complete (epi, x, 0);
+ if (ep_ref[epid].urb->status == RECV_ERROR) {
+ DBG ("RX error unset NAK\n");
+ udc_unset_nak (epid);
+ }
+ }
+ return x;
+}
+
+/* mpc8xx_udc_clock_init
+ *
+ * Obtain a clock reference for Full Speed Signaling
+ */
+static void mpc8xx_udc_clock_init (volatile immap_t * immr,
+ volatile cpm8xx_t * cp)
+{
+
+#if defined(CFG_USB_EXTC_CLK)
+
+ /* This has been tested with a 48MHz crystal on CLK6 */
+ switch (CFG_USB_EXTC_CLK) {
+ case 1:
+ immr->im_ioport.iop_papar |= 0x0100;
+ immr->im_ioport.iop_padir &= ~0x0100;
+ cp->cp_sicr |= 0x24;
+ break;
+ case 2:
+ immr->im_ioport.iop_papar |= 0x0200;
+ immr->im_ioport.iop_padir &= ~0x0200;
+ cp->cp_sicr |= 0x2D;
+ break;
+ case 3:
+ immr->im_ioport.iop_papar |= 0x0400;
+ immr->im_ioport.iop_padir &= ~0x0400;
+ cp->cp_sicr |= 0x36;
+ break;
+ case 4:
+ immr->im_ioport.iop_papar |= 0x0800;
+ immr->im_ioport.iop_padir &= ~0x0800;
+ cp->cp_sicr |= 0x3F;
+ break;
+ default:
+ udc_state = STATE_ERROR;
+ break;
+ }
+
+#elif defined(CFG_USB_BRGCLK)
+
+ /* This has been tested with brgclk == 50MHz */
+ DECLARE_GLOBAL_DATA_PTR;
+ int divisor = 0;
+
+ if (gd->cpu_clk < 48000000L) {
+ ERR ("brgclk is too slow for full-speed USB!\n");
+ udc_state = STATE_ERROR;
+ return;
+ }
+
+ /* Assume the brgclk is 'good enough', we want !(gd->cpu_clk%48Mhz)
+ * but, can /probably/ live with close-ish alternative rates.
+ */
+ divisor = (gd->cpu_clk / 48000000L) - 1;
+ cp->cp_sicr &= ~0x0000003F;
+
+ switch (CFG_USB_BRGCLK) {
+ case 1:
+ cp->cp_brgc1 |= (divisor | CPM_BRG_EN);
+ cp->cp_sicr &= ~0x2F;
+ break;
+ case 2:
+ cp->cp_brgc2 |= (divisor | CPM_BRG_EN);
+ cp->cp_sicr |= 0x00000009;
+ break;
+ case 3:
+ cp->cp_brgc3 |= (divisor | CPM_BRG_EN);
+ cp->cp_sicr |= 0x00000012;
+ break;
+ case 4:
+ cp->cp_brgc4 = (divisor | CPM_BRG_EN);
+ cp->cp_sicr |= 0x0000001B;
+ break;
+ default:
+ udc_state = STATE_ERROR;
+ break;
+ }
+
+#else
+#error "CFG_USB_EXTC_CLK or CFG_USB_BRGCLK must be defined"
+#endif
+
+}
+
+/* mpc8xx_udc_cbd_attach
+ *
+ * attach a cbd to and endpoint
+ */
+static void mpc8xx_udc_cbd_attach (int ep, uchar tx_size, uchar rx_size)
+{
+
+ if (!tx_cbd[ep] || !rx_cbd[ep] || ep >= MAX_ENDPOINTS) {
+ udc_state = STATE_ERROR;
+ return;
+ }
+
+ if (tx_size > USB_MAX_PKT || rx_size > USB_MAX_PKT ||
+ (!tx_size && !rx_size)) {
+ udc_state = STATE_ERROR;
+ return;
+ }
+
+ /* Attach CBD to appropiate Parameter RAM Endpoint data structure */
+ if (rx_size) {
+ endpoints[ep]->rbase = (u32) rx_cbd[rx_ct];
+ endpoints[ep]->rbptr = (u32) rx_cbd[rx_ct];
+ rx_ct++;
+
+ if (!ep) {
+
+ endpoints[ep]->rbptr = (u32) rx_cbd[rx_ct];
+ rx_cbd[rx_ct]->cbd_sc |= RX_BD_W;
+ rx_ct++;
+
+ } else {
+ rx_ct += 2;
+ endpoints[ep]->rbptr = (u32) rx_cbd[rx_ct];
+ rx_cbd[rx_ct]->cbd_sc |= RX_BD_W;
+ rx_ct++;
+ }
+
+ /* Where we expect to RX data on this endpoint */
+ ep_ref[ep].prx = rx_cbd[rx_ct - 1];
+ } else {
+
+ ep_ref[ep].prx = 0;
+ endpoints[ep]->rbase = 0;
+ endpoints[ep]->rbptr = 0;
+ }
+
+ if (tx_size) {
+ endpoints[ep]->tbase = (u32) tx_cbd[tx_ct];
+ endpoints[ep]->tbptr = (u32) tx_cbd[tx_ct];
+ tx_ct++;
+ } else {
+ endpoints[ep]->tbase = 0;
+ endpoints[ep]->tbptr = 0;
+ }
+
+ endpoints[ep]->tstate = 0;
+ endpoints[ep]->tbcnt = 0;
+ endpoints[ep]->mrblr = EP_MAX_PKT;
+ endpoints[ep]->rfcr = 0x18;
+ endpoints[ep]->tfcr = 0x18;
+ ep_ref[ep].sc |= EP_ATTACHED;
+
+ DBG ("ep %d rbase 0x%08x rbptr 0x%08x tbase 0x%08x tbptr 0x%08x prx = %p\n",
+ ep, endpoints[ep]->rbase, endpoints[ep]->rbptr,
+ endpoints[ep]->tbase, endpoints[ep]->tbptr,
+ ep_ref[ep].prx);
+
+ return;
+}
+
+/* mpc8xx_udc_cbd_init
+ *
+ * Allocate space for a cbd and allocate TX/RX data space
+ */
+static void mpc8xx_udc_cbd_init (void)
+{
+ int i = 0;
+
+ for (; i < TX_RING_SIZE; i++) {
+ tx_cbd[i] = (cbd_t *)
+ mpc8xx_udc_alloc (sizeof (cbd_t), sizeof (int));
+ }
+
+ for (i = 0; i < RX_RING_SIZE; i++) {
+ rx_cbd[i] = (cbd_t *)
+ mpc8xx_udc_alloc (sizeof (cbd_t), sizeof (int));
+ }
+
+ for (i = 0; i < TX_RING_SIZE; i++) {
+ tx_cbd[i]->cbd_bufaddr =
+ mpc8xx_udc_alloc (EP_MAX_PKT, sizeof (int));
+
+ tx_cbd[i]->cbd_sc = (TX_BD_I | TX_BD_W);
+ tx_cbd[i]->cbd_datlen = 0x0000;
+ }
+
+
+ for (i = 0; i < RX_RING_SIZE; i++) {
+ rx_cbd[i]->cbd_bufaddr =
+ mpc8xx_udc_alloc (EP_MAX_PKT, sizeof (int));
+ rx_cbd[i]->cbd_sc = (RX_BD_I | RX_BD_E);
+ rx_cbd[i]->cbd_datlen = 0x0000;
+
+ }
+
+ return;
+}
+
+/* mpc8xx_udc_endpoint_init
+ *
+ * Attach an endpoint to some dpram
+ */
+static void mpc8xx_udc_endpoint_init (void)
+{
+ int i = 0;
+
+ for (; i < MAX_ENDPOINTS; i++) {
+ endpoints[i] = (usb_epb_t *)
+ mpc8xx_udc_alloc (sizeof (usb_epb_t), 32);
+ }
+}
+
+/* mpc8xx_udc_alloc
+ *
+ * Grab the address of some dpram
+ */
+static u32 mpc8xx_udc_alloc (u32 data_size, u32 alignment)
+{
+ u32 retaddr = address_base;
+
+ while (retaddr % alignment) {
+ retaddr++;
+ }
+ address_base += data_size;
+
+ return retaddr;
+}
+
+#endif /* CONFIG_MPC885_FAMILY && CONFIG_USB_DEVICE) */
diff --git a/drivers/usbdcore_omap1510.c b/drivers/usbdcore_omap1510.c
index 1d54a63..84bb936 100644
--- a/drivers/usbdcore_omap1510.c
+++ b/drivers/usbdcore_omap1510.c
@@ -1517,4 +1517,31 @@ void udc_startup_events (struct usb_device_instance *device)
udc_enable (device);
}
+/**
+ * udc_irq - do pseudo interrupts
+ */
+void udc_irq(void)
+{
+ /* Loop while we have interrupts.
+ * If we don't do this, the input chain
+ * polling delay is likely to miss
+ * host requests.
+ */
+ while (inw (UDC_IRQ_SRC) & ~UDC_SOF_Flg) {
+ /* Handle any new IRQs */
+ omap1510_udc_irq ();
+ omap1510_udc_noniso_irq ();
+ }
+}
+
+/* Flow control */
+void udc_set_nak(int epid)
+{
+ /* TODO: implement this functionality in omap1510 */
+}
+
+void udc_unset_nak (int epid)
+{
+ /* TODO: implement this functionality in omap1510 */
+}
#endif
diff --git a/drivers/usbtty.c b/drivers/usbtty.c
index ce4a12e..a3b5013 100644
--- a/drivers/usbtty.c
+++ b/drivers/usbtty.c
@@ -2,6 +2,9 @@
* (C) Copyright 2003
* Gerry Hamel, geh@ti.com, Texas Instruments
*
+ * (C) Copyright 2006
+ * Bryan O'Donoghue, bodonoghue@codehermit.ie
+ *
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
@@ -25,20 +28,42 @@
#include <circbuf.h>
#include <devices.h>
#include "usbtty.h"
+#include "usb_cdc_acm.h"
+#include "usbdescriptors.h"
+#include <config.h> /* If defined, override Linux identifiers with
+ * vendor specific ones */
#if 0
-#define TTYDBG(fmt,args...) serial_printf("[%s] %s %d: "fmt, __FILE__,__FUNCTION__,__LINE__,##args)
+#define TTYDBG(fmt,args...)\
+ serial_printf("[%s] %s %d: "fmt, __FILE__,__FUNCTION__,__LINE__,##args)
#else
#define TTYDBG(fmt,args...) do{}while(0)
#endif
-#if 0
-#define TTYERR(fmt,args...) serial_printf("ERROR![%s] %s %d: "fmt, __FILE__,__FUNCTION__,__LINE__,##args)
+#if 1
+#define TTYERR(fmt,args...)\
+ serial_printf("ERROR![%s] %s %d: "fmt, __FILE__,__FUNCTION__,\
+ __LINE__,##args)
#else
#define TTYERR(fmt,args...) do{}while(0)
#endif
/*
+ * Defines
+ */
+#define NUM_CONFIGS 1
+#define MAX_INTERFACES 2
+#define NUM_ENDPOINTS 3
+#define ACM_TX_ENDPOINT 3
+#define ACM_RX_ENDPOINT 2
+#define GSERIAL_TX_ENDPOINT 2
+#define GSERIAL_RX_ENDPOINT 1
+#define NUM_ACM_INTERFACES 2
+#define NUM_GSERIAL_INTERFACES 1
+#define CONFIG_USBD_DATA_INTERFACE_STR "Bulk Data Interface"
+#define CONFIG_USBD_CTRL_INTERFACE_STR "Control Interface"
+
+/*
* Buffers to hold input and output data
*/
#define USBTTY_BUFFER_SIZE 256
@@ -50,157 +75,336 @@ static circbuf_t usbtty_output;
* Instance variables
*/
static device_t usbttydev;
-static struct usb_device_instance device_instance[1];
-static struct usb_bus_instance bus_instance[1];
+static struct usb_device_instance device_instance[1];
+static struct usb_bus_instance bus_instance[1];
static struct usb_configuration_instance config_instance[NUM_CONFIGS];
-static struct usb_interface_instance interface_instance[NUM_INTERFACES];
-static struct usb_alternate_instance alternate_instance[NUM_INTERFACES];
-static struct usb_endpoint_instance endpoint_instance[NUM_ENDPOINTS+1]; /* one extra for control endpoint */
-
-/*
- * Static allocation of urbs
- */
-#define RECV_ENDPOINT 1
-#define TX_ENDPOINT 2
+static struct usb_interface_instance interface_instance[MAX_INTERFACES];
+static struct usb_alternate_instance alternate_instance[MAX_INTERFACES];
+/* one extra for control endpoint */
+static struct usb_endpoint_instance endpoint_instance[NUM_ENDPOINTS+1];
/*
* Global flag
*/
int usbtty_configured_flag = 0;
-
/*
* Serial number
*/
static char serial_number[16];
+
/*
- * Descriptors
+ * Descriptors, Strings, Local variables.
*/
+
+/* defined and used by usbdcore_ep0.c */
+extern struct usb_string_descriptor **usb_strings;
+
+/* Indicies, References */
+static unsigned short rx_endpoint = 0;
+static unsigned short tx_endpoint = 0;
+static unsigned short interface_count = 0;
+static struct usb_string_descriptor *usbtty_string_table[STR_COUNT];
+
+/* USB Descriptor Strings */
static u8 wstrLang[4] = {4,USB_DT_STRING,0x9,0x4};
static u8 wstrManufacturer[2 + 2*(sizeof(CONFIG_USBD_MANUFACTURER)-1)];
static u8 wstrProduct[2 + 2*(sizeof(CONFIG_USBD_PRODUCT_NAME)-1)];
static u8 wstrSerial[2 + 2*(sizeof(serial_number) - 1)];
static u8 wstrConfiguration[2 + 2*(sizeof(CONFIG_USBD_CONFIGURATION_STR)-1)];
-static u8 wstrInterface[2 + 2*(sizeof(CONFIG_USBD_INTERFACE_STR)-1)];
-
-static struct usb_string_descriptor *usbtty_string_table[] = {
- (struct usb_string_descriptor*)wstrLang,
- (struct usb_string_descriptor*)wstrManufacturer,
- (struct usb_string_descriptor*)wstrProduct,
- (struct usb_string_descriptor*)wstrSerial,
- (struct usb_string_descriptor*)wstrConfiguration,
- (struct usb_string_descriptor*)wstrInterface
-};
-extern struct usb_string_descriptor **usb_strings; /* defined and used by omap1510_ep0.c */
+static u8 wstrDataInterface[2 + 2*(sizeof(CONFIG_USBD_DATA_INTERFACE_STR)-1)];
+static u8 wstrCtrlInterface[2 + 2*(sizeof(CONFIG_USBD_DATA_INTERFACE_STR)-1)];
+/* Standard USB Data Structures */
+static struct usb_interface_descriptor interface_descriptors[MAX_INTERFACES];
+static struct usb_endpoint_descriptor *ep_descriptor_ptrs[NUM_ENDPOINTS];
+static struct usb_configuration_descriptor *configuration_descriptor = 0;
static struct usb_device_descriptor device_descriptor = {
- bLength: sizeof(struct usb_device_descriptor),
- bDescriptorType: USB_DT_DEVICE,
- bcdUSB: USB_BCD_VERSION,
- bDeviceClass: USBTTY_DEVICE_CLASS,
- bDeviceSubClass: USBTTY_DEVICE_SUBCLASS,
- bDeviceProtocol: USBTTY_DEVICE_PROTOCOL,
- bMaxPacketSize0: EP0_MAX_PACKET_SIZE,
- idVendor: CONFIG_USBD_VENDORID,
- idProduct: CONFIG_USBD_PRODUCTID,
- bcdDevice: USBTTY_BCD_DEVICE,
- iManufacturer: STR_MANUFACTURER,
- iProduct: STR_PRODUCT,
- iSerialNumber: STR_SERIAL,
- bNumConfigurations: NUM_CONFIGS
- };
-static struct usb_configuration_descriptor config_descriptors[NUM_CONFIGS] = {
- {
- bLength: sizeof(struct usb_configuration_descriptor),
- bDescriptorType: USB_DT_CONFIG,
- wTotalLength: (sizeof(struct usb_configuration_descriptor)*NUM_CONFIGS) +
- (sizeof(struct usb_interface_descriptor)*NUM_INTERFACES) +
- (sizeof(struct usb_endpoint_descriptor)*NUM_ENDPOINTS),
- bNumInterfaces: NUM_INTERFACES,
- bConfigurationValue: 1,
- iConfiguration: STR_CONFIG,
- bmAttributes: BMATTRIBUTE_SELF_POWERED | BMATTRIBUTE_RESERVED,
- bMaxPower: USBTTY_MAXPOWER
- },
-};
-static struct usb_interface_descriptor interface_descriptors[NUM_INTERFACES] = {
- {
- bLength: sizeof(struct usb_interface_descriptor),
- bDescriptorType: USB_DT_INTERFACE,
- bInterfaceNumber: 0,
- bAlternateSetting: 0,
- bNumEndpoints: NUM_ENDPOINTS,
- bInterfaceClass: USBTTY_INTERFACE_CLASS,
- bInterfaceSubClass: USBTTY_INTERFACE_SUBCLASS,
- bInterfaceProtocol: USBTTY_INTERFACE_PROTOCOL,
- iInterface: STR_INTERFACE
- },
+ .bLength = sizeof(struct usb_device_descriptor),
+ .bDescriptorType = USB_DT_DEVICE,
+ .bcdUSB = cpu_to_le16(USB_BCD_VERSION),
+ .bDeviceSubClass = 0x00,
+ .bDeviceProtocol = 0x00,
+ .bMaxPacketSize0 = EP0_MAX_PACKET_SIZE,
+ .idVendor = cpu_to_le16(CONFIG_USBD_VENDORID),
+ .bcdDevice = cpu_to_le16(USBTTY_BCD_DEVICE),
+ .iManufacturer = STR_MANUFACTURER,
+ .iProduct = STR_PRODUCT,
+ .iSerialNumber = STR_SERIAL,
+ .bNumConfigurations = NUM_CONFIGS
};
-static struct usb_endpoint_descriptor ep_descriptors[NUM_ENDPOINTS] = {
- {
- bLength: sizeof(struct usb_endpoint_descriptor),
- bDescriptorType: USB_DT_ENDPOINT,
- bEndpointAddress: CONFIG_USBD_SERIAL_OUT_ENDPOINT | USB_DIR_OUT,
- bmAttributes: USB_ENDPOINT_XFER_BULK,
- wMaxPacketSize: CONFIG_USBD_SERIAL_OUT_PKTSIZE,
- bInterval: 0
- },
- {
- bLength: sizeof(struct usb_endpoint_descriptor),
- bDescriptorType: USB_DT_ENDPOINT,
- bEndpointAddress: CONFIG_USBD_SERIAL_IN_ENDPOINT | USB_DIR_IN,
- bmAttributes: USB_ENDPOINT_XFER_BULK,
- wMaxPacketSize: CONFIG_USBD_SERIAL_IN_PKTSIZE,
- bInterval: 0
- },
- {
- bLength: sizeof(struct usb_endpoint_descriptor),
- bDescriptorType: USB_DT_ENDPOINT,
- bEndpointAddress: CONFIG_USBD_SERIAL_INT_ENDPOINT | USB_DIR_IN,
- bmAttributes: USB_ENDPOINT_XFER_INT,
- wMaxPacketSize: CONFIG_USBD_SERIAL_INT_PKTSIZE,
- bInterval: 0
- },
+
+
+/*
+ * Static CDC ACM specific descriptors
+ */
+
+struct acm_config_desc {
+ struct usb_configuration_descriptor configuration_desc;
+
+ /* Master Interface */
+ struct usb_interface_descriptor interface_desc;
+
+ struct usb_class_header_function_descriptor usb_class_header;
+ struct usb_class_call_management_descriptor usb_class_call_mgt;
+ struct usb_class_abstract_control_descriptor usb_class_acm;
+ struct usb_class_union_function_descriptor usb_class_union;
+ struct usb_endpoint_descriptor notification_endpoint;
+
+ /* Slave Interface */
+ struct usb_interface_descriptor data_class_interface;
+ struct usb_endpoint_descriptor
+ data_endpoints[NUM_ENDPOINTS-1] __attribute__((packed));
+} __attribute__((packed));
+
+static struct acm_config_desc acm_configuration_descriptors[NUM_CONFIGS] = {
+ {
+ .configuration_desc ={
+ .bLength =
+ sizeof(struct usb_configuration_descriptor),
+ .bDescriptorType = USB_DT_CONFIG,
+ .wTotalLength =
+ cpu_to_le16(sizeof(struct acm_config_desc)),
+ .bNumInterfaces = NUM_ACM_INTERFACES,
+ .bConfigurationValue = 1,
+ .iConfiguration = STR_CONFIG,
+ .bmAttributes =
+ BMATTRIBUTE_SELF_POWERED|BMATTRIBUTE_RESERVED,
+ .bMaxPower = USBTTY_MAXPOWER
+ },
+ /* Interface 1 */
+ .interface_desc = {
+ .bLength = sizeof(struct usb_interface_descriptor),
+ .bDescriptorType = USB_DT_INTERFACE,
+ .bInterfaceNumber = 0,
+ .bAlternateSetting = 0,
+ .bNumEndpoints = 0x01,
+ .bInterfaceClass =
+ COMMUNICATIONS_INTERFACE_CLASS_CONTROL,
+ .bInterfaceSubClass = COMMUNICATIONS_ACM_SUBCLASS,
+ .bInterfaceProtocol = COMMUNICATIONS_V25TER_PROTOCOL,
+ .iInterface = STR_CTRL_INTERFACE,
+ },
+ .usb_class_header = {
+ .bFunctionLength =
+ sizeof(struct usb_class_header_function_descriptor),
+ .bDescriptorType = CS_INTERFACE,
+ .bDescriptorSubtype = USB_ST_HEADER,
+ .bcdCDC = cpu_to_le16(110),
+ },
+ .usb_class_call_mgt = {
+ .bFunctionLength =
+ sizeof(struct usb_class_call_management_descriptor),
+ .bDescriptorType = CS_INTERFACE,
+ .bDescriptorSubtype = USB_ST_CMF,
+ .bmCapabilities = 0x00,
+ .bDataInterface = 0x01,
+ },
+ .usb_class_acm = {
+ .bFunctionLength =
+ sizeof(struct usb_class_abstract_control_descriptor),
+ .bDescriptorType = CS_INTERFACE,
+ .bDescriptorSubtype = USB_ST_ACMF,
+ .bmCapabilities = 0x00,
+ },
+ .usb_class_union = {
+ .bFunctionLength =
+ sizeof(struct usb_class_union_function_descriptor),
+ .bDescriptorType = CS_INTERFACE,
+ .bDescriptorSubtype = USB_ST_UF,
+ .bMasterInterface = 0x00,
+ .bSlaveInterface0 = 0x01,
+ },
+ .notification_endpoint = {
+ .bLength =
+ sizeof(struct usb_endpoint_descriptor),
+ .bDescriptorType = USB_DT_ENDPOINT,
+ .bEndpointAddress = 0x01 | USB_DIR_IN,
+ .bmAttributes = USB_ENDPOINT_XFER_INT,
+ .wMaxPacketSize
+ = cpu_to_le16(CONFIG_USBD_SERIAL_INT_PKTSIZE),
+ .bInterval = 0xFF,
+ },
+
+ /* Interface 2 */
+ .data_class_interface = {
+ .bLength =
+ sizeof(struct usb_interface_descriptor),
+ .bDescriptorType = USB_DT_INTERFACE,
+ .bInterfaceNumber = 0x01,
+ .bAlternateSetting = 0x00,
+ .bNumEndpoints = 0x02,
+ .bInterfaceClass =
+ COMMUNICATIONS_INTERFACE_CLASS_DATA,
+ .bInterfaceSubClass = DATA_INTERFACE_SUBCLASS_NONE,
+ .bInterfaceProtocol = DATA_INTERFACE_PROTOCOL_NONE,
+ .iInterface = STR_DATA_INTERFACE,
+ },
+ .data_endpoints = {
+ {
+ .bLength =
+ sizeof(struct usb_endpoint_descriptor),
+ .bDescriptorType = USB_DT_ENDPOINT,
+ .bEndpointAddress = 0x02 | USB_DIR_OUT,
+ .bmAttributes =
+ USB_ENDPOINT_XFER_BULK,
+ .wMaxPacketSize =
+ cpu_to_le16(CONFIG_USBD_SERIAL_BULK_PKTSIZE),
+ .bInterval = 0xFF,
+ },
+ {
+ .bLength =
+ sizeof(struct usb_endpoint_descriptor),
+ .bDescriptorType = USB_DT_ENDPOINT,
+ .bEndpointAddress = 0x03 | USB_DIR_IN,
+ .bmAttributes =
+ USB_ENDPOINT_XFER_BULK,
+ .wMaxPacketSize =
+ cpu_to_le16(CONFIG_USBD_SERIAL_BULK_PKTSIZE),
+ .bInterval = 0xFF,
+ },
+ },
+ },
};
-static struct usb_endpoint_descriptor *ep_descriptor_ptrs[NUM_ENDPOINTS] = {
- &(ep_descriptors[0]),
- &(ep_descriptors[1]),
- &(ep_descriptors[2]),
+
+static struct rs232_emu rs232_desc={
+ .dter = 115200,
+ .stop_bits = 0x00,
+ .parity = 0x00,
+ .data_bits = 0x08
};
-/* utility function for converting char* to wide string used by USB */
-static void str2wide (char *str, u16 * wide)
-{
- int i;
- for (i = 0; i < strlen (str) && str[i]; i++)
- wide[i] = (u16) str[i];
-}
+/*
+ * Static Generic Serial specific data
+ */
+
+
+struct gserial_config_desc {
+
+ struct usb_configuration_descriptor configuration_desc;
+ struct usb_interface_descriptor
+ interface_desc[NUM_GSERIAL_INTERFACES] __attribute__((packed));
+ struct usb_endpoint_descriptor
+ data_endpoints[NUM_ENDPOINTS] __attribute__((packed));
+
+} __attribute__((packed));
+
+static struct gserial_config_desc
+gserial_configuration_descriptors[NUM_CONFIGS] ={
+ {
+ .configuration_desc ={
+ .bLength = sizeof(struct usb_configuration_descriptor),
+ .bDescriptorType = USB_DT_CONFIG,
+ .wTotalLength =
+ cpu_to_le16(sizeof(struct gserial_config_desc)),
+ .bNumInterfaces = NUM_GSERIAL_INTERFACES,
+ .bConfigurationValue = 1,
+ .iConfiguration = STR_CONFIG,
+ .bmAttributes =
+ BMATTRIBUTE_SELF_POWERED|BMATTRIBUTE_RESERVED,
+ .bMaxPower = USBTTY_MAXPOWER
+ },
+ .interface_desc = {
+ {
+ .bLength =
+ sizeof(struct usb_interface_descriptor),
+ .bDescriptorType = USB_DT_INTERFACE,
+ .bInterfaceNumber = 0,
+ .bAlternateSetting = 0,
+ .bNumEndpoints = NUM_ENDPOINTS,
+ .bInterfaceClass =
+ COMMUNICATIONS_INTERFACE_CLASS_VENDOR,
+ .bInterfaceSubClass =
+ COMMUNICATIONS_NO_SUBCLASS,
+ .bInterfaceProtocol =
+ COMMUNICATIONS_NO_PROTOCOL,
+ .iInterface = STR_DATA_INTERFACE
+ },
+ },
+ .data_endpoints = {
+ {
+ .bLength =
+ sizeof(struct usb_endpoint_descriptor),
+ .bDescriptorType = USB_DT_ENDPOINT,
+ .bEndpointAddress = 0x01 | USB_DIR_OUT,
+ .bmAttributes = USB_ENDPOINT_XFER_BULK,
+ .wMaxPacketSize =
+ cpu_to_le16(CONFIG_USBD_SERIAL_OUT_PKTSIZE),
+ .bInterval= 0xFF,
+ },
+ {
+ .bLength =
+ sizeof(struct usb_endpoint_descriptor),
+ .bDescriptorType = USB_DT_ENDPOINT,
+ .bEndpointAddress = 0x02 | USB_DIR_IN,
+ .bmAttributes = USB_ENDPOINT_XFER_BULK,
+ .wMaxPacketSize =
+ cpu_to_le16(CONFIG_USBD_SERIAL_IN_PKTSIZE),
+ .bInterval = 0xFF,
+ },
+ {
+ .bLength =
+ sizeof(struct usb_endpoint_descriptor),
+ .bDescriptorType = USB_DT_ENDPOINT,
+ .bEndpointAddress = 0x03 | USB_DIR_IN,
+ .bmAttributes = USB_ENDPOINT_XFER_INT,
+ .wMaxPacketSize =
+ cpu_to_le16(CONFIG_USBD_SERIAL_INT_PKTSIZE),
+ .bInterval = 0xFF,
+ },
+ },
+ },
+};
/*
- * Prototypes
+ * Static Function Prototypes
*/
+
static void usbtty_init_strings (void);
static void usbtty_init_instances (void);
static void usbtty_init_endpoints (void);
-
+static void usbtty_init_terminal_type(short type);
static void usbtty_event_handler (struct usb_device_instance *device,
- usb_device_event_t event, int data);
+ usb_device_event_t event, int data);
+static int usbtty_cdc_setup(struct usb_device_request *request,
+ struct urb *urb);
static int usbtty_configured (void);
-
static int write_buffer (circbuf_t * buf);
static int fill_buffer (circbuf_t * buf);
void usbtty_poll (void);
-static void pretend_interrupts (void);
+/* utility function for converting char* to wide string used by USB */
+static void str2wide (char *str, u16 * wide)
+{
+ int i;
+ for (i = 0; i < strlen (str) && str[i]; i++){
+ #if defined(__LITTLE_ENDIAN)
+ wide[i] = (u16) str[i];
+ #elif defined(__BIG_ENDIAN)
+ wide[i] = ((u16)(str[i])<<8);
+ #else
+ #error "__LITTLE_ENDIAN or __BIG_ENDIAN undefined"
+ #endif
+ }
+}
/*
* Test whether a character is in the RX buffer
*/
+
int usbtty_tstc (void)
{
+ struct usb_endpoint_instance *endpoint =
+ &endpoint_instance[rx_endpoint];
+
+ /* If no input data exists, allow more RX to be accepted */
+ if(usbtty_input.size <= 0){
+ udc_unset_nak(endpoint->endpoint_address&0x03);
+ }
+
usbtty_poll ();
return (usbtty_input.size > 0);
}
@@ -210,15 +414,21 @@ int usbtty_tstc (void)
* otherwise. When the function is succesfull, the character read is
* written into its argument c.
*/
+
int usbtty_getc (void)
{
char c;
+ struct usb_endpoint_instance *endpoint =
+ &endpoint_instance[rx_endpoint];
while (usbtty_input.size <= 0) {
+ udc_unset_nak(endpoint->endpoint_address&0x03);
usbtty_poll ();
}
buf_pop (&usbtty_input, &c, 1);
+ udc_set_nak(endpoint->endpoint_address&0x03);
+
return c;
}
@@ -238,7 +448,6 @@ void usbtty_putc (const char c)
}
}
-
/* usbtty_puts() helper function for finding the next '\n' in a string */
static int next_nl_pos (const char *s)
{
@@ -252,8 +461,9 @@ static int next_nl_pos (const char *s)
}
/*
- * Output a string to the usb client port.
+ * Output a string to the usb client port - implementing flow control
*/
+
static void __usbtty_puts (const char *str, int len)
{
int maxlen = usbtty_output.totalsize;
@@ -261,22 +471,19 @@ static void __usbtty_puts (const char *str, int len)
/* break str into chunks < buffer size, if needed */
while (len > 0) {
- space = maxlen - usbtty_output.size;
+ usbtty_poll ();
+ space = maxlen - usbtty_output.size;
/* Empty buffer here, if needed, to ensure space... */
- if (space <= 0) {
+ if (space) {
write_buffer (&usbtty_output);
- space = maxlen - usbtty_output.size;
- if (space <= 0) {
- space = len; /* allow old data to be overwritten. */
- }
- }
- n = MIN (space, MIN (len, maxlen));
- buf_push (&usbtty_output, str, n);
+ n = MIN (space, MIN (len, maxlen));
+ buf_push (&usbtty_output, str, n);
- str += n;
- len -= n;
+ str += n;
+ len -= n;
+ }
}
}
@@ -313,8 +520,10 @@ int drv_usbtty_init (void)
{
int rc;
char * sn;
+ char * tt;
int snlen;
+ /* Ger seiral number */
if (!(sn = getenv("serial#"))) {
sn = "000000000000";
}
@@ -327,6 +536,14 @@ int drv_usbtty_init (void)
memcpy (serial_number, sn, snlen);
serial_number[snlen] = '\0';
+ /* Decide on which type of UDC device to be.
+ */
+
+ if(!(tt = getenv("usbtty"))) {
+ tt = "generic";
+ }
+ usbtty_init_terminal_type(strcmp(tt,"cdc_acm"));
+
/* prepare buffers... */
buf_init (&usbtty_input, USBTTY_BUFFER_SIZE);
buf_init (&usbtty_output, USBTTY_BUFFER_SIZE);
@@ -337,7 +554,7 @@ int drv_usbtty_init (void)
usbtty_init_strings ();
usbtty_init_instances ();
- udc_startup_events (device_instance); /* Enable our device, initialize udc pointers */
+ udc_startup_events (device_instance);/* Enable dev, init udc pointers */
udc_connect (); /* Enable pullup for host detection */
usbtty_init_endpoints ();
@@ -362,30 +579,48 @@ static void usbtty_init_strings (void)
{
struct usb_string_descriptor *string;
+ usbtty_string_table[STR_LANG] =
+ (struct usb_string_descriptor*)wstrLang;
+
string = (struct usb_string_descriptor *) wstrManufacturer;
- string->bLength = sizeof (wstrManufacturer);
+ string->bLength = sizeof(wstrManufacturer);
string->bDescriptorType = USB_DT_STRING;
str2wide (CONFIG_USBD_MANUFACTURER, string->wData);
+ usbtty_string_table[STR_MANUFACTURER]=string;
+
string = (struct usb_string_descriptor *) wstrProduct;
- string->bLength = sizeof (wstrProduct);
+ string->bLength = sizeof(wstrProduct);
string->bDescriptorType = USB_DT_STRING;
str2wide (CONFIG_USBD_PRODUCT_NAME, string->wData);
+ usbtty_string_table[STR_PRODUCT]=string;
+
string = (struct usb_string_descriptor *) wstrSerial;
- string->bLength = 2 + 2*strlen(serial_number);
+ string->bLength = sizeof(serial_number);
string->bDescriptorType = USB_DT_STRING;
str2wide (serial_number, string->wData);
+ usbtty_string_table[STR_SERIAL]=string;
+
string = (struct usb_string_descriptor *) wstrConfiguration;
- string->bLength = sizeof (wstrConfiguration);
+ string->bLength = sizeof(wstrConfiguration);
string->bDescriptorType = USB_DT_STRING;
str2wide (CONFIG_USBD_CONFIGURATION_STR, string->wData);
+ usbtty_string_table[STR_CONFIG]=string;
- string = (struct usb_string_descriptor *) wstrInterface;
- string->bLength = sizeof (wstrInterface);
+
+ string = (struct usb_string_descriptor *) wstrDataInterface;
+ string->bLength = sizeof(wstrDataInterface);
string->bDescriptorType = USB_DT_STRING;
- str2wide (CONFIG_USBD_INTERFACE_STR, string->wData);
+ str2wide (CONFIG_USBD_DATA_INTERFACE_STR, string->wData);
+ usbtty_string_table[STR_DATA_INTERFACE]=string;
+
+ string = (struct usb_string_descriptor *) wstrCtrlInterface;
+ string->bLength = sizeof(wstrCtrlInterface);
+ string->bDescriptorType = USB_DT_STRING;
+ str2wide (CONFIG_USBD_CTRL_INTERFACE_STR, string->wData);
+ usbtty_string_table[STR_CTRL_INTERFACE]=string;
/* Now, initialize the string table for ep0 handling */
usb_strings = usbtty_string_table;
@@ -400,6 +635,7 @@ static void usbtty_init_instances (void)
device_instance->device_state = STATE_INIT;
device_instance->device_descriptor = &device_descriptor;
device_instance->event = usbtty_event_handler;
+ device_instance->cdc_recv_setup = usbtty_cdc_setup;
device_instance->bus = bus_instance;
device_instance->configurations = NUM_CONFIGS;
device_instance->configuration_instance_array = config_instance;
@@ -415,8 +651,8 @@ static void usbtty_init_instances (void)
/* configuration instance */
memset (config_instance, 0,
sizeof (struct usb_configuration_instance));
- config_instance->interfaces = NUM_INTERFACES;
- config_instance->configuration_descriptor = config_descriptors;
+ config_instance->interfaces = interface_count;
+ config_instance->configuration_descriptor = configuration_descriptor;
config_instance->interface_instance_array = interface_instance;
/* interface instance */
@@ -447,17 +683,22 @@ static void usbtty_init_instances (void)
sizeof (struct usb_endpoint_instance));
endpoint_instance[i].endpoint_address =
- ep_descriptors[i - 1].bEndpointAddress;
+ ep_descriptor_ptrs[i - 1]->bEndpointAddress;
- endpoint_instance[i].rcv_packetSize =
- ep_descriptors[i - 1].wMaxPacketSize;
endpoint_instance[i].rcv_attributes =
- ep_descriptors[i - 1].bmAttributes;
+ ep_descriptor_ptrs[i - 1]->bmAttributes;
+
+ endpoint_instance[i].rcv_packetSize =
+ le16_to_cpu(ep_descriptor_ptrs[i - 1]->wMaxPacketSize);
+
+ endpoint_instance[i].tx_attributes =
+ ep_descriptor_ptrs[i - 1]->bmAttributes;
endpoint_instance[i].tx_packetSize =
- ep_descriptors[i - 1].wMaxPacketSize;
+ le16_to_cpu(ep_descriptor_ptrs[i - 1]->wMaxPacketSize);
+
endpoint_instance[i].tx_attributes =
- ep_descriptors[i - 1].bmAttributes;
+ ep_descriptor_ptrs[i - 1]->bmAttributes;
urb_link_init (&endpoint_instance[i].rcv);
urb_link_init (&endpoint_instance[i].rdy);
@@ -480,13 +721,79 @@ static void usbtty_init_endpoints (void)
int i;
bus_instance->max_endpoints = NUM_ENDPOINTS + 1;
- for (i = 0; i <= NUM_ENDPOINTS; i++) {
+ for (i = 1; i <= NUM_ENDPOINTS; i++) {
udc_setup_ep (device_instance, i, &endpoint_instance[i]);
}
}
+/* usbtty_init_terminal_type
+ *
+ * Do some late binding for our device type.
+ */
+static void usbtty_init_terminal_type(short type)
+{
+ switch(type){
+ /* CDC ACM */
+ case 0:
+ /* Assign endpoint descriptors */
+ ep_descriptor_ptrs[0] =
+ &acm_configuration_descriptors[0].notification_endpoint;
+ ep_descriptor_ptrs[1] =
+ &acm_configuration_descriptors[0].data_endpoints[0];
+ ep_descriptor_ptrs[2] =
+ &acm_configuration_descriptors[0].data_endpoints[1];
+
+ /* Enumerate Device Descriptor */
+ device_descriptor.bDeviceClass =
+ COMMUNICATIONS_DEVICE_CLASS;
+ device_descriptor.idProduct =
+ cpu_to_le16(CONFIG_USBD_PRODUCTID_CDCACM);
+
+ /* Assign endpoint indices */
+ tx_endpoint = ACM_TX_ENDPOINT;
+ rx_endpoint = ACM_RX_ENDPOINT;
+
+ /* Configuration Descriptor */
+ configuration_descriptor =
+ (struct usb_configuration_descriptor*)
+ &acm_configuration_descriptors;
+
+ /* Interface count */
+ interface_count = NUM_ACM_INTERFACES;
+ break;
+
+ /* BULK IN/OUT & Default */
+ case 1:
+ default:
+ /* Assign endpoint descriptors */
+ ep_descriptor_ptrs[0] =
+ &gserial_configuration_descriptors[0].data_endpoints[0];
+ ep_descriptor_ptrs[1] =
+ &gserial_configuration_descriptors[0].data_endpoints[1];
+ ep_descriptor_ptrs[2] =
+ &gserial_configuration_descriptors[0].data_endpoints[2];
+
+ /* Enumerate Device Descriptor */
+ device_descriptor.bDeviceClass = 0xFF;
+ device_descriptor.idProduct =
+ cpu_to_le16(CONFIG_USBD_PRODUCTID_GSERIAL);
+
+ /* Assign endpoint indices */
+ tx_endpoint = GSERIAL_TX_ENDPOINT;
+ rx_endpoint = GSERIAL_RX_ENDPOINT;
+
+ /* Configuration Descriptor */
+ configuration_descriptor =
+ (struct usb_configuration_descriptor*)
+ &gserial_configuration_descriptors;
+
+ /* Interface count */
+ interface_count = NUM_GSERIAL_INTERFACES;
+ break;
+ }
+}
-/*********************************************************************************/
+/******************************************************************************/
static struct urb *next_urb (struct usb_device_instance *device,
struct usb_endpoint_instance *endpoint)
@@ -526,27 +833,39 @@ static int write_buffer (circbuf_t * buf)
return 0;
}
- if (buf->size) {
+ struct usb_endpoint_instance *endpoint =
+ &endpoint_instance[tx_endpoint];
+ struct urb *current_urb = NULL;
- struct usb_endpoint_instance *endpoint =
- &endpoint_instance[TX_ENDPOINT];
- struct urb *current_urb = NULL;
+ current_urb = next_urb (device_instance, endpoint);
+ /* TX data still exists - send it now
+ */
+ if(endpoint->sent < current_urb->actual_length){
+ if(udc_endpoint_write (endpoint)){
+ /* Write pre-empted by RX */
+ return -1;
+ }
+ }
+
+ if (buf->size) {
char *dest;
int space_avail;
int popnum, popped;
int total = 0;
- /* Break buffer into urb sized pieces, and link each to the endpoint */
+ /* Break buffer into urb sized pieces,
+ * and link each to the endpoint
+ */
while (buf->size > 0) {
- current_urb = next_urb (device_instance, endpoint);
+
if (!current_urb) {
TTYERR ("current_urb is NULL, buf->size %d\n",
buf->size);
return total;
}
- dest = current_urb->buffer +
+ dest = (char*)current_urb->buffer +
current_urb->actual_length;
space_avail =
@@ -562,14 +881,19 @@ static int write_buffer (circbuf_t * buf)
current_urb->actual_length += popped;
total += popped;
- /* If endpoint->last == 0, then transfers have not started on this endpoint */
+ /* If endpoint->last == 0, then transfers have
+ * not started on this endpoint
+ */
if (endpoint->last == 0) {
- udc_endpoint_write (endpoint);
+ if(udc_endpoint_write (endpoint)){
+ /* Write pre-empted by RX */
+ return -1;
+ }
}
- } /* end while */
+ }/* end while */
return total;
- } /* end if tx_urb */
+ }
return 0;
}
@@ -577,18 +901,22 @@ static int write_buffer (circbuf_t * buf)
static int fill_buffer (circbuf_t * buf)
{
struct usb_endpoint_instance *endpoint =
- &endpoint_instance[RECV_ENDPOINT];
+ &endpoint_instance[rx_endpoint];
if (endpoint->rcv_urb && endpoint->rcv_urb->actual_length) {
- unsigned int nb = endpoint->rcv_urb->actual_length;
+ unsigned int nb = 0;
char *src = (char *) endpoint->rcv_urb->buffer;
+ unsigned int rx_avail = buf->totalsize - buf->size;
+
+ if(rx_avail >= endpoint->rcv_urb->actual_length){
- buf_push (buf, src, nb);
- endpoint->rcv_urb->actual_length = 0;
+ nb = endpoint->rcv_urb->actual_length;
+ buf_push (buf, src, nb);
+ endpoint->rcv_urb->actual_length = 0;
+ }
return nb;
}
-
return 0;
}
@@ -597,7 +925,7 @@ static int usbtty_configured (void)
return usbtty_configured_flag;
}
-/*********************************************************************************/
+/******************************************************************************/
static void usbtty_event_handler (struct usb_device_instance *device,
usb_device_event_t event, int data)
@@ -619,8 +947,34 @@ static void usbtty_event_handler (struct usb_device_instance *device,
}
}
-/*********************************************************************************/
+/******************************************************************************/
+
+int usbtty_cdc_setup(struct usb_device_request *request, struct urb *urb)
+{
+ switch (request->bRequest){
+
+ case ACM_SET_CONTROL_LINE_STATE: /* Implies DTE ready */
+ break;
+ case ACM_SEND_ENCAPSULATED_COMMAND : /* Required */
+ break;
+ case ACM_SET_LINE_ENCODING : /* DTE stop/parity bits
+ * per character */
+ break;
+ case ACM_GET_ENCAPSULATED_RESPONSE : /* request response */
+ break;
+ case ACM_GET_LINE_ENCODING : /* request DTE rate,
+ * stop/parity bits */
+ memcpy (urb->buffer , &rs232_desc, sizeof(rs232_desc));
+ urb->actual_length = sizeof(rs232_desc);
+
+ break;
+ default:
+ return 1;
+ }
+ return 0;
+}
+/******************************************************************************/
/*
* Since interrupt handling has not yet been implemented, we use this function
@@ -630,36 +984,29 @@ static void usbtty_event_handler (struct usb_device_instance *device,
void usbtty_poll (void)
{
/* New interrupts? */
- pretend_interrupts ();
+ udc_irq();
- /* Write any output data to host buffer (do this before checking interrupts to avoid missing one) */
+ /* Write any output data to host buffer
+ * (do this before checking interrupts to avoid missing one)
+ */
if (usbtty_configured ()) {
write_buffer (&usbtty_output);
}
/* New interrupts? */
- pretend_interrupts ();
+ udc_irq();
- /* Check for new data from host.. (do this after checking interrupts to get latest data) */
+ /* Check for new data from host..
+ * (do this after checking interrupts to get latest data)
+ */
if (usbtty_configured ()) {
fill_buffer (&usbtty_input);
}
/* New interrupts? */
- pretend_interrupts ();
-}
+ udc_irq();
-static void pretend_interrupts (void)
-{
- /* Loop while we have interrupts.
- * If we don't do this, the input chain
- * polling delay is likely to miss
- * host requests.
- */
- while (inw (UDC_IRQ_SRC) & ~UDC_SOF_Flg) {
- /* Handle any new IRQs */
- omap1510_udc_irq ();
- omap1510_udc_noniso_irq ();
- }
}
+
+
#endif
diff --git a/drivers/usbtty.h b/drivers/usbtty.h
index 79c2fe5..8154e30 100644
--- a/drivers/usbtty.h
+++ b/drivers/usbtty.h
@@ -2,6 +2,9 @@
* (C) Copyright 2003
* Gerry Hamel, geh@ti.com, Texas Instruments
*
+ * (C) Copyright 2006
+ * Bryan O'Donoghue, bodonoghue@codehermit.ie, CodeHermit
+ *
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
@@ -21,44 +24,47 @@
#ifndef __USB_TTY_H__
#define __USB_TTY_H__
-
#include "usbdcore.h"
+#if defined(CONFIG_PPC)
+#include "usbdcore_mpc8xx.h"
+#elif defined(CONFIG_ARM)
#include "usbdcore_omap1510.h"
+#endif
+#include <version_autogenerated.h>
-#define NUM_CONFIGS 1
-#define NUM_INTERFACES 1
-#define NUM_ENDPOINTS 3
+/* If no VendorID/ProductID is defined in config.h, pretend to be Linux
+ * DO NOT Reuse this Vendor/Product setup with protocol incompatible devices */
-#define EP0_MAX_PACKET_SIZE 64
+#define CONFIG_USBD_VENDORID 0x0525 /* Linux/NetChip */
+#define CONFIG_USBD_PRODUCTID_GSERIAL 0xa4a6 /* gserial */
+#define CONFIG_USBD_PRODUCTID_CDCACM 0xa4a7 /* CDC ACM */
+#define CONFIG_USBD_MANUFACTURER "Das U-Boot"
+#define CONFIG_USBD_PRODUCT_NAME U_BOOT_VERSION
-#define CONFIG_USBD_CONFIGURATION_STR "TTY via USB"
-#define CONFIG_USBD_INTERFACE_STR "Simple Serial Data Interface - Bulk Mode"
+#define CONFIG_USBD_CONFIGURATION_STR "TTY via USB"
-#define CONFIG_USBD_SERIAL_OUT_ENDPOINT 2
-#define CONFIG_USBD_SERIAL_OUT_PKTSIZE 64
-#define CONFIG_USBD_SERIAL_IN_ENDPOINT 1
-#define CONFIG_USBD_SERIAL_IN_PKTSIZE 64
-#define CONFIG_USBD_SERIAL_INT_ENDPOINT 5
-#define CONFIG_USBD_SERIAL_INT_PKTSIZE 16
-
+#define CONFIG_USBD_SERIAL_OUT_ENDPOINT UDC_OUT_ENDPOINT
+#define CONFIG_USBD_SERIAL_OUT_PKTSIZE UDC_OUT_PACKET_SIZE
+#define CONFIG_USBD_SERIAL_IN_ENDPOINT UDC_IN_ENDPOINT
+#define CONFIG_USBD_SERIAL_IN_PKTSIZE UDC_IN_PACKET_SIZE
+#define CONFIG_USBD_SERIAL_INT_ENDPOINT UDC_INT_ENDPOINT
+#define CONFIG_USBD_SERIAL_INT_PKTSIZE UDC_INT_PACKET_SIZE
+#define CONFIG_USBD_SERIAL_BULK_PKTSIZE UDC_BULK_PACKET_SIZE
#define USBTTY_DEVICE_CLASS COMMUNICATIONS_DEVICE_CLASS
-#define USBTTY_DEVICE_SUBCLASS COMMUNICATIONS_NO_SUBCLASS
-#define USBTTY_DEVICE_PROTOCOL COMMUNICATIONS_NO_PROTOCOL
-
-#define USBTTY_INTERFACE_CLASS 0xFF /* Vendor Specific */
-#define USBTTY_INTERFACE_SUBCLASS 0x02
-#define USBTTY_INTERFACE_PROTOCOL 0x01
-#define USBTTY_BCD_DEVICE 0x0
-#define USBTTY_MAXPOWER 0x0
+#define USBTTY_BCD_DEVICE 0x00
+#define USBTTY_MAXPOWER 0x00
-#define STR_MANUFACTURER 1
-#define STR_PRODUCT 2
-#define STR_SERIAL 3
-#define STR_CONFIG 4
-#define STR_INTERFACE 5
+#define STR_LANG 0x00
+#define STR_MANUFACTURER 0x01
+#define STR_PRODUCT 0x02
+#define STR_SERIAL 0x03
+#define STR_CONFIG 0x04
+#define STR_DATA_INTERFACE 0x05
+#define STR_CTRL_INTERFACE 0x06
+#define STR_COUNT 0x07
#endif