ENGR00315499-19 Fix eMMC fast boot hang issue

When booting in eMMC fast boot, the uboot v2013.04 always hangs.
The root cause is that MMC host does not exit from boot mode after
bootrom loading image. So the first command 'CMD0' sent
in uboot will pull down the CMD line to low and cause errors.

This patch cleans the MMC boot register in "mmc_init" to put the
MMC host back to normal mode.

Signed-off-by: Ye Li <b37916@freescale.com>
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>

1 files changed, 29 insertions, 8 deletions

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 4c3b93d..1f834d7 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
+ * Copyright 2007, 2010-2013 Freescale Semiconductor, Inc.
  * Andy Fleming
  *
  * Based vaguely on the pxa mmc code:
@@ -47,20 +47,30 @@ struct fsl_esdhc {
 	uint    fevt;		/* Force event register */
 	uint    admaes;		/* ADMA error status register */
 	uint    adsaddr;	/* ADMA system address register */
-	char    reserved2[160];	/* reserved */
+	char    reserved2[4];
+	uint    dllctrl;
+	uint    dllstat;
+	uint    clktunectrlstatus;
+	char    reserved3[84];
+	uint    vendorspec;
+	uint    mmcboot;
+	uint    vendorspec2;
+	char	reserved4[48];
 	uint    hostver;	/* Host controller version register */
-	char    reserved3[4];	/* reserved */
+#ifndef ARCH_MXC
+	char    reserved5[4];	/* reserved */
 	uint    dmaerraddr;	/* DMA error address register */
-	char    reserved4[4];	/* reserved */
+	char    reserved6[4];	/* reserved */
 	uint    dmaerrattr;	/* DMA error attribute register */
-	char    reserved5[4];	/* reserved */
+	char    reserved7[4];	/* reserved */
 	uint    hostcapblt2;	/* Host controller capabilities register 2 */
-	char    reserved6[8];	/* reserved */
+	char    reserved8[8];	/* reserved */
 	uint    tcr;		/* Tuning control register */
-	char    reserved7[28];	/* reserved */
+	char    reserved9[28];	/* reserved */
 	uint    sddirctl;	/* SD direction control register */
-	char    reserved8[712];	/* reserved */
+	char    reserved10[712];/* reserved */
 	uint    scr;		/* eSDHC control register */
+#endif
 };
 
 /* Return the XFERTYP flags for a given command and data packet */
@@ -484,6 +494,17 @@ static int esdhc_init(struct mmc *mmc)
 	while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
 		udelay(1000);
 
+#if defined(CONFIG_FSL_USDHC)
+	/* RSTA doesn't reset MMC_BOOT register, so manually reset it */
+	esdhc_write32(&regs->mmcboot, 0x0);
+	/* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */
+	esdhc_write32(&regs->mixctrl, 0x0);
+	esdhc_write32(&regs->clktunectrlstatus, 0x0);
+
+	/* Put VEND_SPEC to default value */
+	esdhc_write32(&regs->vendorspec, VENDORSPEC_INIT);
+#endif
+
 #ifndef ARCH_MXC
 	/* Enable cache snooping */
 	esdhc_write32(&regs->scr, 0x00000040);