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| author | Simon Glass <sjg@chromium.org> | 2013-03-11 06:08:06 +0000 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2013-03-19 08:45:37 -0700 |
| commit | 1e566bc6dbcfc9f13909d5cb40dd74925bcdd579 (patch) | |
| tree | 225721f4a7cdf6703a4b0408b1e63be1c649cc6f /drivers | |
| parent | 0c456cee952f3fa5ae6f5c42f960eeaa39140b62 (diff) | |
| download | u-boot-imx-1e566bc6dbcfc9f13909d5cb40dd74925bcdd579.zip u-boot-imx-1e566bc6dbcfc9f13909d5cb40dd74925bcdd579.tar.gz u-boot-imx-1e566bc6dbcfc9f13909d5cb40dd74925bcdd579.tar.bz2 | |
sf: Respect maximum SPI write size
Some SPI flash controllers (e.g. Intel ICH) have a limit on the number of
bytes that can be in a write transaction. Support this by breaking the
writes into multiple transactions.
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/mtd/spi/spi_flash.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index 17f3d3c..b82011d 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -87,6 +87,9 @@ int spi_flash_cmd_write_multi(struct spi_flash *flash, u32 offset, for (actual = 0; actual < len; actual += chunk_len) { chunk_len = min(len - actual, page_size - byte_addr); + if (flash->spi->max_write_size) + chunk_len = min(chunk_len, flash->spi->max_write_size); + cmd[1] = page_addr >> 8; cmd[2] = page_addr; cmd[3] = byte_addr; @@ -111,8 +114,11 @@ int spi_flash_cmd_write_multi(struct spi_flash *flash, u32 offset, if (ret) break; - page_addr++; - byte_addr = 0; + byte_addr += chunk_len; + if (byte_addr == page_size) { + page_addr++; + byte_addr = 0; + } } debug("SF: program %s %zu bytes @ %#x\n", |