Merge branch 'master' of git://www.denx.de/git/u-boot-sh

5 files changed, 423 insertions, 32 deletions

diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index fe45839..ad1b7dd 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -31,6 +31,9 @@ COBJS-y += pci_auto.o
 COBJS-y += pci_indirect.o
 COBJS-y += tsi108_pci.o
 COBJS-y += w83c553f.o
+COBJS-$(CONFIG_SH4_PCI) += pci_sh4.o
+COBJS-$(CONFIG_SH7751_PCI) +=pci_sh7751.o
+COBJS-$(CONFIG_SH7780_PCI) +=pci_sh7780.o
 
 COBJS	:= $(COBJS-y)
 SRCS 	:= $(COBJS:.o=.c)
diff --git a/drivers/pci/pci_sh4.c b/drivers/pci/pci_sh4.c
new file mode 100644
index 0000000..1290c0a
--- /dev/null
+++ b/drivers/pci/pci_sh4.c
@@ -0,0 +1,76 @@
+/*
+ * SH4 PCI Controller (PCIC) for U-Boot.
+ * (C) Dustin McIntire (dustin@sensoria.com)
+ * (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ * (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
+ *
+ * u-boot/cpu/sh4/pci-sh4.c
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+#include <pci.h>
+
+int pci_sh4_init(struct pci_controller *hose)
+{
+	hose->first_busno = 0;
+	hose->region_count = 0;
+	hose->last_busno = 0xff;
+
+	/* PCI memory space */
+	pci_set_region(hose->regions + 0,
+		CONFIG_PCI_MEM_BUS,
+		CONFIG_PCI_MEM_PHYS,
+		CONFIG_PCI_MEM_SIZE,
+		PCI_REGION_MEM);
+	hose->region_count++;
+
+	/* PCI IO space */
+	pci_set_region(hose->regions + 1,
+		CONFIG_PCI_IO_BUS,
+		CONFIG_PCI_IO_PHYS,
+		CONFIG_PCI_IO_SIZE,
+		PCI_REGION_IO);
+	hose->region_count++;
+
+	udelay(1000);
+
+	pci_set_ops(hose,
+		    pci_hose_read_config_byte_via_dword,
+		    pci_hose_read_config_word_via_dword,
+		    pci_sh4_read_config_dword,
+		    pci_hose_write_config_byte_via_dword,
+		    pci_hose_write_config_word_via_dword,
+		    pci_sh4_write_config_dword);
+
+	pci_register_hose(hose);
+
+	udelay(1000);
+
+#ifdef CONFIG_PCI_SCAN_SHOW
+	printf("PCI:   Bus Dev VenId DevId Class Int\n");
+#endif
+	hose->last_busno = pci_hose_scan(hose);
+	return 0;
+}
diff --git a/drivers/pci/pci_sh7751.c b/drivers/pci/pci_sh7751.c
new file mode 100644
index 0000000..a058e1d
--- /dev/null
+++ b/drivers/pci/pci_sh7751.c
@@ -0,0 +1,199 @@
+/*
+ * SH7751 PCI Controller (PCIC) for U-Boot.
+ * (C) Dustin McIntire (dustin@sensoria.com)
+ * (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <pci.h>
+
+/* Register addresses and such */
+#define SH7751_BCR1	(vu_long *)0xFF800000
+#define SH7751_BCR2	(vu_short*)0xFF800004
+#define SH7751_WCR1	(vu_long *)0xFF800008
+#define SH7751_WCR2	(vu_long *)0xFF80000C
+#define SH7751_WCR3	(vu_long *)0xFF800010
+#define SH7751_MCR	(vu_long *)0xFF800014
+#define SH7751_BCR3	(vu_short*)0xFF800050
+#define SH7751_PCICONF0 (vu_long *)0xFE200000
+#define SH7751_PCICONF1 (vu_long *)0xFE200004
+#define SH7751_PCICONF2 (vu_long *)0xFE200008
+#define SH7751_PCICONF3 (vu_long *)0xFE20000C
+#define SH7751_PCICONF4 (vu_long *)0xFE200010
+#define SH7751_PCICONF5 (vu_long *)0xFE200014
+#define SH7751_PCICONF6 (vu_long *)0xFE200018
+#define SH7751_PCICR    (vu_long *)0xFE200100
+#define SH7751_PCILSR0  (vu_long *)0xFE200104
+#define SH7751_PCILSR1  (vu_long *)0xFE200108
+#define SH7751_PCILAR0  (vu_long *)0xFE20010C
+#define SH7751_PCILAR1  (vu_long *)0xFE200110
+#define SH7751_PCIMBR   (vu_long *)0xFE2001C4
+#define SH7751_PCIIOBR  (vu_long *)0xFE2001C8
+#define SH7751_PCIPINT  (vu_long *)0xFE2001CC
+#define SH7751_PCIPINTM (vu_long *)0xFE2001D0
+#define SH7751_PCICLKR  (vu_long *)0xFE2001D4
+#define SH7751_PCIBCR1  (vu_long *)0xFE2001E0
+#define SH7751_PCIBCR2  (vu_long *)0xFE2001E4
+#define SH7751_PCIWCR1  (vu_long *)0xFE2001E8
+#define SH7751_PCIWCR2  (vu_long *)0xFE2001EC
+#define SH7751_PCIWCR3  (vu_long *)0xFE2001F0
+#define SH7751_PCIMCR   (vu_long *)0xFE2001F4
+#define SH7751_PCIBCR3  (vu_long *)0xFE2001F8
+
+#define BCR1_BREQEN				0x00080000
+#define PCI_SH7751_ID			0x35051054
+#define PCI_SH7751R_ID			0x350E1054
+#define SH7751_PCICONF1_WCC		0x00000080
+#define SH7751_PCICONF1_PER		0x00000040
+#define SH7751_PCICONF1_BUM		0x00000004
+#define SH7751_PCICONF1_MES		0x00000002
+#define SH7751_PCICONF1_CMDS	0x000000C6
+#define SH7751_PCI_HOST_BRIDGE	0x6
+#define SH7751_PCICR_PREFIX		0xa5000000
+#define SH7751_PCICR_PRST		0x00000002
+#define SH7751_PCICR_CFIN		0x00000001
+#define SH7751_PCIPINT_D3		0x00000002
+#define SH7751_PCIPINT_D0		0x00000001
+#define SH7751_PCICLKR_PREFIX   0xa5000000
+
+#define SH7751_PCI_MEM_BASE		0xFD000000
+#define SH7751_PCI_MEM_SIZE		0x01000000
+#define SH7751_PCI_IO_BASE		0xFE240000
+#define SH7751_PCI_IO_SIZE		0x00040000
+
+#define SH7751_CS3_BASE_ADDR    0x0C000000
+#define SH7751_P2CS3_BASE_ADDR  0xAC000000
+
+#define SH7751_PCIPAR   (vu_long *)0xFE2001C0
+#define SH7751_PCIPDR   (vu_long *)0xFE200220
+
+#define p4_in(addr)     *(addr)
+#define p4_out(data,addr) *(addr) = (data)
+
+/* Double word */
+int pci_sh4_read_config_dword(struct pci_controller *hose,
+			      pci_dev_t dev, int offset, u32 * value)
+{
+	u32 par_data = 0x80000000 | dev;
+
+	p4_out(par_data | (offset & 0xfc), SH7751_PCIPAR);
+	*value = p4_in(SH7751_PCIPDR);
+
+	return 0;
+}
+
+int pci_sh4_write_config_dword(struct pci_controller *hose,
+			       pci_dev_t dev, int offset, u32 * value)
+{
+	u32 par_data = 0x80000000 | dev;
+
+	p4_out(par_data | (offset & 0xfc), SH7751_PCIPAR);
+	p4_out(value, SH7751_PCIPDR);
+
+	return 0;
+}
+
+int pci_sh7751_init(struct pci_controller *hose)
+{
+	/* Double-check that we're a 7751 or 7751R chip */
+	if (p4_in(SH7751_PCICONF0) != PCI_SH7751_ID
+	    && p4_in(SH7751_PCICONF0) != PCI_SH7751R_ID) {
+		printf("PCI: Unknown PCI host bridge.\n");
+		return 1;
+	}
+	printf("PCI: SH7751 PCI host bridge found.\n");
+
+	/* Double-check some BSC config settings */
+	/* (Area 3 non-MPX 32-bit, PCI bus pins) */
+	if ((p4_in(SH7751_BCR1) & 0x20008) == 0x20000) {
+		printf("SH7751_BCR1 0x%08X\n", p4_in(SH7751_BCR1));
+		return 2;
+	}
+	if ((p4_in(SH7751_BCR2) & 0xC0) != 0xC0) {
+		printf("SH7751_BCR2 0x%08X\n", p4_in(SH7751_BCR2));
+		return 3;
+	}
+	if (p4_in(SH7751_BCR2) & 0x01) {
+		printf("SH7751_BCR2 0x%08X\n", p4_in(SH7751_BCR2));
+		return 4;
+	}
+
+	/* Force BREQEN in BCR1 to allow PCIC access */
+	p4_out((p4_in(SH7751_BCR1) | BCR1_BREQEN), SH7751_BCR1);
+
+	/* Toggle PCI reset pin */
+	p4_out((SH7751_PCICR_PREFIX | SH7751_PCICR_PRST), SH7751_PCICR);
+	udelay(32);
+	p4_out(SH7751_PCICR_PREFIX, SH7751_PCICR);
+
+	/* Set cmd bits: WCC, PER, BUM, MES */
+	/* (Addr/Data stepping, Parity enabled, Bus Master, Memory enabled) */
+	p4_out(0xfb900047, SH7751_PCICONF1);	/* K.Kino */
+
+	/* Define this host as the host bridge */
+	p4_out((SH7751_PCI_HOST_BRIDGE << 24), SH7751_PCICONF2);
+
+	/* Force PCI clock(s) on */
+	p4_out(0, SH7751_PCICLKR);
+	p4_out(0x03, SH7751_PCICLKR);
+
+	/* Clear powerdown IRQs, also mask them (unused) */
+	p4_out((SH7751_PCIPINT_D0 | SH7751_PCIPINT_D3), SH7751_PCIPINT);
+	p4_out(0, SH7751_PCIPINTM);
+
+	p4_out(0xab000001, SH7751_PCICONF4);
+
+	/* Set up target memory mappings (for external DMA access) */
+	/* Map both P0 and P2 range to Area 3 RAM for ease of use */
+	p4_out((64 - 1) << 20, SH7751_PCILSR0);
+	p4_out(SH7751_CS3_BASE_ADDR, SH7751_PCILAR0);
+	p4_out(0, SH7751_PCILSR1);
+	p4_out(0, SH7751_PCILAR1);
+	p4_out(SH7751_CS3_BASE_ADDR, SH7751_PCICONF5);
+	p4_out(0xd0000000, SH7751_PCICONF6);
+
+	/* Map memory window to same address on PCI bus */
+	p4_out(SH7751_PCI_MEM_BASE, SH7751_PCIMBR);
+
+	/* Map IO window to same address on PCI bus */
+	p4_out(0x2000 & 0xfffc0000, SH7751_PCIIOBR);
+
+	/* set BREQEN */
+	p4_out(inl(SH7751_BCR1) | 0x00080000, SH7751_BCR1);
+
+	/* Copy BSC registers into PCI BSC */
+	p4_out(inl(SH7751_BCR1), SH7751_PCIBCR1);
+	p4_out(inl(SH7751_BCR2), SH7751_PCIBCR2);
+	p4_out(inl(SH7751_BCR3), SH7751_PCIBCR3);
+	p4_out(inl(SH7751_WCR1), SH7751_PCIWCR1);
+	p4_out(inl(SH7751_WCR2), SH7751_PCIWCR2);
+	p4_out(inl(SH7751_WCR3), SH7751_PCIWCR3);
+	p4_out(inl(SH7751_MCR), SH7751_PCIMCR);
+
+	/* Finally, set central function init complete */
+	p4_out((SH7751_PCICR_PREFIX | SH7751_PCICR_CFIN), SH7751_PCICR);
+
+	pci_sh4_init(hose);
+
+	return 0;
+}
diff --git a/drivers/pci/pci_sh7780.c b/drivers/pci/pci_sh7780.c
new file mode 100644
index 0000000..d63d67d
--- /dev/null
+++ b/drivers/pci/pci_sh7780.c
@@ -0,0 +1,107 @@
+/*
+ * SH7780 PCI Controller (PCIC) for U-Boot.
+ * (C) Dustin McIntire (dustin@sensoria.com)
+ * (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ * (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <pci.h>
+
+#define SH7780_VENDOR_ID	0x1912
+#define SH7780_DEVICE_ID	0x0002
+#define SH7780_PCICR_PREFIX	0xA5000000
+#define SH7780_PCICR_PFCS	0x00000800
+#define SH7780_PCICR_FTO	0x00000400
+#define SH7780_PCICR_PFE	0x00000200
+#define SH7780_PCICR_TBS	0x00000100
+#define SH7780_PCICR_ARBM	0x00000040
+#define SH7780_PCICR_IOCS	0x00000004
+#define SH7780_PCICR_PRST	0x00000002
+#define SH7780_PCICR_CFIN	0x00000001
+
+#define p4_in(addr)			*((vu_long *)addr)
+#define p4_out(data,addr) 	*(vu_long *)(addr) = (data)
+#define p4_inw(addr)		*((vu_short *)addr)
+#define p4_outw(data,addr) 	*(vu_short *)(addr) = (data)
+
+int pci_sh4_read_config_dword(struct pci_controller *hose,
+				    pci_dev_t dev, int offset, u32 *value)
+{
+	u32 par_data = 0x80000000 | dev;
+
+	p4_out(par_data | (offset & 0xfc), SH7780_PCIPAR);
+	*value = p4_in(SH7780_PCIPDR);
+
+	return 0;
+}
+
+int pci_sh4_write_config_dword(struct pci_controller *hose,
+				     pci_dev_t dev, int offset, u32 value)
+{
+	u32 par_data = 0x80000000 | dev;
+
+	p4_out(par_data | (offset & 0xfc), SH7780_PCIPAR);
+	p4_out(value, SH7780_PCIPDR);
+	return 0;
+}
+
+int pci_sh7780_init(struct pci_controller *hose)
+{
+	p4_out(0x01, SH7780_PCIECR);
+
+	if (p4_inw(SH7780_PCIVID) != SH7780_VENDOR_ID
+	    && p4_inw(SH7780_PCIDID) != SH7780_DEVICE_ID){
+		printf("PCI: Unknown PCI host bridge.\n");
+		return;
+	}
+	printf("PCI: SH7780 PCI host bridge found.\n");
+
+	/* Toggle PCI reset pin */
+	p4_out((SH7780_PCICR_PREFIX | SH7780_PCICR_PRST), SH7780_PCICR);
+	udelay(100000);
+	p4_out(SH7780_PCICR_PREFIX, SH7780_PCICR);
+	p4_outw(0x0047, SH7780_PCICMD);
+
+	p4_out(0x07F00001, SH7780_PCILSR0);
+	p4_out(0x08000000, SH7780_PCILAR0);
+	p4_out(0x00000000, SH7780_PCILSR1);
+	p4_out(0, SH7780_PCILAR1);
+	p4_out(0x08000000, SH7780_PCIMBAR0);
+	p4_out(0x00000000, SH7780_PCIMBAR1);
+
+	p4_out(0xFD000000, SH7780_PCIMBR0);
+	p4_out(0x00FC0000, SH7780_PCIMBMR0);
+
+	/* if use Operand Cache then enable PCICSCR Soonp bits. */
+	p4_out(0x08000000, SH7780_PCICSAR0);
+	p4_out(0x0000001B, SH7780_PCICSCR0);	/* Snoop bit :On */
+
+	p4_out((SH7780_PCICR_PREFIX | SH7780_PCICR_CFIN | SH7780_PCICR_ARBM
+	      | SH7780_PCICR_FTO | SH7780_PCICR_PFCS | SH7780_PCICR_PFE),
+	     SH7780_PCICR);
+
+	pci_sh4_init(hose);
+	return 0;
+}
diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c
index 70fd23f..522f96d 100644
--- a/drivers/serial/serial_sh.c
+++ b/drivers/serial/serial_sh.c
@@ -37,39 +37,46 @@
 #define SCFCR	(vu_short *)(SCIF_BASE + 0x18)
 #define SCFDR	(vu_short *)(SCIF_BASE + 0x1C)
 #ifdef CONFIG_CPU_SH7720 /* SH7720 specific */
-#define SCFSR	(vu_short *)(SCIF_BASE + 0x14)   /* SCSSR */
-#define SCFTDR	(vu_char  *)(SCIF_BASE + 0x20)
-#define SCFRDR	(vu_char  *)(SCIF_BASE + 0x24)
+# define SCFSR	(vu_short *)(SCIF_BASE + 0x14) /* SCSSR */
+# define SCFTDR	(vu_char  *)(SCIF_BASE + 0x20)
+# define SCFRDR	(vu_char  *)(SCIF_BASE + 0x24)
 #else
-#define SCFTDR 	(vu_char  *)(SCIF_BASE + 0xC)
-#define SCFSR 	(vu_short *)(SCIF_BASE + 0x10)
-#define SCFRDR 	(vu_char  *)(SCIF_BASE + 0x14)
+# define SCFTDR (vu_char  *)(SCIF_BASE + 0xC)
+# define SCFSR 	(vu_short *)(SCIF_BASE + 0x10)
+# define SCFRDR (vu_char  *)(SCIF_BASE + 0x14)
 #endif
 
-#if defined(CONFIG_SH4A)
-#define SCRFDR	(vu_short *)(SCIF_BASE + 0x20)
-#define SCSPTR	(vu_short *)(SCIF_BASE + 0x24)
-#define SCLSR   (vu_short *)(SCIF_BASE + 0x28)
-#define SCRER	(vu_short *)(SCIF_BASE + 0x2C)
-#define LSR_ORER	1
-#elif defined (CONFIG_SH4)
-#define SCSPTR 	(vu_short *)(SCIF_BASE + 0x20)
-#define SCLSR 	(vu_short *)(SCIF_BASE + 0x24)
-#define LSR_ORER	1
-#elif defined (CONFIG_SH3)
-#ifdef CONFIG_CPU_SH7720 /* SH7720 specific */
-#define SCLSR   (vu_short *)(SCIF_BASE + 0x24)
-#define LSR_ORER	0x0200
-#else
-#define SCLSR	SCFSR	/* SCSSR */
-#define LSR_ORER	1
-#endif
+#if defined(CONFIG_CPU_SH7780) || \
+	defined(CONFIG_CPU_SH7785)
+# define SCRFDR	(vu_short *)(SCIF_BASE + 0x20)
+# define SCSPTR	(vu_short *)(SCIF_BASE + 0x24)
+# define SCLSR   (vu_short *)(SCIF_BASE + 0x28)
+# define SCRER	(vu_short *)(SCIF_BASE + 0x2C)
+# define LSR_ORER	1
+# define FIFOLEVEL_MASK	0xFF
+#elif defined(CONFIG_CPU_SH7750) || \
+	defined(CONFIG_CPU_SH7751) || \
+	defined(CONFIG_CPU_SH7722)
+# define SCSPTR 	(vu_short *)(SCIF_BASE + 0x20)
+# define SCLSR 	(vu_short *)(SCIF_BASE + 0x24)
+# define LSR_ORER	1
+# define FIFOLEVEL_MASK	0x1F
+#elif defined(CONFIG_CPU_SH7720)
+# define SCLSR   (vu_short *)(SCIF_BASE + 0x24)
+# define LSR_ORER	0x0200
+# define FIFOLEVEL_MASK	0x1F
+#elif defined(CONFIG_CPU_SH7710)
+	defined(CONFIG_CPU_SH7712)
+# define SCLSR	SCFSR	/* SCSSR */
+# define LSR_ORER	1
+# define FIFOLEVEL_MASK	0x1F
 #endif
 
+/* SCBRR register value setting */
 #if defined(CONFIG_CPU_SH7720)
-#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
+# define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
 #else	/* Generic SuperH */
-#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
+# define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
 #endif
 
 #define SCR_RE 		(1 << 4)
@@ -105,14 +112,13 @@ int serial_init (void)
 	return 0;
 }
 
-static int serial_tx_fifo_level (void)
-{
-	return (*SCFDR >> 8) & 0x1F;
-}
-
 static int serial_rx_fifo_level (void)
 {
-	return (*SCFDR >> 0) & 0x1F;
+#if defined(CONFIG_SH4A)
+	return (*SCRFDR >> 0) & FIFOLEVEL_MASK;
+#else
+	return (*SCFDR >> 0) & FIFOLEVEL_MASK;
+#endif
 }
 
 void serial_raw_putc (const char c)