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authorSammy He <r62914@freescale.com>2009-11-26 18:55:02 +0800
committerSammy He <r62914@freescale.com>2009-11-26 19:17:00 +0800
commit078cdf97a1ec61134f0c924a209520dfd7f63c5f (patch)
treed84e5845508883efd6f930ada95af6cd9de7c23d /drivers
parent758e16168151f671ee8c97790392bfc8e0746866 (diff)
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ENGR00118816 Fix reboot/reset failure with image on nand
Reset CPLD registers to fix reboot/reset failure issue. Signed-off-by: Sammy He <r62914@freescale.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/spi/imx_spi_cpld.c28
1 files changed, 28 insertions, 0 deletions
diff --git a/drivers/spi/imx_spi_cpld.c b/drivers/spi/imx_spi_cpld.c
index 2e20b9c..6e1e556 100644
--- a/drivers/spi/imx_spi_cpld.c
+++ b/drivers/spi/imx_spi_cpld.c
@@ -27,9 +27,22 @@
#include <linux/types.h>
#include <imx_spi.h>
+#include <asm/arch/imx_spi_cpld.h>
static struct spi_slave *cpld_slave;
+void cpld_reg_write(u32 offset, u32 val)
+{
+ cpld_reg_xfer(offset, val, 0);
+ cpld_reg_xfer(offset + 0x2, (val >> 16), 0);
+}
+
+u32 cpld_reg_read(u32 offset)
+{
+ return cpld_reg_xfer(offset, 0x0, 1) | \
+ (cpld_reg_xfer(offset + 0x2, 0x0, 1) << 16);
+}
+
/*!
* To read/write to a CPLD register.
*
@@ -74,7 +87,22 @@ unsigned int cpld_reg_xfer(unsigned int reg, unsigned int val,
struct spi_slave *spi_cpld_probe()
{
+ u32 reg;
cpld_slave = spi_setup_slave(0, 0, 25000000, 0);
+
+ udelay(1000);
+
+ /* Reset interrupt status reg */
+ cpld_reg_write(PBC_INT_REST, 0x1F);
+ cpld_reg_write(PBC_INT_REST, 0);
+ cpld_reg_write(PBC_INT_MASK, 0xFFFF);
+ /* Reset the XUART and Ethernet controllers */
+ reg = cpld_reg_read(PBC_SW_RESET);
+ reg |= 0x9;
+ cpld_reg_write(PBC_SW_RESET, reg);
+ reg &= ~0x9;
+ cpld_reg_write(PBC_SW_RESET, reg);
+
return cpld_slave;
}