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author | Peter Pearse <peter.pearse@arm.com> | 2007-05-18 14:34:19 +0100 |
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committer | Peter Pearse <peter.pearse@arm.com> | 2007-05-18 14:34:19 +0100 |
commit | 879027daa838d245bf433ca2bb446bedace724f0 (patch) | |
tree | 663792e944d667843d77f81dd3d5ab56ffa7f098 /drivers | |
parent | 93ef45c9ddfdd9fc17c4e74bd8e2f2456580eb72 (diff) | |
parent | 70124c2602ae2d4c5d3dba05b482d91548242de8 (diff) | |
download | u-boot-imx-879027daa838d245bf433ca2bb446bedace724f0.zip u-boot-imx-879027daa838d245bf433ca2bb446bedace724f0.tar.gz u-boot-imx-879027daa838d245bf433ca2bb446bedace724f0.tar.bz2 |
Merge with git://www.denx.de/git/u-boot.git
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/systemace.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/systemace.c b/drivers/systemace.c index 3848d9c..7d82c27 100644 --- a/drivers/systemace.c +++ b/drivers/systemace.c @@ -211,10 +211,16 @@ static unsigned long systemace_read(int dev, unsigned long start, /* Write sector count | ReadMemCardData. */ ace_writew((trans & 0xff) | 0x0300, 0x14); +/* + * For FPGA configuration via SystemACE is reset unacceptable + * CFGDONE bit in STATUSREG is not set to 1. + */ +#ifndef SYSTEMACE_CONFIG_FPGA /* Reset the configruation controller */ val = ace_readw(0x18); val |= 0x0080; ace_writew(val, 0x18); +#endif retry = trans * 16; while (retry > 0) { |