ENGR00152755 MX6 Switch DRAM init script from plugin to DCD for emmc fastboot

ROM requires DCD table instead of plugin to initialize DRAM if emmc fastboot
mode is to be used. Therefore, switched the DRAM script from plugin to
DCD table. The DCD table created is based on the following RVD script:
Arik_init_DDR3_528MHz_002.inc found at
http://compass.freescale.net/livelink/livelink?func=ll&objId=222928845

When fastboot mode is used by ROM, the MMC_BOOT register of USDHC does not
get reset when RSTA bit is set by uboot driver. Therefore, need to write 0
to it manually during driver init. This brings USDHC out of fastboot mode,
allowing normal communication with emmc to proceed in uboot.

Changed comments for DLL delay to be more accurate.

Signed-off-by: Anish Trivedi <anish@freescale.com>

1 files changed, 6 insertions, 2 deletions

diff --git a/drivers/mmc/imx_esdhc.c b/drivers/mmc/imx_esdhc.c
index d086949..093a1b2 100644
--- a/drivers/mmc/imx_esdhc.c
+++ b/drivers/mmc/imx_esdhc.c
@@ -74,7 +74,8 @@ struct fsl_esdhc {
 	uint dllstatus;
 	char	reserved3[88];
 	uint vendorspec;
-	char	reserved4[56];
+	uint	mmcboot;
+	char	reserved4[52];
 	uint	hostver;
 };
 
@@ -362,7 +363,7 @@ static void esdhc_dll_setup(struct mmc *mmc)
 
 /* For DDR mode operation, provide target delay parameter for each SD port.
  * Use cfg->esdhc_base to distinguish the SD port #. The delay for each port
- * is dependent on trace lengths for that particular port. If the following
+ * is dependent on signal layout for that particular port. If the following
  * CONFIG is not defined, then the default target delay value will be used.
  */
 #ifdef CONFIG_GET_DDR_TARGET_DELAY
@@ -474,6 +475,9 @@ static int esdhc_init(struct mmc *mmc)
 	while (readl(&regs->sysctl) & SYSCTL_RSTA)
 		;
 
+	/* RSTA doesn't reset MMC_BOOT register, so manually reset it */
+	writel(0, &regs->mmcboot);
+
 #ifdef CONFIG_IMX_ESDHC_V1
 	tmp = readl(&regs->sysctl) | (SYSCTL_HCKEN | SYSCTL_IPGEN);
 	writel(tmp, &regs->sysctl);