Merge branch 'master' of /home/stefan/git/u-boot/u-boot

28 files changed, 1711 insertions, 93 deletions

diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
index cebb2ba..065433a 100644
--- a/drivers/hwmon/Makefile
+++ b/drivers/hwmon/Makefile
@@ -34,6 +34,7 @@ COBJS-y += adm1021.o
 COBJS-y += ds1621.o
 COBJS-y += ds1722.o
 COBJS-y += ds1775.o
+COBJS-$(CONFIG_DTT_LM73) += lm73.o
 COBJS-y += lm75.o
 COBJS-y += lm81.o
 
diff --git a/drivers/hwmon/ds1775.c b/drivers/hwmon/ds1775.c
index e44cee3..0fbb0b4 100644
--- a/drivers/hwmon/ds1775.c
+++ b/drivers/hwmon/ds1775.c
@@ -25,7 +25,7 @@
 #include <i2c.h>
 #include <dtt.h>
 
-#define DTT_I2C_DEV_CODE 0x49		/* Dallas Semi's DS1775 device code */
+#define DTT_I2C_DEV_CODE	CFG_I2C_DTT_ADDR /* Dallas Semi's DS1775 device code */
 
 int dtt_read(int sensor, int reg)
 {
diff --git a/drivers/hwmon/lm73.c b/drivers/hwmon/lm73.c
new file mode 100644
index 0000000..db8ef66
--- /dev/null
+++ b/drivers/hwmon/lm73.c
@@ -0,0 +1,172 @@
+/*
+ * (C) Copyright 2007
+ * Larry Johnson, lrj@acm.org
+ *
+ * based on dtt/lm75.c which is ...
+ *
+ * (C) Copyright 2001
+ * Bill Hunter,  Wave 7 Optics, williamhunter@mediaone.net
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * National Semiconductor LM73 Temperature Sensor
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <dtt.h>
+
+/*
+ * Device code
+ */
+#define DTT_I2C_DEV_CODE 0x48	/* National Semi's LM73 device */
+
+int dtt_read(int sensor, int reg)
+{
+	int dlen;
+	uchar data[2];
+
+	/*
+	 * Validate 'reg' param and get register size.
+	 */
+	switch (reg) {
+	case DTT_CONFIG:
+	case DTT_CONTROL:
+		dlen = 1;
+		break;
+	case DTT_READ_TEMP:
+	case DTT_TEMP_HIGH:
+	case DTT_TEMP_LOW:
+	case DTT_ID:
+		dlen = 2;
+		break;
+	default:
+		return -1;
+	}
+	/*
+	 * Calculate sensor address and register.
+	 */
+	sensor = DTT_I2C_DEV_CODE + (sensor & 0x07);	/* calculate LM73 addr */
+	/*
+	 * Now try to read the register.
+	 */
+	if (i2c_read(sensor, reg, 1, data, dlen) != 0)
+		return -1;
+	/*
+	 * Handle 2 byte result.
+	 */
+	if (2 == dlen)
+		return ((int)((short)data[1] + (((short)data[0]) << 8)));
+
+	return (int)data[0];
+} /* dtt_read() */
+
+int dtt_write(int sensor, int reg, int val)
+{
+	int dlen;
+	uchar data[2];
+
+	/*
+	 * Validate 'reg' param and handle register size
+	 */
+	switch (reg) {
+	case DTT_CONFIG:
+	case DTT_CONTROL:
+		dlen = 1;
+		data[0] = (char)(val & 0xff);
+		break;
+	case DTT_TEMP_HIGH:
+	case DTT_TEMP_LOW:
+		dlen = 2;
+		data[0] = (char)((val >> 8) & 0xff);	/* MSB first */
+		data[1] = (char)(val & 0xff);
+		break;
+	default:
+		return -1;
+	}
+	/*
+	 * Calculate sensor address and register.
+	 */
+	sensor = DTT_I2C_DEV_CODE + (sensor & 0x07);	/* calculate LM73 addr */
+	/*
+	 * Write value to register.
+	 */
+	return i2c_write(sensor, reg, 1, data, dlen) != 0;
+} /* dtt_write() */
+
+static int _dtt_init(int sensor)
+{
+	int val;
+
+	/*
+	 * Validate the Identification register
+	 */
+	if (0x0190 != dtt_read(sensor, DTT_ID))
+		return 1;
+	/*
+	 * Setup THIGH (upper-limit) and TLOW (lower-limit) registers
+	 */
+	val = CFG_DTT_MAX_TEMP << 7;
+	if (dtt_write(sensor, DTT_TEMP_HIGH, val))
+		return 1;
+
+	val = CFG_DTT_MIN_TEMP << 7;
+	if (dtt_write(sensor, DTT_TEMP_LOW, val))
+		return 1;
+	/*
+	 * Setup configuraton register
+	 */
+	/* config = alert active low, disabled, and reset */
+	val = 0x64;
+	if (dtt_write(sensor, DTT_CONFIG, val))
+		return 1;
+	/*
+	 * Setup control/status register
+	 */
+	/* control = temp resolution 0.25C */
+	val = 0x00;
+	if (dtt_write(sensor, DTT_CONTROL, val))
+		return 1;
+
+	dtt_read(sensor, DTT_CONTROL);	/* clear temperature flags */
+	return 0;
+} /* _dtt_init() */
+
+int dtt_init(void)
+{
+	int i;
+	unsigned char sensors[] = CONFIG_DTT_SENSORS;
+	const char *const header = "DTT:   ";
+
+	for (i = 0; i < sizeof(sensors); i++) {
+		if (_dtt_init(sensors[i]) != 0)
+			printf("%s%d FAILED INIT\n", header, i + 1);
+		else
+			printf("%s%d is %i C\n", header, i + 1,
+			       dtt_get_temp(sensors[i]));
+	}
+	return 0;
+} /* dtt_init() */
+
+int dtt_get_temp(int sensor)
+{
+	return (dtt_read(sensor, DTT_READ_TEMP) + 0x0040) >> 7;
+} /* dtt_get_temp() */
diff --git a/drivers/mtd/nand/nand_util.c b/drivers/mtd/nand/nand_util.c
index 4fd4e16..6c5624a 100644
--- a/drivers/mtd/nand/nand_util.c
+++ b/drivers/mtd/nand/nand_util.c
@@ -1,5 +1,5 @@
 /*
- * drivers/nand/nand_util.c
+ * drivers/mtd/nand/nand_util.c
  *
  * Copyright (C) 2006 by Weiss-Electronic GmbH.
  * All rights reserved.
diff --git a/drivers/net/dc2114x.c b/drivers/net/dc2114x.c
index d5275dc..7238922 100644
--- a/drivers/net/dc2114x.c
+++ b/drivers/net/dc2114x.c
@@ -332,7 +332,7 @@ static int dc21x4x_init(struct eth_device* dev, bd_t* bis)
 
 	if ((INL(dev, DE4X5_STS) & (STS_TS | STS_RS)) != 0) {
 		printf("Error: Cannot reset ethernet controller.\n");
-		return 0;
+		return -1;
 	}
 
 #ifdef CONFIG_TULIP_SELECT_MEDIA
@@ -382,7 +382,7 @@ static int dc21x4x_init(struct eth_device* dev, bd_t* bis)
 
 	send_setup_frame(dev, bis);
 
-	return 1;
+	return 0;
 }
 
 static int dc21x4x_send(struct eth_device* dev, volatile void *packet, int length)
diff --git a/drivers/net/eepro100.c b/drivers/net/eepro100.c
index 738146e..96ed271 100644
--- a/drivers/net/eepro100.c
+++ b/drivers/net/eepro100.c
@@ -485,7 +485,7 @@ int eepro100_initialize (bd_t * bis)
 
 static int eepro100_init (struct eth_device *dev, bd_t * bis)
 {
-	int i, status = 0;
+	int i, status = -1;
 	int tx_cur;
 	struct descriptor *ias_cmd, *cfg_cmd;
 
@@ -598,7 +598,7 @@ static int eepro100_init (struct eth_device *dev, bd_t * bis)
 		goto Done;
 	}
 
-	status = 1;
+	status = 0;
 
   Done:
 	return status;
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index 95cdc49..6657d22 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -423,12 +423,12 @@ static int macb_init(struct eth_device *netdev, bd_t *bd)
 #endif
 
 	if (!macb_phy_init(macb))
-		return 0;
+		return -1;
 
 	/* Enable TX and RX */
 	macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE));
 
-	return 1;
+	return 0;
 }
 
 static void macb_halt(struct eth_device *netdev)
diff --git a/drivers/net/ne2000.c b/drivers/net/ne2000.c
index c978d62..b100657 100644
--- a/drivers/net/ne2000.c
+++ b/drivers/net/ne2000.c
@@ -839,7 +839,7 @@ void uboot_push_packet_len(int len) {
 	}
 	dp83902a_recv(&pbuf[0], len);
 
-	/*Just pass it to the upper layer*/
+	/* Just pass it to the upper layer */
 	NetReceive(&pbuf[0], len);
 }
 
@@ -902,7 +902,6 @@ int eth_init(bd_t *bd) {
 }
 
 void eth_halt() {
-
 	PRINTK("### eth_halt\n");
 	if(initialized)
 		dp83902a_stop();
@@ -910,8 +909,8 @@ void eth_halt() {
 }
 
 int eth_rx() {
-dp83902a_poll();
-return 1;
+	dp83902a_poll();
+	return 1;
 }
 
 int eth_send(volatile void *packet, int length) {
diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c
index 2af0e8f..4e270c9 100644
--- a/drivers/net/pcnet.c
+++ b/drivers/net/pcnet.c
@@ -402,7 +402,7 @@ static int pcnet_init(struct eth_device* dev, bd_t *bis)
     if (i <= 0) {
 	printf("%s: TIMEOUT: controller init failed\n", dev->name);
 	pcnet_reset (dev);
-	return 0;
+	return -1;
     }
 
     /*
@@ -410,7 +410,7 @@ static int pcnet_init(struct eth_device* dev, bd_t *bis)
      */
     pcnet_write_csr (dev, 0, 0x0002);
 
-    return 1;
+    return 0;
 }
 
 static int pcnet_send(struct eth_device* dev, volatile void *packet, int pkt_len)
diff --git a/drivers/net/rtl8139.c b/drivers/net/rtl8139.c
index 2367180..4c24805 100644
--- a/drivers/net/rtl8139.c
+++ b/drivers/net/rtl8139.c
@@ -273,10 +273,10 @@ static int rtl8139_probe(struct eth_device *dev, bd_t *bis)
 
 	if (inb(ioaddr + MediaStatus) & MSRLinkFail) {
 		printf("Cable not connected or other link failure\n");
-		return(0);
+		return -1 ;
 	}
 
-	return 1;
+	return 0;
 }
 
 /* Serial EEPROM section. */
diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c
index 63ea2cc..57ccbd9 100644
--- a/drivers/net/rtl8169.c
+++ b/drivers/net/rtl8169.c
@@ -48,7 +48,10 @@
 *
 *    Indent Options: indent -kr -i8
 ***************************************************************************/
-
+/*
+ * 26 August 2006 Mihai Georgian <u-boot@linuxnotincluded.org.uk>
+ * Modified to use le32_to_cpu and cpu_to_le32 properly
+ */
 #include <common.h>
 #include <malloc.h>
 #include <net.h>
@@ -68,12 +71,7 @@
 static u32 ioaddr;
 
 /* Condensed operations for readability. */
-#define virt_to_le32desc(addr)	cpu_to_le32(virt_to_bus(addr))
-#define le32desc_to_virt(addr)	bus_to_virt(le32_to_cpu(addr))
-
 #define currticks()	get_timer(0)
-#define bus_to_phys(a)	pci_mem_to_phys((pci_dev_t)dev->priv, a)
-#define phys_to_bus(a)	pci_phys_to_mem((pci_dev_t)dev->priv, a)
 
 /* media options */
 #define MAX_UNITS 8
@@ -102,7 +100,7 @@ static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
 #define RTL_MIN_IO_SIZE 0x80
 #define TX_TIMEOUT  (6*HZ)
 
-/* write/read MMIO register */
+/* write/read MMIO register. Notice: {read,write}[wl] do the necessary swapping */
 #define RTL_W8(reg, val8)	writeb ((val8), ioaddr + (reg))
 #define RTL_W16(reg, val16)	writew ((val16), ioaddr + (reg))
 #define RTL_W32(reg, val32)	writel ((val32), ioaddr + (reg))
@@ -218,7 +216,7 @@ enum RTL8169_register_content {
 	PHY_Enable_Auto_Nego = 0x1000,
 
 	/* PHY_STAT_REG = 1; */
-	PHY_Auto_Neco_Comp = 0x0020,
+	PHY_Auto_Nego_Comp = 0x0020,
 
 	/* PHY_AUTO_NEGO_REG = 4; */
 	PHY_Cap_10_Half = 0x0020,
@@ -413,23 +411,23 @@ static int rtl_recv(struct eth_device *dev)
 	ioaddr = dev->iobase;
 
 	cur_rx = tpc->cur_rx;
-	if ((tpc->RxDescArray[cur_rx].status & OWNbit) == 0) {
-		if (!(tpc->RxDescArray[cur_rx].status & RxRES)) {
+	if ((le32_to_cpu(tpc->RxDescArray[cur_rx].status) & OWNbit) == 0) {
+		if (!(le32_to_cpu(tpc->RxDescArray[cur_rx].status) & RxRES)) {
 			unsigned char rxdata[RX_BUF_LEN];
-			length = (int) (tpc->RxDescArray[cur_rx].
-						status & 0x00001FFF) - 4;
+			length = (int) (le32_to_cpu(tpc->RxDescArray[cur_rx].
+						status) & 0x00001FFF) - 4;
 
 			memcpy(rxdata, tpc->RxBufferRing[cur_rx], length);
 			NetReceive(rxdata, length);
 
 			if (cur_rx == NUM_RX_DESC - 1)
 				tpc->RxDescArray[cur_rx].status =
-				    (OWNbit | EORbit) + RX_BUF_SIZE;
+					cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE);
 			else
 				tpc->RxDescArray[cur_rx].status =
-				    OWNbit + RX_BUF_SIZE;
+					cpu_to_le32(OWNbit + RX_BUF_SIZE);
 			tpc->RxDescArray[cur_rx].buf_addr =
-			    virt_to_bus(tpc->RxBufferRing[cur_rx]);
+				cpu_to_le32(tpc->RxBufferRing[cur_rx]);
 		} else {
 			puts("Error Rx");
 		}
@@ -454,6 +452,7 @@ static int rtl_send(struct eth_device *dev, volatile void *packet, int length)
 	u8 *ptxb;
 	int entry = tpc->cur_tx % NUM_TX_DESC;
 	u32 len = length;
+	int ret;
 
 #ifdef DEBUG_RTL8169_TX
 	int stime = currticks();
@@ -470,34 +469,38 @@ static int rtl_send(struct eth_device *dev, volatile void *packet, int length)
 	while (len < ETH_ZLEN)
 		ptxb[len++] = '\0';
 
-	tpc->TxDescArray[entry].buf_addr = virt_to_bus(ptxb);
+	tpc->TxDescArray[entry].buf_addr = cpu_to_le32(ptxb);
 	if (entry != (NUM_TX_DESC - 1)) {
 		tpc->TxDescArray[entry].status =
-		    (OWNbit | FSbit | LSbit) | ((len > ETH_ZLEN) ?
-						len : ETH_ZLEN);
+			cpu_to_le32((OWNbit | FSbit | LSbit) |
+				    ((len > ETH_ZLEN) ? len : ETH_ZLEN));
 	} else {
 		tpc->TxDescArray[entry].status =
-		    (OWNbit | EORbit | FSbit | LSbit) |
-		    ((len > ETH_ZLEN) ? length : ETH_ZLEN);
+			cpu_to_le32((OWNbit | EORbit | FSbit | LSbit) |
+				    ((len > ETH_ZLEN) ? len : ETH_ZLEN));
 	}
 	RTL_W8(TxPoll, 0x40);	/* set polling bit */
 
 	tpc->cur_tx++;
 	to = currticks() + TX_TIMEOUT;
-	while ((tpc->TxDescArray[entry].status & OWNbit) && (currticks() < to));	/* wait */
+	while ((le32_to_cpu(tpc->TxDescArray[entry].status) & OWNbit)
+				&& (currticks() < to));	/* wait */
 
 	if (currticks() >= to) {
 #ifdef DEBUG_RTL8169_TX
 		puts ("tx timeout/error\n");
 		printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime);
 #endif
-		return 0;
+		ret = 0;
 	} else {
 #ifdef DEBUG_RTL8169_TX
 		puts("tx done\n");
 #endif
-		return length;
+		ret = length;
 	}
+	/* Delay to make net console (nc) work properly */
+	udelay(20);
+	return ret;
 }
 
 static void rtl8169_set_rx_mode(struct eth_device *dev)
@@ -564,8 +567,8 @@ static void rtl8169_hw_start(struct eth_device *dev)
 
 	tpc->cur_rx = 0;
 
-	RTL_W32(TxDescStartAddr, virt_to_le32desc(tpc->TxDescArray));
-	RTL_W32(RxDescStartAddr, virt_to_le32desc(tpc->RxDescArray));
+	RTL_W32(TxDescStartAddr, tpc->TxDescArray);
+	RTL_W32(RxDescStartAddr, tpc->RxDescArray);
 	RTL_W8(Cfg9346, Cfg9346_Lock);
 	udelay(10);
 
@@ -603,13 +606,14 @@ static void rtl8169_init_ring(struct eth_device *dev)
 	for (i = 0; i < NUM_RX_DESC; i++) {
 		if (i == (NUM_RX_DESC - 1))
 			tpc->RxDescArray[i].status =
-			    (OWNbit | EORbit) + RX_BUF_SIZE;
+				cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE);
 		else
-			tpc->RxDescArray[i].status = OWNbit + RX_BUF_SIZE;
+			tpc->RxDescArray[i].status =
+				cpu_to_le32(OWNbit + RX_BUF_SIZE);
 
 		tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE];
 		tpc->RxDescArray[i].buf_addr =
-		    virt_to_bus(tpc->RxBufferRing[i]);
+			cpu_to_le32(tpc->RxBufferRing[i]);
 	}
 
 #ifdef DEBUG_RTL8169
@@ -620,11 +624,9 @@ static void rtl8169_init_ring(struct eth_device *dev)
 /**************************************************************************
 RESET - Finish setting up the ethernet interface
 ***************************************************************************/
-static void rtl_reset(struct eth_device *dev, bd_t *bis)
+static int rtl_reset(struct eth_device *dev, bd_t *bis)
 {
 	int i;
-	u8 diff;
-	u32 TxPhyAddr, RxPhyAddr;
 
 #ifdef DEBUG_RTL8169
 	int stime = currticks();
@@ -632,25 +634,14 @@ static void rtl_reset(struct eth_device *dev, bd_t *bis)
 #endif
 
 	tpc->TxDescArrays = tx_ring;
-	if (tpc->TxDescArrays == 0)
-		puts("Allot Error");
 	/* Tx Desscriptor needs 256 bytes alignment; */
-	TxPhyAddr = virt_to_bus(tpc->TxDescArrays);
-	diff = 256 - (TxPhyAddr - ((TxPhyAddr >> 8) << 8));
-	TxPhyAddr += diff;
-	tpc->TxDescArray = (struct TxDesc *) (tpc->TxDescArrays + diff);
+	tpc->TxDescArray = (struct TxDesc *) ((unsigned long)(tpc->TxDescArrays +
+							      255) & ~255);
 
 	tpc->RxDescArrays = rx_ring;
 	/* Rx Desscriptor needs 256 bytes alignment; */
-	RxPhyAddr = virt_to_bus(tpc->RxDescArrays);
-	diff = 256 - (RxPhyAddr - ((RxPhyAddr >> 8) << 8));
-	RxPhyAddr += diff;
-	tpc->RxDescArray = (struct RxDesc *) (tpc->RxDescArrays + diff);
-
-	if (tpc->TxDescArrays == NULL || tpc->RxDescArrays == NULL) {
-		puts("Allocate RxDescArray or TxDescArray failed\n");
-		return;
-	}
+	tpc->RxDescArray = (struct RxDesc *) ((unsigned long)(tpc->RxDescArrays +
+							      255) & ~255);
 
 	rtl8169_init_ring(dev);
 	rtl8169_hw_start(dev);
@@ -669,6 +660,7 @@ static void rtl_reset(struct eth_device *dev, bd_t *bis)
 #ifdef DEBUG_RTL8169
 	printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime);
 #endif
+	return 0;
 }
 
 /**************************************************************************
@@ -733,7 +725,7 @@ static int rtl_init(struct eth_device *dev, bd_t *bis)
 
 	/* Get MAC address.  FIXME: read EEPROM */
 	for (i = 0; i < MAC_ADDR_LEN; i++)
-		dev->enetaddr[i] = RTL_R8(MAC0 + i);
+		bis->bi_enetaddr[i] = dev->enetaddr[i] = RTL_R8(MAC0 + i);
 
 #ifdef DEBUG_RTL8169
 	printf("MAC Address");
@@ -808,7 +800,7 @@ static int rtl_init(struct eth_device *dev, bd_t *bis)
 		/* wait for auto-negotiation process */
 		for (i = 10000; i > 0; i--) {
 			/* check if auto-negotiation complete */
-			if (mdio_read(PHY_STAT_REG) & PHY_Auto_Neco_Comp) {
+			if (mdio_read(PHY_STAT_REG) & PHY_Auto_Nego_Comp) {
 				udelay(100);
 				option = RTL_R8(PHYstatus);
 				if (option & _1000bpsF) {
@@ -818,13 +810,12 @@ static int rtl_init(struct eth_device *dev, bd_t *bis)
 #endif
 				} else {
 #ifdef DEBUG_RTL8169
-					printf
-					    ("%s: %sMbps %s-duplex operation.\n",
-					     dev->name,
-					     (option & _100bps) ? "100" :
-					     "10",
-					     (option & FullDup) ? "Full" :
-					     "Half");
+					printf("%s: %sMbps %s-duplex operation.\n",
+					       dev->name,
+					       (option & _100bps) ? "100" :
+					       "10",
+					       (option & FullDup) ? "Full" :
+					       "Half");
 #endif
 				}
 				break;
@@ -869,7 +860,7 @@ int rtl8169_initialize(bd_t *bis)
 		sprintf (dev->name, "RTL8169#%d", card_number);
 
 		dev->priv = (void *) devno;
-		dev->iobase = (int)bus_to_phys(iobase);
+		dev->iobase = (int)pci_mem_to_phys(devno, iobase);
 
 		dev->init = rtl_reset;
 		dev->halt = rtl_halt;
diff --git a/drivers/net/sk98lin/Makefile b/drivers/net/sk98lin/Makefile
index a7d4a3b..8b83fae 100644
--- a/drivers/net/sk98lin/Makefile
+++ b/drivers/net/sk98lin/Makefile
@@ -20,7 +20,7 @@
 # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 # MA 02111-1307 USA
 #
-# File: drivers/sk98lin/Makefile
+# File: drivers/net/sk98lin/Makefile
 #
 # Makefile for the SysKonnect SK-98xx device driver.
 #
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index ca6284b..25392f6 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -232,7 +232,7 @@ int tsec_init(struct eth_device *dev, bd_t * bd)
 	startup_tsec(dev);
 
 	/* If there's no link, fail */
-	return priv->link;
+	return (priv->link ? 0 : -1);
 
 }
 
@@ -674,6 +674,15 @@ uint mii_cis8204_setmode(uint mii_reg, struct tsec_private * priv)
 		return MIIM_CIS8204_EPHYCON_INIT;
 }
 
+uint mii_m88e1111s_setmode(uint mii_reg, struct tsec_private *priv)
+{
+	uint mii_data = read_phy_reg(priv, mii_reg);
+
+	if (priv->flags & TSEC_REDUCED)
+		mii_data = (mii_data & 0xfff0) | 0x000b;
+	return mii_data;
+}
+
 /* Initialized required registers to appropriate values, zeroing
  * those we don't care about (unless zero is bad, in which case,
  * choose a more appropriate value)
@@ -1034,6 +1043,7 @@ struct phy_info phy_info_M88E1111S = {
 	(struct phy_cmd[]){	/* config */
 			   /* Reset and configure the PHY */
 			   {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
+			   {0x1b, 0x848f, &mii_m88e1111s_setmode},
 			   {0x14, 0x0cd2, NULL}, /* Delay RGMII TX and RX */
 			   {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
 			   {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
diff --git a/drivers/net/tsi108_eth.c b/drivers/net/tsi108_eth.c
index 524e9da..a09115e 100644
--- a/drivers/net/tsi108_eth.c
+++ b/drivers/net/tsi108_eth.c
@@ -792,7 +792,7 @@ static int tsi108_eth_probe (struct eth_device *dev, bd_t * bis)
 	    (dev->enetaddr[0] << 16);
 
 	if (marvell_88e_phy_config(dev, &speed, &duplex) == 0)
-		return 0;
+		return -1;
 
 	value =
 	    MAC_CONFIG_2_PREAMBLE_LENGTH(7) | MAC_CONFIG_2_PAD_CRC |
@@ -864,7 +864,7 @@ static int tsi108_eth_probe (struct eth_device *dev, bd_t * bis)
 	/* enable TX queue */
 	reg_TX_CONTROL(base) = TX_CONTROL_GO | 0x01;
 
-	return 1;
+	return 0;
 }
 
 /*
diff --git a/drivers/net/uli526x.c b/drivers/net/uli526x.c
index 1267c57..8460f69 100644
--- a/drivers/net/uli526x.c
+++ b/drivers/net/uli526x.c
@@ -279,12 +279,12 @@ static int uli526x_init_one(struct eth_device *dev, bd_t *bis)
 	db->desc_pool_ptr = (uchar *)&desc_pool_array[0];
 	db->desc_pool_dma_ptr = (dma_addr_t)&desc_pool_array[0];
 	if (db->desc_pool_ptr == NULL)
-		return 0;
+		return -1;
 
 	db->buf_pool_ptr = &buf_pool[0];
 	db->buf_pool_dma_ptr = (dma_addr_t)&buf_pool[0];
 	if (db->buf_pool_ptr == NULL)
-		return 0;
+		return -1;
 
 	db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
 	db->first_tx_desc_dma = db->desc_pool_dma_ptr;
@@ -331,7 +331,7 @@ static int uli526x_init_one(struct eth_device *dev, bd_t *bis)
 	db->cr6_data |= ULI526X_TXTH_256;
 	db->cr0_data = CR0_DEFAULT;
 	uli526x_init(dev);
-	return 1;
+	return 0;
 }
 
 static void uli526x_disable(struct eth_device *dev)
diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index 7559e92..c802014 100644
--- a/drivers/qe/qe.c
+++ b/drivers/qe/qe.c
@@ -21,6 +21,7 @@
  */
 
 #include "common.h"
+#include <command.h>
 #include "asm/errno.h"
 #include "asm/io.h"
 #include "asm/immap_qe.h"
@@ -34,7 +35,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data)
 {
-	u32           cecr;
+	u32 cecr;
 
 	if (cmd == QE_RESET) {
 		out_be32(&qe_immr->cp.cecr,(u32) (cmd | QE_CR_FLG));
@@ -248,4 +249,222 @@ int qe_set_mii_clk_src(int ucc_num)
 	return 0;
 }
 
+/* The maximum number of RISCs we support */
+#define MAX_QE_RISC     2
+
+/* Firmware information stored here for qe_get_firmware_info() */
+static struct qe_firmware_info qe_firmware_info;
+
+/*
+ * Set to 1 if QE firmware has been uploaded, and therefore
+ * qe_firmware_info contains valid data.
+ */
+static int qe_firmware_uploaded;
+
+/*
+ * Upload a QE microcode
+ *
+ * This function is a worker function for qe_upload_firmware().  It does
+ * the actual uploading of the microcode.
+ */
+static void qe_upload_microcode(const void *base,
+	const struct qe_microcode *ucode)
+{
+	const u32 *code = base + be32_to_cpu(ucode->code_offset);
+	unsigned int i;
+
+	if (ucode->major || ucode->minor || ucode->revision)
+		printf("QE: uploading microcode '%s' version %u.%u.%u\n",
+			ucode->id, ucode->major, ucode->minor, ucode->revision);
+	else
+		printf("QE: uploading microcode '%s'\n", ucode->id);
+
+	/* Use auto-increment */
+	out_be32(&qe_immr->iram.iadd, be32_to_cpu(ucode->iram_offset) |
+		QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR);
+
+	for (i = 0; i < be32_to_cpu(ucode->count); i++)
+		out_be32(&qe_immr->iram.idata, be32_to_cpu(code[i]));
+}
+
+/*
+ * Upload a microcode to the I-RAM at a specific address.
+ *
+ * See docs/README.qe_firmware for information on QE microcode uploading.
+ *
+ * Currently, only version 1 is supported, so the 'version' field must be
+ * set to 1.
+ *
+ * The SOC model and revision are not validated, they are only displayed for
+ * informational purposes.
+ *
+ * 'calc_size' is the calculated size, in bytes, of the firmware structure and
+ * all of the microcode structures, minus the CRC.
+ *
+ * 'length' is the size that the structure says it is, including the CRC.
+ */
+int qe_upload_firmware(const struct qe_firmware *firmware)
+{
+	unsigned int i;
+	unsigned int j;
+	u32 crc;
+	size_t calc_size = sizeof(struct qe_firmware);
+	size_t length;
+	const struct qe_header *hdr;
+
+	if (!firmware) {
+		printf("Invalid address\n");
+		return -EINVAL;
+	}
+
+	hdr = &firmware->header;
+	length = be32_to_cpu(hdr->length);
+
+	/* Check the magic */
+	if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
+	    (hdr->magic[2] != 'F')) {
+		printf("Not a microcode\n");
+		return -EPERM;
+	}
+
+	/* Check the version */
+	if (hdr->version != 1) {
+		printf("Unsupported version\n");
+		return -EPERM;
+	}
+
+	/* Validate some of the fields */
+	if ((firmware->count < 1) || (firmware->count >= MAX_QE_RISC)) {
+		printf("Invalid data\n");
+		return -EINVAL;
+	}
+
+	/* Validate the length and check if there's a CRC */
+	calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);
+
+	for (i = 0; i < firmware->count; i++)
+		/*
+		 * For situations where the second RISC uses the same microcode
+		 * as the first, the 'code_offset' and 'count' fields will be
+		 * zero, so it's okay to add those.
+		 */
+		calc_size += sizeof(u32) *
+			be32_to_cpu(firmware->microcode[i].count);
+
+	/* Validate the length */
+	if (length != calc_size + sizeof(u32)) {
+		printf("Invalid length\n");
+		return -EPERM;
+	}
+
+	/*
+	 * Validate the CRC.  We would normally call crc32_no_comp(), but that
+	 * function isn't available unless you turn on JFFS support.
+	 */
+	crc = be32_to_cpu(*(u32 *)((void *)firmware + calc_size));
+	if (crc != (crc32(-1, (const void *) firmware, calc_size) ^ -1)) {
+		printf("Firmware CRC is invalid\n");
+		return -EIO;
+	}
+
+	/*
+	 * If the microcode calls for it, split the I-RAM.
+	 */
+	if (!firmware->split) {
+		out_be16(&qe_immr->cp.cercr,
+			in_be16(&qe_immr->cp.cercr) | QE_CP_CERCR_CIR);
+	}
+
+	if (firmware->soc.model)
+		printf("Firmware '%s' for %u V%u.%u\n",
+			firmware->id, be16_to_cpu(firmware->soc.model),
+			firmware->soc.major, firmware->soc.minor);
+	else
+		printf("Firmware '%s'\n", firmware->id);
+
+	/*
+	 * The QE only supports one microcode per RISC, so clear out all the
+	 * saved microcode information and put in the new.
+	 */
+	memset(&qe_firmware_info, 0, sizeof(qe_firmware_info));
+	strcpy(qe_firmware_info.id, firmware->id);
+	qe_firmware_info.extended_modes = firmware->extended_modes;
+	memcpy(qe_firmware_info.vtraps, firmware->vtraps,
+		sizeof(firmware->vtraps));
+	qe_firmware_uploaded = 1;
+
+	/* Loop through each microcode. */
+	for (i = 0; i < firmware->count; i++) {
+		const struct qe_microcode *ucode = &firmware->microcode[i];
+
+		/* Upload a microcode if it's present */
+		if (ucode->code_offset)
+			qe_upload_microcode(firmware, ucode);
+
+		/* Program the traps for this processor */
+		for (j = 0; j < 16; j++) {
+			u32 trap = be32_to_cpu(ucode->traps[j]);
+
+			if (trap)
+				out_be32(&qe_immr->rsp[i].tibcr[j], trap);
+		}
+
+		/* Enable traps */
+		out_be32(&qe_immr->rsp[i].eccr, be32_to_cpu(ucode->eccr));
+	}
+
+	return 0;
+}
+
+struct qe_firmware_info *qe_get_firmware_info(void)
+{
+	return qe_firmware_uploaded ? &qe_firmware_info : NULL;
+}
+
+static int qe_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	ulong addr;
+
+	if (argc < 3) {
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+
+	if (strcmp(argv[1], "fw") == 0) {
+		addr = simple_strtoul(argv[2], NULL, 16);
+
+		if (!addr) {
+			printf("Invalid address\n");
+			return -EINVAL;
+		}
+
+		/*
+		 * If a length was supplied, compare that with the 'length'
+		 * field.
+		 */
+
+		if (argc > 3) {
+			ulong length = simple_strtoul(argv[3], NULL, 16);
+			struct qe_firmware *firmware = (void *) addr;
+
+			if (length != be32_to_cpu(firmware->header.length)) {
+				printf("Length mismatch\n");
+				return -EINVAL;
+			}
+		}
+
+		return qe_upload_firmware((const struct qe_firmware *) addr);
+	}
+
+	printf ("Usage:\n%s\n", cmdtp->usage);
+	return 1;
+}
+
+U_BOOT_CMD(
+	qe, 4, 0, qe_cmd,
+	"qe      - QUICC Engine commands\n",
+	"fw <addr> [<length>] - Upload firmware binary at address <addr> to "
+		"the QE,\n\twith optional length <length> verification.\n"
+	);
+
 #endif /* CONFIG_QE */
diff --git a/drivers/qe/qe.h b/drivers/qe/qe.h
index 400b1a6..4c96c67 100644
--- a/drivers/qe/qe.h
+++ b/drivers/qe/qe.h
@@ -222,6 +222,60 @@ typedef enum qe_clock {
 
 #define QE_SDEBCR_BA_MASK		0x01FFFFFF
 
+/* Communication Processor */
+#define QE_CP_CERCR_MEE		0x8000	/* Multi-user RAM ECC enable */
+#define QE_CP_CERCR_IEE		0x4000	/* Instruction RAM ECC enable */
+#define QE_CP_CERCR_CIR		0x0800	/* Common instruction RAM */
+
+/* I-RAM */
+#define QE_IRAM_IADD_AIE	0x80000000	/* Auto Increment Enable */
+#define QE_IRAM_IADD_BADDR	0x00080000	/* Base Address */
+
+/* Structure that defines QE firmware binary files.
+ *
+ * See doc/README.qe_firmware for a description of these fields.
+ */
+struct qe_firmware {
+	struct qe_header {
+		u32 length;  /* Length of the entire structure, in bytes */
+		u8 magic[3];    /* Set to { 'Q', 'E', 'F' } */
+		u8 version;     /* Version of this layout. First ver is '1' */
+	} header;
+	u8 id[62];      /* Null-terminated identifier string */
+	u8 split;	/* 0 = shared I-RAM, 1 = split I-RAM */
+	u8 count;       /* Number of microcode[] structures */
+	struct {
+		u16 model;   	/* The SOC model  */
+		u8 major;       	/* The SOC revision major */
+		u8 minor;       	/* The SOC revision minor */
+	} __attribute__ ((packed)) soc;
+	u8 padding[4];			/* Reserved, for alignment */
+	u64 extended_modes;		/* Extended modes */
+	u32 vtraps[8];		/* Virtual trap addresses */
+	u8 reserved[4];			/* Reserved, for future expansion */
+	struct qe_microcode {
+		u8 id[32];      	/* Null-terminated identifier */
+		u32 traps[16];       /* Trap addresses, 0 == ignore */
+		u32 eccr;    	/* The value for the ECCR register */
+		u32 iram_offset;     /* Offset into I-RAM for the code */
+		u32 count;   	/* Number of 32-bit words of the code */
+		u32 code_offset;     /* Offset of the actual microcode */
+		u8 major;       	/* The microcode version major */
+		u8 minor;       	/* The microcode version minor */
+		u8 revision;		/* The microcode version revision */
+		u8 padding;		/* Reserved, for alignment */
+		u8 reserved[4];		/* Reserved, for future expansion */
+	} __attribute__ ((packed)) microcode[1];
+	/* All microcode binaries should be located here */
+	/* CRC32 should be located here, after the microcode binaries */
+} __attribute__ ((packed));
+
+struct qe_firmware_info {
+	char id[64];		/* Firmware name */
+	u32 vtraps[8];		/* Virtual trap addresses */
+	u64 extended_modes;	/* Extended modes */
+};
+
 void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign);
 void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data);
 uint qe_muram_alloc(uint size, uint align);
@@ -233,5 +287,7 @@ void qe_reset(void);
 void qe_assign_page(uint snum, uint para_ram_base);
 int qe_set_brg(uint brg, uint rate);
 int qe_set_mii_clk_src(int ucc_num);
+int qe_upload_firmware(const struct qe_firmware *firmware);
+struct qe_firmware_info *qe_get_firmware_info(void);
 
 #endif /* __QE_H__ */
diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
index dc2765b..44cbea5 100644
--- a/drivers/qe/uec.c
+++ b/drivers/qe/uec.c
@@ -69,6 +69,25 @@ static uec_info_t eth2_uec_info = {
 };
 #endif
 
+#ifdef CONFIG_UEC_ETH3
+static uec_info_t eth3_uec_info = {
+	.uf_info		= {
+		.ucc_num	= CFG_UEC3_UCC_NUM,
+		.rx_clock	= CFG_UEC3_RX_CLK,
+		.tx_clock	= CFG_UEC3_TX_CLK,
+		.eth_type	= CFG_UEC3_ETH_TYPE,
+	},
+	.num_threads_tx		= UEC_NUM_OF_THREADS_4,
+	.num_threads_rx		= UEC_NUM_OF_THREADS_4,
+	.riscTx			= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+	.riscRx			= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+	.tx_bd_ring_len		= 16,
+	.rx_bd_ring_len		= 16,
+	.phy_address		= CFG_UEC3_PHY_ADDR,
+	.enet_interface		= CFG_UEC3_INTERFACE_MODE,
+};
+#endif
+
 static int uec_mac_enable(uec_private_t *uec, comm_dir_e mode)
 {
 	uec_t		*uec_regs;
@@ -1110,7 +1129,7 @@ static int uec_init(struct eth_device* dev, bd_t *bd)
 		if (dev->enetaddr[0] & 0x01) {
 			printf("%s: MacAddress is multcast address\n",
 				 __FUNCTION__);
-			return 0;
+			return -1;
 		}
 		uec_set_mac_address(uec, dev->enetaddr);
 		uec->the_first_run = 1;
@@ -1119,10 +1138,10 @@ static int uec_init(struct eth_device* dev, bd_t *bd)
 	err = uec_open(uec, COMM_DIR_RX_AND_TX);
 	if (err) {
 		printf("%s: cannot enable UEC device\n", dev->name);
-		return 0;
+		return -1;
 	}
 
-	return uec->mii_info->link;
+	return (uec->mii_info->link ? 0 : -1);
 }
 
 static void uec_halt(struct eth_device* dev)
@@ -1238,6 +1257,10 @@ int uec_initialize(int index)
 #ifdef CONFIG_UEC_ETH2
 		uec_info = &eth2_uec_info;
 #endif
+	} else if (index == 2) {
+#ifdef CONFIG_UEC_ETH3
+		uec_info = &eth3_uec_info;
+#endif
 	} else {
 		printf("%s: index is illegal.\n", __FUNCTION__);
 		return -EINVAL;
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 4a22b0d..8c7f148 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -40,6 +40,7 @@ COBJS-y += ds164x.o
 COBJS-y += ds174x.o
 COBJS-y += ds3231.o
 COBJS-y += m41t11.o
+COBJS-y += m41t60.o
 COBJS-y += max6900.o
 COBJS-y += m48t35ax.o
 COBJS-y += mc146818.o
@@ -49,7 +50,9 @@ COBJS-y += mpc8xx.o
 COBJS-y += pcf8563.o
 COBJS-y += s3c24x0_rtc.o
 COBJS-y += rs5c372.o
+COBJS-y += rx8025.o
 COBJS-y += mcfrtc.o
+COBJS-y += x1205.o
 
 COBJS	:= $(COBJS-y)
 SRCS	:= $(COBJS:.o=.c)
diff --git a/drivers/rtc/m41t60.c b/drivers/rtc/m41t60.c
new file mode 100644
index 0000000..7c80143
--- /dev/null
+++ b/drivers/rtc/m41t60.c
@@ -0,0 +1,261 @@
+/*
+ * (C) Copyright 2007
+ * Larry Johnson, lrj@acm.org
+ *
+ * based on rtc/m41t11.c which is ...
+ *
+ * (C) Copyright 2002
+ * Andrew May, Viasat Inc, amay@viasat.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * STMicroelectronics M41T60 serial access real-time clock
+ */
+
+/* #define DEBUG 1 */
+
+#include <common.h>
+#include <command.h>
+#include <rtc.h>
+#include <i2c.h>
+
+#if defined(CONFIG_RTC_M41T60) && defined(CFG_I2C_RTC_ADDR) && \
+	defined(CONFIG_CMD_DATE)
+
+static unsigned bcd2bin(uchar n)
+{
+	return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F));
+}
+
+static unsigned char bin2bcd(unsigned int n)
+{
+	return (((n / 10) << 4) | (n % 10));
+}
+
+/*
+ * Convert between century and "century bits" (CB1 and CB0).  These routines
+ * assume years are in the range 1900 - 2299.
+ */
+
+static unsigned char year2cb(unsigned const year)
+{
+	if (year < 1900 || year >= 2300)
+		printf("M41T60 RTC: year %d out of range\n", year);
+
+	return (year / 100) & 0x3;
+}
+
+static unsigned cb2year(unsigned const cb)
+{
+	return 1900 + 100 * ((cb + 1) & 0x3);
+}
+
+/*
+ * These are simple defines for the chip local to here so they aren't too
+ * verbose.  DAY/DATE aren't nice but that is how they are on the data sheet.
+ */
+#define RTC_SEC		0x0
+#define RTC_MIN		0x1
+#define RTC_HOUR	0x2
+#define RTC_DAY		0x3
+#define RTC_DATE	0x4
+#define RTC_MONTH	0x5
+#define RTC_YEAR	0x6
+
+#define RTC_REG_CNT	7
+
+#define RTC_CTRL	0x7
+
+#if defined(DEBUG)
+static void rtc_dump(char const *const label)
+{
+	uchar data[8];
+
+	if (i2c_read(CFG_I2C_RTC_ADDR, 0, 1, data, sizeof(data))) {
+		printf("I2C read failed in rtc_dump()\n");
+		return;
+	}
+	printf("RTC dump %s: %02X-%02X-%02X-%02X-%02X-%02X-%02X-%02X\n",
+	       label, data[0], data[1], data[2], data[3],
+	       data[4], data[5], data[6], data[7]);
+}
+#else
+#define rtc_dump(label)
+#endif
+
+static uchar *rtc_validate(void)
+{
+	/*
+	 * This routine uses the OUT bit and the validity of the time values to
+	 * determine whether there has been an initial power-up since the last
+	 * time the routine was run.  It assumes that the OUT bit is not being
+	 * used for any other purpose.
+	 */
+	static const uchar daysInMonth[0x13] = {
+		0x00, 0x31, 0x29, 0x31, 0x30, 0x31, 0x30, 0x31,
+		0x31, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x31, 0x30, 0x31
+	};
+	static uchar data[8];
+	uchar min, date, month, years;
+
+	rtc_dump("begin validate");
+	if (i2c_read(CFG_I2C_RTC_ADDR, 0, 1, data, sizeof(data))) {
+		printf("I2C read failed in rtc_validate()\n");
+		return 0;
+	}
+	/*
+	 * If the OUT bit is "1", there has been a loss of power, so stop the
+	 * oscillator so it can be "kick-started" as per data sheet.
+	 */
+	if (0x00 != (data[RTC_CTRL] & 0x80)) {
+		printf("M41T60 RTC clock lost power.\n");
+		data[RTC_SEC] = 0x80;
+		if (i2c_write(CFG_I2C_RTC_ADDR, RTC_SEC, 1, data, 1)) {
+			printf("I2C write failed in rtc_validate()\n");
+			return 0;
+		}
+	}
+	/*
+	 * If the oscillator is stopped or the date is invalid, then reset the
+	 * OUT bit to "0", reset the date registers, and start the oscillator.
+	 */
+	min = data[RTC_MIN] & 0x7F;
+	date = data[RTC_DATE];
+	month = data[RTC_MONTH] & 0x3F;
+	years = data[RTC_YEAR];
+	if (0x59 < data[RTC_SEC] || 0x09 < (data[RTC_SEC] & 0x0F) ||
+	    0x59 < min || 0x09 < (min & 0x0F) ||
+	    0x23 < data[RTC_HOUR] || 0x09 < (data[RTC_HOUR] & 0x0F) ||
+	    0x07 < data[RTC_DAY] || 0x00 == data[RTC_DAY] ||
+	    0x12 < month ||
+	    0x99 < years || 0x09 < (years & 0x0F) ||
+	    daysInMonth[month] < date || 0x09 < (date & 0x0F) || 0x00 == date ||
+	    (0x29 == date && 0x02 == month &&
+	     ((0x00 != (years & 0x03)) ||
+	      (0x00 == years && 0x00 != (data[RTC_MONTH] & 0xC0))))) {
+		printf("Resetting M41T60 RTC clock.\n");
+		/*
+		 * Set to 00:00:00 1900-01-01 (Monday)
+		 */
+		data[RTC_SEC] = 0x00;
+		data[RTC_MIN] &= 0x80;	/* preserve OFIE bit */
+		data[RTC_HOUR] = 0x00;
+		data[RTC_DAY] = 0x02;
+		data[RTC_DATE] = 0x01;
+		data[RTC_MONTH] = 0xC1;
+		data[RTC_YEAR] = 0x00;
+		data[RTC_CTRL] &= 0x7F;	/* reset OUT bit */
+
+		if (i2c_write(CFG_I2C_RTC_ADDR, 0, 1, data, sizeof(data))) {
+			printf("I2C write failed in rtc_validate()\n");
+			return 0;
+		}
+	}
+	return data;
+}
+
+void rtc_get(struct rtc_time *tmp)
+{
+	uchar const *const data = rtc_validate();
+
+	if (!data)
+		return;
+
+	tmp->tm_sec = bcd2bin(data[RTC_SEC] & 0x7F);
+	tmp->tm_min = bcd2bin(data[RTC_MIN] & 0x7F);
+	tmp->tm_hour = bcd2bin(data[RTC_HOUR] & 0x3F);
+	tmp->tm_mday = bcd2bin(data[RTC_DATE] & 0x3F);
+	tmp->tm_mon = bcd2bin(data[RTC_MONTH] & 0x1F);
+	tmp->tm_year = cb2year(data[RTC_MONTH] >> 6) + bcd2bin(data[RTC_YEAR]);
+	tmp->tm_wday = bcd2bin(data[RTC_DAY] & 0x07) - 1;
+	tmp->tm_yday = 0;
+	tmp->tm_isdst = 0;
+
+	debug("Get DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
+	      tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
+	      tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+}
+
+void rtc_set(struct rtc_time *tmp)
+{
+	uchar *const data = rtc_validate();
+
+	if (!data)
+		return;
+
+	debug("Set DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
+	      tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
+	      tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+
+	data[RTC_SEC] = (data[RTC_SEC] & 0x80) | (bin2bcd(tmp->tm_sec) & 0x7F);
+	data[RTC_MIN] = (data[RTC_MIN] & 0X80) | (bin2bcd(tmp->tm_min) & 0X7F);
+	data[RTC_HOUR] = bin2bcd(tmp->tm_hour) & 0x3F;
+	data[RTC_DATE] = bin2bcd(tmp->tm_mday) & 0x3F;
+	data[RTC_MONTH] = bin2bcd(tmp->tm_mon) & 0x1F;
+	data[RTC_YEAR] = bin2bcd(tmp->tm_year % 100);
+	data[RTC_MONTH] |= year2cb(tmp->tm_year) << 6;
+	data[RTC_DAY] = bin2bcd(tmp->tm_wday + 1) & 0x07;
+	if (i2c_write(CFG_I2C_RTC_ADDR, 0, 1, data, RTC_REG_CNT)) {
+		printf("I2C write failed in rtc_set()\n");
+		return;
+	}
+}
+
+void rtc_reset(void)
+{
+	uchar *const data = rtc_validate();
+	char const *const s = getenv("rtccal");
+
+	if (!data)
+		return;
+
+	rtc_dump("begin reset");
+	/*
+	 * If environmental variable "rtccal" is present, it must be a hex value
+	 * between 0x00 and 0x3F, inclusive.  The five least-significan bits
+	 * represent the calibration magnitude, and the sixth bit the sign bit.
+	 * If these do not match the contents of the hardware register, that
+	 * register is updated.  The value 0x00 imples no correction.  Consult
+	 * the M41T60 documentation for further details.
+	 */
+	if (s) {
+		unsigned long const l = simple_strtoul(s, 0, 16);
+
+		if (l <= 0x3F) {
+			if ((data[RTC_CTRL] & 0x3F) != l) {
+				printf("Setting RTC calibration to 0x%02X\n",
+				       l);
+				data[RTC_CTRL] &= 0xC0;
+				data[RTC_CTRL] |= (uchar) l;
+			}
+		} else
+			printf("environment parameter \"rtccal\" not valid: "
+			       "ignoring\n");
+	}
+	/*
+	 * Turn off frequency test.
+	 */
+	data[RTC_CTRL] &= 0xBF;
+	if (i2c_write(CFG_I2C_RTC_ADDR, RTC_CTRL, 1, data + RTC_CTRL, 1)) {
+		printf("I2C write failed in rtc_reset()\n");
+		return;
+	}
+	rtc_dump("end reset");
+}
+#endif /* CONFIG_RTC_M41T60 && CFG_I2C_RTC_ADDR && CONFIG_CMD_DATE */
diff --git a/drivers/rtc/rx8025.c b/drivers/rtc/rx8025.c
new file mode 100644
index 0000000..6c94ae1
--- /dev/null
+++ b/drivers/rtc/rx8025.c
@@ -0,0 +1,227 @@
+/*
+ * (C) Copyright 2007
+ * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Epson RX8025 RTC driver.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <rtc.h>
+#include <i2c.h>
+
+#if defined(CONFIG_RTC_RX8025) && defined(CONFIG_CMD_DATE)
+
+/*---------------------------------------------------------------------*/
+#undef DEBUG_RTC
+
+#ifdef DEBUG_RTC
+#define DEBUGR(fmt,args...) printf(fmt ,##args)
+#else
+#define DEBUGR(fmt,args...)
+#endif
+/*---------------------------------------------------------------------*/
+
+#ifndef CFG_I2C_RTC_ADDR
+# define CFG_I2C_RTC_ADDR	0x32
+#endif
+
+/*
+ * RTC register addresses
+ */
+#define RTC_SEC_REG_ADDR	0x00
+#define RTC_MIN_REG_ADDR	0x01
+#define RTC_HR_REG_ADDR		0x02
+#define RTC_DAY_REG_ADDR	0x03
+#define RTC_DATE_REG_ADDR	0x04
+#define RTC_MON_REG_ADDR	0x05
+#define RTC_YR_REG_ADDR		0x06
+
+#define RTC_CTL1_REG_ADDR	0x0e
+#define RTC_CTL2_REG_ADDR	0x0f
+
+/*
+ * Control register 1 bits
+ */
+#define RTC_CTL1_BIT_2412	0x20
+
+/*
+ * Control register 2 bits
+ */
+#define RTC_CTL2_BIT_PON	0x10
+#define RTC_CTL2_BIT_VDET	0x40
+#define RTC_CTL2_BIT_XST	0x20
+#define RTC_CTL2_BIT_VDSL	0x80
+
+/*
+ * Note: the RX8025 I2C RTC requires register
+ * reads and write to consist of a single bus
+ * cycle. It is not allowed to write the register
+ * address in a first cycle that is terminated by
+ * a STOP condition. The chips needs a 'restart'
+ * sequence (start sequence without a prior stop).
+ * This driver has been written for a 4xx board.
+ * U-Boot's 4xx i2c driver is currently not capable
+ * to generate such cycles to some work arounds
+ * are used.
+ */
+
+/* static uchar rtc_read (uchar reg); */
+#define rtc_read(reg) buf[((reg) + 1) & 0xf]
+
+static void rtc_write (uchar reg, uchar val);
+static uchar bin2bcd (unsigned int n);
+static unsigned bcd2bin (uchar c);
+
+/*
+ * Get the current time from the RTC
+ */
+void rtc_get (struct rtc_time *tmp)
+{
+	uchar sec, min, hour, mday, wday, mon, year, ctl2;
+	uchar buf[16];
+
+	if (i2c_read(CFG_I2C_RTC_ADDR, 0, 0, buf, 16))
+		printf("Error reading from RTC\n");
+
+	sec = rtc_read(RTC_SEC_REG_ADDR);
+	min = rtc_read(RTC_MIN_REG_ADDR);
+	hour = rtc_read(RTC_HR_REG_ADDR);
+	wday = rtc_read(RTC_DAY_REG_ADDR);
+	mday = rtc_read(RTC_DATE_REG_ADDR);
+	mon = rtc_read(RTC_MON_REG_ADDR);
+	year = rtc_read(RTC_YR_REG_ADDR);
+
+	DEBUGR ("Get RTC year: %02x mon: %02x mday: %02x wday: %02x "
+		"hr: %02x min: %02x sec: %02x\n",
+		year, mon, mday, wday, hour, min, sec);
+
+	/* dump status */
+	ctl2 = rtc_read(RTC_CTL2_REG_ADDR);
+	if (ctl2 & RTC_CTL2_BIT_PON)
+		printf("RTC: power-on detected\n");
+
+	if (ctl2 & RTC_CTL2_BIT_VDET)
+		printf("RTC: voltage drop detected\n");
+
+	if (!(ctl2 & RTC_CTL2_BIT_XST))
+		printf("RTC: oscillator stop detected\n");
+
+	tmp->tm_sec  = bcd2bin (sec & 0x7F);
+	tmp->tm_min  = bcd2bin (min & 0x7F);
+	tmp->tm_hour = bcd2bin (hour & 0x3F);
+	tmp->tm_mday = bcd2bin (mday & 0x3F);
+	tmp->tm_mon  = bcd2bin (mon & 0x1F);
+	tmp->tm_year = bcd2bin (year) + ( bcd2bin (year) >= 70 ? 1900 : 2000);
+	tmp->tm_wday = bcd2bin (wday & 0x07);
+	tmp->tm_yday = 0;
+	tmp->tm_isdst= 0;
+
+	DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
+		tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
+		tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+}
+
+
+/*
+ * Set the RTC
+ */
+void rtc_set (struct rtc_time *tmp)
+{
+	DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
+		tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
+		tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+
+	if (tmp->tm_year < 1970 || tmp->tm_year > 2069)
+		printf("WARNING: year should be between 1970 and 2069!\n");
+
+	rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100));
+	rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon));
+	rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday));
+	rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday));
+	rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour));
+	rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min));
+	rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec));
+
+	rtc_write (RTC_CTL1_REG_ADDR, RTC_CTL1_BIT_2412);
+}
+
+
+/*
+ * Reset the RTC. We setting the date back to 1970-01-01.
+ */
+void rtc_reset (void)
+{
+	struct rtc_time tmp;
+	uchar buf[16];
+	uchar ctl2;
+
+	if (i2c_read(CFG_I2C_RTC_ADDR, 0,    0,   buf, 16))
+		printf("Error reading from RTC\n");
+
+	ctl2 = rtc_read(RTC_CTL2_REG_ADDR);
+	ctl2 &= ~(RTC_CTL2_BIT_PON | RTC_CTL2_BIT_VDET);
+	ctl2 |= RTC_CTL2_BIT_XST | RTC_CTL2_BIT_VDSL;
+	rtc_write (RTC_CTL2_REG_ADDR, ctl2);
+
+	tmp.tm_year = 1970;
+	tmp.tm_mon = 1;
+	tmp.tm_mday= 1;
+	tmp.tm_hour = 0;
+	tmp.tm_min = 0;
+	tmp.tm_sec = 0;
+
+	rtc_set(&tmp);
+
+	printf ( "RTC:   %4d-%02d-%02d %2d:%02d:%02d UTC\n",
+		tmp.tm_year, tmp.tm_mon, tmp.tm_mday,
+		tmp.tm_hour, tmp.tm_min, tmp.tm_sec);
+
+	return;
+}
+
+
+/*
+ * Helper functions
+ */
+static void rtc_write (uchar reg, uchar val)
+{
+	uchar buf[2];
+	buf[0] = reg << 4;
+	buf[1] = val;
+	if (i2c_write(CFG_I2C_RTC_ADDR, 0, 0, buf, 2) != 0)
+		printf("Error writing to RTC\n");
+
+}
+
+static unsigned bcd2bin (uchar n)
+{
+	return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F));
+}
+
+static unsigned char bin2bcd (unsigned int n)
+{
+	return (((n / 10) << 4) | (n % 10));
+}
+
+#endif /* CONFIG_RTC_RX8025 && (CFG_COMMANDS & CFG_CMD_DATE) */
diff --git a/drivers/rtc/x1205.c b/drivers/rtc/x1205.c
new file mode 100644
index 0000000..319f051
--- /dev/null
+++ b/drivers/rtc/x1205.c
@@ -0,0 +1,178 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * based on a the Linux rtc-x1207.c driver which is:
+ *	Copyright 2004 Karen Spearel
+ *	Copyright 2005 Alessandro Zummo
+ *
+ * Information and datasheet:
+ * http://www.intersil.com/cda/deviceinfo/0,1477,X1205,00.html
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Date & Time support for Xicor/Intersil X1205 RTC
+ */
+
+/* #define	DEBUG	*/
+
+#include <common.h>
+#include <command.h>
+#include <rtc.h>
+#include <i2c.h>
+#include <bcd.h>
+
+#if defined(CONFIG_RTC_X1205) && defined(CONFIG_CMD_DATE)
+
+#define CCR_SEC			0
+#define CCR_MIN			1
+#define CCR_HOUR		2
+#define CCR_MDAY		3
+#define CCR_MONTH		4
+#define CCR_YEAR		5
+#define CCR_WDAY		6
+#define CCR_Y2K			7
+
+#define X1205_REG_SR		0x3F	/* status register */
+#define X1205_REG_Y2K		0x37
+#define X1205_REG_DW		0x36
+#define X1205_REG_YR		0x35
+#define X1205_REG_MO		0x34
+#define X1205_REG_DT		0x33
+#define X1205_REG_HR		0x32
+#define X1205_REG_MN		0x31
+#define X1205_REG_SC		0x30
+#define X1205_REG_DTR		0x13
+#define X1205_REG_ATR		0x12
+#define X1205_REG_INT		0x11
+#define X1205_REG_0		0x10
+#define X1205_REG_Y2K1		0x0F
+#define X1205_REG_DWA1		0x0E
+#define X1205_REG_YRA1		0x0D
+#define X1205_REG_MOA1		0x0C
+#define X1205_REG_DTA1		0x0B
+#define X1205_REG_HRA1		0x0A
+#define X1205_REG_MNA1		0x09
+#define X1205_REG_SCA1		0x08
+#define X1205_REG_Y2K0		0x07
+#define X1205_REG_DWA0		0x06
+#define X1205_REG_YRA0		0x05
+#define X1205_REG_MOA0		0x04
+#define X1205_REG_DTA0		0x03
+#define X1205_REG_HRA0		0x02
+#define X1205_REG_MNA0		0x01
+#define X1205_REG_SCA0		0x00
+
+#define X1205_CCR_BASE		0x30	/* Base address of CCR */
+#define X1205_ALM0_BASE		0x00	/* Base address of ALARM0 */
+
+#define X1205_SR_RTCF		0x01	/* Clock failure */
+#define X1205_SR_WEL		0x02	/* Write Enable Latch */
+#define X1205_SR_RWEL		0x04	/* Register Write Enable */
+
+#define X1205_DTR_DTR0		0x01
+#define X1205_DTR_DTR1		0x02
+#define X1205_DTR_DTR2		0x04
+
+#define X1205_HR_MIL		0x80	/* Set in ccr.hour for 24 hr mode */
+
+static void rtc_write(int reg, u8 val)
+{
+	i2c_write(CFG_I2C_RTC_ADDR, reg, 2, &val, 1);
+}
+
+/*
+ * In the routines that deal directly with the x1205 hardware, we use
+ * rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch
+ * Epoch is initialized as 2000. Time is set to UTC.
+ */
+void rtc_get(struct rtc_time *tm)
+{
+	u8 buf[8];
+
+	i2c_read(CFG_I2C_RTC_ADDR, X1205_CCR_BASE, 2, buf, 8);
+
+	debug("%s: raw read data - sec=%02x, min=%02x, hr=%02x, "
+	      "mday=%02x, mon=%02x, year=%02x, wday=%02x, y2k=%02x\n",
+	      __FUNCTION__,
+	      buf[0], buf[1], buf[2], buf[3],
+	      buf[4], buf[5], buf[6], buf[7]);
+
+	tm->tm_sec = BCD2BIN(buf[CCR_SEC]);
+	tm->tm_min = BCD2BIN(buf[CCR_MIN]);
+	tm->tm_hour = BCD2BIN(buf[CCR_HOUR] & 0x3F); /* hr is 0-23 */
+	tm->tm_mday = BCD2BIN(buf[CCR_MDAY]);
+	tm->tm_mon = BCD2BIN(buf[CCR_MONTH]); /* mon is 0-11 */
+	tm->tm_year = BCD2BIN(buf[CCR_YEAR])
+		+ (BCD2BIN(buf[CCR_Y2K]) * 100);
+	tm->tm_wday = buf[CCR_WDAY];
+
+	debug("%s: tm is secs=%d, mins=%d, hours=%d, "
+	      "mday=%d, mon=%d, year=%d, wday=%d\n",
+	      __FUNCTION__,
+	      tm->tm_sec, tm->tm_min, tm->tm_hour,
+	      tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
+}
+
+void rtc_set(struct rtc_time *tm)
+{
+	int i;
+	u8 buf[8];
+
+	debug("Set DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
+	      tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
+	      tm->tm_hour, tm->tm_min, tm->tm_sec);
+
+	buf[CCR_SEC] = BIN2BCD(tm->tm_sec);
+	buf[CCR_MIN] = BIN2BCD(tm->tm_min);
+
+	/* set hour and 24hr bit */
+	buf[CCR_HOUR] = BIN2BCD(tm->tm_hour) | X1205_HR_MIL;
+
+	buf[CCR_MDAY] = BIN2BCD(tm->tm_mday);
+
+	/* month, 1 - 12 */
+	buf[CCR_MONTH] = BIN2BCD(tm->tm_mon);
+
+	/* year, since the rtc epoch*/
+	buf[CCR_YEAR] = BIN2BCD(tm->tm_year % 100);
+	buf[CCR_WDAY] = tm->tm_wday & 0x07;
+	buf[CCR_Y2K] = BIN2BCD(tm->tm_year / 100);
+
+	/* this sequence is required to unlock the chip */
+	rtc_write(X1205_REG_SR, X1205_SR_WEL);
+	rtc_write(X1205_REG_SR, X1205_SR_WEL | X1205_SR_RWEL);
+
+	/* write register's data */
+	for (i = 0; i < 8; i++)
+		rtc_write(X1205_CCR_BASE + i, buf[i]);
+
+	rtc_write(X1205_REG_SR, 0);
+}
+
+void rtc_reset(void)
+{
+	/*
+	 * Nothing to do
+	 */
+}
+
+#endif
diff --git a/drivers/usb/isp116x-hcd.c b/drivers/usb/isp116x-hcd.c
index b21af10..ac67030 100644
--- a/drivers/usb/isp116x-hcd.c
+++ b/drivers/usb/isp116x-hcd.c
@@ -20,7 +20,7 @@
  * MA 02111-1307 USA
  *
  *
- * Derived in part from the SL811 HCD driver "u-boot/drivers/sl811_usb.c"
+ * Derived in part from the SL811 HCD driver "u-boot/drivers/usb/sl811_usb.c"
  * (original copyright message follows):
  *
  *    (C) Copyright 2004
diff --git a/drivers/usb/usb_ohci.c b/drivers/usb/usb_ohci.c
index cfa384e..fb4726f 100644
--- a/drivers/usb/usb_ohci.c
+++ b/drivers/usb/usb_ohci.c
@@ -98,6 +98,7 @@
 static struct pci_device_id ohci_pci_ids[] = {
 	{0x10b9, 0x5237},	/* ULI1575 PCI OHCI module ids */
 	{0x1033, 0x0035},	/* NEC PCI OHCI module ids */
+	{0x1131, 0x1561},	/* Philips 1561 PCI OHCI module ids */
 	/* Please add supported PCI OHCI controller ids here */
 	{0, 0}
 };
diff --git a/drivers/usb/usbdcore_mpc8xx.c b/drivers/usb/usbdcore_mpc8xx.c
index d4c4096..122793c 100644
--- a/drivers/usb/usbdcore_mpc8xx.c
+++ b/drivers/usb/usbdcore_mpc8xx.c
@@ -3,7 +3,8 @@
  * bodonoghue@CodeHermit.ie
  *
  * References
- * DasUBoot/drivers/usbdcore_omap1510.c, for design and implementation ideas.
+ * DasUBoot/drivers/usb/usbdcore_omap1510.c, for design and implementation
+ * ideas.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 36611ec..0e40f2a 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -28,6 +28,7 @@ LIB 	:= $(obj)libvideo.a
 COBJS-y += ati_radeon_fb.o
 COBJS-y += cfb_console.o
 COBJS-y += ct69000.o
+COBJS-y += mb862xx.o
 COBJS-y += sed13806.o
 COBJS-y += sed156x.o
 COBJS-y += sm501.o
diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c
index bcf8771..4f73067 100644
--- a/drivers/video/cfb_console.c
+++ b/drivers/video/cfb_console.c
@@ -141,6 +141,18 @@ CONFIG_VIDEO_HW_CURSOR:	     - Uses the hardware cursor capability of the
 #endif
 
 /*****************************************************************************/
+/* Defines for the MB862xx driver					     */
+/*****************************************************************************/
+#ifdef CONFIG_VIDEO_MB862xx
+
+#ifdef CONFIG_VIDEO_CORALP
+#define VIDEO_FB_LITTLE_ENDIAN
+#endif
+#define VIDEO_HW_RECTFILL
+#define VIDEO_HW_BITBLT
+#endif
+
+/*****************************************************************************/
 /* Include video_fb.h after definitions of VIDEO_HW_RECTFILL etc	     */
 /*****************************************************************************/
 #include <video_fb.h>
@@ -187,9 +199,9 @@ CONFIG_VIDEO_HW_CURSOR:	     - Uses the hardware cursor capability of the
 
 /*****************************************************************************/
 /* Cursor definition:							     */
-/* CONFIG_CONSOLE_CURSOR:  Uses a timer function (see drivers/i8042.c) to    */
-/*			   let the cursor blink. Uses the macros CURSOR_OFF  */
-/*			   and CURSOR_ON.				     */
+/* CONFIG_CONSOLE_CURSOR:  Uses a timer function (see drivers/input/i8042.c) */
+/*                         to let the cursor blink. Uses the macros	     */
+/*                         CURSOR_OFF and CURSOR_ON.			     */
 /* CONFIG_VIDEO_SW_CURSOR: Draws a cursor after the last character. No	     */
 /*			   blinking is provided. Uses the macros CURSOR_SET  */
 /*			   and CURSOR_OFF.				     */
@@ -217,7 +229,7 @@ void	console_cursor (int state);
 #define CURSOR_OFF console_cursor(0);
 #define CURSOR_SET
 #ifndef CONFIG_I8042_KBD
-#warning Cursor drawing on/off needs timer function s.a. drivers/i8042.c
+#warning Cursor drawing on/off needs timer function s.a. drivers/input/i8042.c
 #endif
 #else
 #ifdef	CONFIG_CONSOLE_TIME
@@ -304,7 +316,11 @@ void	console_cursor (int state);
 #else
 #define SWAP16(x)	 (x)
 #define SWAP32(x)	 (x)
+#if !defined(VIDEO_FB_16BPP_PIXEL_SWAP)
 #define SHORTSWAP32(x)	 (x)
+#else
+#define SHORTSWAP32(x)	 ( ((x) >> 16) | ((x) << 16) )
+#endif
 #endif
 
 #if defined(DEBUG) || defined(DEBUG_CFB_CONSOLE)
@@ -647,7 +663,14 @@ static void console_back (void)
 
 static void console_newline (void)
 {
-	CURSOR_OFF console_row++;
+	/* Check if last character in the line was just drawn. If so, cursor was
+	   overwriten and need not to be cleared. Cursor clearing without this
+	   check causes overwriting the 1st character of the line if line lenght
+	   is >= CONSOLE_COLS
+	 */
+	if (console_col < CONSOLE_COLS)
+		CURSOR_OFF
+	console_row++;
 	console_col = 0;
 
 	/* Check if we need to scroll the terminal */
@@ -660,16 +683,26 @@ static void console_newline (void)
 	}
 }
 
+static void console_cr (void)
+{
+	CURSOR_OFF console_col = 0;
+}
+
 /*****************************************************************************/
 
 void video_putc (const char c)
 {
+	static int nl = 1;
+
 	switch (c) {
-	case 13:		/* ignore */
+	case 13:		/* back to first column */
+		console_cr ();
 		break;
 
 	case '\n':		/* next line */
-		console_newline ();
+		if (console_col || (!console_col && nl))
+			console_newline ();
+		nl = 1;
 		break;
 
 	case 9:		/* tab 8 */
@@ -691,8 +724,10 @@ void video_putc (const char c)
 		console_col++;
 
 		/* check for newline */
-		if (console_col >= CONSOLE_COLS)
+		if (console_col >= CONSOLE_COLS) {
 			console_newline ();
+			nl = 0;
+		}
 	}
 CURSOR_SET}
 
@@ -716,10 +751,24 @@ void video_puts (const char *s)
 	fb ++;						\
 }
 
+#if !defined(VIDEO_FB_16BPP_PIXEL_SWAP)
 #define FILL_15BIT_555RGB(r,g,b) {			\
 	*(unsigned short *)fb = SWAP16((unsigned short)(((r>>3)<<10) | ((g>>3)<<5) | (b>>3))); \
 	fb += 2;					\
 }
+#else
+static int tgl;
+static unsigned short p0;
+#define FILL_15BIT_555RGB(r,g,b) {			\
+	if (!tgl++) {					\
+		p0 = SWAP16((unsigned short)(((r>>3)<<10) | ((g>>3)<<5) | (b>>3))); \
+	} else {					\
+		tgl=0;					\
+		*(unsigned long *)(fb-2) = (SWAP16((unsigned short)(((r>>3)<<10) | ((g>>3)<<5) | (b>>3)))<<16) | p0; \
+	}						\
+	fb += 2;					\
+}
+#endif
 
 #define FILL_16BIT_565RGB(r,g,b) {			\
 	*(unsigned short *)fb = SWAP16((unsigned short)((((r)>>3)<<11) | (((g)>>2)<<5) | ((b)>>3))); \
@@ -1061,8 +1110,20 @@ void logo_plot (void *screen, int width, int x, int y)
 				*dest = ((r >> 5) << 5) | ((g >> 5) << 2) | (b >> 6);
 				break;
 			case GDF_15BIT_555RGB:
+#if !defined(VIDEO_FB_16BPP_PIXEL_SWAP)
 				*(unsigned short *) dest =
 					SWAP16 ((unsigned short) (((r >> 3) << 10) | ((g >> 3) << 5) | (b >> 3)));
+#else
+				{
+					if (!tgl++) {
+						p0 = SWAP16 ((unsigned short) (((r >> 3) << 10) | ((g >> 3) << 5) | (b >> 3)));
+					} else {
+						*(unsigned long *)(dest-2) =
+							(SWAP16 ((unsigned short) (((r >> 3) << 10) | ((g >> 3) << 5) | (b >> 3)))<<16) | p0;
+						tgl=0;
+					}
+				}
+#endif
 				break;
 			case GDF_16BIT_565RGB:
 				*(unsigned short *) dest =
diff --git a/drivers/video/mb862xx.c b/drivers/video/mb862xx.c
new file mode 100644
index 0000000..bfb057f
--- /dev/null
+++ b/drivers/video/mb862xx.c
@@ -0,0 +1,414 @@
+/*
+ * (C) Copyright 2007
+ * DENX Software Engineering, Anatolij Gustschin, agust@denx.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * mb862xx.c - Graphic interface for Fujitsu CoralP/Lime
+ * PCI and video mode code was derived from smiLynxEM driver.
+ */
+
+#include <common.h>
+
+#if defined(CONFIG_VIDEO_MB862xx)
+
+#include <asm/io.h>
+#include <pci.h>
+#include <video_fb.h>
+#include "videomodes.h"
+#include <mb862xx.h>
+
+/*
+ * Graphic Device
+ */
+GraphicDevice mb862xx;
+
+/*
+ * 32MB external RAM - 256K Chip MMIO = 0x1FC0000 ;
+ */
+#define VIDEO_MEM_SIZE	0x01FC0000
+
+#if defined(CONFIG_PCI)
+#if defined(CONFIG_VIDEO_CORALP)
+
+static struct pci_device_id supported[] = {
+	{ PCI_VENDOR_ID_FUJITSU, PCI_DEVICE_ID_CORAL_P },
+	{ PCI_VENDOR_ID_FUJITSU, PCI_DEVICE_ID_CORAL_PA },
+	{ }
+};
+
+/* Internal clock frequency divider table, index is mode number */
+unsigned int fr_div[] = { 0x00000f00, 0x00000900, 0x00000500 };
+#endif
+#endif
+
+#if defined(CONFIG_VIDEO_CORALP)
+#define	rd_io		in32r
+#define	wr_io		out32r
+#else
+#define	rd_io(addr)	in_be32((volatile unsigned*)(addr))
+#define	wr_io(addr,val)	out_be32((volatile unsigned*)(addr), (val))
+#endif
+
+#define HOST_RD_REG(off)	rd_io((pGD->frameAdrs + 0x01fc0000 + (off)))
+#define HOST_WR_REG(off, val)	wr_io((pGD->frameAdrs + 0x01fc0000 + (off)), (val))
+#define DISP_RD_REG(off)	rd_io((pGD->frameAdrs + 0x01fd0000 + (off)))
+#define DISP_WR_REG(off, val)	wr_io((pGD->frameAdrs + 0x01fd0000 + (off)), (val))
+#define DE_RD_REG(off)		rd_io((pGD->dprBase + (off)))
+#define DE_WR_REG(off, val)	wr_io((pGD->dprBase + (off)), (val))
+
+#if defined(CONFIG_VIDEO_CORALP)
+#define DE_WR_FIFO(val)		wr_io((pGD->dprBase + (0x8400)), (val))
+#else
+#define DE_WR_FIFO(val)		wr_io((pGD->dprBase + (0x04a0)), (val))
+#endif
+
+#define L0PAL_RD_REG(idx, val)	rd_io((pGD->frameAdrs + 0x01fd0400 + ((idx)<<2)))
+#define L0PAL_WR_REG(idx, val)	wr_io((pGD->frameAdrs + 0x01fd0400 + ((idx)<<2)), (val))
+#define L1PAL_RD_REG(idx, val)	rd_io((pGD->frameAdrs + 0x01fd0800 + ((idx)<<2)))
+#define L1PAL_WR_REG(idx, val)	wr_io((pGD->frameAdrs + 0x01fd0800 + ((idx)<<2)), (val))
+#define L2PAL_RD_REG(idx, val)	rd_io((pGD->frameAdrs + 0x01fd1000 + ((idx)<<2)))
+#define L2PAL_WR_REG(idx, val)	wr_io((pGD->frameAdrs + 0x01fd1000 + ((idx)<<2)), (val))
+#define L3PAL_RD_REG(idx, val)	rd_io((pGD->frameAdrs + 0x01fd1400 + ((idx)<<2)))
+#define L3PAL_WR_REG(idx, val)	wr_io((pGD->frameAdrs + 0x01fd1400 + ((idx)<<2)), (val))
+
+static void gdc_sw_reset(void)
+{
+	GraphicDevice *pGD = (GraphicDevice *)&mb862xx;
+	HOST_WR_REG (0x002c, 0x00000001);
+	udelay (500);
+	video_hw_init ();
+}
+
+
+static void de_wait(void)
+{
+	GraphicDevice *pGD = (GraphicDevice *)&mb862xx;
+	int lc = 0x10000;
+
+	/* Sync with software writes to framebuffer,
+	   try to reset if engine locked */
+	while (DE_RD_REG (0x0400) & 0x00000131)
+		if (lc-- < 0) {
+			gdc_sw_reset ();
+			printf ("gdc reset done after drawing engine lock...\n");
+			break;
+		}
+}
+
+static void de_wait_slots(int slots)
+{
+	GraphicDevice *pGD = (GraphicDevice *)&mb862xx;
+	int lc = 0x10000;
+
+	/* Wait for free fifo slots */
+	while (DE_RD_REG (0x0408) < slots)
+		if (lc-- < 0) {
+			gdc_sw_reset ();
+			printf ("gdc reset done after drawing engine lock...\n");
+			break;
+		}
+}
+
+#if !defined(CONFIG_VIDEO_CORALP)
+static void board_disp_init(void)
+{
+	GraphicDevice *pGD = (GraphicDevice *)&mb862xx;
+	const gdc_regs *regs = board_get_regs ();
+
+	while (regs->index) {
+		DISP_WR_REG (regs->index, regs->value);
+		regs++;
+	}
+}
+#endif
+
+/*
+ * Init drawing engine
+ */
+static void de_init (void)
+{
+	GraphicDevice *pGD = (GraphicDevice *)&mb862xx;
+	int cf = (pGD->gdfBytesPP == 1) ? 0x0000 : 0x8000;
+
+	pGD->dprBase = pGD->frameAdrs + 0x01ff0000;
+
+	/* Setup mode and fbbase, xres, fg, bg */
+	de_wait_slots (2);
+	DE_WR_FIFO (0xf1010108);
+	DE_WR_FIFO (cf | 0x0300);
+	DE_WR_REG (0x0440, 0x0000);
+	DE_WR_REG (0x0444, pGD->winSizeX);
+	DE_WR_REG (0x0480, 0x0000);
+	DE_WR_REG (0x0484, 0x0000);
+	/* Reset clipping */
+	DE_WR_REG (0x0454, 0x0000);
+	DE_WR_REG (0x0458, pGD->winSizeX);
+	DE_WR_REG (0x045c, 0x0000);
+	DE_WR_REG (0x0460, pGD->winSizeY);
+
+	/* Clear framebuffer using drawing engine */
+	de_wait_slots (3);
+	DE_WR_FIFO (0x09410000);
+	DE_WR_FIFO (0x00000000);
+	DE_WR_FIFO (pGD->winSizeY<<16 | pGD->winSizeX);
+}
+
+#if defined(CONFIG_VIDEO_CORALP)
+unsigned int pci_video_init(void)
+{
+	GraphicDevice *pGD = (GraphicDevice *)&mb862xx;
+	pci_dev_t devbusfn;
+
+	if ((devbusfn = pci_find_devices(supported, 0)) < 0)
+	{
+		printf ("PCI video controller not found!\n");
+		return 0;
+	}
+
+	/* PCI setup */
+	pci_write_config_dword (devbusfn, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
+	pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, &pGD->frameAdrs);
+	pGD->frameAdrs = pci_mem_to_phys (devbusfn, pGD->frameAdrs);
+
+	if (pGD->frameAdrs == 0) {
+		printf ("PCI config: failed to get base address\n");
+		return 0;
+	}
+
+	pGD->pciBase = pGD->frameAdrs;
+
+	/* Setup clocks and memory mode for Coral-P Eval. Board */
+	HOST_WR_REG (0x0038, 0x00090000);
+	udelay (200);
+	HOST_WR_REG (0xfffc, 0x11d7fa13);
+	udelay (100);
+	return pGD->frameAdrs;
+}
+
+unsigned int card_init (void)
+{
+	GraphicDevice *pGD = (GraphicDevice *)&mb862xx;
+	unsigned int cf, videomode, div = 0;
+	unsigned long t1, hsync, vsync;
+	char *penv;
+	int tmp, i, bpp;
+	struct ctfb_res_modes *res_mode;
+	struct ctfb_res_modes var_mode;
+
+	memset (pGD, 0, sizeof (GraphicDevice));
+
+	if (!pci_video_init ()) {
+		return 0;
+	}
+
+	printf ("CoralP\n");
+
+	tmp = 0;
+	videomode = 0x310;
+	/* get video mode via environment */
+	if ((penv = getenv ("videomode")) != NULL) {
+		/* deceide if it is a string */
+		if (penv[0] <= '9') {
+			videomode = (int) simple_strtoul (penv, NULL, 16);
+			tmp = 1;
+		}
+	} else {
+		tmp = 1;
+	}
+	if (tmp) {
+		/* parameter are vesa modes */
+		/* search params */
+		for (i = 0; i < VESA_MODES_COUNT; i++) {
+			if (vesa_modes[i].vesanr == videomode)
+				break;
+		}
+		if (i == VESA_MODES_COUNT) {
+			printf ("\tno VESA Mode found, switching to mode 0x%x \n", videomode);
+			i = 0;
+		}
+		res_mode =
+			(struct ctfb_res_modes *) &res_mode_init[vesa_modes[i].resindex];
+		if (vesa_modes[i].resindex > 2) {
+			printf ("\tUnsupported resolution, switching to default\n");
+			bpp = vesa_modes[1].bits_per_pixel;
+			div = fr_div[1];
+		}
+		bpp = vesa_modes[i].bits_per_pixel;
+		div = fr_div[vesa_modes[i].resindex];
+	} else {
+
+		res_mode = (struct ctfb_res_modes *) &var_mode;
+		bpp = video_get_params (res_mode, penv);
+	}
+
+	/* calculate hsync and vsync freq (info only) */
+	t1 = (res_mode->left_margin + res_mode->xres +
+	      res_mode->right_margin + res_mode->hsync_len) / 8;
+	t1 *= 8;
+	t1 *= res_mode->pixclock;
+	t1 /= 1000;
+	hsync = 1000000000L / t1;
+	t1 *= (res_mode->upper_margin + res_mode->yres +
+	       res_mode->lower_margin + res_mode->vsync_len);
+	t1 /= 1000;
+	vsync = 1000000000L / t1;
+
+	/* fill in Graphic device struct */
+	sprintf (pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres,
+		 res_mode->yres, bpp, (hsync / 1000), (vsync / 1000));
+	printf ("\t%s\n", pGD->modeIdent);
+	pGD->winSizeX = res_mode->xres;
+	pGD->winSizeY = res_mode->yres;
+	pGD->memSize = VIDEO_MEM_SIZE;
+
+	switch (bpp) {
+	case 8:
+		pGD->gdfIndex = GDF__8BIT_INDEX;
+		pGD->gdfBytesPP = 1;
+		break;
+	case 15:
+	case 16:
+		pGD->gdfIndex = GDF_15BIT_555RGB;
+		pGD->gdfBytesPP = 2;
+		break;
+	default:
+		printf ("\t%d bpp configured, but only 8,15 and 16 supported.\n", bpp);
+		printf ("\tSwitching back to 15bpp\n");
+		pGD->gdfIndex = GDF_15BIT_555RGB;
+		pGD->gdfBytesPP = 2;
+	}
+
+	/* Setup dot clock (internal pll, division rate) */
+	DISP_WR_REG (0x0100, div);
+	/* L0 init */
+	cf = (pGD->gdfBytesPP == 1) ? 0x00000000 : 0x80000000;
+	DISP_WR_REG (0x0020, ((pGD->winSizeX * pGD->gdfBytesPP)/64)<<16 |
+			     (pGD->winSizeY-1) |
+			     cf);
+	DISP_WR_REG (0x0024, 0x00000000);
+	DISP_WR_REG (0x0028, 0x00000000);
+	DISP_WR_REG (0x002c, 0x00000000);
+	DISP_WR_REG (0x0110, 0x00000000);
+	DISP_WR_REG (0x0114, 0x00000000);
+	DISP_WR_REG (0x0118, (pGD->winSizeY-1)<<16 | pGD->winSizeX);
+
+	/* Display timing init */
+	DISP_WR_REG (0x0004, (pGD->winSizeX+res_mode->left_margin+res_mode->right_margin+res_mode->hsync_len-1)<<16);
+	DISP_WR_REG (0x0008, (pGD->winSizeX-1) << 16 | (pGD->winSizeX-1));
+	DISP_WR_REG (0x000c, (res_mode->vsync_len-1)<<24|(res_mode->hsync_len-1)<<16|(pGD->winSizeX+res_mode->right_margin-1));
+	DISP_WR_REG (0x0010, (pGD->winSizeY+res_mode->lower_margin+res_mode->upper_margin+res_mode->vsync_len-1)<<16);
+	DISP_WR_REG (0x0014, (pGD->winSizeY-1) << 16 | (pGD->winSizeY+res_mode->lower_margin-1));
+	DISP_WR_REG (0x0018, 0x00000000);
+	DISP_WR_REG (0x001c, pGD->winSizeY << 16 | pGD->winSizeX);
+	/* Display enable, L0 layer */
+	DISP_WR_REG (0x0100, 0x80010000 | div);
+
+	return pGD->frameAdrs;
+}
+#endif
+
+void *video_hw_init (void)
+{
+	GraphicDevice *pGD = (GraphicDevice *)&mb862xx;
+
+	printf ("Video: Fujitsu ");
+
+	memset (pGD, 0, sizeof (GraphicDevice));
+
+#if defined(CONFIG_VIDEO_CORALP)
+	if (card_init () == 0) {
+		return (NULL);
+	}
+#else
+	/* Preliminary init of the onboard graphic controller,
+	   retrieve base address */
+	if ((pGD->frameAdrs = board_video_init ()) == 0) {
+		printf ("Controller not found!\n");
+		return (NULL);
+	} else
+		printf("Lime\n");
+#endif
+
+	de_init ();
+
+#if !defined(CONFIG_VIDEO_CORALP)
+	board_disp_init();
+#endif
+
+#if defined(CONFIG_LWMON5)
+	/* Lamp on */
+	board_backlight_switch (1);
+#endif
+
+	return pGD;
+}
+
+/*
+ * Set a RGB color in the LUT
+ */
+void video_set_lut (unsigned int index, unsigned char r, unsigned char g, unsigned char b)
+{
+	GraphicDevice *pGD = (GraphicDevice *)&mb862xx;
+
+	L0PAL_WR_REG (index, (r << 16) | (g << 8) | (b));
+}
+
+/*
+ * Drawing engine Fill and BitBlt screen region
+ */
+void video_hw_rectfill (unsigned int bpp, unsigned int dst_x, unsigned int dst_y,
+			unsigned int dim_x, unsigned int dim_y, unsigned int color)
+{
+	GraphicDevice *pGD = (GraphicDevice *)&mb862xx;
+
+	de_wait_slots (3);
+	DE_WR_REG (0x0480, color);
+	DE_WR_FIFO (0x09410000);
+	DE_WR_FIFO ((dst_y << 16) | dst_x);
+	DE_WR_FIFO ((dim_y << 16) | dim_x);
+	de_wait ();
+}
+
+void video_hw_bitblt (unsigned int bpp, unsigned int src_x, unsigned int src_y,
+		      unsigned int dst_x, unsigned int dst_y, unsigned int width,
+		      unsigned int height)
+{
+	GraphicDevice *pGD = (GraphicDevice *)&mb862xx;
+	unsigned int ctrl = 0x0d000000L;
+
+	if (src_x >= dst_x && src_y >= dst_y)
+		ctrl |= 0x00440000L;
+	else if (src_x >= dst_x && src_y <= dst_y)
+		ctrl |= 0x00460000L;
+	else if (src_x <= dst_x && src_y >= dst_y)
+		ctrl |= 0x00450000L;
+	else
+		ctrl |= 0x00470000L;
+
+	de_wait_slots (4);
+	DE_WR_FIFO (ctrl);
+	DE_WR_FIFO ((src_y << 16) | src_x);
+	DE_WR_FIFO ((dst_y << 16) | dst_x);
+	DE_WR_FIFO ((height << 16) | width);
+	de_wait (); /* sync */
+}
+#endif /* CONFIG_VIDEO_MB862xx */