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authorKumar Gala <galak@kernel.crashing.org>2008-10-16 21:58:50 -0500
committerWolfgang Denk <wd@denx.de>2008-10-17 10:51:35 +0200
commitf7d190b1c0b3ab7fc53074ad2862f7de99de37ff (patch)
tree522784dc12eeb2294ddc7b647889691764a3603d /drivers
parent42653b826adb319a1df06e24ef26096b2a5d9d2a (diff)
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85xx: Using proper I2C source clock divider for MPC8544
The MPC8544 RM incorrect shows the SEC_CFG bit in PORDEVSR2 as being bit 26, instead it should be bit 28. This caused in incorrect interpretation of the i2c_clk which is the same as the SEC clk on MPC8544. The SEC clk is controlled by cfg_sec_freq that is reported in PORDEVSR2. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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