Merge branch 'master' of git://88.191.163.10/u-boot-arm

Fixup an easy conflict over adding the clk_get prototype and USB_OTG
defines for am33xx having moved.

Conflicts:
	arch/arm/include/asm/arch-am33xx/hardware.h

Signed-off-by: Tom Rini <trini@ti.com>

9 files changed, 359 insertions, 24 deletions

diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index af94bf5..71ddb00 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -33,6 +33,7 @@ COBJS-$(CONFIG_BCM2835_GPIO)	+= bcm2835_gpio.o
 COBJS-$(CONFIG_S3C2440_GPIO)	+= s3c2440_gpio.o
 COBJS-$(CONFIG_XILINX_GPIO)	+= xilinx_gpio.o
 COBJS-$(CONFIG_ADI_GPIO2)	+= adi_gpio2.o
+COBJS-$(CONFIG_TCA642X)		+= tca642x.o
 
 COBJS	:= $(COBJS-y)
 SRCS 	:= $(COBJS:.o=.c)
diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c
index 46c0255..6a572d5 100644
--- a/drivers/gpio/mxc_gpio.c
+++ b/drivers/gpio/mxc_gpio.c
@@ -127,10 +127,10 @@ int gpio_direction_input(unsigned gpio)
 
 int gpio_direction_output(unsigned gpio, int value)
 {
-	int ret = mxc_gpio_direction(gpio, MXC_GPIO_DIRECTION_OUT);
+	int ret = gpio_set_value(gpio, value);
 
 	if (ret < 0)
 		return ret;
 
-	return gpio_set_value(gpio, value);
+	return mxc_gpio_direction(gpio, MXC_GPIO_DIRECTION_OUT);
 }
diff --git a/drivers/gpio/tca642x.c b/drivers/gpio/tca642x.c
new file mode 100644
index 0000000..6386835
--- /dev/null
+++ b/drivers/gpio/tca642x.c
@@ -0,0 +1,333 @@
+/*
+ * Copyright 2013 Texas Instruments, Inc.
+ * Author: Dan Murphy <dmurphy@ti.com>
+ *
+ * Derived work from the pca953x.c driver
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <tca642x.h>
+
+/* tca642x register address definitions */
+struct tca642x_bank_info tca642x_regs[] = {
+	{ .input_reg = 0x00,
+	  .output_reg = 0x04,
+	  .polarity_reg = 0x08,
+	  .configuration_reg = 0x0c },
+	{ .input_reg = 0x01,
+	  .output_reg = 0x05,
+	  .polarity_reg = 0x09,
+	  .configuration_reg = 0x0d },
+	{ .input_reg = 0x02,
+	  .output_reg = 0x06,
+	  .polarity_reg = 0x0a,
+	  .configuration_reg = 0x0e },
+};
+
+/*
+ * Modify masked bits in register
+ */
+static int tca642x_reg_write(uchar chip, uint8_t addr,
+		uint8_t reg_bit, uint8_t data)
+{
+	uint8_t valw;
+	int org_bus_num;
+	int ret;
+
+	org_bus_num = i2c_get_bus_num();
+	i2c_set_bus_num(CONFIG_SYS_I2C_TCA642X_BUS_NUM);
+
+	if (i2c_read(chip, addr, 1, (uint8_t *)&valw, 1)) {
+		printf("Could not read before writing\n");
+		ret = -1;
+		goto error;
+	}
+	valw &= ~reg_bit;
+	valw |= data;
+
+	ret = i2c_write(chip, addr, 1, (u8 *)&valw, 1);
+
+error:
+	i2c_set_bus_num(org_bus_num);
+	return ret;
+}
+
+static int tca642x_reg_read(uchar chip, uint8_t addr, uint8_t *data)
+{
+	uint8_t valw;
+	int org_bus_num;
+	int ret = 0;
+
+	org_bus_num = i2c_get_bus_num();
+	i2c_set_bus_num(CONFIG_SYS_I2C_TCA642X_BUS_NUM);
+	if (i2c_read(chip, addr, 1, (u8 *)&valw, 1)) {
+		ret = -1;
+		goto error;
+	}
+
+	*data = valw;
+
+error:
+	i2c_set_bus_num(org_bus_num);
+	return ret;
+}
+
+/*
+ * Set output value of IO pins in 'reg_bit' to corresponding value in 'data'
+ * 0 = low, 1 = high
+ */
+int tca642x_set_val(uchar chip, uint8_t gpio_bank,
+					uint8_t reg_bit, uint8_t data)
+{
+	uint8_t out_reg = tca642x_regs[gpio_bank].output_reg;
+
+	return tca642x_reg_write(chip, out_reg, reg_bit, data);
+}
+
+/*
+ * Set read polarity of IO pins in 'reg_bit' to corresponding value in 'data'
+ * 0 = read pin value, 1 = read inverted pin value
+ */
+int tca642x_set_pol(uchar chip, uint8_t gpio_bank,
+					uint8_t reg_bit, uint8_t data)
+{
+	uint8_t pol_reg = tca642x_regs[gpio_bank].polarity_reg;
+
+	return tca642x_reg_write(chip, pol_reg, reg_bit, data);
+}
+
+/*
+ * Set direction of IO pins in 'reg_bit' to corresponding value in 'data'
+ * 0 = output, 1 = input
+ */
+int tca642x_set_dir(uchar chip, uint8_t gpio_bank,
+					uint8_t reg_bit, uint8_t data)
+{
+	uint8_t config_reg = tca642x_regs[gpio_bank].configuration_reg;
+
+	return tca642x_reg_write(chip, config_reg, reg_bit, data);
+}
+
+/*
+ * Read current logic level of all IO pins
+ */
+int tca642x_get_val(uchar chip, uint8_t gpio_bank)
+{
+	uint8_t val;
+	uint8_t in_reg = tca642x_regs[gpio_bank].input_reg;
+
+	if (tca642x_reg_read(chip, in_reg, &val) < 0)
+		return -1;
+
+	return (int)val;
+}
+
+/*
+ * Set the inital register states for the tca642x gpio expander
+ */
+int tca642x_set_inital_state(uchar chip, struct tca642x_bank_info init_data[])
+{
+	int i, ret;
+	uint8_t config_reg;
+	uint8_t polarity_reg;
+	uint8_t output_reg;
+
+	for (i = 0; i < 3; i++) {
+		config_reg = tca642x_regs[i].configuration_reg;
+		ret = tca642x_reg_write(chip, config_reg, 0xff,
+				init_data[i].configuration_reg);
+		polarity_reg = tca642x_regs[i].polarity_reg;
+		ret = tca642x_reg_write(chip, polarity_reg, 0xff,
+				init_data[i].polarity_reg);
+		output_reg = tca642x_regs[i].output_reg;
+		ret = tca642x_reg_write(chip, output_reg, 0xff,
+				init_data[i].output_reg);
+	}
+
+	return ret;
+}
+
+#ifdef CONFIG_CMD_TCA642X
+/*
+ * Display tca642x information
+ */
+static int tca642x_info(uchar chip)
+{
+	int i, j;
+	uint8_t data;
+
+	printf("tca642x@ 0x%x (%d pins):\n", chip, 24);
+	for (i = 0; i < 3; i++) {
+		printf("Bank %i\n", i);
+		if (tca642x_reg_read(chip,
+				     tca642x_regs[i].configuration_reg,
+				     &data) < 0)
+			return -1;
+		printf("\tConfiguration: ");
+		for (j = 7; j >= 0; j--)
+			printf("%c", data & (1 << j) ? 'i' : 'o');
+		printf("\n");
+
+		if (tca642x_reg_read(chip,
+				     tca642x_regs[i].polarity_reg, &data) < 0)
+			return -1;
+		printf("\tPolarity: ");
+		for (j = 7; j >= 0; j--)
+			printf("%c", data & (1 << j) ? '1' : '0');
+		printf("\n");
+
+		if (tca642x_reg_read(chip,
+				     tca642x_regs[i].input_reg, &data) < 0)
+			return -1;
+		printf("\tInput value: ");
+		for (j = 7; j >= 0; j--)
+			printf("%c", data & (1 << j) ? '1' : '0');
+		printf("\n");
+
+		if (tca642x_reg_read(chip,
+				     tca642x_regs[i].output_reg, &data) < 0)
+			return -1;
+		printf("\tOutput value: ");
+		for (j = 7; j >= 0; j--)
+			printf("%c", data & (1 << j) ? '1' : '0');
+		printf("\n");
+	}
+
+	return 0;
+}
+
+cmd_tbl_t cmd_tca642x[] = {
+	U_BOOT_CMD_MKENT(device, 3, 0, (void *)TCA642X_CMD_DEVICE, "", ""),
+	U_BOOT_CMD_MKENT(output, 4, 0, (void *)TCA642X_CMD_OUTPUT, "", ""),
+	U_BOOT_CMD_MKENT(input, 3, 0, (void *)TCA642X_CMD_INPUT, "", ""),
+	U_BOOT_CMD_MKENT(invert, 4, 0, (void *)TCA642X_CMD_INVERT, "", ""),
+	U_BOOT_CMD_MKENT(info, 2, 0, (void *)TCA642X_CMD_INFO, "", ""),
+};
+
+int do_tca642x(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	static uchar chip = CONFIG_SYS_I2C_TCA642X_ADDR;
+	int ret = CMD_RET_USAGE, val;
+	uint8_t gpio_bank = 0;
+	uint8_t bank_shift;
+	ulong ul_arg2 = 0;
+	ulong ul_arg3 = 0;
+	cmd_tbl_t *c;
+
+	c = find_cmd_tbl(argv[1], cmd_tca642x, ARRAY_SIZE(cmd_tca642x));
+
+	/* All commands but "device" require 'maxargs' arguments */
+	if (!c ||
+	    !((argc == (c->maxargs)) ||
+	    (((int)c->cmd == TCA642X_CMD_DEVICE) &&
+	    (argc == (c->maxargs - 1))))) {
+		return CMD_RET_USAGE;
+	}
+
+	/* arg2 used as chip number or pin number */
+	if (argc > 2)
+		ul_arg2 = simple_strtoul(argv[2], NULL, 10);
+
+	/* arg3 used as pin or invert value */
+	if (argc > 3) {
+		ul_arg3 = simple_strtoul(argv[3], NULL, 10) & 0x1;
+		if (ul_arg2 <= 7) {
+			gpio_bank = 0;
+		} else if ((ul_arg2 >= 10) && (ul_arg2 <= 17)) {
+			gpio_bank = 1;
+		} else if ((ul_arg2 >= 20) && (ul_arg2 <= 27)) {
+			gpio_bank = 2;
+		} else {
+			printf("Requested pin is not available\n");
+			ret = CMD_RET_FAILURE;
+			goto error;
+		}
+	}
+
+	switch ((int)c->cmd) {
+	case TCA642X_CMD_INFO:
+		ret = tca642x_info(chip);
+		if (ret)
+			ret = CMD_RET_FAILURE;
+		break;
+
+	case TCA642X_CMD_DEVICE:
+		if (argc == 3)
+			chip = (uint8_t)ul_arg2;
+		printf("Current device address: 0x%x\n", chip);
+		ret = CMD_RET_SUCCESS;
+		break;
+
+	case TCA642X_CMD_INPUT:
+		bank_shift = ul_arg2 - (gpio_bank * 10);
+		ret = tca642x_set_dir(chip, gpio_bank, (1 << bank_shift),
+				TCA642X_DIR_IN << bank_shift);
+		val = (tca642x_get_val(chip, gpio_bank) &
+				(1 << bank_shift)) != 0;
+
+		if (ret)
+			ret = CMD_RET_FAILURE;
+		else
+			printf("chip 0x%02x, pin 0x%lx = %d\n", chip,
+			       ul_arg2, val);
+		break;
+
+	case TCA642X_CMD_OUTPUT:
+		bank_shift = ul_arg2 - (gpio_bank * 10);
+		ret = tca642x_set_dir(chip, gpio_bank, (1 << bank_shift),
+				(TCA642X_DIR_OUT << bank_shift));
+		if (!ret)
+			ret = tca642x_set_val(chip,
+					      gpio_bank, (1 << bank_shift),
+					      (ul_arg3 << bank_shift));
+		if (ret)
+			ret = CMD_RET_FAILURE;
+		break;
+
+	case TCA642X_CMD_INVERT:
+		bank_shift = ul_arg2 - (gpio_bank * 10);
+		ret = tca642x_set_pol(chip, gpio_bank, (1 << bank_shift),
+					(ul_arg3 << bank_shift));
+		if (ret)
+			ret = CMD_RET_FAILURE;
+		break;
+	}
+error:
+	if (ret == CMD_RET_FAILURE)
+		eprintf("Error talking to chip at 0x%x\n", chip);
+
+	return ret;
+}
+
+U_BOOT_CMD(
+	tca642x,	5,	1,	do_tca642x,
+	"tca642x gpio access",
+	"device [dev]\n"
+	"	- show or set current device address\n"
+	"tca642x info\n"
+	"	- display info for current chip\n"
+	"tca642x output pin 0|1\n"
+	"	- set pin as output and drive low or high\n"
+	"tca642x invert pin 0|1\n"
+	"	- disable/enable polarity inversion for reads\n"
+	"tca642x input pin\n"
+	"	- set pin as input and read value"
+);
+
+#endif /* CONFIG_CMD_TCA642X */
diff --git a/drivers/net/calxedaxgmac.c b/drivers/net/calxedaxgmac.c
index 2c61710..ff94865 100644
--- a/drivers/net/calxedaxgmac.c
+++ b/drivers/net/calxedaxgmac.c
@@ -390,7 +390,7 @@ static int xgmac_init(struct eth_device *dev, bd_t * bis)
 	/* set flow control parameters and store and forward mode */
 	value = (FIFO_MINUS_12K << XGMAC_CORE_OMR_RFD_SHIFT) |
 		(FIFO_MINUS_4K << XGMAC_CORE_OMR_RFA_SHIFT) |
-		XGMAC_CORE_OMR_EFC | XGMAC_CORE_OMR_TSF | XGMAC_CORE_OMR_RSF;
+		XGMAC_CORE_OMR_EFC | XGMAC_CORE_OMR_TSF;
 	writel(value, &regs->core_opmode);
 
 	/* enable pause frames */
diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c
index 379b679..9bab71a 100644
--- a/drivers/net/cpsw.c
+++ b/drivers/net/cpsw.c
@@ -51,8 +51,6 @@
 #define CPDMA_RXCP_VER1		0x160
 #define CPDMA_RXCP_VER2		0x260
 
-#define CPDMA_RAM_ADDR		0x4a102000
-
 /* Descriptor mode bits */
 #define CPDMA_DESC_SOP		BIT(31)
 #define CPDMA_DESC_EOP		BIT(30)
@@ -489,7 +487,7 @@ static inline void wait_for_idle(void)
 static int cpsw_mdio_read(struct mii_dev *bus, int phy_id,
 				int dev_addr, int phy_reg)
 {
-	unsigned short data;
+	int data;
 	u32 reg;
 
 	if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
@@ -774,6 +772,7 @@ static int cpsw_init(struct eth_device *dev, bd_t *bis)
 
 	/* enable statistics collection only on the host port */
 	__raw_writel(BIT(priv->host_port), &priv->regs->stat_port_en);
+	__raw_writel(0x7, &priv->regs->stat_port_en);
 
 	cpsw_ale_port_state(priv, priv->host_port, ALE_PORT_STATE_FORWARD);
 
@@ -984,12 +983,12 @@ int cpsw_register(struct cpsw_platform_data *data)
 		return -ENOMEM;
 	}
 
-	priv->descs		= (void *)CPDMA_RAM_ADDR;
 	priv->host_port		= data->host_port_num;
 	priv->regs		= regs;
 	priv->host_port_regs	= regs + data->host_port_reg_ofs;
 	priv->dma_regs		= regs + data->cpdma_reg_ofs;
 	priv->ale_regs		= regs + data->ale_reg_ofs;
+	priv->descs		= (void *)regs + data->bd_ram_ofs;
 
 	int idx = 0;
 
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 6fe793d..62925bb 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -277,7 +277,7 @@ int genphy_parse_link(struct phy_device *phydev)
 	/* We're using autonegotiation */
 	if (mii_reg & BMSR_ANEGCAPABLE) {
 		u32 lpa = 0;
-		u32 gblpa = 0;
+		int gblpa = 0;
 		u32 estatus = 0;
 
 		/* Check for gigabit capability */
@@ -286,6 +286,10 @@ int genphy_parse_link(struct phy_device *phydev)
 			 * both PHYs in the link
 			 */
 			gblpa = phy_read(phydev, MDIO_DEVAD_NONE, MII_STAT1000);
+			if (gblpa < 0) {
+				debug("Could not read MII_STAT1000. Ignoring gigabit capability\n");
+				gblpa = 0;
+			}
 			gblpa &= phy_read(phydev,
 					MDIO_DEVAD_NONE, MII_CTRL1000) << 2;
 		}
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index d77c25f..181c818 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -57,7 +57,8 @@ void NS16550_init(NS16550_t com_port, int baud_divisor)
 
 	serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier);
 #if (defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)) || \
-			defined(CONFIG_AM33XX) || defined(CONFIG_TI814X)
+			defined(CONFIG_AM33XX) || defined(CONFIG_TI81XX) || \
+			defined(CONFIG_AM43XX)
 	serial_out(0x7, &com_port->mdr1);	/* mode select reset TL16C750*/
 #endif
 	serial_out(UART_LCR_BKSE | UART_LCRVAL, &com_port->lcr);
@@ -72,7 +73,7 @@ void NS16550_init(NS16550_t com_port, int baud_divisor)
 	serial_out(UART_LCRVAL, &com_port->lcr);
 #if (defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)) || \
 	defined(CONFIG_AM33XX) || defined(CONFIG_SOC_DA8XX) || \
-	defined(CONFIG_TI814X)
+	defined(CONFIG_TI81XX) || defined(CONFIG_AM43XX)
 
 	/* /16 is proper to hit 115200 with 48MHz */
 	serial_out(0, &com_port->mdr1);
diff --git a/drivers/usb/musb-new/musb_core.c b/drivers/usb/musb-new/musb_core.c
index da93571..36681b6 100644
--- a/drivers/usb/musb-new/musb_core.c
+++ b/drivers/usb/musb-new/musb_core.c
@@ -1311,9 +1311,7 @@ static int __devinit ep_config_from_table(struct musb *musb)
 		break;
 	}
 
-	printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
-			musb_driver_name, fifo_mode);
-
+	pr_debug("%s: setup fifo_mode %d\n", musb_driver_name, fifo_mode);
 
 done:
 	offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
@@ -1341,10 +1339,9 @@ done:
 		musb->nr_endpoints = max(epn, musb->nr_endpoints);
 	}
 
-	printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
-			musb_driver_name,
-			n + 1, musb->config->num_eps * 2 - 1,
-			offset, (1 << (musb->config->ram_bits + 2)));
+	pr_debug("%s: %d/%d max ep, %d/%d memory\n", musb_driver_name, n + 1,
+		 musb->config->num_eps * 2 - 1, offset,
+		 (1 << (musb->config->ram_bits + 2)));
 
 	if (!musb->bulk_ep) {
 		pr_debug("%s: missing bulk\n", musb_driver_name);
@@ -1447,8 +1444,7 @@ static int __devinit musb_core_init(u16 musb_type, struct musb *musb)
 	if (reg & MUSB_CONFIGDATA_SOFTCONE)
 		strcat(aInfo, ", SoftConn");
 
-	printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
-			musb_driver_name, reg, aInfo);
+	pr_debug("%s:ConfigData=0x%02x (%s)\n", musb_driver_name, reg, aInfo);
 
 	aDate[0] = 0;
 	if (MUSB_CONTROLLER_MHDRC == musb_type) {
@@ -1469,8 +1465,8 @@ static int __devinit musb_core_init(u16 musb_type, struct musb *musb)
 	snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
 		MUSB_HWVERS_MINOR(musb->hwvers),
 		(musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
-	printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
-			musb_driver_name, type, aRevision, aDate);
+	pr_debug("%s: %sHDRC RTL version %s %s\n", musb_driver_name, type,
+		 aRevision, aDate);
 
 	/* configure ep0 */
 	musb_configure_ep0(musb);
@@ -2122,7 +2118,7 @@ musb_init_controller(struct musb_hdrc_platform_data *plat, struct device *dev,
 
 	pm_runtime_put(musb->controller);
 
-	dev_info(dev, "USB %s mode controller at %p using %s, IRQ %d\n",
+	pr_debug("USB %s mode controller at %p using %s, IRQ %d\n",
 			({char *s;
 			 switch (musb->board_mode) {
 			 case MUSB_HOST:		s = "Host"; break;
diff --git a/drivers/video/mxc_ipuv3_fb.c b/drivers/video/mxc_ipuv3_fb.c
index fd74370..3e21fb2 100644
--- a/drivers/video/mxc_ipuv3_fb.c
+++ b/drivers/video/mxc_ipuv3_fb.c
@@ -399,8 +399,9 @@ static int mxcfb_map_video_memory(struct fb_info *fbi)
 		fbi->fix.smem_len = fbi->var.yres_virtual *
 				    fbi->fix.line_length;
 	}
-
-	fbi->screen_base = (char *)malloc(fbi->fix.smem_len);
+	fbi->fix.smem_len = roundup(fbi->fix.smem_len, ARCH_DMA_MINALIGN);
+	fbi->screen_base = (char *)memalign(ARCH_DMA_MINALIGN,
+					    fbi->fix.smem_len);
 	fbi->fix.smem_start = (unsigned long)fbi->screen_base;
 	if (fbi->screen_base == 0) {
 		puts("Unable to allocate framebuffer memory\n");