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authorWolfgang Denk <wd@denx.de>2012-07-18 10:47:03 +0200
committerWolfgang Denk <wd@denx.de>2012-07-18 10:47:03 +0200
commit66714b1a6df0a5a9f1656a6d4e6eea3c7ecdf7ae (patch)
tree946a13465467eb58f68cf8cf5e121017d380fe2a /drivers
parent3a9469b5cbd467b3a7b176b4feb2073a04f294b6 (diff)
parentcf65d478ab4e0bb0247c374e6b0b40ef77eddbe8 (diff)
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Merge branch 'next' of git://git.denx.de/u-boot-video
* 'next' of git://git.denx.de/u-boot-video: ipu_common: Add ldb_clk for use in parenting the pixel clock ipu_common: Do not hardcode the ipu_clk frequency ipu_common: Rename MXC_CCM_BASE ipu_common: Let clk_ipu_enable/disable only run on MX51 and MX53 ipu_common: Only apply the erratum to MX51 video: Rename CONFIG_VIDEO_MX5 mx6: Allow mx6 to access the IPUv3 registers common lcd: minor coding style changes Signed-off-by: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/video/Makefile2
-rw-r--r--drivers/video/cfb_console.c2
-rw-r--r--drivers/video/ipu_common.c23
-rw-r--r--drivers/video/ipu_disp.c3
-rw-r--r--drivers/video/ipu_regs.h12
5 files changed, 33 insertions, 9 deletions
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 44b7feb..2f8e2b5 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -42,7 +42,7 @@ COBJS-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o
COBJS-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o
COBJS-$(CONFIG_VIDEO_MB86R0xGDC) += mb86r0xgdc.o videomodes.o
COBJS-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o
-COBJS-$(CONFIG_VIDEO_MX5) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o
+COBJS-$(CONFIG_VIDEO_IPUV3) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o
COBJS-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o
COBJS-$(CONFIG_VIDEO_SED13806) += sed13806.o
COBJS-$(CONFIG_VIDEO_SM501) += sm501.o
diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c
index 92fa77d..19d061f 100644
--- a/drivers/video/cfb_console.c
+++ b/drivers/video/cfb_console.c
@@ -164,7 +164,7 @@
/*
* Defines for the i.MX31 driver (mx3fb.c)
*/
-#if defined(CONFIG_VIDEO_MX3) || defined(CONFIG_VIDEO_MX5)
+#if defined(CONFIG_VIDEO_MX3) || defined(CONFIG_VIDEO_IPUV3)
#define VIDEO_FB_16BPP_WORD_SWAP
#endif
diff --git a/drivers/video/ipu_common.c b/drivers/video/ipu_common.c
index 9d20c86..2020da9 100644
--- a/drivers/video/ipu_common.c
+++ b/drivers/video/ipu_common.c
@@ -163,6 +163,7 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
static int clk_ipu_enable(struct clk *clk)
{
+#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
u32 reg;
reg = __raw_readl(clk->enable_reg);
@@ -178,12 +179,13 @@ static int clk_ipu_enable(struct clk *clk)
reg = __raw_readl(&mxc_ccm->clpcr);
reg &= ~MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS;
__raw_writel(reg, &mxc_ccm->clpcr);
-
+#endif
return 0;
}
static void clk_ipu_disable(struct clk *clk)
{
+#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
u32 reg;
reg = __raw_readl(clk->enable_reg);
@@ -202,13 +204,14 @@ static void clk_ipu_disable(struct clk *clk)
reg = __raw_readl(&mxc_ccm->clpcr);
reg |= MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS;
__raw_writel(reg, &mxc_ccm->clpcr);
+#endif
}
static struct clk ipu_clk = {
.name = "ipu_clk",
- .rate = 133000000,
- .enable_reg = (u32 *)(MXC_CCM_BASE +
+ .rate = CONFIG_IPUV3_CLK,
+ .enable_reg = (u32 *)(CCM_BASE_ADDR +
offsetof(struct mxc_ccm_reg, CCGR5)),
.enable_shift = MXC_CCM_CCGR5_CG5_OFFSET,
.enable = clk_ipu_enable,
@@ -216,8 +219,15 @@ static struct clk ipu_clk = {
.usecount = 0,
};
+static struct clk ldb_clk = {
+ .name = "ldb_clk",
+ .rate = 65000000,
+ .usecount = 0,
+};
+
/* Globals */
struct clk *g_ipu_clk;
+struct clk *g_ldb_clk;
unsigned char g_ipu_clk_enabled;
struct clk *g_di_clk[2];
struct clk *g_pixel_clk[2];
@@ -340,7 +350,7 @@ static int ipu_pixel_clk_set_parent(struct clk *clk, struct clk *parent)
if (parent == g_ipu_clk)
di_gen &= ~DI_GEN_DI_CLK_EXT;
- else if (!IS_ERR(g_di_clk[clk->id]) && parent == g_di_clk[clk->id])
+ else if (!IS_ERR(g_di_clk[clk->id]) && parent == g_ldb_clk)
di_gen |= DI_GEN_DI_CLK_EXT;
else
return -EINVAL;
@@ -401,6 +411,7 @@ void ipu_reset(void)
int ipu_probe(void)
{
unsigned long ipu_base;
+#if defined CONFIG_MX51
u32 temp;
u32 *reg_hsc_mcd = (u32 *)MIPI_HSC_BASE_ADDR;
@@ -414,6 +425,7 @@ int ipu_probe(void)
temp = __raw_readl(reg_hsc_mxt_conf);
__raw_writel(temp | 0x10000, reg_hsc_mxt_conf);
+#endif
ipu_base = IPU_CTRL_BASE_ADDR;
ipu_cpmem_base = (u32 *)(ipu_base + IPU_CPMEM_REG_BASE);
@@ -424,7 +436,8 @@ int ipu_probe(void)
g_ipu_clk = &ipu_clk;
debug("ipu_clk = %u\n", clk_get_rate(g_ipu_clk));
-
+ g_ldb_clk = &ldb_clk;
+ debug("ldb_clk = %u\n", clk_get_rate(g_ldb_clk));
ipu_reset();
clk_set_parent(g_pixel_clk[0], g_ipu_clk);
diff --git a/drivers/video/ipu_disp.c b/drivers/video/ipu_disp.c
index fa8fb2c..b4116df 100644
--- a/drivers/video/ipu_disp.c
+++ b/drivers/video/ipu_disp.c
@@ -64,6 +64,7 @@ static int dmfc_size_28, dmfc_size_29, dmfc_size_24, dmfc_size_27, dmfc_size_23;
int g_di1_tvout;
extern struct clk *g_ipu_clk;
+extern struct clk *g_ldb_clk;
extern struct clk *g_di_clk[2];
extern struct clk *g_pixel_clk[2];
@@ -941,7 +942,7 @@ int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk,
udelay(10000);
}
}
- clk_set_parent(g_pixel_clk[disp], g_di_clk[disp]);
+ clk_set_parent(g_pixel_clk[disp], g_ldb_clk);
} else {
if (clk_get_usecount(g_pixel_clk[disp]) != 0)
clk_set_parent(g_pixel_clk[disp], g_ipu_clk);
diff --git a/drivers/video/ipu_regs.h b/drivers/video/ipu_regs.h
index 93b195f..a43aa03 100644
--- a/drivers/video/ipu_regs.h
+++ b/drivers/video/ipu_regs.h
@@ -47,14 +47,24 @@
#define IPU_SMFC_REG_BASE 0x00050000
#define IPU_DC_REG_BASE 0x00058000
#define IPU_DMFC_REG_BASE 0x00060000
+#define IPU_VDI_REG_BASE 0x00680000
+#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
#define IPU_CPMEM_REG_BASE 0x01000000
#define IPU_LUT_REG_BASE 0x01020000
#define IPU_SRM_REG_BASE 0x01040000
#define IPU_TPM_REG_BASE 0x01060000
#define IPU_DC_TMPL_REG_BASE 0x01080000
#define IPU_ISP_TBPR_REG_BASE 0x010C0000
-#define IPU_VDI_REG_BASE 0x00680000
+#elif defined(CONFIG_MX6Q)
+#define IPU_CPMEM_REG_BASE 0x00100000
+#define IPU_LUT_REG_BASE 0x00120000
+#define IPU_SRM_REG_BASE 0x00140000
+#define IPU_TPM_REG_BASE 0x00160000
+#define IPU_DC_TMPL_REG_BASE 0x00180000
+#define IPU_ISP_TBPR_REG_BASE 0x001C0000
+#endif
+#define IPU_CTRL_BASE_ADDR (IPU_SOC_BASE_ADDR + IPU_SOC_OFFSET)
extern u32 *ipu_dc_tmpl_reg;