Merge branch 'master' of git://git.denx.de/u-boot-net

5 files changed, 26 insertions, 4 deletions

diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c
index 2d4da4b..8ba98b2 100644
--- a/drivers/net/e1000.c
+++ b/drivers/net/e1000.c
@@ -1688,6 +1688,16 @@ e1000_init_hw(struct eth_device *nic)
 		E1000_WRITE_REG(hw, TXDCTL, ctrl);
 	}
 
+	/* Set the receive descriptor write back policy */
+
+	if (hw->mac_type >= e1000_82571) {
+		ctrl = E1000_READ_REG(hw, RXDCTL);
+		ctrl =
+		    (ctrl & ~E1000_RXDCTL_WTHRESH) |
+		    E1000_RXDCTL_FULL_RX_DESC_WB;
+		E1000_WRITE_REG(hw, RXDCTL, ctrl);
+	}
+
 	switch (hw->mac_type) {
 	default:
 		break;
diff --git a/drivers/net/e1000.h b/drivers/net/e1000.h
index fd1d8f8..1bbae50 100644
--- a/drivers/net/e1000.h
+++ b/drivers/net/e1000.h
@@ -1551,6 +1551,7 @@ struct e1000_hw {
 #define E1000_RXDCTL_HTHRESH 0x00003F00	/* RXDCTL Host Threshold */
 #define E1000_RXDCTL_WTHRESH 0x003F0000	/* RXDCTL Writeback Threshold */
 #define E1000_RXDCTL_GRAN    0x01000000	/* RXDCTL Granularity */
+#define E1000_RXDCTL_FULL_RX_DESC_WB 0x01010000	/* GRAN=1, WTHRESH=1 */
 
 /* Transmit Descriptor Control */
 #define E1000_TXDCTL_PTHRESH 0x0000003F	/* TXDCTL Prefetch Threshold */
diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index e51e799..4b27198 100644
--- a/drivers/net/phy/marvell.c
+++ b/drivers/net/phy/marvell.c
@@ -425,6 +425,16 @@ static struct phy_driver M88E1118_driver = {
 	.shutdown = &genphy_shutdown,
 };
 
+static struct phy_driver M88E1118R_driver = {
+	.name = "Marvell 88E1118R",
+	.uid = 0x1410e40,
+	.mask = 0xffffff0,
+	.features = PHY_GBIT_FEATURES,
+	.config = &m88e1118_config,
+	.startup = &m88e1118_startup,
+	.shutdown = &genphy_shutdown,
+};
+
 static struct phy_driver M88E1121R_driver = {
 	.name = "Marvell 88E1121R",
 	.uid = 0x1410cb0,
@@ -461,6 +471,7 @@ int phy_marvell_init(void)
 	phy_register(&M88E1145_driver);
 	phy_register(&M88E1121R_driver);
 	phy_register(&M88E1118_driver);
+	phy_register(&M88E1118R_driver);
 	phy_register(&M88E1111S_driver);
 	phy_register(&M88E1011S_driver);
 
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index 2d9cc32..e6fc8c8 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -417,7 +417,7 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
 		printf(SHETHER_NAME ": 100Base/");
 #if defined(SH_ETH_TYPE_GETHER)
 		sh_eth_write(eth, GECMR_100B, GECMR);
-#elif defined(CONFIG_CPU_SH7757)
+#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
 		sh_eth_write(eth, 1, RTRATE);
 #elif defined(CONFIG_CPU_SH7724)
 		val = ECMR_RTM;
@@ -426,7 +426,7 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
 		printf(SHETHER_NAME ": 10Base/");
 #if defined(SH_ETH_TYPE_GETHER)
 		sh_eth_write(eth, GECMR_10B, GECMR);
-#elif defined(CONFIG_CPU_SH7757)
+#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
 		sh_eth_write(eth, 0, RTRATE);
 #endif
 	}
diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h
index 61d2df9..568fafe 100644
--- a/drivers/net/sh_eth.h
+++ b/drivers/net/sh_eth.h
@@ -288,7 +288,7 @@ static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
 #if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
 #define SH_ETH_TYPE_GETHER
 #define BASE_IO_ADDR	0xfee00000
-#elif defined(CONFIG_CPU_SH7757)
+#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
 #if defined(CONFIG_SH_ETHER_USE_GETHER)
 #define SH_ETH_TYPE_GETHER
 #define BASE_IO_ADDR	0xfee00000
@@ -346,7 +346,7 @@ enum DMAC_T_BIT {
 
 /* GECMR */
 enum GECMR_BIT {
-#if defined(CONFIG_CPU_SH7757)
+#if defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
 	GECMR_1000B = 0x20, GECMR_100B = 0x01, GECMR_10B = 0x00,
 #else
 	GECMR_1000B = 0x01, GECMR_100B = 0x04, GECMR_10B = 0x00,