* Patches by Richard Woodruff, 01 Oct 2004:

  add support for the TI OMAP2420 processor and its H4 reference
  board

* Patch by Christian Pellegrin, 24 Sep 2004:
  Added support for NE2000 compatible (DP8390, DP83902) NICs.

7 files changed, 1703 insertions, 6 deletions

diff --git a/drivers/8390.h b/drivers/8390.h
new file mode 100644
index 0000000..4e3cdd2
--- /dev/null
+++ b/drivers/8390.h
@@ -0,0 +1,126 @@
+/*
+
+Ported to U-Boot  by Christian Pellegrin <chri@ascensit.com>
+
+Based on sources from the Linux kernel (pcnet_cs.c, 8390.h) and
+eCOS(if_dp83902a.c, if_dp83902a.h). Both of these 2 wonderful world
+are GPL, so this is, of course, GPL.
+
+*/
+
+/* Generic NS8390 register definitions. */
+/* This file is part of Donald Becker's 8390 drivers, and is distributed
+   under the same license. Auto-loading of 8390.o only in v2.2 - Paul G.
+   Some of these names and comments originated from the Crynwr
+   packet drivers, which are distributed under the GPL. */
+
+#ifndef _8390_h
+#define _8390_h
+
+/* Some generic ethernet register configurations. */
+#define E8390_TX_IRQ_MASK	0xa	/* For register EN0_ISR */
+#define E8390_RX_IRQ_MASK	0x5
+#define E8390_RXCONFIG		0x4	/* EN0_RXCR: broadcasts, no multicast,errors */
+#define E8390_RXOFF		0x20	/* EN0_RXCR: Accept no packets */
+#define E8390_TXCONFIG		0x00	/* EN0_TXCR: Normal transmit mode */
+#define E8390_TXOFF		0x02	/* EN0_TXCR: Transmitter off */
+
+/*  Register accessed at EN_CMD, the 8390 base addr.  */
+#define E8390_STOP	0x01	/* Stop and reset the chip */
+#define E8390_START	0x02	/* Start the chip, clear reset */
+#define E8390_TRANS	0x04	/* Transmit a frame */
+#define E8390_RREAD	0x08	/* Remote read */
+#define E8390_RWRITE	0x10	/* Remote write  */
+#define E8390_NODMA	0x20	/* Remote DMA */
+#define E8390_PAGE0	0x00	/* Select page chip registers */
+#define E8390_PAGE1	0x40	/* using the two high-order bits */
+#define E8390_PAGE2	0x80	/* Page 3 is invalid. */
+
+/*
+ *	Only generate indirect loads given a machine that needs them.
+ *      - removed AMIGA_PCMCIA from this list, handled as ISA io now
+ */
+
+#define n2k_inb(port)   (*((volatile unsigned char *)(port+CONFIG_DRIVER_NE2000_BASE)))
+#define n2k_outb(val,port)  (*((volatile unsigned char *)(port+CONFIG_DRIVER_NE2000_BASE)) = val)
+
+#define EI_SHIFT(x)	(x)
+
+#define E8390_CMD	EI_SHIFT(0x00)  /* The command register (for all pages) */
+/* Page 0 register offsets. */
+#define EN0_CLDALO	EI_SHIFT(0x01)	/* Low byte of current local dma addr  RD */
+#define EN0_STARTPG	EI_SHIFT(0x01)	/* Starting page of ring bfr WR */
+#define EN0_CLDAHI	EI_SHIFT(0x02)	/* High byte of current local dma addr  RD */
+#define EN0_STOPPG	EI_SHIFT(0x02)	/* Ending page +1 of ring bfr WR */
+#define EN0_BOUNDARY	EI_SHIFT(0x03)	/* Boundary page of ring bfr RD WR */
+#define EN0_TSR		EI_SHIFT(0x04)	/* Transmit status reg RD */
+#define EN0_TPSR	EI_SHIFT(0x04)	/* Transmit starting page WR */
+#define EN0_NCR		EI_SHIFT(0x05)	/* Number of collision reg RD */
+#define EN0_TCNTLO	EI_SHIFT(0x05)	/* Low  byte of tx byte count WR */
+#define EN0_FIFO	EI_SHIFT(0x06)	/* FIFO RD */
+#define EN0_TCNTHI	EI_SHIFT(0x06)	/* High byte of tx byte count WR */
+#define EN0_ISR		EI_SHIFT(0x07)	/* Interrupt status reg RD WR */
+#define EN0_CRDALO	EI_SHIFT(0x08)	/* low byte of current remote dma address RD */
+#define EN0_RSARLO	EI_SHIFT(0x08)	/* Remote start address reg 0 */
+#define EN0_CRDAHI	EI_SHIFT(0x09)	/* high byte, current remote dma address RD */
+#define EN0_RSARHI	EI_SHIFT(0x09)	/* Remote start address reg 1 */
+#define EN0_RCNTLO	EI_SHIFT(0x0a)	/* Remote byte count reg WR */
+#define EN0_RCNTHI	EI_SHIFT(0x0b)	/* Remote byte count reg WR */
+#define EN0_RSR		EI_SHIFT(0x0c)	/* rx status reg RD */
+#define EN0_RXCR	EI_SHIFT(0x0c)	/* RX configuration reg WR */
+#define EN0_TXCR	EI_SHIFT(0x0d)	/* TX configuration reg WR */
+#define EN0_COUNTER0	EI_SHIFT(0x0d)	/* Rcv alignment error counter RD */
+#define EN0_DCFG	EI_SHIFT(0x0e)	/* Data configuration reg WR */
+#define EN0_COUNTER1	EI_SHIFT(0x0e)	/* Rcv CRC error counter RD */
+#define EN0_IMR		EI_SHIFT(0x0f)	/* Interrupt mask reg WR */
+#define EN0_COUNTER2	EI_SHIFT(0x0f)	/* Rcv missed frame error counter RD */
+
+/* Bits in EN0_ISR - Interrupt status register */
+#define ENISR_RX	0x01	/* Receiver, no error */
+#define ENISR_TX	0x02	/* Transmitter, no error */
+#define ENISR_RX_ERR	0x04	/* Receiver, with error */
+#define ENISR_TX_ERR	0x08	/* Transmitter, with error */
+#define ENISR_OVER	0x10	/* Receiver overwrote the ring */
+#define ENISR_COUNTERS	0x20	/* Counters need emptying */
+#define ENISR_RDC	0x40	/* remote dma complete */
+#define ENISR_RESET	0x80	/* Reset completed */
+#define ENISR_ALL	0x3f	/* Interrupts we will enable */
+
+/* Bits in EN0_DCFG - Data config register */
+#define ENDCFG_WTS	0x01	/* word transfer mode selection */
+#define ENDCFG_BOS	0x02	/* byte order selection */
+#define ENDCFG_AUTO_INIT   0x10        /* Auto-init to remove packets from ring */
+#define ENDCFG_FIFO		0x40	/* 8 bytes */
+
+
+
+/* Page 1 register offsets. */
+#define EN1_PHYS   EI_SHIFT(0x01)	/* This board's physical enet addr RD WR */
+#define EN1_PHYS_SHIFT(i)  EI_SHIFT(i+1) /* Get and set mac address */
+#define EN1_CURPAG EI_SHIFT(0x07)	/* Current memory page RD WR */
+#define EN1_MULT   EI_SHIFT(0x08)	/* Multicast filter mask array (8 bytes) RD WR */
+#define EN1_MULT_SHIFT(i)  EI_SHIFT(8+i) /* Get and set multicast filter */
+
+/* Bits in received packet status byte and EN0_RSR*/
+#define ENRSR_RXOK	0x01	/* Received a good packet */
+#define ENRSR_CRC	0x02	/* CRC error */
+#define ENRSR_FAE	0x04	/* frame alignment error */
+#define ENRSR_FO	0x08	/* FIFO overrun */
+#define ENRSR_MPA	0x10	/* missed pkt */
+#define ENRSR_PHY	0x20	/* physical/multicast address */
+#define ENRSR_DIS	0x40	/* receiver disable. set in monitor mode */
+#define ENRSR_DEF	0x80	/* deferring */
+
+/* Transmitted packet status, EN0_TSR. */
+#define ENTSR_PTX 0x01	/* Packet transmitted without error */
+#define ENTSR_ND  0x02	/* The transmit wasn't deferred. */
+#define ENTSR_COL 0x04	/* The transmit collided at least once. */
+#define ENTSR_ABT 0x08  /* The transmit collided 16 times, and was deferred. */
+#define ENTSR_CRS 0x10	/* The carrier sense was lost. */
+#define ENTSR_FU  0x20  /* A "FIFO underrun" occurred during transmit. */
+#define ENTSR_CDH 0x40	/* The collision detect "heartbeat" signal was lost. */
+#define ENTSR_OWC 0x80  /* There was an out-of-window collision. */
+
+#define NIC_RECEIVE_MONITOR_MODE 0x20
+
+#endif /* _8390_h */
diff --git a/drivers/Makefile b/drivers/Makefile
index 8b73d66..cc13a7f 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -32,9 +32,10 @@ OBJS	= 3c589.o 5701rls.o ali512x.o \
 	  cs8900.o ct69000.o dataflash.o dc2114x.o dm9000x.o \
 	  e1000.o eepro100.o \
 	  i8042.o i82365.o inca-ip_sw.o keyboard.o \
-	  lan91c96.o natsemi.o netarm_eth.o netconsole.o \
+	  lan91c96.o \
+	  natsemi.o ne2000.o netarm_eth.o netconsole.o \
 	  ns16550.o ns8382x.o ns87308.o omap1510_i2c.o \
-	  pci.o pci_auto.o pci_indirect.o \
+	  omap24xx_i2c.o pci.o pci_auto.o pci_indirect.o \
 	  pcnet.o plb2800_eth.o \
 	  ps2ser.o ps2mult.o pc_keyb.o \
 	  rtl8019.o rtl8139.o rtl8169.o \
diff --git a/drivers/ne2000.c b/drivers/ne2000.c
new file mode 100644
index 0000000..b7ed876
--- /dev/null
+++ b/drivers/ne2000.c
@@ -0,0 +1,963 @@
+/*
+Ported to U-Boot  by Christian Pellegrin <chri@ascensit.com>
+
+Based on sources from the Linux kernel (pcnet_cs.c, 8390.h) and
+eCOS(if_dp83902a.c, if_dp83902a.h). Both of these 2 wonderful world
+are GPL, so this is, of course, GPL.
+
+
+==========================================================================
+
+dev/if_dp83902a.c
+
+Ethernet device driver for NS DP83902a ethernet controller
+
+==========================================================================
+####ECOSGPLCOPYRIGHTBEGIN####
+-------------------------------------------
+This file is part of eCos, the Embedded Configurable Operating System.
+Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+
+eCos is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free
+Software Foundation; either version 2 or (at your option) any later version.
+
+eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or
+FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+for more details.
+
+You should have received a copy of the GNU General Public License along
+with eCos; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+
+As a special exception, if other files instantiate templates or use macros
+or inline functions from this file, or you compile this file and link it
+with other works to produce a work based on this file, this file does not
+by itself cause the resulting work to be covered by the GNU General Public
+License. However the source code for this file must still be made available
+in accordance with section (3) of the GNU General Public License.
+
+This exception does not invalidate any other reasons why a work based on
+this file might be covered by the GNU General Public License.
+
+Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+at http://sources.redhat.com/ecos/ecos-license/
+-------------------------------------------
+####ECOSGPLCOPYRIGHTEND####
+####BSDCOPYRIGHTBEGIN####
+
+-------------------------------------------
+
+Portions of this software may have been derived from OpenBSD or other sources,
+and are covered by the appropriate copyright disclaimers included herein.
+
+-------------------------------------------
+
+####BSDCOPYRIGHTEND####
+==========================================================================
+#####DESCRIPTIONBEGIN####
+
+Author(s):    gthomas
+Contributors: gthomas, jskov, rsandifo
+Date:	      2001-06-13
+Purpose:
+Description:
+
+FIXME:	      Will fail if pinged with large packets (1520 bytes)
+Add promisc config
+Add SNMP
+
+####DESCRIPTIONEND####
+
+
+==========================================================================
+
+*/
+
+#include <common.h>
+#include <command.h>
+#include <net.h>
+#include <malloc.h>
+
+#ifdef CONFIG_DRIVER_NE2000
+
+/* wor around udelay resetting OCR */
+static void my_udelay(long us) {
+	long tmo;
+
+	tmo = get_timer (0) + us * CFG_HZ / 1000000; /* will this be much greater than 0 ? */
+	while (get_timer (0) < tmo);
+}
+
+#define mdelay(n)       my_udelay((n)*1000)
+
+/* forward definition of function used for the uboot interface */
+void uboot_push_packet_len(int len);
+void uboot_push_tx_done(int key, int val);
+
+/* timeout for tx/rx in s */
+#define TOUT 5
+
+#define ETHER_ADDR_LEN 6
+
+/*
+  ------------------------------------------------------------------------
+  Debugging details
+
+  Set to perms of:
+  0 disables all debug output
+  1 for process debug output
+  2 for added data IO output: get_reg, put_reg
+  4 for packet allocation/free output
+  8 for only startup status, so we can tell we're installed OK
+*/
+/*#define DEBUG 0xf*/
+#define DEBUG 0
+
+#if DEBUG & 1
+#define DEBUG_FUNCTION() do { printf("%s\n", __FUNCTION__); } while (0)
+#define DEBUG_LINE() do { printf("%d\n", __LINE__); } while (0)
+#else
+#define DEBUG_FUNCTION() do {} while(0)
+#define DEBUG_LINE() do {} while(0)
+#endif
+
+#include "ne2000.h"
+
+#if DEBUG & 1
+#define PRINTK(args...) printf(args)
+#else
+#define PRINTK(args...)
+#endif
+
+static dp83902a_priv_data_t nic; /* just one instance of the card supported */
+
+static bool
+dp83902a_init(void)
+{
+	dp83902a_priv_data_t *dp = &nic;
+	cyg_uint8* base;
+	int i;
+
+	DEBUG_FUNCTION();
+
+	base = dp->base;
+	if (!base) return false;  /* No device found */
+
+	DEBUG_LINE();
+
+	/* Prepare ESA */
+	DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE1);  /* Select page 1 */
+	/* Use the address from the serial EEPROM */
+	for (i = 0; i < 6; i++)
+		DP_IN(base, DP_P1_PAR0+i, dp->esa[i]);
+	DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE0);  /* Select page 0 */
+
+	printf("NE2000 - %s ESA: %02x:%02x:%02x:%02x:%02x:%02x\n",
+	       "eeprom",
+	       dp->esa[0],
+	       dp->esa[1],
+	       dp->esa[2],
+	       dp->esa[3],
+	       dp->esa[4],
+	       dp->esa[5] );
+
+	return true;
+}
+
+static void
+dp83902a_stop(void)
+{
+	dp83902a_priv_data_t *dp = &nic;
+	cyg_uint8 *base = dp->base;
+
+	DEBUG_FUNCTION();
+
+	DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_STOP);  /* Brutal */
+	DP_OUT(base, DP_ISR, 0xFF);		/* Clear any pending interrupts */
+	DP_OUT(base, DP_IMR, 0x00);		/* Disable all interrupts */
+
+	dp->running = false;
+}
+
+/*
+  This function is called to "start up" the interface.  It may be called
+  multiple times, even when the hardware is already running.  It will be
+  called whenever something "hardware oriented" changes and should leave
+  the hardware ready to send/receive packets.
+*/
+static void
+dp83902a_start(unsigned char * enaddr)
+{
+	dp83902a_priv_data_t *dp = &nic;
+	cyg_uint8 *base = dp->base;
+	int i;
+
+	DEBUG_FUNCTION();
+
+	DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_STOP); /* Brutal */
+	DP_OUT(base, DP_DCR, DP_DCR_INIT);
+	DP_OUT(base, DP_RBCH, 0);		/* Remote byte count */
+	DP_OUT(base, DP_RBCL, 0);
+	DP_OUT(base, DP_RCR, DP_RCR_MON);	/* Accept no packets */
+	DP_OUT(base, DP_TCR, DP_TCR_LOCAL);	/* Transmitter [virtually] off */
+	DP_OUT(base, DP_TPSR, dp->tx_buf1);	/* Transmitter start page */
+	dp->tx1 = dp->tx2 = 0;
+	dp->tx_next = dp->tx_buf1;
+	dp->tx_started = false;
+	DP_OUT(base, DP_PSTART, dp->rx_buf_start); /* Receive ring start page */
+	DP_OUT(base, DP_BNDRY, dp->rx_buf_end-1); /* Receive ring boundary */
+	DP_OUT(base, DP_PSTOP, dp->rx_buf_end);	/* Receive ring end page */
+	dp->rx_next = dp->rx_buf_start-1;
+	DP_OUT(base, DP_ISR, 0xFF);		/* Clear any pending interrupts */
+	DP_OUT(base, DP_IMR, DP_IMR_All);	/* Enable all interrupts */
+	DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE1 | DP_CR_STOP);  /* Select page 1 */
+	DP_OUT(base, DP_P1_CURP, dp->rx_buf_start);   /* Current page - next free page for Rx */
+	for (i = 0;  i < ETHER_ADDR_LEN;  i++) {
+		DP_OUT(base, DP_P1_PAR0+i, enaddr[i]);
+	}
+	/* Enable and start device */
+	DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START);
+	DP_OUT(base, DP_TCR, DP_TCR_NORMAL); /* Normal transmit operations */
+	DP_OUT(base, DP_RCR, DP_RCR_AB);  /* Accept broadcast, no errors, no multicast */
+	dp->running = true;
+}
+
+/*
+  This routine is called to start the transmitter.  It is split out from the
+  data handling routine so it may be called either when data becomes first
+  available or when an Tx interrupt occurs
+*/
+
+static void
+dp83902a_start_xmit(int start_page, int len)
+{
+	dp83902a_priv_data_t *dp = (dp83902a_priv_data_t *) &nic;
+	cyg_uint8 *base = dp->base;
+
+	DEBUG_FUNCTION();
+
+#if DEBUG & 1
+	printf("Tx pkt %d len %d\n", start_page, len);
+	if (dp->tx_started)
+		printf("TX already started?!?\n");
+#endif
+
+	DP_OUT(base, DP_ISR, (DP_ISR_TxP | DP_ISR_TxE));
+	DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START);
+	DP_OUT(base, DP_TBCL, len & 0xFF);
+	DP_OUT(base, DP_TBCH, len >> 8);
+	DP_OUT(base, DP_TPSR, start_page);
+	DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_TXPKT | DP_CR_START);
+
+	dp->tx_started = true;
+}
+
+/*
+  This routine is called to send data to the hardware.  It is known a-priori
+  that there is free buffer space (dp->tx_next).
+*/
+static void
+dp83902a_send(unsigned char *data, int total_len, unsigned long key)
+{
+	struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
+	cyg_uint8 *base = dp->base;
+	int len, start_page, pkt_len, i, isr;
+#if DEBUG & 4
+	int dx;
+#endif
+
+	DEBUG_FUNCTION();
+
+	len = pkt_len = total_len;
+	if (pkt_len < IEEE_8023_MIN_FRAME) pkt_len = IEEE_8023_MIN_FRAME;
+
+	start_page = dp->tx_next;
+	if (dp->tx_next == dp->tx_buf1) {
+		dp->tx1 = start_page;
+		dp->tx1_len = pkt_len;
+		dp->tx1_key = key;
+		dp->tx_next = dp->tx_buf2;
+	} else {
+		dp->tx2 = start_page;
+		dp->tx2_len = pkt_len;
+		dp->tx2_key = key;
+		dp->tx_next = dp->tx_buf1;
+	}
+
+#if DEBUG & 5
+	printf("TX prep page %d len %d\n", start_page, pkt_len);
+#endif
+
+	DP_OUT(base, DP_ISR, DP_ISR_RDC);  /* Clear end of DMA */
+	{
+		/* Dummy read. The manual sez something slightly different, */
+		/* but the code is extended a bit to do what Hitachi's monitor */
+		/* does (i.e., also read data). */
+
+		cyg_uint16 tmp;
+		int len = 1;
+
+		DP_OUT(base, DP_RSAL, 0x100-len);
+		DP_OUT(base, DP_RSAH, (start_page-1) & 0xff);
+		DP_OUT(base, DP_RBCL, len);
+		DP_OUT(base, DP_RBCH, 0);
+		DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_RDMA | DP_CR_START);
+		DP_IN_DATA(dp->data, tmp);
+	}
+
+#ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_TX_DMA
+	/* Stall for a bit before continuing to work around random data */
+	/* corruption problems on some platforms. */
+	CYGACC_CALL_IF_DELAY_US(1);
+#endif
+
+	/* Send data to device buffer(s) */
+	DP_OUT(base, DP_RSAL, 0);
+	DP_OUT(base, DP_RSAH, start_page);
+	DP_OUT(base, DP_RBCL, pkt_len & 0xFF);
+	DP_OUT(base, DP_RBCH, pkt_len >> 8);
+	DP_OUT(base, DP_CR, DP_CR_WDMA | DP_CR_START);
+
+	/* Put data into buffer */
+#if DEBUG & 4
+	printf(" sg buf %08lx len %08x\n ", (unsigned long) data, len);
+	dx = 0;
+#endif
+	while (len > 0) {
+#if DEBUG & 4
+		printf(" %02x", *data);
+		if (0 == (++dx % 16)) printf("\n ");
+#endif
+		DP_OUT_DATA(dp->data, *data++);
+		len--;
+	}
+#if DEBUG & 4
+	printf("\n");
+#endif
+	if (total_len < pkt_len) {
+#if DEBUG & 4
+		printf("  + %d bytes of padding\n", pkt_len - total_len);
+#endif
+		/* Padding to 802.3 length was required */
+		for (i = total_len;  i < pkt_len;) {
+			i++;
+			DP_OUT_DATA(dp->data, 0);
+		}
+	}
+
+#ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_TX_DMA
+	/* After last data write, delay for a bit before accessing the */
+	/* device again, or we may get random data corruption in the last */
+	/* datum (on some platforms). */
+	CYGACC_CALL_IF_DELAY_US(1);
+#endif
+
+	/* Wait for DMA to complete */
+	do {
+		DP_IN(base, DP_ISR, isr);
+	} while ((isr & DP_ISR_RDC) == 0);
+	/* Then disable DMA */
+	DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START);
+
+	/* Start transmit if not already going */
+	if (!dp->tx_started) {
+		if (start_page == dp->tx1) {
+			dp->tx_int = 1;  /* Expecting interrupt from BUF1 */
+		} else {
+			dp->tx_int = 2;  /* Expecting interrupt from BUF2 */
+		}
+		dp83902a_start_xmit(start_page, pkt_len);
+	}
+}
+
+/*
+  This function is called when a packet has been received.  It's job is
+  to prepare to unload the packet from the hardware.  Once the length of
+  the packet is known, the upper layer of the driver can be told.  When
+  the upper layer is ready to unload the packet, the internal function
+  'dp83902a_recv' will be called to actually fetch it from the hardware.
+*/
+static void
+dp83902a_RxEvent(void)
+{
+	struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
+	cyg_uint8 *base = dp->base;
+	unsigned char rsr;
+	unsigned char rcv_hdr[4];
+	int i, len, pkt, cur;
+
+	DEBUG_FUNCTION();
+
+	DP_IN(base, DP_RSR, rsr);
+	while (true) {
+		/* Read incoming packet header */
+		DP_OUT(base, DP_CR, DP_CR_PAGE1 | DP_CR_NODMA | DP_CR_START);
+		DP_IN(base, DP_P1_CURP, cur);
+		DP_OUT(base, DP_P1_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START);
+		DP_IN(base, DP_BNDRY, pkt);
+
+		pkt += 1;
+		if (pkt == dp->rx_buf_end)
+			pkt = dp->rx_buf_start;
+
+		if (pkt == cur) {
+			break;
+		}
+		DP_OUT(base, DP_RBCL, sizeof(rcv_hdr));
+		DP_OUT(base, DP_RBCH, 0);
+		DP_OUT(base, DP_RSAL, 0);
+		DP_OUT(base, DP_RSAH, pkt);
+		if (dp->rx_next == pkt) {
+			if (cur == dp->rx_buf_start)
+				DP_OUT(base, DP_BNDRY, dp->rx_buf_end-1);
+			else
+				DP_OUT(base, DP_BNDRY, cur-1); /* Update pointer */
+			return;
+		}
+		dp->rx_next = pkt;
+		DP_OUT(base, DP_ISR, DP_ISR_RDC); /* Clear end of DMA */
+		DP_OUT(base, DP_CR, DP_CR_RDMA | DP_CR_START);
+#ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_RX_DMA
+		CYGACC_CALL_IF_DELAY_US(10);
+#endif
+
+		for (i = 0;  i < sizeof(rcv_hdr);) {
+			DP_IN_DATA(dp->data, rcv_hdr[i++]);
+		}
+
+#if DEBUG & 5
+		printf("rx hdr %02x %02x %02x %02x\n",
+		       rcv_hdr[0], rcv_hdr[1], rcv_hdr[2], rcv_hdr[3]);
+#endif
+		len = ((rcv_hdr[3] << 8) | rcv_hdr[2]) - sizeof(rcv_hdr);
+		uboot_push_packet_len(len);
+		if (rcv_hdr[1] == dp->rx_buf_start)
+			DP_OUT(base, DP_BNDRY, dp->rx_buf_end-1);
+		else
+			DP_OUT(base, DP_BNDRY, rcv_hdr[1]-1); /* Update pointer */
+	}
+}
+
+/*
+  This function is called as a result of the "eth_drv_recv()" call above.
+  It's job is to actually fetch data for a packet from the hardware once
+  memory buffers have been allocated for the packet.  Note that the buffers
+  may come in pieces, using a scatter-gather list.  This allows for more
+  efficient processing in the upper layers of the stack.
+*/
+static void
+dp83902a_recv(unsigned char *data, int len)
+{
+	struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
+	cyg_uint8 *base = dp->base;
+	int i, mlen;
+	cyg_uint8 saved_char = 0;
+	bool saved;
+#if DEBUG & 4
+	int dx;
+#endif
+
+	DEBUG_FUNCTION();
+
+#if DEBUG & 5
+	printf("Rx packet %d length %d\n", dp->rx_next, len);
+#endif
+
+	/* Read incoming packet data */
+	DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START);
+	DP_OUT(base, DP_RBCL, len & 0xFF);
+	DP_OUT(base, DP_RBCH, len >> 8);
+	DP_OUT(base, DP_RSAL, 4);		/* Past header */
+	DP_OUT(base, DP_RSAH, dp->rx_next);
+	DP_OUT(base, DP_ISR, DP_ISR_RDC); /* Clear end of DMA */
+	DP_OUT(base, DP_CR, DP_CR_RDMA | DP_CR_START);
+#ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_RX_DMA
+	CYGACC_CALL_IF_DELAY_US(10);
+#endif
+
+	saved = false;
+	for (i = 0;  i < 1;  i++) {
+		if (data) {
+			mlen = len;
+#if DEBUG & 4
+			printf(" sg buf %08lx len %08x \n", (unsigned long) data, mlen);
+			dx = 0;
+#endif
+			while (0 < mlen) {
+				/* Saved byte from previous loop? */
+				if (saved) {
+					*data++ = saved_char;
+					mlen--;
+					saved = false;
+					continue;
+				}
+
+				{
+					cyg_uint8 tmp;
+					DP_IN_DATA(dp->data, tmp);
+#if DEBUG & 4
+					printf(" %02x", tmp);
+					if (0 == (++dx % 16)) printf("\n ");
+#endif
+					*data++ = tmp;;
+					mlen--;
+				}
+			}
+#if DEBUG & 4
+			printf("\n");
+#endif
+		}
+	}
+}
+
+static void
+dp83902a_TxEvent(void)
+{
+	struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
+	cyg_uint8 *base = dp->base;
+	unsigned char tsr;
+	unsigned long key;
+
+	DEBUG_FUNCTION();
+
+	DP_IN(base, DP_TSR, tsr);
+	if (dp->tx_int == 1) {
+		key = dp->tx1_key;
+		dp->tx1 = 0;
+	} else {
+		key = dp->tx2_key;
+		dp->tx2 = 0;
+	}
+	/* Start next packet if one is ready */
+	dp->tx_started = false;
+	if (dp->tx1) {
+		dp83902a_start_xmit(dp->tx1, dp->tx1_len);
+		dp->tx_int = 1;
+	} else if (dp->tx2) {
+		dp83902a_start_xmit(dp->tx2, dp->tx2_len);
+		dp->tx_int = 2;
+	} else {
+		dp->tx_int = 0;
+	}
+	/* Tell higher level we sent this packet */
+	uboot_push_tx_done(key, 0);
+}
+
+/* Read the tally counters to clear them.  Called in response to a CNT */
+/* interrupt. */
+static void
+dp83902a_ClearCounters(void)
+{
+	struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
+	cyg_uint8 *base = dp->base;
+	cyg_uint8 cnt1, cnt2, cnt3;
+
+	DP_IN(base, DP_FER, cnt1);
+	DP_IN(base, DP_CER, cnt2);
+	DP_IN(base, DP_MISSED, cnt3);
+	DP_OUT(base, DP_ISR, DP_ISR_CNT);
+}
+
+/* Deal with an overflow condition.  This code follows the procedure set */
+/* out in section 7.0 of the datasheet. */
+static void
+dp83902a_Overflow(void)
+{
+	struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *)&nic;
+	cyg_uint8 *base = dp->base;
+	cyg_uint8 isr;
+
+	/* Issue a stop command and wait 1.6ms for it to complete. */
+	DP_OUT(base, DP_CR, DP_CR_STOP | DP_CR_NODMA);
+	CYGACC_CALL_IF_DELAY_US(1600);
+
+	/* Clear the remote byte counter registers. */
+	DP_OUT(base, DP_RBCL, 0);
+	DP_OUT(base, DP_RBCH, 0);
+
+	/* Enter loopback mode while we clear the buffer. */
+	DP_OUT(base, DP_TCR, DP_TCR_LOCAL);
+	DP_OUT(base, DP_CR, DP_CR_START | DP_CR_NODMA);
+
+	/* Read in as many packets as we can and acknowledge any and receive */
+	/* interrupts.  Since the buffer has overflowed, a receive event of */
+	/* some kind will have occured. */
+	dp83902a_RxEvent();
+	DP_OUT(base, DP_ISR, DP_ISR_RxP|DP_ISR_RxE);
+
+	/* Clear the overflow condition and leave loopback mode. */
+	DP_OUT(base, DP_ISR, DP_ISR_OFLW);
+	DP_OUT(base, DP_TCR, DP_TCR_NORMAL);
+
+	/* If a transmit command was issued, but no transmit event has occured, */
+	/* restart it here. */
+	DP_IN(base, DP_ISR, isr);
+	if (dp->tx_started && !(isr & (DP_ISR_TxP|DP_ISR_TxE))) {
+		DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_TXPKT | DP_CR_START);
+	}
+}
+
+static void
+dp83902a_poll(void)
+{
+	struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
+	cyg_uint8 *base = dp->base;
+	unsigned char isr;
+
+	DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE0 | DP_CR_START);
+	DP_IN(base, DP_ISR, isr);
+	while (0 != isr) {
+		/* The CNT interrupt triggers when the MSB of one of the error */
+		/* counters is set.  We don't much care about these counters, but */
+		/* we should read their values to reset them. */
+		if (isr & DP_ISR_CNT) {
+			dp83902a_ClearCounters();
+		}
+		/* Check for overflow.  It's a special case, since there's a */
+		/* particular procedure that must be followed to get back into */
+		/* a running state.a */
+		if (isr & DP_ISR_OFLW) {
+			dp83902a_Overflow();
+		} else {
+			/* Other kinds of interrupts can be acknowledged simply by */
+			/* clearing the relevant bits of the ISR.  Do that now, then */
+			/* handle the interrupts we care about. */
+			DP_OUT(base, DP_ISR, isr);      /* Clear set bits */
+			if (!dp->running) break;	/* Is this necessary? */
+			/* Check for tx_started on TX event since these may happen */
+			/* spuriously it seems. */
+			if (isr & (DP_ISR_TxP|DP_ISR_TxE) && dp->tx_started) {
+				dp83902a_TxEvent();
+			}
+			if (isr & (DP_ISR_RxP|DP_ISR_RxE)) {
+				dp83902a_RxEvent();
+			}
+		}
+		DP_IN(base, DP_ISR, isr);
+	}
+}
+
+/* find prom (taken from pc_net_cs.c from Linux) */
+
+#include "8390.h"
+
+typedef struct hw_info_t {
+	u_int	offset;
+	u_char	a0, a1, a2;
+	u_int	flags;
+} hw_info_t;
+
+#define DELAY_OUTPUT	0x01
+#define HAS_MISC_REG	0x02
+#define USE_BIG_BUF	0x04
+#define HAS_IBM_MISC	0x08
+#define IS_DL10019	0x10
+#define IS_DL10022	0x20
+#define HAS_MII		0x40
+#define USE_SHMEM	0x80	/* autodetected */
+
+#define AM79C9XX_HOME_PHY	0x00006B90  /* HomePNA PHY */
+#define AM79C9XX_ETH_PHY	0x00006B70  /* 10baseT PHY */
+#define MII_PHYID_REV_MASK	0xfffffff0
+#define MII_PHYID_REG1		0x02
+#define MII_PHYID_REG2		0x03
+
+static hw_info_t hw_info[] = {
+	{ /* Accton EN2212 */ 0x0ff0, 0x00, 0x00, 0xe8, DELAY_OUTPUT },
+	{ /* Allied Telesis LA-PCM */ 0x0ff0, 0x00, 0x00, 0xf4, 0 },
+	{ /* APEX MultiCard */ 0x03f4, 0x00, 0x20, 0xe5, 0 },
+	{ /* ASANTE FriendlyNet */ 0x4910, 0x00, 0x00, 0x94,
+	  DELAY_OUTPUT | HAS_IBM_MISC },
+	{ /* Danpex EN-6200P2 */ 0x0110, 0x00, 0x40, 0xc7, 0 },
+	{ /* DataTrek NetCard */ 0x0ff0, 0x00, 0x20, 0xe8, 0 },
+	{ /* Dayna CommuniCard E */ 0x0110, 0x00, 0x80, 0x19, 0 },
+	{ /* D-Link DE-650 */ 0x0040, 0x00, 0x80, 0xc8, 0 },
+	{ /* EP-210 Ethernet */ 0x0110, 0x00, 0x40, 0x33, 0 },
+	{ /* EP4000 Ethernet */ 0x01c0, 0x00, 0x00, 0xb4, 0 },
+	{ /* Epson EEN10B */ 0x0ff0, 0x00, 0x00, 0x48,
+	  HAS_MISC_REG | HAS_IBM_MISC },
+	{ /* ELECOM Laneed LD-CDWA */ 0xb8, 0x08, 0x00, 0x42, 0 },
+	{ /* Hypertec Ethernet */ 0x01c0, 0x00, 0x40, 0x4c, 0 },
+	{ /* IBM CCAE */ 0x0ff0, 0x08, 0x00, 0x5a,
+	  HAS_MISC_REG | HAS_IBM_MISC },
+	{ /* IBM CCAE */ 0x0ff0, 0x00, 0x04, 0xac,
+	  HAS_MISC_REG | HAS_IBM_MISC },
+	{ /* IBM CCAE */ 0x0ff0, 0x00, 0x06, 0x29,
+	  HAS_MISC_REG | HAS_IBM_MISC },
+	{ /* IBM FME */ 0x0374, 0x08, 0x00, 0x5a,
+	  HAS_MISC_REG | HAS_IBM_MISC },
+	{ /* IBM FME */ 0x0374, 0x00, 0x04, 0xac,
+	  HAS_MISC_REG | HAS_IBM_MISC },
+	{ /* Kansai KLA-PCM/T */ 0x0ff0, 0x00, 0x60, 0x87,
+	  HAS_MISC_REG | HAS_IBM_MISC },
+	{ /* NSC DP83903 */ 0x0374, 0x08, 0x00, 0x17,
+	  HAS_MISC_REG | HAS_IBM_MISC },
+	{ /* NSC DP83903 */ 0x0374, 0x00, 0xc0, 0xa8,
+	  HAS_MISC_REG | HAS_IBM_MISC },
+	{ /* NSC DP83903 */ 0x0374, 0x00, 0xa0, 0xb0,
+	  HAS_MISC_REG | HAS_IBM_MISC },
+	{ /* NSC DP83903 */ 0x0198, 0x00, 0x20, 0xe0,
+	  HAS_MISC_REG | HAS_IBM_MISC },
+	{ /* I-O DATA PCLA/T */ 0x0ff0, 0x00, 0xa0, 0xb0, 0 },
+	{ /* Katron PE-520 */ 0x0110, 0x00, 0x40, 0xf6, 0 },
+	{ /* Kingston KNE-PCM/x */ 0x0ff0, 0x00, 0xc0, 0xf0,
+	  HAS_MISC_REG | HAS_IBM_MISC },
+	{ /* Kingston KNE-PCM/x */ 0x0ff0, 0xe2, 0x0c, 0x0f,
+	  HAS_MISC_REG | HAS_IBM_MISC },
+	{ /* Kingston KNE-PC2 */ 0x0180, 0x00, 0xc0, 0xf0, 0 },
+	{ /* Maxtech PCN2000 */ 0x5000, 0x00, 0x00, 0xe8, 0 },
+	{ /* NDC Instant-Link */ 0x003a, 0x00, 0x80, 0xc6, 0 },
+	{ /* NE2000 Compatible */ 0x0ff0, 0x00, 0xa0, 0x0c, 0 },
+	{ /* Network General Sniffer */ 0x0ff0, 0x00, 0x00, 0x65,
+	  HAS_MISC_REG | HAS_IBM_MISC },
+	{ /* Panasonic VEL211 */ 0x0ff0, 0x00, 0x80, 0x45,
+	  HAS_MISC_REG | HAS_IBM_MISC },
+	{ /* PreMax PE-200 */ 0x07f0, 0x00, 0x20, 0xe0, 0 },
+	{ /* RPTI EP400 */ 0x0110, 0x00, 0x40, 0x95, 0 },
+	{ /* SCM Ethernet */ 0x0ff0, 0x00, 0x20, 0xcb, 0 },
+	{ /* Socket EA */ 0x4000, 0x00, 0xc0, 0x1b,
+	  DELAY_OUTPUT | HAS_MISC_REG | USE_BIG_BUF },
+	{ /* Socket LP-E CF+ */ 0x01c0, 0x00, 0xc0, 0x1b, 0 },
+	{ /* SuperSocket RE450T */ 0x0110, 0x00, 0xe0, 0x98, 0 },
+	{ /* Volktek NPL-402CT */ 0x0060, 0x00, 0x40, 0x05, 0 },
+	{ /* NEC PC-9801N-J12 */ 0x0ff0, 0x00, 0x00, 0x4c, 0 },
+	{ /* PCMCIA Technology OEM */ 0x01c8, 0x00, 0xa0, 0x0c, 0 }
+};
+
+#define NR_INFO		(sizeof(hw_info)/sizeof(hw_info_t))
+
+static hw_info_t default_info = { 0, 0, 0, 0, 0 };
+
+unsigned char dev_addr[6];
+
+#define PCNET_CMD	0x00
+#define PCNET_DATAPORT	0x10	/* NatSemi-defined port window offset. */
+#define PCNET_RESET	0x1f	/* Issue a read to reset, a write to clear. */
+#define PCNET_MISC	0x18	/* For IBM CCAE and Socket EA cards */
+
+unsigned long nic_base;
+
+static void pcnet_reset_8390(void)
+{
+	int i, r;
+
+	PRINTK("nic base is %lx\n", nic_base);
+
+#if 1
+	n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD);
+	PRINTK("cmd (at %lx) is %x\n", nic_base+ E8390_CMD, n2k_inb(E8390_CMD));
+	n2k_outb(E8390_NODMA+E8390_PAGE1+E8390_STOP, E8390_CMD);
+	PRINTK("cmd (at %lx) is %x\n", nic_base+ E8390_CMD, n2k_inb(E8390_CMD));
+	n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD);
+	PRINTK("cmd (at %lx) is %x\n", nic_base+ E8390_CMD, n2k_inb(E8390_CMD));
+#endif
+	n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD);
+
+	n2k_outb(n2k_inb(nic_base + PCNET_RESET), PCNET_RESET);
+
+	for (i = 0; i < 100; i++) {
+		if ((r = (n2k_inb(EN0_ISR) & ENISR_RESET)) != 0)
+			break;
+		PRINTK("got %x in reset\n", r);
+		my_udelay(100);
+	}
+	n2k_outb(ENISR_RESET, EN0_ISR); /* Ack intr. */
+
+	if (i == 100)
+		printf("pcnet_reset_8390() did not complete.\n");
+} /* pcnet_reset_8390 */
+
+static hw_info_t * get_prom(void ) {
+	unsigned char prom[32];
+	int i, j;
+	struct {
+		u_char value, offset;
+	} program_seq[] = {
+		{E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD}, /* Select page 0*/
+		{0x48,	EN0_DCFG},	/* Set byte-wide (0x48) access. */
+		{0x00,	EN0_RCNTLO},	/* Clear the count regs. */
+		{0x00,	EN0_RCNTHI},
+		{0x00,	EN0_IMR},	/* Mask completion irq. */
+		{0xFF,	EN0_ISR},
+		{E8390_RXOFF, EN0_RXCR},	/* 0x20  Set to monitor */
+		{E8390_TXOFF, EN0_TXCR},	/* 0x02  and loopback mode. */
+		{32,	EN0_RCNTLO},
+		{0x00,	EN0_RCNTHI},
+		{0x00,	EN0_RSARLO},	/* DMA starting at 0x0000. */
+		{0x00,	EN0_RSARHI},
+		{E8390_RREAD+E8390_START, E8390_CMD},
+	};
+
+	PRINTK("trying to get MAC via prom reading\n");
+
+	pcnet_reset_8390();
+
+	mdelay(10);
+
+	for (i = 0; i < sizeof(program_seq)/sizeof(program_seq[0]); i++)
+		n2k_outb(program_seq[i].value, program_seq[i].offset);
+
+	PRINTK("PROM:");
+	for (i = 0; i < 32; i++) {
+		prom[i] = n2k_inb(PCNET_DATAPORT);
+		PRINTK(" %02x", prom[i]);
+	}
+	PRINTK("\n");
+	for (i = 0; i < NR_INFO; i++) {
+		if ((prom[0] == hw_info[i].a0) &&
+		    (prom[2] == hw_info[i].a1) &&
+		    (prom[4] == hw_info[i].a2)) {
+			PRINTK("matched board %d\n", i);
+			break;
+		}
+	}
+	if ((i < NR_INFO) || ((prom[28] == 0x57) && (prom[30] == 0x57))) {
+		for (j = 0; j < 6; j++)
+			dev_addr[j] = prom[j<<1];
+		PRINTK("on exit i is %d/%ld\n", i, NR_INFO);
+		PRINTK("MAC address is %02x:%02x:%02x:%02x:%02x:%02x\n",
+		       dev_addr[0],dev_addr[1],dev_addr[2],dev_addr[3],dev_addr[4],dev_addr[5]);
+		return (i < NR_INFO) ? hw_info+i : &default_info;
+	}
+	return NULL;
+}
+
+/* U-boot specific routines */
+
+#define NB 5
+
+static unsigned char *pbuf = NULL;
+static int plen[NB];
+static int nrx = 0;
+
+static int pkey = -1;
+
+void uboot_push_packet_len(int len) {
+	PRINTK("pushed len = %d, nrx = %d\n", len, nrx);
+	if (len>=2000) {
+		printf("NE2000: packet too big\n");
+		return;
+	}
+	if (nrx >= NB) {
+		printf("losing packets in rx\n");
+		return;
+	}
+	plen[nrx] = len;
+	dp83902a_recv(&pbuf[nrx*2000], len);
+	nrx++;
+}
+
+void uboot_push_tx_done(int key, int val) {
+	PRINTK("pushed key = %d\n", key);
+	pkey = key;
+}
+
+int eth_init(bd_t *bd) {
+	static hw_info_t * r;
+	char ethaddr[20];
+
+	PRINTK("### eth_init\n");
+
+	if (!pbuf) {
+		pbuf = malloc(NB*2000);
+		if (!pbuf) {
+			printf("Cannot allocate rx buffers\n");
+			return -1;
+		}
+	}
+
+#ifdef CONFIG_DRIVER_NE2000_CCR
+	{
+		volatile unsigned char *p =  (volatile unsigned char *) CONFIG_DRIVER_NE2000_CCR;
+
+		PRINTK("CCR before is %x\n", *p);
+		*p = CONFIG_DRIVER_NE2000_VAL;
+		PRINTK("CCR after is %x\n", *p);
+	}
+#endif
+
+	nic_base = CONFIG_DRIVER_NE2000_BASE;
+	nic.base = (cyg_uint8 *) CONFIG_DRIVER_NE2000_BASE;
+
+	r = get_prom();
+	if (!r)
+		return -1;
+
+	sprintf (ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X",
+		 dev_addr[0], dev_addr[1],
+		 dev_addr[2], dev_addr[3],
+		 dev_addr[4], dev_addr[5]) ;
+	PRINTK("Set environment from HW MAC addr = \"%s\"\n", ethaddr);
+	setenv ("ethaddr", ethaddr);
+
+
+#define DP_DATA		0x10
+	nic.data = nic.base + DP_DATA;
+	nic.tx_buf1 = 0x40;
+	nic.tx_buf2 = 0x48;
+	nic.rx_buf_start = 0x50;
+	nic.rx_buf_end = 0x80;
+
+	if (dp83902a_init() == false)
+		return -1;
+	dp83902a_start(dev_addr);
+	return 0;
+}
+
+void eth_halt() {
+
+	PRINTK("### eth_halt\n");
+
+	dp83902a_stop();
+}
+
+int eth_rx() {
+	int j, tmo;
+
+	PRINTK("### eth_rx\n");
+
+	tmo = get_timer (0) + TOUT * CFG_HZ;
+	while(1) {
+		dp83902a_poll();
+		if (nrx > 0) {
+			for(j=0; j<nrx; j++) {
+				NetReceive(&pbuf[j*2000], plen[j]);
+			}
+			nrx = 0;
+			return 1;
+		}
+		if (get_timer (0) >= tmo) {
+			printf("timeout during rx\n");
+			return 0;
+		}
+	}
+	return 0;
+}
+
+int eth_send(volatile void *packet, int length) {
+	int tmo;
+
+	PRINTK("### eth_send\n");
+
+	pkey = -1;
+
+	dp83902a_send((unsigned char *) packet, length, 666);
+	tmo = get_timer (0) + TOUT * CFG_HZ;
+	while(1) {
+		dp83902a_poll();
+		if (pkey != -1) {
+			PRINTK("Packet sucesfully sent\n");
+			return 0;
+		}
+		if (get_timer (0) >= tmo) {
+			printf("transmission error (timoeut)\n");
+			return 0;
+		}
+
+	}
+	return 0;
+}
+
+#endif
diff --git a/drivers/ne2000.h b/drivers/ne2000.h
new file mode 100644
index 0000000..2955533
--- /dev/null
+++ b/drivers/ne2000.h
@@ -0,0 +1,279 @@
+/*
+Ported to U-Boot  by Christian Pellegrin <chri@ascensit.com>
+
+Based on sources from the Linux kernel (pcnet_cs.c, 8390.h) and
+eCOS(if_dp83902a.c, if_dp83902a.h). Both of these 2 wonderful world
+are GPL, so this is, of course, GPL.
+
+
+==========================================================================
+
+      dev/dp83902a.h
+
+      National Semiconductor DP83902a ethernet chip
+
+==========================================================================
+####ECOSGPLCOPYRIGHTBEGIN####
+ -------------------------------------------
+ This file is part of eCos, the Embedded Configurable Operating System.
+ Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+
+ eCos is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License as published by the Free
+ Software Foundation; either version 2 or (at your option) any later version.
+
+ eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with eCos; if not, write to the Free Software Foundation, Inc.,
+ 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+
+ As a special exception, if other files instantiate templates or use macros
+ or inline functions from this file, or you compile this file and link it
+ with other works to produce a work based on this file, this file does not
+ by itself cause the resulting work to be covered by the GNU General Public
+ License. However the source code for this file must still be made available
+ in accordance with section (3) of the GNU General Public License.
+
+ This exception does not invalidate any other reasons why a work based on
+ this file might be covered by the GNU General Public License.
+
+ Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+ at http://sources.redhat.com/ecos/ecos-license/ */
+ -------------------------------------------
+####ECOSGPLCOPYRIGHTEND####
+####BSDCOPYRIGHTBEGIN####
+
+ -------------------------------------------
+
+ Portions of this software may have been derived from OpenBSD or other sources,
+ and are covered by the appropriate copyright disclaimers included herein.
+
+ -------------------------------------------
+
+####BSDCOPYRIGHTEND####
+==========================================================================
+#####DESCRIPTIONBEGIN####
+
+ Author(s):    gthomas
+ Contributors: gthomas, jskov
+ Date:         2001-06-13
+ Purpose:
+ Description:
+
+####DESCRIPTIONEND####
+
+==========================================================================
+
+*/
+
+/*
+ ------------------------------------------------------------------------
+ Macros for accessing DP registers
+ These can be overridden by the platform header
+*/
+
+#define DP_IN(_b_, _o_, _d_)  (_d_) = *( (volatile unsigned char *) ((_b_)+(_o_)))
+#define DP_OUT(_b_, _o_, _d_) *( (volatile unsigned char *) ((_b_)+(_o_))) = (_d_)
+
+#define DP_IN_DATA(_b_, _d_)  (_d_) = *( (volatile unsigned char *) ((_b_)))
+#define DP_OUT_DATA(_b_, _d_) *( (volatile unsigned char *) ((_b_))) = (_d_)
+
+
+/* here is all the data */
+
+#define cyg_uint8 unsigned char
+#define cyg_uint16 unsigned short
+#define bool int
+
+#define false 0
+#define true 1
+
+#define CYGHWR_NS_DP83902A_PLF_BROKEN_TX_DMA 1
+#define CYGACC_CALL_IF_DELAY_US(X) my_udelay(X)
+
+typedef struct dp83902a_priv_data {
+    cyg_uint8* base;
+    cyg_uint8* data;
+    cyg_uint8* reset;
+    int tx_next;           /* First free Tx page */
+    int tx_int;            /* Expecting interrupt from this buffer */
+    int rx_next;           /* First free Rx page */
+    int tx1, tx2;          /* Page numbers for Tx buffers */
+    unsigned long tx1_key, tx2_key;   /* Used to ack when packet sent */
+    int tx1_len, tx2_len;
+    bool tx_started, running, hardwired_esa;
+    cyg_uint8 esa[6];
+    void* plf_priv;
+
+    /* Buffer allocation */
+    int tx_buf1, tx_buf2;
+    int rx_buf_start, rx_buf_end;
+} dp83902a_priv_data_t;
+
+/*
+ ------------------------------------------------------------------------
+ Some forward declarations
+*/
+static void dp83902a_poll(void);
+
+/* ------------------------------------------------------------------------ */
+/* Register offsets */
+
+#define DP_CR          0x00
+#define DP_CLDA0       0x01
+#define DP_PSTART      0x01             /* write */
+#define DP_CLDA1       0x02
+#define DP_PSTOP       0x02             /* write */
+#define DP_BNDRY       0x03
+#define DP_TSR         0x04
+#define DP_TPSR        0x04             /* write */
+#define DP_NCR         0x05
+#define DP_TBCL        0x05             /* write */
+#define DP_FIFO        0x06
+#define DP_TBCH        0x06             /* write */
+#define DP_ISR         0x07
+#define DP_CRDA0       0x08
+#define DP_RSAL        0x08             /* write */
+#define DP_CRDA1       0x09
+#define DP_RSAH        0x09             /* write */
+#define DP_RBCL        0x0a             /* write */
+#define DP_RBCH        0x0b             /* write */
+#define DP_RSR         0x0c
+#define DP_RCR         0x0c             /* write */
+#define DP_FER         0x0d
+#define DP_TCR         0x0d             /* write */
+#define DP_CER         0x0e
+#define DP_DCR         0x0e             /* write */
+#define DP_MISSED      0x0f
+#define DP_IMR         0x0f             /* write */
+#define DP_DATAPORT    0x10             /* "eprom" data port */
+
+#define DP_P1_CR       0x00
+#define DP_P1_PAR0     0x01
+#define DP_P1_PAR1     0x02
+#define DP_P1_PAR2     0x03
+#define DP_P1_PAR3     0x04
+#define DP_P1_PAR4     0x05
+#define DP_P1_PAR5     0x06
+#define DP_P1_CURP     0x07
+#define DP_P1_MAR0     0x08
+#define DP_P1_MAR1     0x09
+#define DP_P1_MAR2     0x0a
+#define DP_P1_MAR3     0x0b
+#define DP_P1_MAR4     0x0c
+#define DP_P1_MAR5     0x0d
+#define DP_P1_MAR6     0x0e
+#define DP_P1_MAR7     0x0f
+
+#define DP_P2_CR       0x00
+#define DP_P2_PSTART   0x01
+#define DP_P2_CLDA0    0x01             /* write */
+#define DP_P2_PSTOP    0x02
+#define DP_P2_CLDA1    0x02             /* write */
+#define DP_P2_RNPP     0x03
+#define DP_P2_TPSR     0x04
+#define DP_P2_LNPP     0x05
+#define DP_P2_ACH      0x06
+#define DP_P2_ACL      0x07
+#define DP_P2_RCR      0x0c
+#define DP_P2_TCR      0x0d
+#define DP_P2_DCR      0x0e
+#define DP_P2_IMR      0x0f
+
+/* Command register - common to all pages */
+
+#define DP_CR_STOP    0x01   /* Stop: software reset */
+#define DP_CR_START   0x02   /* Start: initialize device */
+#define DP_CR_TXPKT   0x04   /* Transmit packet */
+#define DP_CR_RDMA    0x08   /* Read DMA  (recv data from device) */
+#define DP_CR_WDMA    0x10   /* Write DMA (send data to device) */
+#define DP_CR_SEND    0x18   /* Send packet */
+#define DP_CR_NODMA   0x20   /* Remote (or no) DMA */
+#define DP_CR_PAGE0   0x00   /* Page select */
+#define DP_CR_PAGE1   0x40
+#define DP_CR_PAGE2   0x80
+#define DP_CR_PAGEMSK 0x3F   /* Used to mask out page bits */
+
+/* Data configuration register */
+
+#define DP_DCR_WTS    0x01   /* 1=16 bit word transfers */
+#define DP_DCR_BOS    0x02   /* 1=Little Endian */
+#define DP_DCR_LAS    0x04   /* 1=Single 32 bit DMA mode */
+#define DP_DCR_LS     0x08   /* 1=normal mode, 0=loopback */
+#define DP_DCR_ARM    0x10   /* 0=no send command (program I/O) */
+#define DP_DCR_FIFO_1 0x00   /* FIFO threshold */
+#define DP_DCR_FIFO_2 0x20
+#define DP_DCR_FIFO_4 0x40
+#define DP_DCR_FIFO_6 0x60
+
+#define DP_DCR_INIT   (DP_DCR_LS|DP_DCR_FIFO_4)
+
+/* Interrupt status register */
+
+#define DP_ISR_RxP    0x01   /* Packet received */
+#define DP_ISR_TxP    0x02   /* Packet transmitted */
+#define DP_ISR_RxE    0x04   /* Receive error */
+#define DP_ISR_TxE    0x08   /* Transmit error */
+#define DP_ISR_OFLW   0x10   /* Receive overflow */
+#define DP_ISR_CNT    0x20   /* Tally counters need emptying */
+#define DP_ISR_RDC    0x40   /* Remote DMA complete */
+#define DP_ISR_RESET  0x80   /* Device has reset (shutdown, error) */
+
+/* Interrupt mask register */
+
+#define DP_IMR_RxP    0x01   /* Packet received */
+#define DP_IMR_TxP    0x02   /* Packet transmitted */
+#define DP_IMR_RxE    0x04   /* Receive error */
+#define DP_IMR_TxE    0x08   /* Transmit error */
+#define DP_IMR_OFLW   0x10   /* Receive overflow */
+#define DP_IMR_CNT    0x20   /* Tall counters need emptying */
+#define DP_IMR_RDC    0x40   /* Remote DMA complete */
+
+#define DP_IMR_All    0x3F   /* Everything but remote DMA */
+
+/* Receiver control register */
+
+#define DP_RCR_SEP    0x01   /* Save bad(error) packets */
+#define DP_RCR_AR     0x02   /* Accept runt packets */
+#define DP_RCR_AB     0x04   /* Accept broadcast packets */
+#define DP_RCR_AM     0x08   /* Accept multicast packets */
+#define DP_RCR_PROM   0x10   /* Promiscuous mode */
+#define DP_RCR_MON    0x20   /* Monitor mode - 1=accept no packets */
+
+/* Receiver status register */
+
+#define DP_RSR_RxP    0x01   /* Packet received */
+#define DP_RSR_CRC    0x02   /* CRC error */
+#define DP_RSR_FRAME  0x04   /* Framing error */
+#define DP_RSR_FO     0x08   /* FIFO overrun */
+#define DP_RSR_MISS   0x10   /* Missed packet */
+#define DP_RSR_PHY    0x20   /* 0=pad match, 1=mad match */
+#define DP_RSR_DIS    0x40   /* Receiver disabled */
+#define DP_RSR_DFR    0x80   /* Receiver processing deferred */
+
+/* Transmitter control register */
+
+#define DP_TCR_NOCRC  0x01   /* 1=inhibit CRC */
+#define DP_TCR_NORMAL 0x00   /* Normal transmitter operation */
+#define DP_TCR_LOCAL  0x02   /* Internal NIC loopback */
+#define DP_TCR_INLOOP 0x04   /* Full internal loopback */
+#define DP_TCR_OUTLOOP 0x08  /* External loopback */
+#define DP_TCR_ATD    0x10   /* Auto transmit disable */
+#define DP_TCR_OFFSET 0x20   /* Collision offset adjust */
+
+/* Transmit status register */
+
+#define DP_TSR_TxP    0x01   /* Packet transmitted */
+#define DP_TSR_COL    0x04   /* Collision (at least one) */
+#define DP_TSR_ABT    0x08   /* Aborted because of too many collisions */
+#define DP_TSR_CRS    0x10   /* Lost carrier */
+#define DP_TSR_FU     0x20   /* FIFO underrun */
+#define DP_TSR_CDH    0x40   /* Collision Detect Heartbeat */
+#define DP_TSR_OWC    0x80   /* Collision outside normal window */
+
+#define IEEE_8023_MAX_FRAME         1518    /* Largest possible ethernet frame */
+#define IEEE_8023_MIN_FRAME           64    /* Smallest possible ethernet frame */
diff --git a/drivers/ns16550.c b/drivers/ns16550.c
index f9fe819..2429464 100644
--- a/drivers/ns16550.c
+++ b/drivers/ns16550.c
@@ -17,7 +17,7 @@
 void NS16550_init (NS16550_t com_port, int baud_divisor)
 {
 	com_port->ier = 0x00;
-#ifdef CONFIG_OMAP1510
+#ifdef CONFIG_OMAP
 	com_port->mdr1 = 0x7;	/* mode select reset TL16C750*/
 #endif
 	com_port->lcr = LCR_BKSE | LCRVAL;
@@ -26,8 +26,12 @@ void NS16550_init (NS16550_t com_port, int baud_divisor)
 	com_port->lcr = LCRVAL;
 	com_port->mcr = MCRVAL;
 	com_port->fcr = FCRVAL;
-#if defined(CONFIG_OMAP1510) || defined(CONFIG_OMAP1610) || defined(CONFIG_OMAP730)
-	com_port->mdr1 = 0;	/* select uart mode */
+#if defined(CONFIG_OMAP)
+#if defined(CONFIG_APTIX)
+	com_port->mdr1 = 3;	/* /13 mode so Aptix 6MHz can hit 115200 */
+#else
+	com_port->mdr1 = 0;	/* /16 is proper to hit 115200 with 48MHz */
+#endif
 #endif
 }
 
diff --git a/drivers/omap24xx_i2c.c b/drivers/omap24xx_i2c.c
new file mode 100644
index 0000000..7423863
--- /dev/null
+++ b/drivers/omap24xx_i2c.c
@@ -0,0 +1,317 @@
+/*
+ * Basic I2C functions
+ *
+ * Copyright (c) 2004 Texas Instruments
+ *
+ * This package is free software;  you can redistribute it and/or
+ * modify it under the terms of the license found in the file
+ * named COPYING that should have accompanied this file.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Author: Jian Zhang jzhang@ti.com, Texas Instruments
+ *
+ * Copyright (c) 2003 Wolfgang Denk, wd@denx.de
+ * Rewritten to fit into the current U-Boot framework
+ *
+ * Adapted for OMAP2420 I2C, r-woodruff2@ti.com
+ *
+ */
+
+#include <common.h>
+#include <asm/arch/i2c.h>
+#include <asm/io.h>
+
+#define inw(a) __raw_readw(a)
+#define outw(a,v) __raw_writew(a,v)
+
+#ifdef CONFIG_DRIVER_OMAP24XX_I2C
+
+static void wait_for_bb (void);
+static u16 wait_for_pin (void);
+void flush_fifo(void);
+
+void i2c_init (int speed, int slaveadd)
+{
+	u16 scl;
+
+	if (inw (I2C_CON) & I2C_CON_EN) {
+		outw (0, I2C_CON);
+		udelay (50000);
+	}
+
+	/* 12Mhz I2C module clock */
+	outw (0, I2C_PSC);
+        speed = speed/1000;                 /* 100 or 400 */
+        scl = ((12000/(speed*2)) - 7);  /* use 7 when PSC = 0 */
+	outw (scl, I2C_SCLL);
+	outw (scl, I2C_SCLH);
+	/* own address */
+	outw (slaveadd, I2C_OA);
+	outw (I2C_CON_EN, I2C_CON);
+	outw (0, I2C_CNT);
+	/* have to enable intrrupts or OMAP i2c module doesn't work */
+	outw (I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE |
+	      I2C_IE_NACK_IE | I2C_IE_AL_IE, I2C_IE);
+	udelay (1000);
+}
+
+static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value)
+{
+	int i2c_error = 0;
+	u16 status;
+
+	/* wait until bus not busy */
+	wait_for_bb ();
+
+	/* one byte only */
+	outw (1, I2C_CNT);
+	/* set slave address */
+	outw (devaddr, I2C_SA);
+	/* no stop bit needed here */
+	outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, I2C_CON);
+
+	status = wait_for_pin ();
+
+	if (status & I2C_STAT_XRDY) {
+		/* Important: have to use byte access */
+		*(volatile u8 *) (I2C_DATA) = regoffset;
+		udelay (20000);
+		if (inw (I2C_STAT) & I2C_STAT_NACK) {
+			i2c_error = 1;
+		}
+	} else {
+		i2c_error = 1;
+	}
+
+	if (!i2c_error) {
+		/* free bus, otherwise we can't use a combined transction */
+		outw (0, I2C_CON);
+		while (inw (I2C_STAT) || (inw (I2C_CON) & I2C_CON_MST)) {
+			udelay (10000);
+			/* Have to clear pending interrupt to clear I2C_STAT */
+			outw (0xFFFF, I2C_STAT);
+		}
+
+		wait_for_bb ();
+		/* set slave address */
+		outw (devaddr, I2C_SA);
+		/* read one byte from slave */
+		outw (1, I2C_CNT);
+		/* need stop bit here */
+		outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP,
+		      I2C_CON);
+
+		status = wait_for_pin ();
+		if (status & I2C_STAT_RRDY) {
+			*value = inw (I2C_DATA);
+			udelay (20000);
+		} else {
+			i2c_error = 1;
+		}
+
+		if (!i2c_error) {
+			outw (I2C_CON_EN, I2C_CON);
+			while (inw (I2C_STAT)
+			       || (inw (I2C_CON) & I2C_CON_MST)) {
+				udelay (10000);
+				outw (0xFFFF, I2C_STAT);
+			}
+		}
+	}
+	flush_fifo();
+	outw (0xFFFF, I2C_STAT);
+	outw (0, I2C_CNT);
+	return i2c_error;
+}
+
+static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value)
+{
+	int i2c_error = 0;
+	u16 status, stat;
+
+	/* wait until bus not busy */
+	wait_for_bb ();
+
+	/* two bytes */
+	outw (2, I2C_CNT);
+	/* set slave address */
+	outw (devaddr, I2C_SA);
+	/* stop bit needed here */
+	outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
+	      I2C_CON_STP, I2C_CON);
+
+	/* wait until state change */
+	status = wait_for_pin ();
+
+	if (status & I2C_STAT_XRDY) {
+		/* send out two bytes */
+		outw ((value << 8) + regoffset, I2C_DATA);
+		/* must have enough delay to allow BB bit to go low */
+		udelay (50000);
+		if (inw (I2C_STAT) & I2C_STAT_NACK) {
+			i2c_error = 1;
+		}
+	} else {
+		i2c_error = 1;
+	}
+
+	if (!i2c_error) {
+		outw (I2C_CON_EN, I2C_CON);
+		while ((stat = inw (I2C_STAT)) || (inw (I2C_CON) & I2C_CON_MST)) {
+			udelay (1000);
+			/* have to read to clear intrrupt */
+			outw (0xFFFF, I2C_STAT);
+		}
+	}
+	flush_fifo();
+	outw (0xFFFF, I2C_STAT);
+	outw (0, I2C_CNT);
+	return i2c_error;
+}
+
+void flush_fifo(void)
+{	u16 stat;
+	
+	/* note: if you try and read data when its not there or ready 
+         * you get a bus error
+         */
+	while(1){
+		stat = inw(I2C_STAT);
+		if(stat == I2C_STAT_RRDY){
+			inw(I2C_DATA);
+			outw(I2C_STAT_RRDY,I2C_STAT);
+			udelay(1000);
+		}else
+			break;
+	}
+}
+
+int i2c_probe (uchar chip)
+{
+	int res = 1; /* default = fail */
+
+	if (chip == inw (I2C_OA)) {
+		return res;
+	}
+
+	/* wait until bus not busy */
+	wait_for_bb ();
+
+	/* try to read one byte */
+	outw (1, I2C_CNT);
+	/* set slave address */
+	outw (chip, I2C_SA);
+	/* stop bit needed here */
+	outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, I2C_CON);
+	/* enough delay for the NACK bit set */
+	udelay (50000);
+
+	if (!(inw (I2C_STAT) & I2C_STAT_NACK)) {
+		res = 0;      /* success case */ 
+		flush_fifo();
+		outw(0xFFFF, I2C_STAT);
+	} else {
+		outw(0xFFFF, I2C_STAT);  /* failue, clear sources*/
+		outw (inw (I2C_CON) | I2C_CON_STP, I2C_CON); /* finish up xfer */
+		udelay(20000);
+		wait_for_bb ();
+	}
+	flush_fifo();
+	outw (0, I2C_CNT); /* don't allow any more data in...we don't want it.*/
+	outw(0xFFFF, I2C_STAT);
+	return res;
+}
+
+int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
+{
+	int i;
+
+	if (alen > 1) {
+		printf ("I2C read: addr len %d not supported\n", alen);
+		return 1;
+	}
+
+	if (addr + len > 256) {
+		printf ("I2C read: address out of range\n");
+		return 1;
+	}
+
+	for (i = 0; i < len; i++) {
+		if (i2c_read_byte (chip, addr + i, &buffer[i])) {
+			printf ("I2C read: I/O error\n");
+			i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+			return 1;
+		}
+	}
+
+	return 0;
+}
+
+int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len)
+{
+	int i;
+
+	if (alen > 1) {
+		printf ("I2C read: addr len %d not supported\n", alen);
+		return 1;
+	}
+
+	if (addr + len > 256) {
+		printf ("I2C read: address out of range\n");
+		return 1;
+	}
+
+	for (i = 0; i < len; i++) {
+		if (i2c_write_byte (chip, addr + i, buffer[i])) {
+			printf ("I2C read: I/O error\n");
+			i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+			return 1;
+		}
+	}
+
+	return 0;
+}
+
+static void wait_for_bb (void)
+{
+	int timeout = 10;
+	u16 stat;
+
+	outw(0xFFFF, I2C_STAT);  /* clear current interruts...*/
+	while ((stat = inw (I2C_STAT) & I2C_STAT_BB) && timeout--) {
+		outw (stat, I2C_STAT);
+		udelay (50000);
+	}
+
+	if (timeout <= 0) {
+		printf ("timed out in wait_for_bb: I2C_STAT=%x\n",
+			inw (I2C_STAT));
+	}
+	outw(0xFFFF, I2C_STAT);  /* clear delayed stuff*/
+}
+
+static u16 wait_for_pin (void)
+{
+	u16 status;
+	int timeout = 10;
+
+	do {
+		udelay (1000);
+		status = inw (I2C_STAT);
+	} while (  !(status &
+		   (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY |
+		    I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK |
+		    I2C_STAT_AL)) && timeout--);
+
+	if (timeout <= 0) {
+		printf ("timed out in wait_for_pin: I2C_STAT=%x\n",
+			inw (I2C_STAT));
+			outw(0xFFFF, I2C_STAT);	
+}
+	return status;
+}
+
+#endif /* CONFIG_DRIVER_OMAP24XX_I2C */
diff --git a/drivers/serial.c b/drivers/serial.c
index f5b51d6..b13b05e 100644
--- a/drivers/serial.c
+++ b/drivers/serial.c
@@ -59,7 +59,14 @@ static int calc_divisor (void)
 		return (26);		/* return 26 for base divisor */
 	}
 #endif
-	return (CFG_NS16550_CLK / 16 / gd->baudrate);
+
+#ifdef CONFIG_APTIX
+#define MODE_X_DIV 13
+#else
+#define MODE_X_DIV 16
+#endif
+	return (CFG_NS16550_CLK / MODE_X_DIV / gd->baudrate);
+
 }
 
 int serial_init (void)