Initial revision

3 files changed, 1845 insertions, 0 deletions

diff --git a/drivers/eepro100.c b/drivers/eepro100.c
new file mode 100644
index 0000000..c8d07de
--- /dev/null
+++ b/drivers/eepro100.c
@@ -0,0 +1,820 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <net.h>
+#include <asm/io.h>
+#include <pci.h>
+
+#undef DEBUG
+
+#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
+	defined(CONFIG_EEPRO100)
+
+	/* Ethernet chip registers.
+	 */
+#define SCBStatus       	0	/* Rx/Command Unit Status *Word* */
+#define SCBIntAckByte   	1	/* Rx/Command Unit STAT/ACK byte */
+#define SCBCmd          	2	/* Rx/Command Unit Command *Word* */
+#define SCBIntrCtlByte  	3	/* Rx/Command Unit Intr.Control Byte */
+#define SCBPointer      	4	/* General purpose pointer. */
+#define SCBPort         	8	/* Misc. commands and operands. */
+#define SCBflash        	12	/* Flash memory control. */
+#define SCBeeprom       	14	/* EEPROM memory control. */
+#define SCBCtrlMDI      	16	/* MDI interface control. */
+#define SCBEarlyRx      	20	/* Early receive byte count. */
+#define SCBGenControl   	28	/* 82559 General Control Register */
+#define SCBGenStatus    	29	/* 82559 General Status register */
+
+	/* 82559 SCB status word defnitions
+	 */
+#define SCB_STATUS_CX   	0x8000	/* CU finished command (transmit) */
+#define SCB_STATUS_FR   	0x4000	/* frame received */
+#define SCB_STATUS_CNA  	0x2000	/* CU left active state */
+#define SCB_STATUS_RNR  	0x1000	/* receiver left ready state */
+#define SCB_STATUS_MDI  	0x0800	/* MDI read/write cycle done */
+#define SCB_STATUS_SWI  	0x0400	/* software generated interrupt */
+#define SCB_STATUS_FCP  	0x0100	/* flow control pause interrupt */
+
+#define SCB_INTACK_MASK 	0xFD00	/* all the above */
+
+#define SCB_INTACK_TX 		(SCB_STATUS_CX | SCB_STATUS_CNA)
+#define SCB_INTACK_RX 		(SCB_STATUS_FR | SCB_STATUS_RNR)
+
+	/* System control block commands
+	 */
+/* CU Commands */
+#define CU_NOP          	0x0000
+#define	CU_START        	0x0010
+#define	CU_RESUME       	0x0020
+#define	CU_STATSADDR    	0x0040	/* Load Dump Statistics ctrs addr */
+#define	CU_SHOWSTATS    	0x0050	/* Dump statistics counters. */
+#define	CU_ADDR_LOAD    	0x0060	/* Base address to add to CU commands */
+#define	CU_DUMPSTATS    	0x0070	/* Dump then reset stats counters. */
+
+/* RUC Commands */
+#define RUC_NOP         	0x0000
+#define	RUC_START       	0x0001
+#define	RUC_RESUME      	0x0002
+#define RUC_ABORT       	0x0004
+#define	RUC_ADDR_LOAD   	0x0006	/* (seems not to clear on acceptance) */
+#define RUC_RESUMENR    	0x0007
+
+#define CU_CMD_MASK     	0x00f0
+#define RU_CMD_MASK     	0x0007
+
+#define SCB_M	        	0x0100	/* 0 = enable interrupt, 1 = disable */
+#define SCB_SWI         	0x0200	/* 1 - cause device to interrupt */
+
+#define CU_STATUS_MASK  	0x00C0
+#define RU_STATUS_MASK  	0x003C
+
+#define RU_STATUS_IDLE  	(0<<2)
+#define RU_STATUS_SUS   	(1<<2)
+#define RU_STATUS_NORES 	(2<<2)
+#define RU_STATUS_READY 	(4<<2)
+#define RU_STATUS_NO_RBDS_SUS   ((1<<2)|(8<<2))
+#define RU_STATUS_NO_RBDS_NORES ((2<<2)|(8<<2))
+#define RU_STATUS_NO_RBDS_READY ((4<<2)|(8<<2))
+
+	/* 82559 Port interface commands.
+	 */
+#define I82559_RESET		0x00000000	/* Software reset */
+#define I82559_SELFTEST		0x00000001	/* 82559 Selftest command */
+#define I82559_SELECTIVE_RESET	0x00000002
+#define I82559_DUMP		0x00000003
+#define I82559_DUMP_WAKEUP	0x00000007
+
+	/* 82559 Eeprom interface.
+	 */
+#define EE_SHIFT_CLK		0x01	/* EEPROM shift clock. */
+#define EE_CS			0x02	/* EEPROM chip select. */
+#define EE_DATA_WRITE		0x04	/* EEPROM chip data in. */
+#define EE_WRITE_0		0x01
+#define EE_WRITE_1		0x05
+#define EE_DATA_READ		0x08	/* EEPROM chip data out. */
+#define EE_ENB			(0x4800 | EE_CS)
+#define EE_CMD_BITS		3
+#define EE_DATA_BITS		16
+
+	/* The EEPROM commands include the alway-set leading bit.
+	 */
+#define EE_EWENB_CMD		(4 << addr_len)
+#define EE_WRITE_CMD		(5 << addr_len)
+#define EE_READ_CMD		(6 << addr_len)
+#define EE_ERASE_CMD		(7 << addr_len)
+
+	/* Receive frame descriptors.
+	 */
+struct RxFD {
+	volatile u16 status;
+	volatile u16 control;
+	volatile u32 link;		/* struct RxFD * */
+	volatile u32 rx_buf_addr;	/* void * */
+	volatile u32 count;
+
+	volatile u8 data[PKTSIZE_ALIGN];
+};
+
+#define RFD_STATUS_C		0x8000	/* completion of received frame */
+#define RFD_STATUS_OK   	0x2000	/* frame received with no errors */
+
+#define RFD_CONTROL_EL   	0x8000	/* 1=last RFD in RFA */
+#define RFD_CONTROL_S    	0x4000	/* 1=suspend RU after receiving frame */
+#define RFD_CONTROL_H    	0x0010	/* 1=RFD is a header RFD */
+#define RFD_CONTROL_SF   	0x0008	/* 0=simplified, 1=flexible mode */
+
+#define RFD_COUNT_MASK     	0x3fff
+#define RFD_COUNT_F        	0x4000
+#define RFD_COUNT_EOF      	0x8000
+
+#define RFD_RX_CRC          	0x0800	/* crc error */
+#define RFD_RX_ALIGNMENT    	0x0400	/* alignment error */
+#define RFD_RX_RESOURCE     	0x0200	/* out of space, no resources */
+#define RFD_RX_DMA_OVER     	0x0100	/* DMA overrun */
+#define RFD_RX_SHORT        	0x0080	/* short frame error */
+#define RFD_RX_LENGTH       	0x0020
+#define RFD_RX_ERROR        	0x0010	/* receive error */
+#define RFD_RX_NO_ADR_MATCH 	0x0004	/* no address match */
+#define RFD_RX_IA_MATCH     	0x0002	/* individual address does not match */
+#define RFD_RX_TCO          	0x0001	/* TCO indication */
+
+	/* Transmit frame descriptors
+	 */
+struct TxFD {				/* Transmit frame descriptor set. */
+	volatile u16 status;
+	volatile u16 command;
+	volatile u32 link;		/* void * */
+	volatile u32 tx_desc_addr;	/* Always points to the tx_buf_addr element. */
+	volatile s32 count;
+
+	volatile u32 tx_buf_addr0;	/* void *, frame to be transmitted.  */
+	volatile s32 tx_buf_size0;	/* Length of Tx frame. */
+	volatile u32 tx_buf_addr1;	/* void *, frame to be transmitted.  */
+	volatile s32 tx_buf_size1;	/* Length of Tx frame. */
+};
+
+#define TxCB_CMD_TRANSMIT	0x0004	/* transmit command */
+#define TxCB_CMD_SF         	0x0008	/* 0=simplified, 1=flexible mode */
+#define TxCB_CMD_NC         	0x0010	/* 0=CRC insert by controller */
+#define TxCB_CMD_I          	0x2000	/* generate interrupt on completion */
+#define TxCB_CMD_S          	0x4000	/* suspend on completion */
+#define TxCB_CMD_EL         	0x8000	/* last command block in CBL */
+
+#define TxCB_COUNT_MASK     	0x3fff
+#define TxCB_COUNT_EOF      	0x8000
+
+	/* The Speedo3 Rx and Tx frame/buffer descriptors.
+	 */
+struct descriptor {			/* A generic descriptor. */
+	volatile u16 status;
+	volatile u16 command;
+	volatile u32 link;		/* struct descriptor *  */
+
+	unsigned char params[0];
+};
+
+#define CFG_CMD_EL         	0x8000
+#define CFG_CMD_SUSPEND    	0x4000
+#define CFG_CMD_INT        	0x2000
+#define CFG_CMD_IAS        	0x0001	/* individual address setup */
+#define CFG_CMD_CONFIGURE  	0x0002	/* configure */
+
+#define CFG_STATUS_C       	0x8000
+#define CFG_STATUS_OK      	0x2000
+
+	/* Misc.
+	 */
+#define NUM_RX_DESC 		PKTBUFSRX
+#define NUM_TX_DESC 		1	/* Number of TX descriptors   */
+
+#define TOUT_LOOP		1000000
+
+#define ETH_ALEN		6
+
+static struct RxFD rx_ring[NUM_RX_DESC];	/* RX descriptor ring         */
+static struct TxFD tx_ring[NUM_TX_DESC];	/* TX descriptor ring         */
+static int rx_next;			/* RX descriptor ring pointer */
+static int tx_next;			/* TX descriptor ring pointer */
+static int tx_threshold;
+
+/*
+ * The parameters for a CmdConfigure operation.
+ * There are so many options that it would be difficult to document
+ * each bit. We mostly use the default or recommended settings.
+ */
+static const char i82557_config_cmd[] = {
+	22, 0x08, 0, 0, 0, 0, 0x32, 0x03, 1,	/* 1=Use MII  0=Use AUI */
+	0, 0x2E, 0, 0x60, 0,
+	0xf2, 0x48, 0, 0x40, 0xf2, 0x80,	/* 0x40=Force full-duplex */
+	0x3f, 0x05,
+};
+static const char i82558_config_cmd[] = {
+	22, 0x08, 0, 1, 0, 0, 0x22, 0x03, 1,	/* 1=Use MII  0=Use AUI */
+	0, 0x2E, 0, 0x60, 0x08, 0x88,
+	0x68, 0, 0x40, 0xf2, 0x84,		/* Disable FC */
+	0x31, 0x05,
+};
+
+static void init_rx_ring (struct eth_device *dev);
+static void purge_tx_ring (struct eth_device *dev);
+
+static void read_hw_addr (struct eth_device *dev, bd_t * bis);
+
+static int eepro100_init (struct eth_device *dev, bd_t * bis);
+static int eepro100_send (struct eth_device *dev, volatile void *packet,
+						  int length);
+static int eepro100_recv (struct eth_device *dev);
+static void eepro100_halt (struct eth_device *dev);
+
+#define bus_to_phys(a)	pci_mem_to_phys((pci_dev_t)dev->priv, a)
+#define phys_to_bus(a)	pci_phys_to_mem((pci_dev_t)dev->priv, a)
+
+static inline int INW (struct eth_device *dev, u_long addr)
+{
+	return le16_to_cpu (*(volatile u16 *) (addr + dev->iobase));
+}
+
+static inline void OUTW (struct eth_device *dev, int command, u_long addr)
+{
+	*(volatile u16 *) ((addr + dev->iobase)) = cpu_to_le16 (command);
+}
+
+static inline void OUTL (struct eth_device *dev, int command, u_long addr)
+{
+	*(volatile u32 *) ((addr + dev->iobase)) = cpu_to_le32 (command);
+}
+
+	/* Wait for the chip get the command.
+	 */
+static int wait_for_eepro100 (struct eth_device *dev)
+{
+	int i;
+
+	for (i = 0; INW (dev, SCBCmd) & (CU_CMD_MASK | RU_CMD_MASK); i++) {
+		if (i >= TOUT_LOOP) {
+			return 0;
+		}
+	}
+
+	return 1;
+}
+
+static struct pci_device_id supported[] = {
+	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82557},
+	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559},
+	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559ER},
+	{}
+};
+
+int eepro100_initialize (bd_t * bis)
+{
+	pci_dev_t devno;
+	int card_number = 0;
+	struct eth_device *dev;
+	u32 iobase, status;
+	int idx = 0;
+
+	while (1) {
+		/* Find PCI device
+		 */
+		if ((devno = pci_find_devices (supported, idx++)) < 0) {
+			break;
+		}
+
+		pci_read_config_dword (devno, PCI_BASE_ADDRESS_0, &iobase);
+		iobase &= ~0xf;
+
+#ifdef DEBUG
+		printf ("eepro100: Intel i82559 PCI EtherExpressPro @0x%x\n",
+				iobase);
+#endif
+
+		pci_write_config_dword (devno,
+					PCI_COMMAND,
+					PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+
+		/* Check if I/O accesses and Bus Mastering are enabled.
+		 */
+		pci_read_config_dword (devno, PCI_COMMAND, &status);
+		if (!(status & PCI_COMMAND_MEMORY)) {
+			printf ("Error: Can not enable MEM access.\n");
+			continue;
+		}
+
+		if (!(status & PCI_COMMAND_MASTER)) {
+			printf ("Error: Can not enable Bus Mastering.\n");
+			continue;
+		}
+
+		dev = (struct eth_device *) malloc (sizeof *dev);
+
+		sprintf (dev->name, "i82559#%d", card_number);
+		dev->iobase = bus_to_phys (iobase);
+		dev->priv = (void *) devno;
+		dev->init = eepro100_init;
+		dev->halt = eepro100_halt;
+		dev->send = eepro100_send;
+		dev->recv = eepro100_recv;
+
+		eth_register (dev);
+
+		card_number++;
+
+		/* Set the latency timer for value.
+		 */
+		pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x20);
+
+		udelay (10 * 1000);
+
+		read_hw_addr (dev, bis);
+	}
+
+	return card_number;
+}
+
+
+static int eepro100_init (struct eth_device *dev, bd_t * bis)
+{
+	int i, status = 0;
+	int tx_cur;
+	struct descriptor *ias_cmd, *cfg_cmd;
+
+	/* Reset the ethernet controller
+	 */
+	OUTL (dev, I82559_SELECTIVE_RESET, SCBPort);
+	udelay (20);
+
+	OUTL (dev, I82559_RESET, SCBPort);
+	udelay (20);
+
+	if (!wait_for_eepro100 (dev)) {
+		printf ("Error: Can not reset ethernet controller.\n");
+		goto Done;
+	}
+	OUTL (dev, 0, SCBPointer);
+	OUTW (dev, SCB_M | RUC_ADDR_LOAD, SCBCmd);
+
+	if (!wait_for_eepro100 (dev)) {
+		printf ("Error: Can not reset ethernet controller.\n");
+		goto Done;
+	}
+	OUTL (dev, 0, SCBPointer);
+	OUTW (dev, SCB_M | CU_ADDR_LOAD, SCBCmd);
+
+	/* Initialize Rx and Tx rings.
+	 */
+	init_rx_ring (dev);
+	purge_tx_ring (dev);
+
+	/* Tell the adapter where the RX ring is located.
+	 */
+	if (!wait_for_eepro100 (dev)) {
+		printf ("Error: Can not reset ethernet controller.\n");
+		goto Done;
+	}
+
+	OUTL (dev, phys_to_bus ((u32) & rx_ring[rx_next]), SCBPointer);
+	OUTW (dev, SCB_M | RUC_START, SCBCmd);
+
+	/* Send the Configure frame */
+	tx_cur = tx_next;
+	tx_next = ((tx_next + 1) % NUM_TX_DESC);
+
+	cfg_cmd = (struct descriptor *) &tx_ring[tx_cur];
+	cfg_cmd->command = cpu_to_le16 ((CFG_CMD_SUSPEND | CFG_CMD_CONFIGURE));
+	cfg_cmd->status = 0;
+	cfg_cmd->link = cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next]));
+
+	memcpy (cfg_cmd->params, i82558_config_cmd,
+			sizeof (i82558_config_cmd));
+
+	if (!wait_for_eepro100 (dev)) {
+		printf ("Error---CFG_CMD_CONFIGURE: Can not reset ethernet controller.\n");
+		goto Done;
+	}
+
+	OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer);
+	OUTW (dev, SCB_M | CU_START, SCBCmd);
+
+	for (i = 0;
+	     !(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_C);
+	     i++) {
+		if (i >= TOUT_LOOP) {
+			printf ("%s: Tx error buffer not ready\n", dev->name);
+			goto Done;
+		}
+	}
+
+	if (!(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_OK)) {
+		printf ("TX error status = 0x%08X\n",
+			le16_to_cpu (tx_ring[tx_cur].status));
+		goto Done;
+	}
+
+	/* Send the Individual Address Setup frame
+	 */
+	tx_cur = tx_next;
+	tx_next = ((tx_next + 1) % NUM_TX_DESC);
+
+	ias_cmd = (struct descriptor *) &tx_ring[tx_cur];
+	ias_cmd->command = cpu_to_le16 ((CFG_CMD_SUSPEND | CFG_CMD_IAS));
+	ias_cmd->status = 0;
+	ias_cmd->link = cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next]));
+
+	memcpy (ias_cmd->params, dev->enetaddr, 6);
+
+	/* Tell the adapter where the TX ring is located.
+	 */
+	if (!wait_for_eepro100 (dev)) {
+		printf ("Error: Can not reset ethernet controller.\n");
+		goto Done;
+	}
+
+	OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer);
+	OUTW (dev, SCB_M | CU_START, SCBCmd);
+
+	for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_C);
+		 i++) {
+		if (i >= TOUT_LOOP) {
+			printf ("%s: Tx error buffer not ready\n",
+				dev->name);
+			goto Done;
+		}
+	}
+
+	if (!(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_OK)) {
+		printf ("TX error status = 0x%08X\n",
+			le16_to_cpu (tx_ring[tx_cur].status));
+		goto Done;
+	}
+
+	status = 1;
+
+  Done:
+	return status;
+}
+
+static int eepro100_send (struct eth_device *dev, volatile void *packet, int length)
+{
+	int i, status = -1;
+	int tx_cur;
+
+	if (length <= 0) {
+		printf ("%s: bad packet size: %d\n", dev->name, length);
+		goto Done;
+	}
+
+	tx_cur = tx_next;
+	tx_next = (tx_next + 1) % NUM_TX_DESC;
+
+	tx_ring[tx_cur].command = cpu_to_le16 ( TxCB_CMD_TRANSMIT |
+						TxCB_CMD_SF	|
+						TxCB_CMD_S	|
+						TxCB_CMD_EL );
+	tx_ring[tx_cur].status = 0;
+	tx_ring[tx_cur].count = cpu_to_le32 (tx_threshold);
+	tx_ring[tx_cur].link =
+		cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next]));
+	tx_ring[tx_cur].tx_desc_addr =
+		cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_cur].tx_buf_addr0));
+	tx_ring[tx_cur].tx_buf_addr0 =
+		cpu_to_le32 (phys_to_bus ((u_long) packet));
+	tx_ring[tx_cur].tx_buf_size0 = cpu_to_le32 (length);
+
+	if (!wait_for_eepro100 (dev)) {
+		printf ("%s: Tx error ethernet controller not ready.\n",
+				dev->name);
+		goto Done;
+	}
+
+	/* Send the packet.
+	 */
+	OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer);
+	OUTW (dev, SCB_M | CU_START, SCBCmd);
+
+	for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_C);
+		 i++) {
+		if (i >= TOUT_LOOP) {
+			printf ("%s: Tx error buffer not ready\n", dev->name);
+			goto Done;
+		}
+	}
+
+	if (!(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_OK)) {
+		printf ("TX error status = 0x%08X\n",
+			le16_to_cpu (tx_ring[tx_cur].status));
+		goto Done;
+	}
+
+	status = length;
+
+  Done:
+	return status;
+}
+
+static int eepro100_recv (struct eth_device *dev)
+{
+	u16 status, stat;
+	int rx_prev, length = 0;
+
+	stat = INW (dev, SCBStatus);
+	OUTW (dev, stat & SCB_STATUS_RNR, SCBStatus);
+
+	for (;;) {
+		status = le16_to_cpu (rx_ring[rx_next].status);
+
+		if (!(status & RFD_STATUS_C)) {
+			break;
+		}
+
+		/* Valid frame status.
+		 */
+		if ((status & RFD_STATUS_OK)) {
+			/* A valid frame received.
+			 */
+			length = le32_to_cpu (rx_ring[rx_next].count) & 0x3fff;
+
+			/* Pass the packet up to the protocol
+			 * layers.
+			 */
+			NetReceive (rx_ring[rx_next].data, length);
+		} else {
+			/* There was an error.
+			 */
+			printf ("RX error status = 0x%08X\n", status);
+		}
+
+		rx_ring[rx_next].control = cpu_to_le16 (RFD_CONTROL_S);
+		rx_ring[rx_next].status = 0;
+		rx_ring[rx_next].count = cpu_to_le32 (PKTSIZE_ALIGN << 16);
+
+		rx_prev = (rx_next + NUM_RX_DESC - 1) % NUM_RX_DESC;
+		rx_ring[rx_prev].control = 0;
+
+		/* Update entry information.
+		 */
+		rx_next = (rx_next + 1) % NUM_RX_DESC;
+	}
+
+	if (stat & SCB_STATUS_RNR) {
+
+		printf ("%s: Receiver is not ready, restart it !\n", dev->name);
+
+		/* Reinitialize Rx ring.
+		 */
+		init_rx_ring (dev);
+
+		if (!wait_for_eepro100 (dev)) {
+			printf ("Error: Can not restart ethernet controller.\n");
+			goto Done;
+		}
+
+		OUTL (dev, phys_to_bus ((u32) & rx_ring[rx_next]), SCBPointer);
+		OUTW (dev, SCB_M | RUC_START, SCBCmd);
+	}
+
+  Done:
+	return length;
+}
+
+static void eepro100_halt (struct eth_device *dev)
+{
+	/* Reset the ethernet controller
+	 */
+	OUTL (dev, I82559_SELECTIVE_RESET, SCBPort);
+	udelay (20);
+
+	OUTL (dev, I82559_RESET, SCBPort);
+	udelay (20);
+
+	if (!wait_for_eepro100 (dev)) {
+		printf ("Error: Can not reset ethernet controller.\n");
+		goto Done;
+	}
+	OUTL (dev, 0, SCBPointer);
+	OUTW (dev, SCB_M | RUC_ADDR_LOAD, SCBCmd);
+
+	if (!wait_for_eepro100 (dev)) {
+		printf ("Error: Can not reset ethernet controller.\n");
+		goto Done;
+	}
+	OUTL (dev, 0, SCBPointer);
+	OUTW (dev, SCB_M | CU_ADDR_LOAD, SCBCmd);
+
+  Done:
+	return;
+}
+
+	/* SROM Read.
+	 */
+static int read_eeprom (struct eth_device *dev, int location, int addr_len)
+{
+	unsigned short retval = 0;
+	int read_cmd = location | EE_READ_CMD;
+	int i;
+
+	OUTW (dev, EE_ENB & ~EE_CS, SCBeeprom);
+	OUTW (dev, EE_ENB, SCBeeprom);
+
+	/* Shift the read command bits out. */
+	for (i = 12; i >= 0; i--) {
+		short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
+
+		OUTW (dev, EE_ENB | dataval, SCBeeprom);
+		udelay (1);
+		OUTW (dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
+		udelay (1);
+	}
+	OUTW (dev, EE_ENB, SCBeeprom);
+
+	for (i = 15; i >= 0; i--) {
+		OUTW (dev, EE_ENB | EE_SHIFT_CLK, SCBeeprom);
+		udelay (1);
+		retval = (retval << 1) |
+				((INW (dev, SCBeeprom) & EE_DATA_READ) ? 1 : 0);
+		OUTW (dev, EE_ENB, SCBeeprom);
+		udelay (1);
+	}
+
+	/* Terminate the EEPROM access. */
+	OUTW (dev, EE_ENB & ~EE_CS, SCBeeprom);
+	return retval;
+}
+
+#ifdef CONFIG_EEPRO100_SROM_WRITE
+int eepro100_write_eeprom (struct eth_device* dev, int location, int addr_len, unsigned short data)
+{
+    unsigned short dataval;
+    int enable_cmd = 0x3f | EE_EWENB_CMD;
+    int write_cmd  = location | EE_WRITE_CMD;
+    int i;
+    unsigned long datalong, tmplong;
+
+    OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
+    udelay(1);
+    OUTW(dev, EE_ENB, SCBeeprom);
+
+    /* Shift the enable command bits out. */
+    for (i = (addr_len+EE_CMD_BITS-1); i >= 0; i--)
+    {
+        dataval = (enable_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
+        OUTW(dev, EE_ENB | dataval, SCBeeprom);
+        udelay(1);
+        OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
+        udelay(1);
+    }
+
+    OUTW(dev, EE_ENB, SCBeeprom);
+    udelay(1);
+    OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
+    udelay(1);
+    OUTW(dev, EE_ENB, SCBeeprom);
+
+
+    /* Shift the write command bits out. */
+    for (i = (addr_len+EE_CMD_BITS-1); i >= 0; i--)
+    {
+        dataval = (write_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
+        OUTW(dev, EE_ENB | dataval, SCBeeprom);
+        udelay(1);
+        OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
+        udelay(1);
+    }
+
+    /* Write the data */
+    datalong= (unsigned long) ((((data) & 0x00ff) << 8) | ( (data) >> 8));
+
+    for (i = 0; i< EE_DATA_BITS; i++)
+    {
+    /* Extract and move data bit to bit DI */
+    dataval = ((datalong & 0x8000)>>13) ? EE_DATA_WRITE : 0;
+
+    OUTW(dev, EE_ENB | dataval, SCBeeprom);
+    udelay(1);
+    OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
+    udelay(1);
+    OUTW(dev, EE_ENB | dataval, SCBeeprom);
+    udelay(1);
+
+    datalong = datalong << 1; /* Adjust significant data bit*/
+    }
+
+    /* Finish up command  (toggle CS) */
+    OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
+    udelay(1);                /* delay for more than 250 ns */
+    OUTW(dev, EE_ENB, SCBeeprom);
+
+    /* Wait for programming ready (D0 = 1) */
+    tmplong = 10;
+    do
+    {
+        dataval = INW(dev, SCBeeprom);
+        if (dataval & EE_DATA_READ)
+            break;
+        udelay(10000);
+    }
+    while (-- tmplong);
+
+    if (tmplong == 0)
+    {
+        printf ("Write i82559 eeprom timed out (100 ms waiting for data ready.\n");
+        return -1;
+    }
+
+    /* Terminate the EEPROM access. */
+    OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
+
+    return 0;
+}
+#endif
+
+static void init_rx_ring (struct eth_device *dev)
+{
+	int i;
+
+	for (i = 0; i < NUM_RX_DESC; i++) {
+		rx_ring[i].status = 0;
+		rx_ring[i].control =
+				(i == NUM_RX_DESC - 1) ? cpu_to_le16 (RFD_CONTROL_S) : 0;
+		rx_ring[i].link =
+				cpu_to_le32 (phys_to_bus
+							 ((u32) & rx_ring[(i + 1) % NUM_RX_DESC]));
+		rx_ring[i].rx_buf_addr = 0xffffffff;
+		rx_ring[i].count = cpu_to_le32 (PKTSIZE_ALIGN << 16);
+	}
+
+	rx_next = 0;
+}
+
+static void purge_tx_ring (struct eth_device *dev)
+{
+	int i;
+
+	tx_next = 0;
+	tx_threshold = 0x01208000;
+
+	for (i = 0; i < NUM_TX_DESC; i++) {
+		tx_ring[i].status = 0;
+		tx_ring[i].command = 0;
+		tx_ring[i].link = 0;
+		tx_ring[i].tx_desc_addr = 0;
+		tx_ring[i].count = 0;
+
+		tx_ring[i].tx_buf_addr0 = 0;
+		tx_ring[i].tx_buf_size0 = 0;
+		tx_ring[i].tx_buf_addr1 = 0;
+		tx_ring[i].tx_buf_size1 = 0;
+	}
+}
+
+static void read_hw_addr (struct eth_device *dev, bd_t * bis)
+{
+	u16 eeprom[0x40];
+	u16 sum = 0;
+	int i, j;
+	int addr_len = read_eeprom (dev, 0, 6) == 0xffff ? 8 : 6;
+
+	for (j = 0, i = 0; i < 0x40; i++) {
+		u16 value = read_eeprom (dev, i, addr_len);
+
+		eeprom[i] = value;
+		sum += value;
+		if (i < 3) {
+			dev->enetaddr[j++] = value;
+			dev->enetaddr[j++] = value >> 8;
+		}
+	}
+
+	if (sum != 0xBABA) {
+		memset (dev->enetaddr, 0, ETH_ALEN);
+#ifdef DEBUG
+		printf ("%s: Invalid EEPROM checksum %#4.4x, "
+			"check settings before activating this device!\n",
+			dev->name, sum);
+#endif
+	}
+}
+
+#endif
diff --git a/drivers/sym53c8xx.c b/drivers/sym53c8xx.c
new file mode 100644
index 0000000..e03a049
--- /dev/null
+++ b/drivers/sym53c8xx.c
@@ -0,0 +1,799 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ * partly derived from
+ * linux/drivers/scsi/sym53c8xx.c
+ *
+ */
+
+/*
+ * SCSI support based on the chip sym53C810.
+ *
+ * 09-19-2001 Andreas Heppel, Sysgo RTS GmbH <aheppel@sysgo.de>
+ *		The local version of this driver for the BAB750 board does not
+ *		use interrupts but polls the chip instead (see the call of
+ *		'handle_scsi_int()' in 'scsi_issue()'.
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_SCSI_SYM53C8XX
+
+#include <command.h>
+#include <cmd_boot.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <sym53c8xx.h>
+#include <scsi.h>
+
+#undef	SYM53C8XX_DEBUG
+
+#ifdef	SYM53C8XX_DEBUG
+#define	PRINTF(fmt,args...)	printf (fmt ,##args)
+#else
+#define PRINTF(fmt,args...)
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_SCSI) && defined(CONFIG_SCSI_SYM53C8XX)
+
+#undef SCSI_SINGLE_STEP
+/*
+ * Single Step is only used for debug purposes
+ */
+#ifdef SCSI_SINGLE_STEP
+static unsigned long start_script_select;
+static unsigned long start_script_msgout;
+static unsigned long start_script_msgin;
+static unsigned long start_script_msg_ext;
+static unsigned long start_script_cmd;
+static unsigned long start_script_data_in;
+static unsigned long start_script_data_out;
+static unsigned long start_script_status;
+static unsigned long start_script_complete;
+static unsigned long start_script_error;
+static unsigned long start_script_reselection;
+static unsigned int len_script_select;
+static unsigned int len_script_msgout;
+static unsigned int len_script_msgin;
+static unsigned int len_script_msg_ext;
+static unsigned int len_script_cmd;
+static unsigned int len_script_data_in;
+static unsigned int len_script_data_out;
+static unsigned int len_script_status;
+static unsigned int len_script_complete;
+static unsigned int len_script_error;
+static unsigned int len_script_reselection;
+#endif
+
+
+static unsigned short scsi_int_mask;		/* shadow register for SCSI related interrupts */
+static unsigned char  script_int_mask;	/* shadow register for SCRIPT related interrupts */
+static unsigned long script_select[8]; /* script for selection */
+static unsigned long script_msgout[8]; /* script for message out phase (NOT USED) */
+static unsigned long script_msgin[14]; /* script for message in phase */
+static unsigned long script_msg_ext[32]; /* script for message in phase when more than 1 byte message */
+static unsigned long script_cmd[18];    /* script for command phase */
+static unsigned long script_data_in[8]; /* script for data in phase */
+static unsigned long script_data_out[8]; /* script for data out phase */
+static unsigned long script_status[6]; /* script for status phase */
+static unsigned long script_complete[10]; /* script for complete */
+static unsigned long script_reselection[4]; /* script for reselection (NOT USED) */
+static unsigned long script_error[2]; /* script for error handling */
+
+static unsigned long int_stat[3]; /* interrupt status */
+static unsigned long scsi_mem_addr; /* base memory address =SCSI_MEM_ADDRESS; */
+
+#define bus_to_phys(a)	pci_mem_to_phys(busdevfunc, (unsigned long) (a))
+#define phys_to_bus(a)	pci_phys_to_mem(busdevfunc, (unsigned long) (a))
+
+#define SCSI_MAX_RETRY 3 /* number of retries in scsi_issue() */
+
+#define SCSI_MAX_RETRY_NOT_READY 10 /* number of retries when device is not ready */
+#define SCSI_NOT_READY_TIME_OUT 500 /* timeout per retry when not ready */
+
+/*********************************************************************************
+ * forward declerations
+ */
+
+void scsi_chip_init(void);
+void handle_scsi_int(void);
+
+
+/********************************************************************************
+ * reports SCSI errors to the user
+ */
+void scsi_print_error(ccb *pccb)
+{
+	int i;
+	printf("SCSI Error: Target %d LUN %d Command %02X\n",pccb->target, pccb->lun, pccb->cmd[0]);
+	printf("       CCB: ");
+	for(i=0;i<pccb->cmdlen;i++)
+		printf("%02X ",pccb->cmd[i]);
+	printf("(len=%d)\n",pccb->cmdlen);
+	printf("     Cntrl: ");
+	switch(pccb->contr_stat) {
+		case SIR_COMPLETE: 						printf("Complete (no Error)\n"); break;
+		case SIR_SEL_ATN_NO_MSG_OUT: 	printf("Selected with ATN no MSG out phase\n"); break;
+		case SIR_CMD_OUT_ILL_PH: 			printf("Command out illegal phase\n"); break;
+		case SIR_MSG_RECEIVED: 				printf("MSG received Error\n"); break;
+		case SIR_DATA_IN_ERR: 				printf("Data in Error\n"); break;
+		case SIR_DATA_OUT_ERR: 				printf("Data out Error\n"); break;
+		case SIR_SCRIPT_ERROR: 				printf("Script Error\n"); break;
+		case SIR_MSG_OUT_NO_CMD: 			printf("MSG out no Command phase\n"); break;
+		case SIR_MSG_OVER7: 					printf("MSG in over 7 bytes\n"); break;
+		case INT_ON_FY: 							printf("Interrupt on fly\n"); break;
+		case SCSI_SEL_TIME_OUT:				printf("SCSI Selection Timeout\n"); break;
+		case SCSI_HNS_TIME_OUT:				printf("SCSI Handshake Timeout\n"); break;
+		case SCSI_MA_TIME_OUT:				printf("SCSI Phase Error\n"); break;
+		case SCSI_UNEXP_DIS:					printf("SCSI unexpected disconnect\n"); break;
+		default:											printf("unknown status %lx\n",pccb->contr_stat); break;
+	}
+	printf("     Sense: SK %x (",pccb->sense_buf[2]&0x0f);
+	switch(pccb->sense_buf[2]&0xf) {
+		case SENSE_NO_SENSE: printf("No Sense)"); break;
+		case SENSE_RECOVERED_ERROR: printf("Recovered Error)"); break;
+		case SENSE_NOT_READY:	printf("Not Ready)"); break;
+		case SENSE_MEDIUM_ERROR: printf("Medium Error)"); break;
+		case SENSE_HARDWARE_ERROR: printf("Hardware Error)"); break;
+		case SENSE_ILLEGAL_REQUEST: printf("Illegal request)"); break;
+		case SENSE_UNIT_ATTENTION: printf("Unit Attention)"); break;
+		case SENSE_DATA_PROTECT: printf("Data Protect)"); break;
+		case SENSE_BLANK_CHECK:	printf("Blank check)"); break;
+		case SENSE_VENDOR_SPECIFIC: printf("Vendor specific)"); break;
+		case SENSE_COPY_ABORTED: printf("Copy aborted)"); break;
+		case SENSE_ABORTED_COMMAND:	printf("Aborted Command)"); break;
+		case SENSE_VOLUME_OVERFLOW:	printf("Volume overflow)"); break;
+		case SENSE_MISCOMPARE: printf("Misscompare\n"); break;
+		default: printf("Illegal Sensecode\n"); break;
+	}
+	printf(" ASC %x ASCQ %x\n",pccb->sense_buf[12],pccb->sense_buf[13]);
+	printf("    Status: ");
+	switch(pccb->status) {
+		case S_GOOD :	printf("Good\n"); break;
+		case S_CHECK_COND: printf("Check condition\n"); break;
+		case S_COND_MET: printf("Condition Met\n"); break;
+		case S_BUSY: printf("Busy\n"); break;
+		case S_INT: printf("Intermediate\n"); break;
+		case S_INT_COND_MET: printf("Intermediate condition met\n"); break;
+		case S_CONFLICT: printf("Reservation conflict\n"); break;
+		case S_TERMINATED: printf("Command terminated\n"); break;
+		case S_QUEUE_FULL: printf("Task set full\n"); break;
+		default: printf("unknown: %02X\n",pccb->status); break;
+	}
+
+}
+
+
+
+/******************************************************************************
+ * sets-up the SCSI controller
+ * the base memory address is retrived via the pci_read_config_dword
+ */
+void scsi_low_level_init(int busdevfunc)
+{
+	unsigned int cmd;
+	unsigned int addr;
+	unsigned char vec;
+
+	pci_read_config_byte(busdevfunc, PCI_INTERRUPT_LINE, &vec);
+	pci_read_config_dword(busdevfunc, PCI_BASE_ADDRESS_1, &addr);
+
+	addr = bus_to_phys(addr & ~0xf);
+
+	/*
+	 * Enable bus mastering in case this has not been done, yet.
+	 */
+	pci_read_config_dword(busdevfunc, PCI_COMMAND, &cmd);
+	cmd |= PCI_COMMAND_MASTER;
+	pci_write_config_dword(busdevfunc, PCI_COMMAND, cmd);
+
+	scsi_mem_addr = addr;
+
+	scsi_chip_init();
+	scsi_bus_reset();
+}
+
+
+/************************************************************************************
+ * Low level Part of SCSI Driver
+ */
+
+/*
+ * big-endian -> little endian conversion for the script
+ */
+unsigned long swap_script(unsigned long val)
+{
+	unsigned long tmp;
+	tmp = ((val>>24)&0xff) | ((val>>8)&0xff00) | ((val<<8)&0xff0000) | ((val<<24)&0xff000000);
+	return tmp;
+}
+
+
+void scsi_write_byte(ulong offset,unsigned char val)
+{
+	out8(scsi_mem_addr+offset,val);
+}
+
+
+unsigned char scsi_read_byte(ulong offset)
+{
+	return(in8(scsi_mem_addr+offset));
+}
+
+
+/********************************************************************************
+ * interrupt handler
+ */
+void handle_scsi_int(void)
+{
+	unsigned char stat,stat1,stat2;
+	unsigned short sstat;
+	int i;
+#ifdef SCSI_SINGLE_STEP
+	unsigned long tt;
+#endif
+	stat=scsi_read_byte(ISTAT);
+	if((stat & DIP)==DIP) { /* DMA Interrupt pending */
+		stat1=scsi_read_byte(DSTAT);
+#ifdef SCSI_SINGLE_STEP
+		if((stat1 & SSI)==SSI)
+		{
+			tt=in32r(scsi_mem_addr+DSP);
+			if(((tt)>=start_script_select) && ((tt)<start_script_select+len_script_select)) {
+				printf("select %d\n",(tt-start_script_select)>>2);
+				goto end_single;
+			}
+			if(((tt)>=start_script_msgout) && ((tt)<start_script_msgout+len_script_msgout)) {
+				printf("msgout %d\n",(tt-start_script_msgout)>>2);
+				goto end_single;
+			}
+			if(((tt)>=start_script_msgin) && ((tt)<start_script_msgin+len_script_msgin)) {
+				printf("msgin %d\n",(tt-start_script_msgin)>>2);
+				goto end_single;
+			}
+			if(((tt)>=start_script_msg_ext) && ((tt)<start_script_msg_ext+len_script_msg_ext)) {
+				printf("msgin_ext %d\n",(tt-start_script_msg_ext)>>2);
+				goto end_single;
+			}
+			if(((tt)>=start_script_cmd) && ((tt)<start_script_cmd+len_script_cmd)) {
+				printf("cmd %d\n",(tt-start_script_cmd)>>2);
+				goto end_single;
+			}
+			if(((tt)>=start_script_data_in) && ((tt)<start_script_data_in+len_script_data_in)) {
+				printf("data_in %d\n",(tt-start_script_data_in)>>2);
+				goto end_single;
+			}
+			if(((tt)>=start_script_data_out) && ((tt)<start_script_data_out+len_script_data_out)) {
+				printf("data_out %d\n",(tt-start_script_data_out)>>2);
+				goto end_single;
+			}
+			if(((tt)>=start_script_status) && ((tt)<start_script_status+len_script_status)) {
+				printf("status %d\n",(tt-start_script_status)>>2);
+				goto end_single;
+			}
+			if(((tt)>=start_script_complete) && ((tt)<start_script_complete+len_script_complete)) {
+				printf("complete %d\n",(tt-start_script_complete)>>2);
+				goto end_single;
+			}
+			if(((tt)>=start_script_error) && ((tt)<start_script_error+len_script_error)) {
+				printf("error %d\n",(tt-start_script_error)>>2);
+				goto end_single;
+			}
+			if(((tt)>=start_script_reselection) && ((tt)<start_script_reselection+len_script_reselection)) {
+				printf("reselection %d\n",(tt-start_script_reselection)>>2);
+				goto end_single;
+			}
+			printf("sc: %lx\n",tt);
+end_single:
+			stat2=scsi_read_byte(DCNTL);
+			stat2|=STD;
+			scsi_write_byte(DCNTL,stat2);
+		}
+#endif
+		if((stat1 & SIR)==SIR) /* script interrupt */
+		{
+			int_stat[0]=in32(scsi_mem_addr+DSPS);
+		}
+		if((stat1 & DFE)==0) { /* fifo not epmty */
+			scsi_write_byte(CTEST3,CLF); /* Clear DMA FIFO */
+			stat2=scsi_read_byte(STEST3);
+			scsi_write_byte(STEST3,(stat2 | CSF)); /* Clear SCSI FIFO */
+		}
+	}
+	if((stat & SIP)==SIP) {  /* scsi interrupt */
+		sstat = (unsigned short)scsi_read_byte(SIST+1);
+		sstat <<=8;
+		sstat |= (unsigned short)scsi_read_byte(SIST);
+		for(i=0;i<3;i++) {
+			if(int_stat[i]==0)
+				break; /* found an empty int status */
+		}
+		int_stat[i]=SCSI_INT_STATE | sstat;
+		stat1=scsi_read_byte(DSTAT);
+		if((stat1 & DFE)==0) { /* fifo not epmty */
+			scsi_write_byte(CTEST3,CLF); /* Clear DMA FIFO */
+			stat2=scsi_read_byte(STEST3);
+			scsi_write_byte(STEST3,(stat2 | CSF)); /* Clear SCSI FIFO */
+		}
+	}
+	if((stat & INTF)==INTF) { /* interrupt on Fly */
+		scsi_write_byte(ISTAT,stat); /* clear it */
+		for(i=0;i<3;i++) {
+			if(int_stat[i]==0)
+				break; /* found an empty int status */
+		}
+		int_stat[i]=INT_ON_FY;
+	}
+}
+
+void scsi_bus_reset(void)
+{
+	unsigned char t;
+	int i;
+	int end = CFG_SCSI_SPIN_UP_TIME*1000;
+
+	t=scsi_read_byte(SCNTL1);
+	scsi_write_byte(SCNTL1,(t | CRST));
+	udelay(50);
+	scsi_write_byte(SCNTL1,t);
+
+	puts("waiting for devices to spin up");
+	for(i=0;i<end;i++) {
+		udelay(1000); /* give the devices time to spin up */
+		if (i % 1000 == 0)
+			putc('.');
+	}
+	putc('\n');
+	scsi_chip_init(); /* reinit the chip ...*/
+
+}
+
+void scsi_int_enable(void)
+{
+	scsi_write_byte(SIEN,(unsigned char)scsi_int_mask);
+	scsi_write_byte(SIEN+1,(unsigned char)(scsi_int_mask>>8));
+	scsi_write_byte(DIEN,script_int_mask);
+}
+
+void scsi_write_dsp(unsigned long start)
+{
+	unsigned long val;
+#ifdef SCSI_SINGLE_STEP
+	unsigned char t;
+#endif
+	val = start;
+	out32r(scsi_mem_addr + DSP,start);
+#ifdef SCSI_SINGLE_STEP
+	t=scsi_read_byte(DCNTL);
+  t|=STD;
+	scsi_write_byte(DCNTL,t);
+#endif
+}
+
+/* only used for debug purposes */
+void scsi_print_script(void)
+{
+	printf("script_select @         0x%08lX\n",(unsigned long)&script_select[0]);
+	printf("script_msgout @         0x%08lX\n",(unsigned long)&script_msgout[0]);
+	printf("script_msgin @          0x%08lX\n",(unsigned long)&script_msgin[0]);
+	printf("script_msgext @         0x%08lX\n",(unsigned long)&script_msg_ext[0]);
+	printf("script_cmd @            0x%08lX\n",(unsigned long)&script_cmd[0]);
+	printf("script_data_in @        0x%08lX\n",(unsigned long)&script_data_in[0]);
+	printf("script_data_out @       0x%08lX\n",(unsigned long)&script_data_out[0]);
+	printf("script_status @         0x%08lX\n",(unsigned long)&script_status[0]);
+	printf("script_complete @       0x%08lX\n",(unsigned long)&script_complete[0]);
+	printf("script_error @          0x%08lX\n",(unsigned long)&script_error[0]);
+}
+
+
+
+void scsi_set_script(ccb *pccb)
+{
+	int busdevfunc = pccb->priv;
+	int i;
+	i=0;
+	script_select[i++]=swap_script(SCR_REG_REG(GPREG, SCR_AND, 0xfe));
+	script_select[i++]=0; /* LED ON */
+	script_select[i++]=swap_script(SCR_CLR(SCR_TRG)); /* select initiator mode */
+	script_select[i++]=0;
+	/* script_select[i++]=swap_script(SCR_SEL_ABS_ATN | pccb->target << 16); */
+	script_select[i++]=swap_script(SCR_SEL_ABS | pccb->target << 16);
+	script_select[i++]=swap_script(phys_to_bus(&script_cmd[4])); /* error handling */
+	script_select[i++]=swap_script(SCR_JUMP); /* next section */
+	/*	script_select[i++]=swap_script((unsigned long)&script_msgout[0]); */ /* message out */
+	script_select[i++]=swap_script(phys_to_bus(&script_cmd[0])); /* command out */
+
+#ifdef SCSI_SINGLE_STEP
+	start_script_select=(unsigned long)&script_select[0];
+	len_script_select=i*4;
+#endif
+
+	i=0;
+	script_msgout[i++]=swap_script(SCR_INT ^ IFFALSE (WHEN (SCR_MSG_OUT)));
+	script_msgout[i++]=SIR_SEL_ATN_NO_MSG_OUT;
+	script_msgout[i++]=swap_script(	SCR_MOVE_ABS(1) ^ SCR_MSG_OUT);
+	script_msgout[i++]=swap_script(phys_to_bus(&pccb->msgout[0]));
+	script_msgout[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_COMMAND))); /* if Command phase */
+	script_msgout[i++]=swap_script(phys_to_bus(&script_cmd[0])); /* switch to command */
+	script_msgout[i++]=swap_script(SCR_INT); /* interrupt if not */
+	script_msgout[i++]=SIR_MSG_OUT_NO_CMD;
+
+#ifdef SCSI_SINGLE_STEP
+	start_script_msgout=(unsigned long)&script_msgout[0];
+	len_script_msgout=i*4;
+#endif
+	i=0;
+	script_cmd[i++]=swap_script(SCR_MOVE_ABS(pccb->cmdlen) ^ SCR_COMMAND);
+	script_cmd[i++]=swap_script(phys_to_bus(&pccb->cmd[0]));
+	script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN))); /* message in ? */
+	script_cmd[i++]=swap_script(phys_to_bus(&script_msgin[0]));
+	script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_DATA_OUT))); /* data out ? */
+	script_cmd[i++]=swap_script(phys_to_bus(&script_data_out[0]));
+	script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_DATA_IN))); /* data in ? */
+	script_cmd[i++]=swap_script(phys_to_bus(&script_data_in[0]));
+	script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_STATUS)));  /* status ? */
+	script_cmd[i++]=swap_script(phys_to_bus(&script_status[0]));
+	script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_COMMAND)));  /* command ? */
+	script_cmd[i++]=swap_script(phys_to_bus(&script_cmd[0]));
+	script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_MSG_OUT)));  /* message out ? */
+	script_cmd[i++]=swap_script(phys_to_bus(&script_msgout[0]));
+	script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_MSG_IN))); /* just for error handling message in ? */
+	script_cmd[i++]=swap_script(phys_to_bus(&script_msgin[0]));
+	script_cmd[i++]=swap_script(SCR_INT); /* interrupt if not */
+	script_cmd[i++]=SIR_CMD_OUT_ILL_PH;
+#ifdef SCSI_SINGLE_STEP
+	start_script_cmd=(unsigned long)&script_cmd[0];
+	len_script_cmd=i*4;
+#endif
+	i=0;
+	script_data_out[i++]=swap_script(SCR_MOVE_ABS(pccb->datalen)^ SCR_DATA_OUT); /* move */
+	script_data_out[i++]=swap_script(phys_to_bus(pccb->pdata)); /* pointer to buffer */
+	script_data_out[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_STATUS)));
+	script_data_out[i++]=swap_script(phys_to_bus(&script_status[0]));
+	script_data_out[i++]=swap_script(SCR_INT);
+	script_data_out[i++]=SIR_DATA_OUT_ERR;
+
+#ifdef SCSI_SINGLE_STEP
+	start_script_data_out=(unsigned long)&script_data_out[0];
+	len_script_data_out=i*4;
+#endif
+	i=0;
+	script_data_in[i++]=swap_script(SCR_MOVE_ABS(pccb->datalen)^ SCR_DATA_IN); /* move  */
+	script_data_in[i++]=swap_script(phys_to_bus(pccb->pdata)); /* pointer to buffer */
+	script_data_in[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_STATUS)));
+	script_data_in[i++]=swap_script(phys_to_bus(&script_status[0]));
+	script_data_in[i++]=swap_script(SCR_INT);
+	script_data_in[i++]=SIR_DATA_IN_ERR;
+#ifdef SCSI_SINGLE_STEP
+	start_script_data_in=(unsigned long)&script_data_in[0];
+	len_script_data_in=i*4;
+#endif
+	i=0;
+	script_msgin[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN);
+	script_msgin[i++]=swap_script(phys_to_bus(&pccb->msgin[0]));
+	script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_COMPLETE)));
+	script_msgin[i++]=swap_script(phys_to_bus(&script_complete[0]));
+	script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_DISCONNECT)));
+	script_msgin[i++]=swap_script(phys_to_bus(&script_complete[0]));
+	script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_SAVE_DP)));
+	script_msgin[i++]=swap_script(phys_to_bus(&script_complete[0]));
+	script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_RESTORE_DP)));
+	script_msgin[i++]=swap_script(phys_to_bus(&script_complete[0]));
+	script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_EXTENDED)));
+	script_msgin[i++]=swap_script(phys_to_bus(&script_msg_ext[0]));
+	script_msgin[i++]=swap_script(SCR_INT);
+	script_msgin[i++]=SIR_MSG_RECEIVED;
+#ifdef SCSI_SINGLE_STEP
+	start_script_msgin=(unsigned long)&script_msgin[0];
+	len_script_msgin=i*4;
+#endif
+	i=0;
+	script_msg_ext[i++]=swap_script(SCR_CLR (SCR_ACK)); /* clear ACK */
+	script_msg_ext[i++]=0;
+	script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* assuming this is the msg length */
+	script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[1]));
+	script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN)));
+	script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */
+	script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */
+	script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[2]));
+	script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN)));
+	script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */
+	script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */
+	script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[3]));
+	script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN)));
+	script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */
+	script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */
+	script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[4]));
+	script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN)));
+	script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */
+	script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */
+	script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[5]));
+	script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN)));
+	script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */
+	script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */
+	script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[6]));
+	script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN)));
+	script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */
+	script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */
+	script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[7]));
+	script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN)));
+	script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */
+	script_msg_ext[i++]=swap_script(SCR_INT);
+	script_msg_ext[i++]=SIR_MSG_OVER7;
+#ifdef SCSI_SINGLE_STEP
+	start_script_msg_ext=(unsigned long)&script_msg_ext[0];
+	len_script_msg_ext=i*4;
+#endif
+	i=0;
+	script_status[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_STATUS);
+	script_status[i++]=swap_script(phys_to_bus(&pccb->status));
+	script_status[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)));
+	script_status[i++]=swap_script(phys_to_bus(&script_msgin[0]));
+	script_status[i++]=swap_script(SCR_INT);
+	script_status[i++]=SIR_STATUS_ILL_PH;
+#ifdef SCSI_SINGLE_STEP
+	start_script_status=(unsigned long)&script_status[0];
+	len_script_status=i*4;
+#endif
+	i=0;
+	script_complete[i++]=swap_script(SCR_REG_REG (SCNTL2, SCR_AND, 0x7f));
+	script_complete[i++]=0;
+	script_complete[i++]=swap_script(SCR_CLR (SCR_ACK|SCR_ATN));
+	script_complete[i++]=0;
+	script_complete[i++]=swap_script(SCR_WAIT_DISC);
+	script_complete[i++]=0;
+	script_complete[i++]=swap_script(SCR_REG_REG(GPREG, SCR_OR, 0x01));
+	script_complete[i++]=0; /* LED OFF */
+	script_complete[i++]=swap_script(SCR_INT);
+	script_complete[i++]=SIR_COMPLETE;
+#ifdef SCSI_SINGLE_STEP
+	start_script_complete=(unsigned long)&script_complete[0];
+	len_script_complete=i*4;
+#endif
+	i=0;
+	script_error[i++]=swap_script(SCR_INT); /* interrupt if error */
+	script_error[i++]=SIR_SCRIPT_ERROR;
+#ifdef SCSI_SINGLE_STEP
+	start_script_error=(unsigned long)&script_error[0];
+	len_script_error=i*4;
+#endif
+	i=0;
+	script_reselection[i++]=swap_script(SCR_CLR (SCR_TRG)); /* target status */
+	script_reselection[i++]=0;
+	script_reselection[i++]=swap_script(SCR_WAIT_RESEL);
+	script_reselection[i++]=swap_script(phys_to_bus(&script_select[0])); /* len = 4 */
+#ifdef SCSI_SINGLE_STEP
+	start_script_reselection=(unsigned long)&script_reselection[0];
+	len_script_reselection=i*4;
+#endif
+}
+
+
+
+void scsi_issue(ccb *pccb)
+{
+	int busdevfunc = pccb->priv;
+	int i;
+	unsigned short sstat;
+ 	int retrycnt;  /* retry counter */
+	for(i=0;i<3;i++)
+		int_stat[i]=0; /* delete all int status */
+	/* struct pccb must be set-up correctly */
+	retrycnt=0;
+	PRINTF("ID %d issue cmd %02X\n",pccb->target,pccb->cmd[0]);
+	pccb->trans_bytes=0; /* no bytes transfered yet */
+	scsi_set_script(pccb); /* fill in SCRIPT		*/
+	scsi_int_mask=STO | UDC | MA; /* | CMP; / * Interrupts which are enabled */
+	script_int_mask=0xff; /* enable all Ints */
+	scsi_int_enable();
+	scsi_write_dsp(phys_to_bus(&script_select[0])); /* start script */
+	/* now we have to wait for IRQs */
+retry:
+	/*
+	 * This version of the driver is _not_ interrupt driven,
+	 * but polls the chip's interrupt registers (ISTAT, DSTAT).
+	 */
+	while(int_stat[0]==0)
+		handle_scsi_int();
+
+	if(int_stat[0]==SIR_COMPLETE) {
+		if(pccb->msgin[0]==M_DISCONNECT) {
+			PRINTF("Wait for reselection\n");
+			for(i=0;i<3;i++)
+				int_stat[i]=0; /* delete all int status */
+			scsi_write_dsp(phys_to_bus(&script_reselection[0])); /* start reselection script */
+			goto retry;
+		}
+		pccb->contr_stat=SIR_COMPLETE;
+		return;
+	}
+	if((int_stat[0] & SCSI_INT_STATE)==SCSI_INT_STATE) { /* scsi interrupt */
+		sstat=(unsigned short)int_stat[0];
+		if((sstat & STO)==STO) { /* selection timeout */
+			pccb->contr_stat=SCSI_SEL_TIME_OUT;
+			scsi_write_byte(GPREG,0x01);
+			PRINTF("ID: %X Selection Timeout\n",pccb->target);
+			return;
+		}
+		if((sstat & UDC)==UDC) { /* unexpected disconnect */
+			pccb->contr_stat=SCSI_UNEXP_DIS;
+			scsi_write_byte(GPREG,0x01);
+			PRINTF("ID: %X Unexpected Disconnect\n",pccb->target);
+			return;
+		}
+		if((sstat & RSL)==RSL) { /* reselection */
+			pccb->contr_stat=SCSI_UNEXP_DIS;
+			scsi_write_byte(GPREG,0x01);
+			PRINTF("ID: %X Unexpected Disconnect\n",pccb->target);
+			return;
+		}
+		if(((sstat & MA)==MA)||((sstat & HTH)==HTH)) { /* phase missmatch */
+			if(retrycnt<SCSI_MAX_RETRY) {
+				pccb->trans_bytes=pccb->datalen -
+					((unsigned long)scsi_read_byte(DBC) |
+					((unsigned long)scsi_read_byte(DBC+1)<<8) |
+					((unsigned long)scsi_read_byte(DBC+2)<<16));
+				for(i=0;i<3;i++)
+					int_stat[i]=0; /* delete all int status */
+				retrycnt++;
+				PRINTF("ID: %X Phase Missmatch Retry %d Phase %02X transfered %lx\n",
+						pccb->target,retrycnt,scsi_read_byte(SBCL),pccb->trans_bytes);
+				scsi_write_dsp(phys_to_bus(&script_cmd[4])); /* start retry script */
+				goto retry;
+			}
+			if((sstat & MA)==MA)
+				pccb->contr_stat=SCSI_MA_TIME_OUT;
+			else
+				pccb->contr_stat=SCSI_HNS_TIME_OUT;
+			PRINTF("Phase Missmatch stat %lx\n",pccb->contr_stat);
+			return;
+		} /* no phase int */
+/*		if((sstat & CMP)==CMP) {
+			pccb->contr_stat=SIR_COMPLETE;
+			return;
+		}
+*/
+		PRINTF("SCSI INT %lX\n",int_stat[0]);
+		pccb->contr_stat=int_stat[0];
+		return;
+	} /* end scsi int */
+	PRINTF("SCRIPT INT %lX phase %02X\n",int_stat[0],scsi_read_byte(SBCL));
+	pccb->contr_stat=int_stat[0];
+	return;
+}
+
+int scsi_exec(ccb *pccb)
+{
+	unsigned char tmpcmd[16],tmpstat;
+	int i,retrycnt,t;
+	unsigned long transbytes,datalen;
+	unsigned char *tmpptr;
+	retrycnt=0;
+retry:
+	scsi_issue(pccb);
+	if(pccb->contr_stat!=SIR_COMPLETE)
+		return FALSE;
+	if(pccb->status==S_GOOD)
+		return TRUE;
+	if(pccb->status==S_CHECK_COND) { /* check condition */
+		for(i=0;i<16;i++)
+			tmpcmd[i]=pccb->cmd[i];
+		pccb->cmd[0]=SCSI_REQ_SENSE;
+		pccb->cmd[1]=pccb->lun<<5;
+		pccb->cmd[2]=0;
+		pccb->cmd[3]=0;
+		pccb->cmd[4]=14;
+		pccb->cmd[5]=0;
+		pccb->cmdlen=6;
+		pccb->msgout[0]=SCSI_IDENTIFY;
+		transbytes=pccb->trans_bytes;
+		tmpptr=pccb->pdata;
+		pccb->pdata=&pccb->sense_buf[0];
+		datalen=pccb->datalen;
+		pccb->datalen=14;
+		tmpstat=pccb->status;
+		scsi_issue(pccb);
+		for(i=0;i<16;i++)
+			pccb->cmd[i]=tmpcmd[i];
+		pccb->trans_bytes=transbytes;
+		pccb->pdata=tmpptr;
+		pccb->datalen=datalen;
+		pccb->status=tmpstat;
+		PRINTF("Request_sense sense key %x ASC %x ASCQ %x\n",pccb->sense_buf[2]&0x0f,
+			pccb->sense_buf[12],pccb->sense_buf[13]);
+		switch(pccb->sense_buf[2]&0xf) {
+			case SENSE_NO_SENSE:
+			case SENSE_RECOVERED_ERROR:
+				/* seems to be ok */
+				return TRUE;
+				break;
+			case SENSE_NOT_READY:
+				if((pccb->sense_buf[12]!=0x04)||(pccb->sense_buf[13]!=0x01)) {
+					/* if device is not in process of becoming ready */
+					return FALSE;
+					break;
+				} /* else fall through */
+			case SENSE_UNIT_ATTENTION:
+				if(retrycnt<SCSI_MAX_RETRY_NOT_READY) {
+					PRINTF("Target %d not ready, retry %d\n",pccb->target,retrycnt);
+					for(t=0;t<SCSI_NOT_READY_TIME_OUT;t++)
+						udelay(1000); /* 1sec wait */
+					retrycnt++;
+					goto retry;
+				}
+				PRINTF("Target %d not ready, %d retried\n",pccb->target,retrycnt);
+				return FALSE;
+			default:
+				return FALSE;
+		}
+	}
+	PRINTF("Status = %X\n",pccb->status);
+	return FALSE;
+}
+
+
+
+
+void scsi_chip_init(void)
+{
+	/* first we issue a soft reset */
+	scsi_write_byte(ISTAT,SRST);
+	udelay(1000);
+	scsi_write_byte(ISTAT,0);
+	/* setup chip */
+	scsi_write_byte(SCNTL0,0xC0); /* full arbitration no start, no message, parity disabled, master */
+	scsi_write_byte(SCNTL1,0x00);
+	scsi_write_byte(SCNTL2,0x00);
+#ifndef CFG_SCSI_SYM53C8XX_CCF    /* config value for none 40 mhz clocks */
+	scsi_write_byte(SCNTL3,0x13); /* synchronous clock 40/4=10MHz, asynchronous 40MHz */
+#else
+	scsi_write_byte(SCNTL3,CFG_SCSI_SYM53C8XX_CCF); /* config value for none 40 mhz clocks */
+#endif
+	scsi_write_byte(SCID,0x47); /* ID=7, enable reselection */
+	scsi_write_byte(SXFER,0x00); /* synchronous transfer period 10MHz, asynchronous */
+	scsi_write_byte(SDID,0x00);  /* targed SCSI ID = 0 */
+	scsi_int_mask=0x0000; /* no Interrupt is enabled */
+	script_int_mask=0x00;
+	scsi_int_enable();
+	scsi_write_byte(GPREG,0x01); /* GPIO0 is LED (off) */
+	scsi_write_byte(GPCNTL,0x0E); /* GPIO0 is Output */
+	scsi_write_byte(STIME0,0x08); /* handshake timer disabled, selection timeout 512msec */
+	scsi_write_byte(RESPID,0x80); /* repond only to the own ID (reselection) */
+	scsi_write_byte(STEST1,0x00); /* not isolated, SCLK is used */
+	scsi_write_byte(STEST2,0x00); /* no Lowlevel Mode? */
+	scsi_write_byte(STEST3,0x80); /* enable tolerANT */
+	scsi_write_byte(CTEST3,0x04); /* clear FIFO */
+	scsi_write_byte(CTEST4,0x00);
+	scsi_write_byte(CTEST5,0x00);
+#ifdef SCSI_SINGLE_STEP
+/*	scsi_write_byte(DCNTL,IRQM | SSM);	*/
+	scsi_write_byte(DCNTL,IRQD | SSM);
+	scsi_write_byte(DMODE,MAN);
+#else
+/*	scsi_write_byte(DCNTL,IRQM);	*/
+	scsi_write_byte(DCNTL,IRQD);
+	scsi_write_byte(DMODE,0x00);
+#endif
+}
+#endif /* (CONFIG_COMMANDS & CFG_CMD_SCSI) */
+
+
+#endif /* CONFIG_SCSI_SYM53C8XX */
diff --git a/drivers/w83c553f.c b/drivers/w83c553f.c
new file mode 100644
index 0000000..5d82ed4
--- /dev/null
+++ b/drivers/w83c553f.c
@@ -0,0 +1,226 @@
+/*
+ * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Andreas Heppel <aheppel@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Initialisation of the PCI-to-ISA bridge and disabling the BIOS
+ * write protection (for flash) in function 0 of the chip.
+ * Enabling function 1 (IDE controller of the chip.
+ */
+
+#include <common.h>
+#include <config.h>
+
+#ifdef CFG_WINBOND_83C553
+
+#include <asm/io.h>
+#include <pci.h>
+
+#include <w83c553f.h>
+
+#define out8(addr,val)	do { \
+			out_8((u8*) (addr),(val)); udelay(1); \
+			} while (0)
+#define out16(addr,val)	do { \
+			out_be16((u16*) (addr),(val)); udelay(1); \
+			} while (0)
+
+extern uint ide_bus_offset[CFG_IDE_MAXBUS];
+
+void initialise_pic(void);
+void initialise_dma(void);
+
+void initialise_w83c553f(void)
+{
+	pci_dev_t devbusfn;
+	unsigned char reg8;
+	unsigned short reg16;
+	unsigned int reg32;
+
+	devbusfn = pci_find_device(W83C553F_VID, W83C553F_DID, 0);
+	if (devbusfn == -1)
+	{
+		printf("Error: Cannot find W83C553F controller on any PCI bus.");
+		return;
+	}
+
+	pci_read_config_word(devbusfn, PCI_COMMAND, &reg16);
+	reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
+	pci_write_config_word(devbusfn, PCI_COMMAND, reg16);
+
+	pci_read_config_byte(devbusfn, WINBOND_IPADCR, &reg8);
+	/* 16 MB ISA memory space */
+	reg8 |= (IPADCR_IPATOM4 | IPADCR_IPATOM5 | IPADCR_IPATOM6 | IPADCR_IPATOM7);
+	reg8 &= ~IPADCR_MBE512;
+	pci_write_config_byte(devbusfn, WINBOND_IPADCR, reg8);
+
+	pci_read_config_byte(devbusfn, WINBOND_CSCR, &reg8);
+	/* switch off BIOS write protection */
+	reg8 |= CSCR_UBIOSCSE;
+	reg8 &= ~CSCR_BIOSWP;
+	pci_write_config_byte(devbusfn, WINBOND_CSCR, reg8);
+
+	/*
+	 * Interrupt routing:
+	 *  - IDE  -> IRQ 9/0
+	 *  - INTA -> IRQ 10
+	 *  - INTB -> IRQ 11
+	 *  - INTC -> IRQ 14
+	 *  - INTD -> IRQ 15
+	 */
+	pci_write_config_byte(devbusfn, WINBOND_IDEIRCR, 0x90);
+	pci_write_config_word(devbusfn, WINBOND_PCIIRCR, 0xABEF);
+
+	/*
+	 * Read IDE bus offsets from function 1 device.
+	 * We must unmask the LSB indicating that ist is an IO address.
+	 */
+	devbusfn |= PCI_BDF(0,0,1);
+
+	/*
+	 * Switch off legacy IRQ for IDE and IDE port 1.
+	 */
+	pci_write_config_byte(devbusfn, 0x09, 0x8F);
+
+	pci_read_config_dword(devbusfn, WINDOND_IDECSR, &reg32);
+	reg32 &= ~(IDECSR_LEGIRQ | IDECSR_P1EN | IDECSR_P1F16);
+	pci_write_config_dword(devbusfn, WINDOND_IDECSR, reg32);
+
+	pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &ide_bus_offset[0]);
+	ide_bus_offset[0] &= ~1;
+#if CFG_IDE_MAXBUS > 1
+	pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_2, &ide_bus_offset[1]);
+	ide_bus_offset[1] &= ~1;
+#endif
+
+	/*
+	 * Enable function 1, IDE -> busmastering and IO space access
+	 */
+	pci_read_config_word(devbusfn, PCI_COMMAND, &reg16);
+	reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO;
+	pci_write_config_word(devbusfn, PCI_COMMAND, reg16);
+
+	/*
+	 * Initialise ISA interrupt controller
+	 */
+	initialise_pic();
+
+	/*
+	 * Initialise DMA controller
+	 */
+	initialise_dma();
+}
+
+void initialise_pic(void)
+{
+	out8(W83C553F_PIC1_ICW1, 0x11);
+	out8(W83C553F_PIC1_ICW2, 0x08);
+	out8(W83C553F_PIC1_ICW3, 0x04);
+	out8(W83C553F_PIC1_ICW4, 0x01);
+	out8(W83C553F_PIC1_OCW1, 0xfb);
+	out8(W83C553F_PIC1_ELC, 0x20);
+
+	out8(W83C553F_PIC2_ICW1, 0x11);
+	out8(W83C553F_PIC2_ICW2, 0x08);
+	out8(W83C553F_PIC2_ICW3, 0x02);
+	out8(W83C553F_PIC2_ICW4, 0x01);
+	out8(W83C553F_PIC2_OCW1, 0xff);
+	out8(W83C553F_PIC2_ELC, 0xce);
+
+	out8(W83C553F_TMR1_CMOD, 0x74);
+
+	out8(W83C553F_PIC2_OCW1, 0x20);
+	out8(W83C553F_PIC1_OCW1, 0x20);
+
+	out8(W83C553F_PIC2_OCW1, 0x2b);
+	out8(W83C553F_PIC1_OCW1, 0x2b);
+}
+
+void initialise_dma(void)
+{
+	unsigned int channel;
+	unsigned int rvalue1, rvalue2;
+
+	/* perform a H/W reset of the devices */
+
+	out8(W83C553F_DMA1 + W83C553F_DMA1_MC, 0x00);
+	out16(W83C553F_DMA2 + W83C553F_DMA2_MC, 0x0000);
+
+	/* initialise all channels to a sane state */
+
+	for (channel = 0; channel < 4; channel++) {
+		/*
+		 * dependent upon the channel, setup the specifics:
+		 *
+		 * demand
+		 * address-increment
+		 * autoinitialize-disable
+		 * verify-transfer
+		 */
+
+		switch (channel) {
+		case 0:
+			rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH0SEL|W83C553F_MODE_TT_VERIFY);
+			rvalue2 = (W83C553F_MODE_TM_CASCADE|W83C553F_MODE_CH0SEL);
+			break;
+	    	case 1:
+			rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH1SEL|W83C553F_MODE_TT_VERIFY);
+			rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH1SEL|W83C553F_MODE_TT_VERIFY);
+			break;
+		case 2:
+			rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH2SEL|W83C553F_MODE_TT_VERIFY);
+			rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH2SEL|W83C553F_MODE_TT_VERIFY);
+			break;
+		case 3:
+			rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH3SEL|W83C553F_MODE_TT_VERIFY);
+			rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH3SEL|W83C553F_MODE_TT_VERIFY);
+			break;
+		default:
+			rvalue1 = 0x00;
+			rvalue2 = 0x00;
+			break;
+		}
+
+		/* write to write mode registers */
+
+		out8(W83C553F_DMA1 + W83C553F_DMA1_WM, rvalue1 & 0xFF);
+		out16(W83C553F_DMA2 + W83C553F_DMA2_WM, rvalue2 & 0x00FF);
+	}
+
+	/* enable all channels */
+
+	out8(W83C553F_DMA1 + W83C553F_DMA1_CM, 0x00);
+	out16(W83C553F_DMA2 + W83C553F_DMA2_CM, 0x0000);
+	/*
+	 * initialize the global DMA configuration
+	 *
+	 * DACK# active low
+	 * DREQ active high
+	 * fixed priority
+	 * channel group enable
+	 */
+
+	out8(W83C553F_DMA1 + W83C553F_DMA1_CS, 0x00);
+	out16(W83C553F_DMA2 + W83C553F_DMA2_CS, 0x0000);
+}
+
+#endif /* CFG_WINBOND_83C553 */