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| author | Hans de Goede <hdegoede@redhat.com> | 2015-01-25 15:33:07 +0100 |
|---|---|---|
| committer | Hans de Goede <hdegoede@redhat.com> | 2015-02-02 13:57:16 +0100 |
| commit | fb75d972eaf5c887ada28e73d3e84d52931d4cb0 (patch) | |
| tree | 1bd562e1ddadc7242ca3027a898c0f7461bd6501 /drivers/video | |
| parent | 8d0df9be927eff1be9aef29aa995f6b54900962e (diff) | |
| download | u-boot-imx-fb75d972eaf5c887ada28e73d3e84d52931d4cb0.zip u-boot-imx-fb75d972eaf5c887ada28e73d3e84d52931d4cb0.tar.gz u-boot-imx-fb75d972eaf5c887ada28e73d3e84d52931d4cb0.tar.bz2 | |
sunxi: video: Force h/vsync active high when using ext. vga dac on some boards
On both my A13-OLinuxIno and my A13-OLinuxIno-Micro, the vga output gives an
unstable image when active low v or hsync is used.
The problem seems to be specific to the OLinuxIno A13 (normal & micro)
boards. I've just looked up the schematics and they use an opendrain driver
for the vga sync lines, and with sync pulses it is the logical high->low
edge of the pulse which counts for the timing, which with an active low
sync is being driven by the pull-up, and that simply seems to not drive
it hard enough to get a stable image.
So force v and hsync active high on these boards. independent of what the
modeline says. This fixes the unstable image.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Diffstat (limited to 'drivers/video')
| -rw-r--r-- | drivers/video/sunxi_display.c | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/drivers/video/sunxi_display.c b/drivers/video/sunxi_display.c index af728b5..f5f24fc 100644 --- a/drivers/video/sunxi_display.c +++ b/drivers/video/sunxi_display.c @@ -645,7 +645,8 @@ static int sunxi_lcdc_get_clk_delay(const struct ctfb_res_modes *mode) return (delay > 30) ? 30 : delay; } -static void sunxi_lcdc_tcon0_mode_set(const struct ctfb_res_modes *mode) +static void sunxi_lcdc_tcon0_mode_set(const struct ctfb_res_modes *mode, + bool for_ext_vga_dac) { struct sunxi_lcdc_reg * const lcdc = (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE; @@ -719,6 +720,11 @@ static void sunxi_lcdc_tcon0_mode_set(const struct ctfb_res_modes *mode) val |= SUNXI_LCDC_TCON_HSYNC_MASK; if (!(mode->sync & FB_SYNC_VERT_HIGH_ACT)) val |= SUNXI_LCDC_TCON_VSYNC_MASK; + +#ifdef CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH + if (for_ext_vga_dac) + val = 0; +#endif writel(val, &lcdc->tcon0_io_polarity); writel(0, &lcdc->tcon0_io_tristate); @@ -1015,7 +1021,7 @@ static void sunxi_mode_set(const struct ctfb_res_modes *mode, hitachi_tx18d42vm_init(); } sunxi_composer_mode_set(mode, address); - sunxi_lcdc_tcon0_mode_set(mode); + sunxi_lcdc_tcon0_mode_set(mode, false); sunxi_composer_enable(); sunxi_lcdc_enable(); #ifdef CONFIG_VIDEO_LCD_SSD2828 @@ -1033,7 +1039,7 @@ static void sunxi_mode_set(const struct ctfb_res_modes *mode, sunxi_vga_enable(); #elif defined CONFIG_VIDEO_VGA_VIA_LCD sunxi_composer_mode_set(mode, address); - sunxi_lcdc_tcon0_mode_set(mode); + sunxi_lcdc_tcon0_mode_set(mode, true); sunxi_composer_enable(); sunxi_lcdc_enable(); sunxi_vga_external_dac_enable(); |