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authorSiarhei Siamashka <siarhei.siamashka@gmail.com>2015-01-19 05:23:35 +0200
committerHans de Goede <hdegoede@redhat.com>2015-01-22 12:34:56 +0100
commitdddccd6913142e0ba63ce6e529c38651c2ab0197 (patch)
treee1819e3251f887c0e2724be99b82f75512706ece /drivers/video/ssd2828.h
parentaaa6ac5eab8df95a3b9646194d90f49e79476258 (diff)
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video: ssd2828: Allow using 'pclk' as the PLL clock source
Instead of using the internal 'tx_clk' clock source, it is also possible to use the pixel clock signal from the parallel LCD interface ('pclk') as the reference clock for PLL. The 'tx_clk' clock speed may be different on different boards/devices (the allowed range is 8MHz - 30MHz). Which is not very convenient, especially considering the need to know the exact 'tx_clk' clock speed. This clock speed may be difficult to identify without having device schematics and/or accurate documentation/sources every time. Using 'pclk' is free from all these problems. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Anatolij Gustschin <agust@denx.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Diffstat (limited to 'drivers/video/ssd2828.h')
-rw-r--r--drivers/video/ssd2828.h11
1 files changed, 8 insertions, 3 deletions
diff --git a/drivers/video/ssd2828.h b/drivers/video/ssd2828.h
index 14b96c5..1af6fa4 100644
--- a/drivers/video/ssd2828.h
+++ b/drivers/video/ssd2828.h
@@ -47,8 +47,12 @@ struct ssd2828_config {
* to TX_CLK_XIO/TX_CLK_XIN pins), which is necessary at least for
* clocking SPI after reset. The exact clock speed is not strictly,
* defined, but the datasheet says that it must be somewhere in the
- * 8MHz - 30MHz range (see "TX_CLK Timing" section). It is used as
- * a reference clock for PLL and must be set correctly.
+ * 8MHz - 30MHz range (see "TX_CLK Timing" section). It can be also
+ * used as a reference clock for PLL. If the exact clock frequency
+ * is known, then it can be specified here. If it is unknown, or the
+ * information is not trustworthy, then it can be set to 0.
+ *
+ * If unsure, set to 0.
*/
int ssd2828_tx_clk_khz;
@@ -115,7 +119,8 @@ struct ssd2828_config {
* The right place to insert this function call is after the parallel LCD
* interface is initialized and before turning on the backlight. This is
* advised in the "Example for system sleep in and out" section of the
- * SSD2828 datasheet.
+ * SSD2828 datasheet. And also SS2828 may use 'pclk' as the clock source
+ * for PLL, which means that the input signal must be already there.
*/
int ssd2828_init(const struct ssd2828_config *cfg,
const struct ctfb_res_modes *mode);