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authorFabio Estevam <fabio.estevam@freescale.com>2012-05-15 08:01:16 +0000
committerAnatolij Gustschin <agust@denx.de>2012-05-25 10:36:29 +0200
commitfff6ef72b33050344362ca441cdb6b5f9b4fb8b0 (patch)
treefdea1001ff59d86ec2cbb020a2feda4b195156a4 /drivers/video/ipu_regs.h
parentf1adefd2393f0322c1c1db8e813e65d95c752cd0 (diff)
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mx53: Allow IPUv3 driver to also work on mx53
Adjust the IPU base registers so that ipuv3 driver can work on both mx51 and mx53 SoCs. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Diffstat (limited to 'drivers/video/ipu_regs.h')
-rw-r--r--drivers/video/ipu_regs.h42
1 files changed, 21 insertions, 21 deletions
diff --git a/drivers/video/ipu_regs.h b/drivers/video/ipu_regs.h
index 9964c20..93b195f 100644
--- a/drivers/video/ipu_regs.h
+++ b/drivers/video/ipu_regs.h
@@ -33,27 +33,27 @@
#define IPU_DISP0_BASE 0x00000000
#define IPU_MCU_T_DEFAULT 8
#define IPU_DISP1_BASE (IPU_MCU_T_DEFAULT << 25)
-#define IPU_CM_REG_BASE 0x1E000000
-#define IPU_STAT_REG_BASE 0x1E000200
-#define IPU_IDMAC_REG_BASE 0x1E008000
-#define IPU_ISP_REG_BASE 0x1E010000
-#define IPU_DP_REG_BASE 0x1E018000
-#define IPU_IC_REG_BASE 0x1E020000
-#define IPU_IRT_REG_BASE 0x1E028000
-#define IPU_CSI0_REG_BASE 0x1E030000
-#define IPU_CSI1_REG_BASE 0x1E038000
-#define IPU_DI0_REG_BASE 0x1E040000
-#define IPU_DI1_REG_BASE 0x1E048000
-#define IPU_SMFC_REG_BASE 0x1E050000
-#define IPU_DC_REG_BASE 0x1E058000
-#define IPU_DMFC_REG_BASE 0x1E060000
-#define IPU_CPMEM_REG_BASE 0x1F000000
-#define IPU_LUT_REG_BASE 0x1F020000
-#define IPU_SRM_REG_BASE 0x1F040000
-#define IPU_TPM_REG_BASE 0x1F060000
-#define IPU_DC_TMPL_REG_BASE 0x1F080000
-#define IPU_ISP_TBPR_REG_BASE 0x1F0C0000
-#define IPU_VDI_REG_BASE 0x1E068000
+#define IPU_CM_REG_BASE 0x00000000
+#define IPU_STAT_REG_BASE 0x00000200
+#define IPU_IDMAC_REG_BASE 0x00008000
+#define IPU_ISP_REG_BASE 0x00010000
+#define IPU_DP_REG_BASE 0x00018000
+#define IPU_IC_REG_BASE 0x00020000
+#define IPU_IRT_REG_BASE 0x00028000
+#define IPU_CSI0_REG_BASE 0x00030000
+#define IPU_CSI1_REG_BASE 0x00038000
+#define IPU_DI0_REG_BASE 0x00040000
+#define IPU_DI1_REG_BASE 0x00048000
+#define IPU_SMFC_REG_BASE 0x00050000
+#define IPU_DC_REG_BASE 0x00058000
+#define IPU_DMFC_REG_BASE 0x00060000
+#define IPU_CPMEM_REG_BASE 0x01000000
+#define IPU_LUT_REG_BASE 0x01020000
+#define IPU_SRM_REG_BASE 0x01040000
+#define IPU_TPM_REG_BASE 0x01060000
+#define IPU_DC_TMPL_REG_BASE 0x01080000
+#define IPU_ISP_TBPR_REG_BASE 0x010C0000
+#define IPU_VDI_REG_BASE 0x00680000
extern u32 *ipu_dc_tmpl_reg;