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| author | Liu Ying <b17645@freescale.com> | 2010-12-10 16:03:10 +0800 |
|---|---|---|
| committer | Liu Ying <b17645@freescale.com> | 2010-12-16 09:58:44 +0800 |
| commit | 00bcc7e6fb772a0d195c997287c6795ed0c58fb4 (patch) | |
| tree | c521ddcbf279634d88e102eb858b512f2267f6a6 /drivers/video/ipu_disp.c | |
| parent | dca35697e3758ac81894ca305c3f206ff552b697 (diff) | |
| download | u-boot-imx-00bcc7e6fb772a0d195c997287c6795ed0c58fb4.zip u-boot-imx-00bcc7e6fb772a0d195c997287c6795ed0c58fb4.tar.gz u-boot-imx-00bcc7e6fb772a0d195c997287c6795ed0c58fb4.tar.bz2 | |
ENGR00134068 MX51 BBG:Support CLAA WVGA splashimage
1) IOMUX/backlight support for CLAA WVGA LCD panel.
2) Add video mode for CLAA WVGA LCD panel.
3) Support IPU di1 interface for framebuffer.
4) Enhance IPU driver.
5) Add freescale 600x400 8BPP BMP logo.
Signed-off-by: Terry Lv <R65388@freescale.com>
Signed-off-by: Liu Ying <b17645@freescale.com>
Diffstat (limited to 'drivers/video/ipu_disp.c')
| -rw-r--r-- | drivers/video/ipu_disp.c | 26 |
1 files changed, 24 insertions, 2 deletions
diff --git a/drivers/video/ipu_disp.c b/drivers/video/ipu_disp.c index ad03a01..8ea12f8 100644 --- a/drivers/video/ipu_disp.c +++ b/drivers/video/ipu_disp.c @@ -913,6 +913,9 @@ int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk, /* Init clocking */ debug("pixel clk = %d\n", pixel_clk); + /* clear DI */ + __raw_writel((1 << 21), DI_GENERAL(disp)); + if (sig.ext_clk) { if (!(g_di1_tvout && (disp == 1))) { /*not round div for tvout*/ /* @@ -951,6 +954,14 @@ int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk, div = clk_get_rate(clk_get_parent(g_pixel_clk[disp])) / rounded_pixel_clk; + /* Enable for a divide by 2 clock change. */ + reg = __raw_readl(IPU_PM); + reg &= ~(0x7f << 7); + reg |= 0x20 << 7; + reg &= ~(0x7f << 23); + reg |= 0x20 << 23; + __raw_writel(reg, IPU_PM); + ipu_di_data_wave_config(disp, SYNC_WAVE, div - 1, div - 1); ipu_di_data_pin_config(disp, SYNC_WAVE, DI_PIN15, 3, 0, div * 2); @@ -1175,6 +1186,11 @@ int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk, __raw_writel(0, DI_STP_REP(disp, 7)); __raw_writel(0, DI_STP_REP(disp, 9)); + h_total = ((width + h_start_width + h_sync_width) / 2) - 2; + ipu_di_sync_config(disp, 6, 1, 0, 2, DI_SYNC_CLK, h_total, + DI_SYNC_INT_HSYNC, 0, DI_SYNC_NONE, + DI_SYNC_NONE, 0, 0); + /* Init template microcode */ if (disp) { ipu_dc_write_tmpl(2, WROD(0), 0, map, SYNC_WAVE, 8, 5); @@ -1194,12 +1210,18 @@ int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk, if (sig.clk_pol) di_gen |= DI_GEN_POL_CLK; + /* Set the clock to stop at counter 6. */ + di_gen |= 0x6000000; } __raw_writel(di_gen, DI_GENERAL(disp)); - __raw_writel((--vsync_cnt << DI_VSYNC_SEL_OFFSET) | - 0x00000002, DI_SYNC_AS_GEN(disp)); + if (sig.interlaced) + __raw_writel((--vsync_cnt << DI_VSYNC_SEL_OFFSET) | + 0x00000002, DI_SYNC_AS_GEN(disp)); + else + __raw_writel((--vsync_cnt << DI_VSYNC_SEL_OFFSET), + DI_SYNC_AS_GEN(disp)); reg = __raw_readl(DI_POL(disp)); reg &= ~(DI_POL_DRDY_DATA_POLARITY | DI_POL_DRDY_POLARITY_15); |