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author | Tom Rini <trini@konsulko.com> | 2015-08-19 18:04:48 -0400 |
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committer | Tom Rini <trini@konsulko.com> | 2015-08-19 18:04:48 -0400 |
commit | a5d338b2f24d8e193bfa2b6ee33eb39cff0b4adf (patch) | |
tree | d76b05507789305b36c78f478acde37fde1cd994 /drivers/usb/host/ehci-mx6.c | |
parent | d1221462fece27ad163dcd0c181a456c73fe2011 (diff) | |
parent | 7a1386f96bca550240670fa3461d3a0dc060aa01 (diff) | |
download | u-boot-imx-a5d338b2f24d8e193bfa2b6ee33eb39cff0b4adf.zip u-boot-imx-a5d338b2f24d8e193bfa2b6ee33eb39cff0b4adf.tar.gz u-boot-imx-a5d338b2f24d8e193bfa2b6ee33eb39cff0b4adf.tar.bz2 |
Merge git://git.denx.de/u-boot-usb
Diffstat (limited to 'drivers/usb/host/ehci-mx6.c')
-rw-r--r-- | drivers/usb/host/ehci-mx6.c | 211 |
1 files changed, 159 insertions, 52 deletions
diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c index 951dd3b..2666351 100644 --- a/drivers/usb/host/ehci-mx6.c +++ b/drivers/usb/host/ehci-mx6.c @@ -45,7 +45,10 @@ #define ANADIG_USB2_PLL_480_CTRL_POWER 0x00001000 #define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS 0x00000040 - +#define USBNC_OFFSET 0x200 +#define USBNC_PHYSTATUS_ID_DIG (1 << 4) /* otg_id status */ +#define USBNC_PHYCFG2_ACAENB (1 << 4) /* otg_id detection enable */ +#define UCTRL_PM (1 << 9) /* OTG Power Mask */ #define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */ #define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */ @@ -53,6 +56,7 @@ #define UCMD_RUN_STOP (1 << 0) /* controller run/stop */ #define UCMD_RESET (1 << 1) /* controller reset */ +#if defined(CONFIG_MX6) static const unsigned phy_bases[] = { USB_PHY0_BASE_ADDR, USB_PHY1_BASE_ADDR, @@ -67,7 +71,7 @@ static void usb_internal_phy_clock_gate(int index, int on) phy_reg = (void __iomem *)phy_bases[index]; phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET; - __raw_writel(USBPHY_CTRL_CLKGATE, phy_reg); + writel(USBPHY_CTRL_CLKGATE, phy_reg); } static void usb_power_config(int index) @@ -100,26 +104,52 @@ static void usb_power_config(int index) * is totally controlled by IC, so the Software only needs * to enable them at initializtion. */ - __raw_writel(ANADIG_USB2_CHRG_DETECT_EN_B | + writel(ANADIG_USB2_CHRG_DETECT_EN_B | ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B, chrg_detect); - __raw_writel(ANADIG_USB2_PLL_480_CTRL_BYPASS, + writel(ANADIG_USB2_PLL_480_CTRL_BYPASS, pll_480_ctrl_clr); - __raw_writel(ANADIG_USB2_PLL_480_CTRL_ENABLE | + writel(ANADIG_USB2_PLL_480_CTRL_ENABLE | ANADIG_USB2_PLL_480_CTRL_POWER | ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS, pll_480_ctrl_set); } +static int wait_for_bit(u32 *reg, const u32 mask, bool set) +{ + u32 val; + const unsigned int timeout = 10000; + unsigned long start = get_timer(0); + + while(1) { + val = readl(reg); + if (!set) + val = ~val; + + if ((val & mask) == mask) + return 0; + + if (get_timer(start) > timeout) + break; + + udelay(1); + } + + debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n", + __func__, reg, mask, set); + + return -ETIMEDOUT; +} + /* Return 0 : host node, <>0 : device mode */ static int usb_phy_enable(int index, struct usb_ehci *ehci) { void __iomem *phy_reg; void __iomem *phy_ctrl; void __iomem *usb_cmd; - u32 val; + int ret; if (index >= ARRAY_SIZE(phy_bases)) return 0; @@ -129,40 +159,50 @@ static int usb_phy_enable(int index, struct usb_ehci *ehci) usb_cmd = (void __iomem *)&ehci->usbcmd; /* Stop then Reset */ - val = __raw_readl(usb_cmd); - val &= ~UCMD_RUN_STOP; - __raw_writel(val, usb_cmd); - while (__raw_readl(usb_cmd) & UCMD_RUN_STOP) - ; - - val = __raw_readl(usb_cmd); - val |= UCMD_RESET; - __raw_writel(val, usb_cmd); - while (__raw_readl(usb_cmd) & UCMD_RESET) - ; + clrbits_le32(usb_cmd, UCMD_RUN_STOP); + ret = wait_for_bit(usb_cmd, UCMD_RUN_STOP, 0); + if (ret) + return ret; + + setbits_le32(usb_cmd, UCMD_RESET); + ret = wait_for_bit(usb_cmd, UCMD_RESET, 0); + if (ret) + return ret; /* Reset USBPHY module */ - val = __raw_readl(phy_ctrl); - val |= USBPHY_CTRL_SFTRST; - __raw_writel(val, phy_ctrl); + setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST); udelay(10); /* Remove CLKGATE and SFTRST */ - val = __raw_readl(phy_ctrl); - val &= ~(USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST); - __raw_writel(val, phy_ctrl); + clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST); udelay(10); /* Power up the PHY */ - __raw_writel(0, phy_reg + USBPHY_PWD); + writel(0, phy_reg + USBPHY_PWD); /* enable FS/LS device */ - val = __raw_readl(phy_ctrl); - val |= (USBPHY_CTRL_ENUTMILEVEL2 | USBPHY_CTRL_ENUTMILEVEL3); - __raw_writel(val, phy_ctrl); + setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 | + USBPHY_CTRL_ENUTMILEVEL3); return 0; } +int usb_phy_mode(int port) +{ + void __iomem *phy_reg; + void __iomem *phy_ctrl; + u32 val; + + phy_reg = (void __iomem *)phy_bases[port]; + phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL); + + val = readl(phy_ctrl); + + if (val & USBPHY_CTRL_OTG_ID) + return USB_INIT_DEVICE; + else + return USB_INIT_HOST; +} + /* Base address for this IP block is 0x02184800 */ struct usbnc_regs { u32 ctrl[4]; /* otg/host1-3 */ @@ -171,55 +211,113 @@ struct usbnc_regs { u32 otg_phy_ctrl_0; u32 uh1_phy_ctrl_0; }; +#elif defined(CONFIG_MX7) +struct usbnc_regs { + u32 ctrl1; + u32 ctrl2; + u32 reserve1[10]; + u32 phy_cfg1; + u32 phy_cfg2; + u32 phy_status; + u32 reserve2[4]; + u32 adp_cfg1; + u32 adp_cfg2; + u32 adp_status; +}; -static void usb_oc_config(int index) +static void usb_power_config(int index) { struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR + - USB_OTHERREGS_OFFSET); - void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]); - u32 val; + (0x10000 * index) + USBNC_OFFSET); + void __iomem *phy_cfg2 = (void __iomem *)(&usbnc->phy_cfg2); - val = __raw_readl(ctrl); -#if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2 - /* mx6qarm2 seems to required a different setting*/ - val &= ~UCTRL_OVER_CUR_POL; -#else - val |= UCTRL_OVER_CUR_POL; -#endif - __raw_writel(val, ctrl); - - val = __raw_readl(ctrl); - val |= UCTRL_OVER_CUR_DIS; - __raw_writel(val, ctrl); + /* Enable usb_otg_id detection */ + setbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB); } int usb_phy_mode(int port) { - void __iomem *phy_reg; - void __iomem *phy_ctrl; + struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR + + (0x10000 * port) + USBNC_OFFSET); + void __iomem *status = (void __iomem *)(&usbnc->phy_status); u32 val; - phy_reg = (void __iomem *)phy_bases[port]; - phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL); - - val = __raw_readl(phy_ctrl); + val = readl(status); - if (val & USBPHY_CTRL_OTG_ID) + if (val & USBNC_PHYSTATUS_ID_DIG) return USB_INIT_DEVICE; else return USB_INIT_HOST; } +#endif +static void usb_oc_config(int index) +{ +#if defined(CONFIG_MX6) + struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR + + USB_OTHERREGS_OFFSET); + void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]); +#elif defined(CONFIG_MX7) + struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR + + (0x10000 * index) + USBNC_OFFSET); + void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl1); +#endif + +#if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2 + /* mx6qarm2 seems to required a different setting*/ + clrbits_le32(ctrl, UCTRL_OVER_CUR_POL); +#else + setbits_le32(ctrl, UCTRL_OVER_CUR_POL); +#endif + +#if defined(CONFIG_MX6) + setbits_le32(ctrl, UCTRL_OVER_CUR_DIS); +#elif defined(CONFIG_MX7) + setbits_le32(ctrl, UCTRL_OVER_CUR_DIS | UCTRL_PM); +#endif +} + +/** + * board_ehci_hcd_init - override usb phy mode + * @port: usb host/otg port + * + * Target board specific, override usb_phy_mode. + * When usb-otg is used as usb host port, iomux pad usb_otg_id can be + * left disconnected in this case usb_phy_mode will not be able to identify + * the phy mode that usb port is used. + * Machine file overrides board_usb_phy_mode. + * + * Return: USB_INIT_DEVICE or USB_INIT_HOST + */ int __weak board_usb_phy_mode(int port) { return usb_phy_mode(port); } +/** + * board_ehci_hcd_init - set usb vbus voltage + * @port: usb otg port + * + * Target board specific, setup iomux pad to setup supply vbus voltage + * for usb otg port. Machine board file overrides board_ehci_hcd_init + * + * Return: 0 Success + */ int __weak board_ehci_hcd_init(int port) { return 0; } +/** + * board_ehci_power - enables/disables usb vbus voltage + * @port: usb otg port + * @on: on/off vbus voltage + * + * Enables/disables supply vbus voltage for usb otg port. + * Machine board file overrides board_ehci_power + * + * Return: 0 Success + */ int __weak board_ehci_power(int port, int on) { return 0; @@ -229,8 +327,13 @@ int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr, struct ehci_hcor **hcor) { enum usb_init_type type; +#if defined(CONFIG_MX6) + u32 controller_spacing = 0x200; +#elif defined(CONFIG_MX7) + u32 controller_spacing = 0x10000; +#endif struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR + - (0x200 * index)); + (controller_spacing * index)); if (index > 3) return -EINVAL; @@ -242,8 +345,11 @@ int ehci_hcd_init(int index, enum usb_init_type init, usb_power_config(index); usb_oc_config(index); + +#if defined(CONFIG_MX6) usb_internal_phy_clock_gate(index, 1); usb_phy_enable(index, ehci); +#endif type = board_usb_phy_mode(index); *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); @@ -256,8 +362,9 @@ int ehci_hcd_init(int index, enum usb_init_type init, return -ENODEV; if (type == USB_INIT_DEVICE) return 0; + setbits_le32(&ehci->usbmode, CM_HOST); - __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); + writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); setbits_le32(&ehci->portsc, USB_EN); mdelay(10); |