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| author | Marek Vasut <marex@denx.de> | 2015-12-04 02:44:33 +0100 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2015-12-17 21:54:40 +0100 |
| commit | 507e677bc4f25b15d81d599c3d8b669ab9846493 (patch) | |
| tree | 90c28230656c338a3bfba6fc5574a0758061c38a /drivers/usb/gadget/dwc2_udc_otg_regs.h | |
| parent | be5e4bdcedbd3bf5f2717fc22356e825bca0fbcd (diff) | |
| download | u-boot-imx-507e677bc4f25b15d81d599c3d8b669ab9846493.zip u-boot-imx-507e677bc4f25b15d81d599c3d8b669ab9846493.tar.gz u-boot-imx-507e677bc4f25b15d81d599c3d8b669ab9846493.tar.bz2 | |
usb: s3c-otg: Rename remaining macros
The driver is actually for the Designware DWC2 controller.
This patch renames the remaining S3C_* macros to match the
DWC2 naming.
Signed-off-by: Marek Vasut <marex@denx.de>
Diffstat (limited to 'drivers/usb/gadget/dwc2_udc_otg_regs.h')
| -rw-r--r-- | drivers/usb/gadget/dwc2_udc_otg_regs.h | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/drivers/usb/gadget/dwc2_udc_otg_regs.h b/drivers/usb/gadget/dwc2_udc_otg_regs.h index 57affcb..78ec90e 100644 --- a/drivers/usb/gadget/dwc2_udc_otg_regs.h +++ b/drivers/usb/gadget/dwc2_udc_otg_regs.h @@ -83,11 +83,11 @@ struct dwc2_usbotg_reg { /*===================================================================== */ /*definitions related to CSR setting */ -/* S3C_UDC_OTG_GOTGCTL */ +/* DWC2_UDC_OTG_GOTGCTL */ #define B_SESSION_VALID (0x1<<19) #define A_SESSION_VALID (0x1<<18) -/* S3C_UDC_OTG_GAHBCFG */ +/* DWC2_UDC_OTG_GAHBCFG */ #define PTXFE_HALF (0<<8) #define PTXFE_ZERO (1<<8) #define NPTXFE_HALF (0<<7) @@ -102,11 +102,11 @@ struct dwc2_usbotg_reg { #define GBL_INT_UNMASK (1<<0) #define GBL_INT_MASK (0<<0) -/* S3C_UDC_OTG_GRSTCTL */ +/* DWC2_UDC_OTG_GRSTCTL */ #define AHB_MASTER_IDLE (1u<<31) #define CORE_SOFT_RESET (0x1<<0) -/* S3C_UDC_OTG_GINTSTS/S3C_UDC_OTG_GINTMSK core interrupt register */ +/* DWC2_UDC_OTG_GINTSTS/DWC2_UDC_OTG_GINTMSK core interrupt register */ #define INT_RESUME (1u<<31) #define INT_DISCONN (0x1<<29) #define INT_CONN_ID_STS_CNG (0x1<<28) @@ -146,22 +146,22 @@ struct dwc2_usbotg_reg { #define USB_LOW_6MHZ (0x2<<1) #define USB_FULL_48MHZ (0x3<<1) -/* S3C_UDC_OTG_GRXSTSP STATUS */ +/* DWC2_UDC_OTG_GRXSTSP STATUS */ #define OUT_PKT_RECEIVED (0x2<<17) #define OUT_TRANSFER_COMPLELTED (0x3<<17) #define SETUP_TRANSACTION_COMPLETED (0x4<<17) #define SETUP_PKT_RECEIVED (0x6<<17) #define GLOBAL_OUT_NAK (0x1<<17) -/* S3C_UDC_OTG_DCTL device control register */ +/* DWC2_UDC_OTG_DCTL device control register */ #define NORMAL_OPERATION (0x1<<0) #define SOFT_DISCONNECT (0x1<<1) -/* S3C_UDC_OTG_DAINT device all endpoint interrupt register */ +/* DWC2_UDC_OTG_DAINT device all endpoint interrupt register */ #define DAINT_OUT_BIT (16) #define DAINT_MASK (0xFFFF) -/* S3C_UDC_OTG_DIEPCTL0/DOEPCTL0 device +/* DWC2_UDC_OTG_DIEPCTL0/DOEPCTL0 device control IN/OUT endpoint 0 control register */ #define DEPCTL_EPENA (0x1<<31) #define DEPCTL_EPDIS (0x1<<30) @@ -191,9 +191,9 @@ struct dwc2_usbotg_reg { #define DIEPCTL0_NEXT_EP_BIT (11) -/* S3C_UDC_OTG_DIEPMSK/DOEPMSK device IN/OUT endpoint +/* DWC2_UDC_OTG_DIEPMSK/DOEPMSK device IN/OUT endpoint common interrupt mask register */ -/* S3C_UDC_OTG_DIEPINTn/DOEPINTn device IN/OUT endpoint interrupt register */ +/* DWC2_UDC_OTG_DIEPINTn/DOEPINTn device IN/OUT endpoint interrupt register */ #define BACK2BACK_SETUP_RECEIVED (0x1<<6) #define INTKNEPMIS (0x1<<5) #define INTKN_TXFEMP (0x1<<4) |